1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/ppc/ppc.h" 30 #include "hw/i2c/ppc4xx_i2c.h" 31 #include "hw/irq.h" 32 #include "ppc405.h" 33 #include "hw/char/serial.h" 34 #include "qemu/timer.h" 35 #include "sysemu/reset.h" 36 #include "sysemu/sysemu.h" 37 #include "qemu/log.h" 38 #include "exec/address-spaces.h" 39 40 //#define DEBUG_OPBA 41 //#define DEBUG_SDRAM 42 //#define DEBUG_GPIO 43 //#define DEBUG_SERIAL 44 //#define DEBUG_OCM 45 //#define DEBUG_GPT 46 //#define DEBUG_CLOCKS 47 //#define DEBUG_CLOCKS_LL 48 49 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd, 50 uint32_t flags) 51 { 52 CPUState *cs = env_cpu(env); 53 ram_addr_t bdloc; 54 int i, n; 55 56 /* We put the bd structure at the top of memory */ 57 if (bd->bi_memsize >= 0x01000000UL) 58 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 59 else 60 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 61 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 62 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 63 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 64 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 65 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 66 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 67 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 68 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 69 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 70 for (i = 0; i < 6; i++) { 71 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 72 } 73 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 74 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 75 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 76 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 77 for (i = 0; i < 4; i++) { 78 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 79 } 80 for (i = 0; i < 32; i++) { 81 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 82 } 83 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 84 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 85 for (i = 0; i < 6; i++) { 86 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 87 } 88 n = 0x6A; 89 if (flags & 0x00000001) { 90 for (i = 0; i < 6; i++) 91 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 92 } 93 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 94 n += 4; 95 for (i = 0; i < 2; i++) { 96 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 97 n += 4; 98 } 99 100 return bdloc; 101 } 102 103 /*****************************************************************************/ 104 /* Shared peripherals */ 105 106 /*****************************************************************************/ 107 /* Peripheral local bus arbitrer */ 108 enum { 109 PLB3A0_ACR = 0x077, 110 PLB4A0_ACR = 0x081, 111 PLB0_BESR = 0x084, 112 PLB0_BEAR = 0x086, 113 PLB0_ACR = 0x087, 114 PLB4A1_ACR = 0x089, 115 }; 116 117 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 118 struct ppc4xx_plb_t { 119 uint32_t acr; 120 uint32_t bear; 121 uint32_t besr; 122 }; 123 124 static uint32_t dcr_read_plb (void *opaque, int dcrn) 125 { 126 ppc4xx_plb_t *plb; 127 uint32_t ret; 128 129 plb = opaque; 130 switch (dcrn) { 131 case PLB0_ACR: 132 ret = plb->acr; 133 break; 134 case PLB0_BEAR: 135 ret = plb->bear; 136 break; 137 case PLB0_BESR: 138 ret = plb->besr; 139 break; 140 default: 141 /* Avoid gcc warning */ 142 ret = 0; 143 break; 144 } 145 146 return ret; 147 } 148 149 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 150 { 151 ppc4xx_plb_t *plb; 152 153 plb = opaque; 154 switch (dcrn) { 155 case PLB0_ACR: 156 /* We don't care about the actual parameters written as 157 * we don't manage any priorities on the bus 158 */ 159 plb->acr = val & 0xF8000000; 160 break; 161 case PLB0_BEAR: 162 /* Read only */ 163 break; 164 case PLB0_BESR: 165 /* Write-clear */ 166 plb->besr &= ~val; 167 break; 168 } 169 } 170 171 static void ppc4xx_plb_reset (void *opaque) 172 { 173 ppc4xx_plb_t *plb; 174 175 plb = opaque; 176 plb->acr = 0x00000000; 177 plb->bear = 0x00000000; 178 plb->besr = 0x00000000; 179 } 180 181 void ppc4xx_plb_init(CPUPPCState *env) 182 { 183 ppc4xx_plb_t *plb; 184 185 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 186 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 187 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 188 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 189 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 190 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 191 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 192 qemu_register_reset(ppc4xx_plb_reset, plb); 193 } 194 195 /*****************************************************************************/ 196 /* PLB to OPB bridge */ 197 enum { 198 POB0_BESR0 = 0x0A0, 199 POB0_BESR1 = 0x0A2, 200 POB0_BEAR = 0x0A4, 201 }; 202 203 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 204 struct ppc4xx_pob_t { 205 uint32_t bear; 206 uint32_t besr0; 207 uint32_t besr1; 208 }; 209 210 static uint32_t dcr_read_pob (void *opaque, int dcrn) 211 { 212 ppc4xx_pob_t *pob; 213 uint32_t ret; 214 215 pob = opaque; 216 switch (dcrn) { 217 case POB0_BEAR: 218 ret = pob->bear; 219 break; 220 case POB0_BESR0: 221 ret = pob->besr0; 222 break; 223 case POB0_BESR1: 224 ret = pob->besr1; 225 break; 226 default: 227 /* Avoid gcc warning */ 228 ret = 0; 229 break; 230 } 231 232 return ret; 233 } 234 235 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 236 { 237 ppc4xx_pob_t *pob; 238 239 pob = opaque; 240 switch (dcrn) { 241 case POB0_BEAR: 242 /* Read only */ 243 break; 244 case POB0_BESR0: 245 /* Write-clear */ 246 pob->besr0 &= ~val; 247 break; 248 case POB0_BESR1: 249 /* Write-clear */ 250 pob->besr1 &= ~val; 251 break; 252 } 253 } 254 255 static void ppc4xx_pob_reset (void *opaque) 256 { 257 ppc4xx_pob_t *pob; 258 259 pob = opaque; 260 /* No error */ 261 pob->bear = 0x00000000; 262 pob->besr0 = 0x0000000; 263 pob->besr1 = 0x0000000; 264 } 265 266 static void ppc4xx_pob_init(CPUPPCState *env) 267 { 268 ppc4xx_pob_t *pob; 269 270 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 271 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 272 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 273 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 274 qemu_register_reset(ppc4xx_pob_reset, pob); 275 } 276 277 /*****************************************************************************/ 278 /* OPB arbitrer */ 279 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 280 struct ppc4xx_opba_t { 281 MemoryRegion io; 282 uint8_t cr; 283 uint8_t pr; 284 }; 285 286 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 287 { 288 ppc4xx_opba_t *opba; 289 uint32_t ret; 290 291 #ifdef DEBUG_OPBA 292 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 293 #endif 294 opba = opaque; 295 switch (addr) { 296 case 0x00: 297 ret = opba->cr; 298 break; 299 case 0x01: 300 ret = opba->pr; 301 break; 302 default: 303 ret = 0x00; 304 break; 305 } 306 307 return ret; 308 } 309 310 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 311 unsigned size) 312 { 313 ppc4xx_opba_t *opba; 314 315 #ifdef DEBUG_OPBA 316 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 317 value); 318 #endif 319 opba = opaque; 320 switch (addr) { 321 case 0x00: 322 opba->cr = value & 0xF8; 323 break; 324 case 0x01: 325 opba->pr = value & 0xFF; 326 break; 327 default: 328 break; 329 } 330 } 331 static const MemoryRegionOps opba_ops = { 332 .read = opba_readb, 333 .write = opba_writeb, 334 .impl.min_access_size = 1, 335 .impl.max_access_size = 1, 336 .valid.min_access_size = 1, 337 .valid.max_access_size = 4, 338 .endianness = DEVICE_BIG_ENDIAN, 339 }; 340 341 static void ppc4xx_opba_reset (void *opaque) 342 { 343 ppc4xx_opba_t *opba; 344 345 opba = opaque; 346 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 347 opba->pr = 0x11; 348 } 349 350 static void ppc4xx_opba_init(hwaddr base) 351 { 352 ppc4xx_opba_t *opba; 353 354 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 355 #ifdef DEBUG_OPBA 356 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 357 #endif 358 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 359 memory_region_add_subregion(get_system_memory(), base, &opba->io); 360 qemu_register_reset(ppc4xx_opba_reset, opba); 361 } 362 363 /*****************************************************************************/ 364 /* Code decompression controller */ 365 /* XXX: TODO */ 366 367 /*****************************************************************************/ 368 /* Peripheral controller */ 369 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 370 struct ppc4xx_ebc_t { 371 uint32_t addr; 372 uint32_t bcr[8]; 373 uint32_t bap[8]; 374 uint32_t bear; 375 uint32_t besr0; 376 uint32_t besr1; 377 uint32_t cfg; 378 }; 379 380 enum { 381 EBC0_CFGADDR = 0x012, 382 EBC0_CFGDATA = 0x013, 383 }; 384 385 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 386 { 387 ppc4xx_ebc_t *ebc; 388 uint32_t ret; 389 390 ebc = opaque; 391 switch (dcrn) { 392 case EBC0_CFGADDR: 393 ret = ebc->addr; 394 break; 395 case EBC0_CFGDATA: 396 switch (ebc->addr) { 397 case 0x00: /* B0CR */ 398 ret = ebc->bcr[0]; 399 break; 400 case 0x01: /* B1CR */ 401 ret = ebc->bcr[1]; 402 break; 403 case 0x02: /* B2CR */ 404 ret = ebc->bcr[2]; 405 break; 406 case 0x03: /* B3CR */ 407 ret = ebc->bcr[3]; 408 break; 409 case 0x04: /* B4CR */ 410 ret = ebc->bcr[4]; 411 break; 412 case 0x05: /* B5CR */ 413 ret = ebc->bcr[5]; 414 break; 415 case 0x06: /* B6CR */ 416 ret = ebc->bcr[6]; 417 break; 418 case 0x07: /* B7CR */ 419 ret = ebc->bcr[7]; 420 break; 421 case 0x10: /* B0AP */ 422 ret = ebc->bap[0]; 423 break; 424 case 0x11: /* B1AP */ 425 ret = ebc->bap[1]; 426 break; 427 case 0x12: /* B2AP */ 428 ret = ebc->bap[2]; 429 break; 430 case 0x13: /* B3AP */ 431 ret = ebc->bap[3]; 432 break; 433 case 0x14: /* B4AP */ 434 ret = ebc->bap[4]; 435 break; 436 case 0x15: /* B5AP */ 437 ret = ebc->bap[5]; 438 break; 439 case 0x16: /* B6AP */ 440 ret = ebc->bap[6]; 441 break; 442 case 0x17: /* B7AP */ 443 ret = ebc->bap[7]; 444 break; 445 case 0x20: /* BEAR */ 446 ret = ebc->bear; 447 break; 448 case 0x21: /* BESR0 */ 449 ret = ebc->besr0; 450 break; 451 case 0x22: /* BESR1 */ 452 ret = ebc->besr1; 453 break; 454 case 0x23: /* CFG */ 455 ret = ebc->cfg; 456 break; 457 default: 458 ret = 0x00000000; 459 break; 460 } 461 break; 462 default: 463 ret = 0x00000000; 464 break; 465 } 466 467 return ret; 468 } 469 470 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 471 { 472 ppc4xx_ebc_t *ebc; 473 474 ebc = opaque; 475 switch (dcrn) { 476 case EBC0_CFGADDR: 477 ebc->addr = val; 478 break; 479 case EBC0_CFGDATA: 480 switch (ebc->addr) { 481 case 0x00: /* B0CR */ 482 break; 483 case 0x01: /* B1CR */ 484 break; 485 case 0x02: /* B2CR */ 486 break; 487 case 0x03: /* B3CR */ 488 break; 489 case 0x04: /* B4CR */ 490 break; 491 case 0x05: /* B5CR */ 492 break; 493 case 0x06: /* B6CR */ 494 break; 495 case 0x07: /* B7CR */ 496 break; 497 case 0x10: /* B0AP */ 498 break; 499 case 0x11: /* B1AP */ 500 break; 501 case 0x12: /* B2AP */ 502 break; 503 case 0x13: /* B3AP */ 504 break; 505 case 0x14: /* B4AP */ 506 break; 507 case 0x15: /* B5AP */ 508 break; 509 case 0x16: /* B6AP */ 510 break; 511 case 0x17: /* B7AP */ 512 break; 513 case 0x20: /* BEAR */ 514 break; 515 case 0x21: /* BESR0 */ 516 break; 517 case 0x22: /* BESR1 */ 518 break; 519 case 0x23: /* CFG */ 520 break; 521 default: 522 break; 523 } 524 break; 525 default: 526 break; 527 } 528 } 529 530 static void ebc_reset (void *opaque) 531 { 532 ppc4xx_ebc_t *ebc; 533 int i; 534 535 ebc = opaque; 536 ebc->addr = 0x00000000; 537 ebc->bap[0] = 0x7F8FFE80; 538 ebc->bcr[0] = 0xFFE28000; 539 for (i = 0; i < 8; i++) { 540 ebc->bap[i] = 0x00000000; 541 ebc->bcr[i] = 0x00000000; 542 } 543 ebc->besr0 = 0x00000000; 544 ebc->besr1 = 0x00000000; 545 ebc->cfg = 0x80400000; 546 } 547 548 void ppc405_ebc_init(CPUPPCState *env) 549 { 550 ppc4xx_ebc_t *ebc; 551 552 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 553 qemu_register_reset(&ebc_reset, ebc); 554 ppc_dcr_register(env, EBC0_CFGADDR, 555 ebc, &dcr_read_ebc, &dcr_write_ebc); 556 ppc_dcr_register(env, EBC0_CFGDATA, 557 ebc, &dcr_read_ebc, &dcr_write_ebc); 558 } 559 560 /*****************************************************************************/ 561 /* DMA controller */ 562 enum { 563 DMA0_CR0 = 0x100, 564 DMA0_CT0 = 0x101, 565 DMA0_DA0 = 0x102, 566 DMA0_SA0 = 0x103, 567 DMA0_SG0 = 0x104, 568 DMA0_CR1 = 0x108, 569 DMA0_CT1 = 0x109, 570 DMA0_DA1 = 0x10A, 571 DMA0_SA1 = 0x10B, 572 DMA0_SG1 = 0x10C, 573 DMA0_CR2 = 0x110, 574 DMA0_CT2 = 0x111, 575 DMA0_DA2 = 0x112, 576 DMA0_SA2 = 0x113, 577 DMA0_SG2 = 0x114, 578 DMA0_CR3 = 0x118, 579 DMA0_CT3 = 0x119, 580 DMA0_DA3 = 0x11A, 581 DMA0_SA3 = 0x11B, 582 DMA0_SG3 = 0x11C, 583 DMA0_SR = 0x120, 584 DMA0_SGC = 0x123, 585 DMA0_SLP = 0x125, 586 DMA0_POL = 0x126, 587 }; 588 589 typedef struct ppc405_dma_t ppc405_dma_t; 590 struct ppc405_dma_t { 591 qemu_irq irqs[4]; 592 uint32_t cr[4]; 593 uint32_t ct[4]; 594 uint32_t da[4]; 595 uint32_t sa[4]; 596 uint32_t sg[4]; 597 uint32_t sr; 598 uint32_t sgc; 599 uint32_t slp; 600 uint32_t pol; 601 }; 602 603 static uint32_t dcr_read_dma (void *opaque, int dcrn) 604 { 605 return 0; 606 } 607 608 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 609 { 610 } 611 612 static void ppc405_dma_reset (void *opaque) 613 { 614 ppc405_dma_t *dma; 615 int i; 616 617 dma = opaque; 618 for (i = 0; i < 4; i++) { 619 dma->cr[i] = 0x00000000; 620 dma->ct[i] = 0x00000000; 621 dma->da[i] = 0x00000000; 622 dma->sa[i] = 0x00000000; 623 dma->sg[i] = 0x00000000; 624 } 625 dma->sr = 0x00000000; 626 dma->sgc = 0x00000000; 627 dma->slp = 0x7C000000; 628 dma->pol = 0x00000000; 629 } 630 631 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 632 { 633 ppc405_dma_t *dma; 634 635 dma = g_malloc0(sizeof(ppc405_dma_t)); 636 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 637 qemu_register_reset(&ppc405_dma_reset, dma); 638 ppc_dcr_register(env, DMA0_CR0, 639 dma, &dcr_read_dma, &dcr_write_dma); 640 ppc_dcr_register(env, DMA0_CT0, 641 dma, &dcr_read_dma, &dcr_write_dma); 642 ppc_dcr_register(env, DMA0_DA0, 643 dma, &dcr_read_dma, &dcr_write_dma); 644 ppc_dcr_register(env, DMA0_SA0, 645 dma, &dcr_read_dma, &dcr_write_dma); 646 ppc_dcr_register(env, DMA0_SG0, 647 dma, &dcr_read_dma, &dcr_write_dma); 648 ppc_dcr_register(env, DMA0_CR1, 649 dma, &dcr_read_dma, &dcr_write_dma); 650 ppc_dcr_register(env, DMA0_CT1, 651 dma, &dcr_read_dma, &dcr_write_dma); 652 ppc_dcr_register(env, DMA0_DA1, 653 dma, &dcr_read_dma, &dcr_write_dma); 654 ppc_dcr_register(env, DMA0_SA1, 655 dma, &dcr_read_dma, &dcr_write_dma); 656 ppc_dcr_register(env, DMA0_SG1, 657 dma, &dcr_read_dma, &dcr_write_dma); 658 ppc_dcr_register(env, DMA0_CR2, 659 dma, &dcr_read_dma, &dcr_write_dma); 660 ppc_dcr_register(env, DMA0_CT2, 661 dma, &dcr_read_dma, &dcr_write_dma); 662 ppc_dcr_register(env, DMA0_DA2, 663 dma, &dcr_read_dma, &dcr_write_dma); 664 ppc_dcr_register(env, DMA0_SA2, 665 dma, &dcr_read_dma, &dcr_write_dma); 666 ppc_dcr_register(env, DMA0_SG2, 667 dma, &dcr_read_dma, &dcr_write_dma); 668 ppc_dcr_register(env, DMA0_CR3, 669 dma, &dcr_read_dma, &dcr_write_dma); 670 ppc_dcr_register(env, DMA0_CT3, 671 dma, &dcr_read_dma, &dcr_write_dma); 672 ppc_dcr_register(env, DMA0_DA3, 673 dma, &dcr_read_dma, &dcr_write_dma); 674 ppc_dcr_register(env, DMA0_SA3, 675 dma, &dcr_read_dma, &dcr_write_dma); 676 ppc_dcr_register(env, DMA0_SG3, 677 dma, &dcr_read_dma, &dcr_write_dma); 678 ppc_dcr_register(env, DMA0_SR, 679 dma, &dcr_read_dma, &dcr_write_dma); 680 ppc_dcr_register(env, DMA0_SGC, 681 dma, &dcr_read_dma, &dcr_write_dma); 682 ppc_dcr_register(env, DMA0_SLP, 683 dma, &dcr_read_dma, &dcr_write_dma); 684 ppc_dcr_register(env, DMA0_POL, 685 dma, &dcr_read_dma, &dcr_write_dma); 686 } 687 688 /*****************************************************************************/ 689 /* GPIO */ 690 typedef struct ppc405_gpio_t ppc405_gpio_t; 691 struct ppc405_gpio_t { 692 MemoryRegion io; 693 uint32_t or; 694 uint32_t tcr; 695 uint32_t osrh; 696 uint32_t osrl; 697 uint32_t tsrh; 698 uint32_t tsrl; 699 uint32_t odr; 700 uint32_t ir; 701 uint32_t rr1; 702 uint32_t isr1h; 703 uint32_t isr1l; 704 }; 705 706 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 707 { 708 #ifdef DEBUG_GPIO 709 printf("%s: addr " TARGET_FMT_plx " size %d\n", __func__, addr, size); 710 #endif 711 712 return 0; 713 } 714 715 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 716 unsigned size) 717 { 718 #ifdef DEBUG_GPIO 719 printf("%s: addr " TARGET_FMT_plx " size %d val %08" PRIx32 "\n", 720 __func__, addr, size, value); 721 #endif 722 } 723 724 static const MemoryRegionOps ppc405_gpio_ops = { 725 .read = ppc405_gpio_read, 726 .write = ppc405_gpio_write, 727 .endianness = DEVICE_NATIVE_ENDIAN, 728 }; 729 730 static void ppc405_gpio_reset (void *opaque) 731 { 732 } 733 734 static void ppc405_gpio_init(hwaddr base) 735 { 736 ppc405_gpio_t *gpio; 737 738 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 739 #ifdef DEBUG_GPIO 740 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 741 #endif 742 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 743 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 744 qemu_register_reset(&ppc405_gpio_reset, gpio); 745 } 746 747 /*****************************************************************************/ 748 /* On Chip Memory */ 749 enum { 750 OCM0_ISARC = 0x018, 751 OCM0_ISACNTL = 0x019, 752 OCM0_DSARC = 0x01A, 753 OCM0_DSACNTL = 0x01B, 754 }; 755 756 typedef struct ppc405_ocm_t ppc405_ocm_t; 757 struct ppc405_ocm_t { 758 MemoryRegion ram; 759 MemoryRegion isarc_ram; 760 MemoryRegion dsarc_ram; 761 uint32_t isarc; 762 uint32_t isacntl; 763 uint32_t dsarc; 764 uint32_t dsacntl; 765 }; 766 767 static void ocm_update_mappings (ppc405_ocm_t *ocm, 768 uint32_t isarc, uint32_t isacntl, 769 uint32_t dsarc, uint32_t dsacntl) 770 { 771 #ifdef DEBUG_OCM 772 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32 773 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32 774 " (%08" PRIx32 " %08" PRIx32 ")\n", 775 isarc, isacntl, dsarc, dsacntl, 776 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl); 777 #endif 778 if (ocm->isarc != isarc || 779 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 780 if (ocm->isacntl & 0x80000000) { 781 /* Unmap previously assigned memory region */ 782 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc); 783 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 784 } 785 if (isacntl & 0x80000000) { 786 /* Map new instruction memory region */ 787 #ifdef DEBUG_OCM 788 printf("OCM map ISA %08" PRIx32 "\n", isarc); 789 #endif 790 memory_region_add_subregion(get_system_memory(), isarc, 791 &ocm->isarc_ram); 792 } 793 } 794 if (ocm->dsarc != dsarc || 795 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 796 if (ocm->dsacntl & 0x80000000) { 797 /* Beware not to unmap the region we just mapped */ 798 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 799 /* Unmap previously assigned memory region */ 800 #ifdef DEBUG_OCM 801 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc); 802 #endif 803 memory_region_del_subregion(get_system_memory(), 804 &ocm->dsarc_ram); 805 } 806 } 807 if (dsacntl & 0x80000000) { 808 /* Beware not to remap the region we just mapped */ 809 if (!(isacntl & 0x80000000) || dsarc != isarc) { 810 /* Map new data memory region */ 811 #ifdef DEBUG_OCM 812 printf("OCM map DSA %08" PRIx32 "\n", dsarc); 813 #endif 814 memory_region_add_subregion(get_system_memory(), dsarc, 815 &ocm->dsarc_ram); 816 } 817 } 818 } 819 } 820 821 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 822 { 823 ppc405_ocm_t *ocm; 824 uint32_t ret; 825 826 ocm = opaque; 827 switch (dcrn) { 828 case OCM0_ISARC: 829 ret = ocm->isarc; 830 break; 831 case OCM0_ISACNTL: 832 ret = ocm->isacntl; 833 break; 834 case OCM0_DSARC: 835 ret = ocm->dsarc; 836 break; 837 case OCM0_DSACNTL: 838 ret = ocm->dsacntl; 839 break; 840 default: 841 ret = 0; 842 break; 843 } 844 845 return ret; 846 } 847 848 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 849 { 850 ppc405_ocm_t *ocm; 851 uint32_t isarc, dsarc, isacntl, dsacntl; 852 853 ocm = opaque; 854 isarc = ocm->isarc; 855 dsarc = ocm->dsarc; 856 isacntl = ocm->isacntl; 857 dsacntl = ocm->dsacntl; 858 switch (dcrn) { 859 case OCM0_ISARC: 860 isarc = val & 0xFC000000; 861 break; 862 case OCM0_ISACNTL: 863 isacntl = val & 0xC0000000; 864 break; 865 case OCM0_DSARC: 866 isarc = val & 0xFC000000; 867 break; 868 case OCM0_DSACNTL: 869 isacntl = val & 0xC0000000; 870 break; 871 } 872 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 873 ocm->isarc = isarc; 874 ocm->dsarc = dsarc; 875 ocm->isacntl = isacntl; 876 ocm->dsacntl = dsacntl; 877 } 878 879 static void ocm_reset (void *opaque) 880 { 881 ppc405_ocm_t *ocm; 882 uint32_t isarc, dsarc, isacntl, dsacntl; 883 884 ocm = opaque; 885 isarc = 0x00000000; 886 isacntl = 0x00000000; 887 dsarc = 0x00000000; 888 dsacntl = 0x00000000; 889 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 890 ocm->isarc = isarc; 891 ocm->dsarc = dsarc; 892 ocm->isacntl = isacntl; 893 ocm->dsacntl = dsacntl; 894 } 895 896 static void ppc405_ocm_init(CPUPPCState *env) 897 { 898 ppc405_ocm_t *ocm; 899 900 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 901 /* XXX: Size is 4096 or 0x04000000 */ 902 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 903 &error_fatal); 904 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 905 &ocm->isarc_ram, 0, 4 * KiB); 906 qemu_register_reset(&ocm_reset, ocm); 907 ppc_dcr_register(env, OCM0_ISARC, 908 ocm, &dcr_read_ocm, &dcr_write_ocm); 909 ppc_dcr_register(env, OCM0_ISACNTL, 910 ocm, &dcr_read_ocm, &dcr_write_ocm); 911 ppc_dcr_register(env, OCM0_DSARC, 912 ocm, &dcr_read_ocm, &dcr_write_ocm); 913 ppc_dcr_register(env, OCM0_DSACNTL, 914 ocm, &dcr_read_ocm, &dcr_write_ocm); 915 } 916 917 /*****************************************************************************/ 918 /* General purpose timers */ 919 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 920 struct ppc4xx_gpt_t { 921 MemoryRegion iomem; 922 int64_t tb_offset; 923 uint32_t tb_freq; 924 QEMUTimer *timer; 925 qemu_irq irqs[5]; 926 uint32_t oe; 927 uint32_t ol; 928 uint32_t im; 929 uint32_t is; 930 uint32_t ie; 931 uint32_t comp[5]; 932 uint32_t mask[5]; 933 }; 934 935 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 936 { 937 /* XXX: TODO */ 938 return 0; 939 } 940 941 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 942 { 943 /* XXX: TODO */ 944 } 945 946 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 947 { 948 uint32_t mask; 949 int i; 950 951 mask = 0x80000000; 952 for (i = 0; i < 5; i++) { 953 if (gpt->oe & mask) { 954 /* Output is enabled */ 955 if (ppc4xx_gpt_compare(gpt, i)) { 956 /* Comparison is OK */ 957 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 958 } else { 959 /* Comparison is KO */ 960 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 961 } 962 } 963 mask = mask >> 1; 964 } 965 } 966 967 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 968 { 969 uint32_t mask; 970 int i; 971 972 mask = 0x00008000; 973 for (i = 0; i < 5; i++) { 974 if (gpt->is & gpt->im & mask) 975 qemu_irq_raise(gpt->irqs[i]); 976 else 977 qemu_irq_lower(gpt->irqs[i]); 978 mask = mask >> 1; 979 } 980 } 981 982 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 983 { 984 /* XXX: TODO */ 985 } 986 987 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 988 { 989 ppc4xx_gpt_t *gpt; 990 uint32_t ret; 991 int idx; 992 993 #ifdef DEBUG_GPT 994 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr); 995 #endif 996 gpt = opaque; 997 switch (addr) { 998 case 0x00: 999 /* Time base counter */ 1000 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1001 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1002 break; 1003 case 0x10: 1004 /* Output enable */ 1005 ret = gpt->oe; 1006 break; 1007 case 0x14: 1008 /* Output level */ 1009 ret = gpt->ol; 1010 break; 1011 case 0x18: 1012 /* Interrupt mask */ 1013 ret = gpt->im; 1014 break; 1015 case 0x1C: 1016 case 0x20: 1017 /* Interrupt status */ 1018 ret = gpt->is; 1019 break; 1020 case 0x24: 1021 /* Interrupt enable */ 1022 ret = gpt->ie; 1023 break; 1024 case 0x80 ... 0x90: 1025 /* Compare timer */ 1026 idx = (addr - 0x80) >> 2; 1027 ret = gpt->comp[idx]; 1028 break; 1029 case 0xC0 ... 0xD0: 1030 /* Compare mask */ 1031 idx = (addr - 0xC0) >> 2; 1032 ret = gpt->mask[idx]; 1033 break; 1034 default: 1035 ret = -1; 1036 break; 1037 } 1038 1039 return ret; 1040 } 1041 1042 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1043 unsigned size) 1044 { 1045 ppc4xx_gpt_t *gpt; 1046 int idx; 1047 1048 #ifdef DEBUG_I2C 1049 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr, 1050 value); 1051 #endif 1052 gpt = opaque; 1053 switch (addr) { 1054 case 0x00: 1055 /* Time base counter */ 1056 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1057 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1058 ppc4xx_gpt_compute_timer(gpt); 1059 break; 1060 case 0x10: 1061 /* Output enable */ 1062 gpt->oe = value & 0xF8000000; 1063 ppc4xx_gpt_set_outputs(gpt); 1064 break; 1065 case 0x14: 1066 /* Output level */ 1067 gpt->ol = value & 0xF8000000; 1068 ppc4xx_gpt_set_outputs(gpt); 1069 break; 1070 case 0x18: 1071 /* Interrupt mask */ 1072 gpt->im = value & 0x0000F800; 1073 break; 1074 case 0x1C: 1075 /* Interrupt status set */ 1076 gpt->is |= value & 0x0000F800; 1077 ppc4xx_gpt_set_irqs(gpt); 1078 break; 1079 case 0x20: 1080 /* Interrupt status clear */ 1081 gpt->is &= ~(value & 0x0000F800); 1082 ppc4xx_gpt_set_irqs(gpt); 1083 break; 1084 case 0x24: 1085 /* Interrupt enable */ 1086 gpt->ie = value & 0x0000F800; 1087 ppc4xx_gpt_set_irqs(gpt); 1088 break; 1089 case 0x80 ... 0x90: 1090 /* Compare timer */ 1091 idx = (addr - 0x80) >> 2; 1092 gpt->comp[idx] = value & 0xF8000000; 1093 ppc4xx_gpt_compute_timer(gpt); 1094 break; 1095 case 0xC0 ... 0xD0: 1096 /* Compare mask */ 1097 idx = (addr - 0xC0) >> 2; 1098 gpt->mask[idx] = value & 0xF8000000; 1099 ppc4xx_gpt_compute_timer(gpt); 1100 break; 1101 } 1102 } 1103 1104 static const MemoryRegionOps gpt_ops = { 1105 .read = ppc4xx_gpt_read, 1106 .write = ppc4xx_gpt_write, 1107 .valid.min_access_size = 4, 1108 .valid.max_access_size = 4, 1109 .endianness = DEVICE_NATIVE_ENDIAN, 1110 }; 1111 1112 static void ppc4xx_gpt_cb (void *opaque) 1113 { 1114 ppc4xx_gpt_t *gpt; 1115 1116 gpt = opaque; 1117 ppc4xx_gpt_set_irqs(gpt); 1118 ppc4xx_gpt_set_outputs(gpt); 1119 ppc4xx_gpt_compute_timer(gpt); 1120 } 1121 1122 static void ppc4xx_gpt_reset (void *opaque) 1123 { 1124 ppc4xx_gpt_t *gpt; 1125 int i; 1126 1127 gpt = opaque; 1128 timer_del(gpt->timer); 1129 gpt->oe = 0x00000000; 1130 gpt->ol = 0x00000000; 1131 gpt->im = 0x00000000; 1132 gpt->is = 0x00000000; 1133 gpt->ie = 0x00000000; 1134 for (i = 0; i < 5; i++) { 1135 gpt->comp[i] = 0x00000000; 1136 gpt->mask[i] = 0x00000000; 1137 } 1138 } 1139 1140 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1141 { 1142 ppc4xx_gpt_t *gpt; 1143 int i; 1144 1145 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1146 for (i = 0; i < 5; i++) { 1147 gpt->irqs[i] = irqs[i]; 1148 } 1149 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1150 #ifdef DEBUG_GPT 1151 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base); 1152 #endif 1153 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1154 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1155 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1156 } 1157 1158 /*****************************************************************************/ 1159 /* PowerPC 405EP */ 1160 /* CPU control */ 1161 enum { 1162 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1163 PPC405EP_CPC0_BOOT = 0x0F1, 1164 PPC405EP_CPC0_EPCTL = 0x0F3, 1165 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1166 PPC405EP_CPC0_UCR = 0x0F5, 1167 PPC405EP_CPC0_SRR = 0x0F6, 1168 PPC405EP_CPC0_JTAGID = 0x0F7, 1169 PPC405EP_CPC0_PCI = 0x0F9, 1170 #if 0 1171 PPC405EP_CPC0_ER = xxx, 1172 PPC405EP_CPC0_FR = xxx, 1173 PPC405EP_CPC0_SR = xxx, 1174 #endif 1175 }; 1176 1177 enum { 1178 PPC405EP_CPU_CLK = 0, 1179 PPC405EP_PLB_CLK = 1, 1180 PPC405EP_OPB_CLK = 2, 1181 PPC405EP_EBC_CLK = 3, 1182 PPC405EP_MAL_CLK = 4, 1183 PPC405EP_PCI_CLK = 5, 1184 PPC405EP_UART0_CLK = 6, 1185 PPC405EP_UART1_CLK = 7, 1186 PPC405EP_CLK_NB = 8, 1187 }; 1188 1189 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1190 struct ppc405ep_cpc_t { 1191 uint32_t sysclk; 1192 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1193 uint32_t boot; 1194 uint32_t epctl; 1195 uint32_t pllmr[2]; 1196 uint32_t ucr; 1197 uint32_t srr; 1198 uint32_t jtagid; 1199 uint32_t pci; 1200 /* Clock and power management */ 1201 uint32_t er; 1202 uint32_t fr; 1203 uint32_t sr; 1204 }; 1205 1206 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1207 { 1208 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1209 uint32_t UART0_clk, UART1_clk; 1210 uint64_t VCO_out, PLL_out; 1211 int M, D; 1212 1213 VCO_out = 0; 1214 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1215 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1216 #ifdef DEBUG_CLOCKS_LL 1217 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M); 1218 #endif 1219 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1220 #ifdef DEBUG_CLOCKS_LL 1221 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D); 1222 #endif 1223 VCO_out = (uint64_t)cpc->sysclk * M * D; 1224 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1225 /* Error - unlock the PLL */ 1226 printf("VCO out of range %" PRIu64 "\n", VCO_out); 1227 #if 0 1228 cpc->pllmr[1] &= ~0x80000000; 1229 goto pll_bypass; 1230 #endif 1231 } 1232 PLL_out = VCO_out / D; 1233 /* Pretend the PLL is locked */ 1234 cpc->boot |= 0x00000001; 1235 } else { 1236 #if 0 1237 pll_bypass: 1238 #endif 1239 PLL_out = cpc->sysclk; 1240 if (cpc->pllmr[1] & 0x40000000) { 1241 /* Pretend the PLL is not locked */ 1242 cpc->boot &= ~0x00000001; 1243 } 1244 } 1245 /* Now, compute all other clocks */ 1246 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1247 #ifdef DEBUG_CLOCKS_LL 1248 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D); 1249 #endif 1250 CPU_clk = PLL_out / D; 1251 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1252 #ifdef DEBUG_CLOCKS_LL 1253 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D); 1254 #endif 1255 PLB_clk = CPU_clk / D; 1256 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1257 #ifdef DEBUG_CLOCKS_LL 1258 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D); 1259 #endif 1260 OPB_clk = PLB_clk / D; 1261 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1262 #ifdef DEBUG_CLOCKS_LL 1263 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D); 1264 #endif 1265 EBC_clk = PLB_clk / D; 1266 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1267 #ifdef DEBUG_CLOCKS_LL 1268 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D); 1269 #endif 1270 MAL_clk = PLB_clk / D; 1271 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1272 #ifdef DEBUG_CLOCKS_LL 1273 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D); 1274 #endif 1275 PCI_clk = PLB_clk / D; 1276 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1277 #ifdef DEBUG_CLOCKS_LL 1278 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D); 1279 #endif 1280 UART0_clk = PLL_out / D; 1281 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1282 #ifdef DEBUG_CLOCKS_LL 1283 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D); 1284 #endif 1285 UART1_clk = PLL_out / D; 1286 #ifdef DEBUG_CLOCKS 1287 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1288 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out); 1289 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1290 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1291 " UART1 %" PRIu32 "\n", 1292 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1293 UART0_clk, UART1_clk); 1294 #endif 1295 /* Setup CPU clocks */ 1296 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1297 /* Setup PLB clock */ 1298 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1299 /* Setup OPB clock */ 1300 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1301 /* Setup external clock */ 1302 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1303 /* Setup MAL clock */ 1304 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1305 /* Setup PCI clock */ 1306 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1307 /* Setup UART0 clock */ 1308 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1309 /* Setup UART1 clock */ 1310 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1311 } 1312 1313 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1314 { 1315 ppc405ep_cpc_t *cpc; 1316 uint32_t ret; 1317 1318 cpc = opaque; 1319 switch (dcrn) { 1320 case PPC405EP_CPC0_BOOT: 1321 ret = cpc->boot; 1322 break; 1323 case PPC405EP_CPC0_EPCTL: 1324 ret = cpc->epctl; 1325 break; 1326 case PPC405EP_CPC0_PLLMR0: 1327 ret = cpc->pllmr[0]; 1328 break; 1329 case PPC405EP_CPC0_PLLMR1: 1330 ret = cpc->pllmr[1]; 1331 break; 1332 case PPC405EP_CPC0_UCR: 1333 ret = cpc->ucr; 1334 break; 1335 case PPC405EP_CPC0_SRR: 1336 ret = cpc->srr; 1337 break; 1338 case PPC405EP_CPC0_JTAGID: 1339 ret = cpc->jtagid; 1340 break; 1341 case PPC405EP_CPC0_PCI: 1342 ret = cpc->pci; 1343 break; 1344 default: 1345 /* Avoid gcc warning */ 1346 ret = 0; 1347 break; 1348 } 1349 1350 return ret; 1351 } 1352 1353 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1354 { 1355 ppc405ep_cpc_t *cpc; 1356 1357 cpc = opaque; 1358 switch (dcrn) { 1359 case PPC405EP_CPC0_BOOT: 1360 /* Read-only register */ 1361 break; 1362 case PPC405EP_CPC0_EPCTL: 1363 /* Don't care for now */ 1364 cpc->epctl = val & 0xC00000F3; 1365 break; 1366 case PPC405EP_CPC0_PLLMR0: 1367 cpc->pllmr[0] = val & 0x00633333; 1368 ppc405ep_compute_clocks(cpc); 1369 break; 1370 case PPC405EP_CPC0_PLLMR1: 1371 cpc->pllmr[1] = val & 0xC0F73FFF; 1372 ppc405ep_compute_clocks(cpc); 1373 break; 1374 case PPC405EP_CPC0_UCR: 1375 /* UART control - don't care for now */ 1376 cpc->ucr = val & 0x003F7F7F; 1377 break; 1378 case PPC405EP_CPC0_SRR: 1379 cpc->srr = val; 1380 break; 1381 case PPC405EP_CPC0_JTAGID: 1382 /* Read-only */ 1383 break; 1384 case PPC405EP_CPC0_PCI: 1385 cpc->pci = val; 1386 break; 1387 } 1388 } 1389 1390 static void ppc405ep_cpc_reset (void *opaque) 1391 { 1392 ppc405ep_cpc_t *cpc = opaque; 1393 1394 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1395 cpc->epctl = 0x00000000; 1396 cpc->pllmr[0] = 0x00011010; 1397 cpc->pllmr[1] = 0x40000000; 1398 cpc->ucr = 0x00000000; 1399 cpc->srr = 0x00040000; 1400 cpc->pci = 0x00000000; 1401 cpc->er = 0x00000000; 1402 cpc->fr = 0x00000000; 1403 cpc->sr = 0x00000000; 1404 ppc405ep_compute_clocks(cpc); 1405 } 1406 1407 /* XXX: sysclk should be between 25 and 100 MHz */ 1408 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1409 uint32_t sysclk) 1410 { 1411 ppc405ep_cpc_t *cpc; 1412 1413 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1414 memcpy(cpc->clk_setup, clk_setup, 1415 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1416 cpc->jtagid = 0x20267049; 1417 cpc->sysclk = sysclk; 1418 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1419 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1420 &dcr_read_epcpc, &dcr_write_epcpc); 1421 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1422 &dcr_read_epcpc, &dcr_write_epcpc); 1423 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1424 &dcr_read_epcpc, &dcr_write_epcpc); 1425 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1426 &dcr_read_epcpc, &dcr_write_epcpc); 1427 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1428 &dcr_read_epcpc, &dcr_write_epcpc); 1429 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1430 &dcr_read_epcpc, &dcr_write_epcpc); 1431 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1432 &dcr_read_epcpc, &dcr_write_epcpc); 1433 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1434 &dcr_read_epcpc, &dcr_write_epcpc); 1435 #if 0 1436 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1437 &dcr_read_epcpc, &dcr_write_epcpc); 1438 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1439 &dcr_read_epcpc, &dcr_write_epcpc); 1440 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1441 &dcr_read_epcpc, &dcr_write_epcpc); 1442 #endif 1443 } 1444 1445 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem, 1446 MemoryRegion ram_memories[2], 1447 hwaddr ram_bases[2], 1448 hwaddr ram_sizes[2], 1449 uint32_t sysclk, qemu_irq **picp, 1450 int do_init) 1451 { 1452 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1453 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1454 PowerPCCPU *cpu; 1455 CPUPPCState *env; 1456 qemu_irq *pic, *irqs; 1457 1458 memset(clk_setup, 0, sizeof(clk_setup)); 1459 /* init CPUs */ 1460 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1461 &clk_setup[PPC405EP_CPU_CLK], 1462 &tlb_clk_setup, sysclk); 1463 env = &cpu->env; 1464 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1465 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1466 /* Internal devices init */ 1467 /* Memory mapped devices registers */ 1468 /* PLB arbitrer */ 1469 ppc4xx_plb_init(env); 1470 /* PLB to OPB bridge */ 1471 ppc4xx_pob_init(env); 1472 /* OBP arbitrer */ 1473 ppc4xx_opba_init(0xef600600); 1474 /* Initialize timers */ 1475 ppc_booke_timers_init(cpu, sysclk, 0); 1476 /* Universal interrupt controller */ 1477 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB); 1478 irqs[PPCUIC_OUTPUT_INT] = 1479 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; 1480 irqs[PPCUIC_OUTPUT_CINT] = 1481 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; 1482 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); 1483 *picp = pic; 1484 /* SDRAM controller */ 1485 /* XXX 405EP has no ECC interrupt */ 1486 ppc4xx_sdram_init(env, pic[17], 2, ram_memories, 1487 ram_bases, ram_sizes, do_init); 1488 /* External bus controller */ 1489 ppc405_ebc_init(env); 1490 /* DMA controller */ 1491 dma_irqs[0] = pic[5]; 1492 dma_irqs[1] = pic[6]; 1493 dma_irqs[2] = pic[7]; 1494 dma_irqs[3] = pic[8]; 1495 ppc405_dma_init(env, dma_irqs); 1496 /* IIC controller */ 1497 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, pic[2]); 1498 /* GPIO */ 1499 ppc405_gpio_init(0xef600700); 1500 /* Serial ports */ 1501 if (serial_hd(0) != NULL) { 1502 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], 1503 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1504 DEVICE_BIG_ENDIAN); 1505 } 1506 if (serial_hd(1) != NULL) { 1507 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], 1508 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1509 DEVICE_BIG_ENDIAN); 1510 } 1511 /* OCM */ 1512 ppc405_ocm_init(env); 1513 /* GPT */ 1514 gpt_irqs[0] = pic[19]; 1515 gpt_irqs[1] = pic[20]; 1516 gpt_irqs[2] = pic[21]; 1517 gpt_irqs[3] = pic[22]; 1518 gpt_irqs[4] = pic[23]; 1519 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1520 /* PCI */ 1521 /* Uses pic[3], pic[16], pic[18] */ 1522 /* MAL */ 1523 mal_irqs[0] = pic[11]; 1524 mal_irqs[1] = pic[12]; 1525 mal_irqs[2] = pic[13]; 1526 mal_irqs[3] = pic[14]; 1527 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1528 /* Ethernet */ 1529 /* Uses pic[9], pic[15], pic[17] */ 1530 /* CPU control */ 1531 ppc405ep_cpc_init(env, clk_setup, sysclk); 1532 1533 return env; 1534 } 1535