1 /* 2 * QEMU PowerPC 405 embedded processors emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/log.h" 29 #include "cpu.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/i2c/ppc4xx_i2c.h" 32 #include "hw/irq.h" 33 #include "ppc405.h" 34 #include "hw/char/serial.h" 35 #include "qemu/timer.h" 36 #include "sysemu/reset.h" 37 #include "sysemu/sysemu.h" 38 #include "exec/address-spaces.h" 39 #include "hw/intc/ppc-uic.h" 40 #include "hw/qdev-properties.h" 41 #include "qapi/error.h" 42 #include "trace.h" 43 44 static void ppc405_set_default_bootinfo(ppc4xx_bd_info_t *bd, 45 ram_addr_t ram_size) 46 { 47 memset(bd, 0, sizeof(*bd)); 48 49 bd->bi_memstart = PPC405EP_SDRAM_BASE; 50 bd->bi_memsize = ram_size; 51 bd->bi_sramstart = PPC405EP_SRAM_BASE; 52 bd->bi_sramsize = PPC405EP_SRAM_SIZE; 53 bd->bi_bootflags = 0; 54 bd->bi_intfreq = 133333333; 55 bd->bi_busfreq = 33333333; 56 bd->bi_baudrate = 115200; 57 bd->bi_s_version[0] = 'Q'; 58 bd->bi_s_version[1] = 'M'; 59 bd->bi_s_version[2] = 'U'; 60 bd->bi_s_version[3] = '\0'; 61 bd->bi_r_version[0] = 'Q'; 62 bd->bi_r_version[1] = 'E'; 63 bd->bi_r_version[2] = 'M'; 64 bd->bi_r_version[3] = 'U'; 65 bd->bi_r_version[4] = '\0'; 66 bd->bi_procfreq = 133333333; 67 bd->bi_plb_busfreq = 33333333; 68 bd->bi_pci_busfreq = 33333333; 69 bd->bi_opbfreq = 33333333; 70 } 71 72 static ram_addr_t __ppc405_set_bootinfo(CPUPPCState *env, ppc4xx_bd_info_t *bd) 73 { 74 CPUState *cs = env_cpu(env); 75 ram_addr_t bdloc; 76 int i, n; 77 78 /* We put the bd structure at the top of memory */ 79 if (bd->bi_memsize >= 0x01000000UL) 80 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); 81 else 82 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); 83 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart); 84 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize); 85 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart); 86 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize); 87 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset); 88 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart); 89 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize); 90 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags); 91 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr); 92 for (i = 0; i < 6; i++) { 93 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]); 94 } 95 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed); 96 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq); 97 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq); 98 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate); 99 for (i = 0; i < 4; i++) { 100 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]); 101 } 102 for (i = 0; i < 32; i++) { 103 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]); 104 } 105 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq); 106 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq); 107 for (i = 0; i < 6; i++) { 108 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); 109 } 110 n = 0x6A; 111 for (i = 0; i < 6; i++) { 112 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]); 113 } 114 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq); 115 n += 4; 116 for (i = 0; i < 2; i++) { 117 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]); 118 n += 4; 119 } 120 121 return bdloc; 122 } 123 124 ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size) 125 { 126 ppc4xx_bd_info_t bd; 127 128 memset(&bd, 0, sizeof(bd)); 129 130 ppc405_set_default_bootinfo(&bd, ram_size); 131 132 return __ppc405_set_bootinfo(env, &bd); 133 } 134 135 /*****************************************************************************/ 136 /* Shared peripherals */ 137 138 /*****************************************************************************/ 139 /* Peripheral local bus arbitrer */ 140 enum { 141 PLB3A0_ACR = 0x077, 142 PLB4A0_ACR = 0x081, 143 PLB0_BESR = 0x084, 144 PLB0_BEAR = 0x086, 145 PLB0_ACR = 0x087, 146 PLB4A1_ACR = 0x089, 147 }; 148 149 typedef struct ppc4xx_plb_t ppc4xx_plb_t; 150 struct ppc4xx_plb_t { 151 uint32_t acr; 152 uint32_t bear; 153 uint32_t besr; 154 }; 155 156 static uint32_t dcr_read_plb (void *opaque, int dcrn) 157 { 158 ppc4xx_plb_t *plb; 159 uint32_t ret; 160 161 plb = opaque; 162 switch (dcrn) { 163 case PLB0_ACR: 164 ret = plb->acr; 165 break; 166 case PLB0_BEAR: 167 ret = plb->bear; 168 break; 169 case PLB0_BESR: 170 ret = plb->besr; 171 break; 172 default: 173 /* Avoid gcc warning */ 174 ret = 0; 175 break; 176 } 177 178 return ret; 179 } 180 181 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val) 182 { 183 ppc4xx_plb_t *plb; 184 185 plb = opaque; 186 switch (dcrn) { 187 case PLB0_ACR: 188 /* We don't care about the actual parameters written as 189 * we don't manage any priorities on the bus 190 */ 191 plb->acr = val & 0xF8000000; 192 break; 193 case PLB0_BEAR: 194 /* Read only */ 195 break; 196 case PLB0_BESR: 197 /* Write-clear */ 198 plb->besr &= ~val; 199 break; 200 } 201 } 202 203 static void ppc4xx_plb_reset (void *opaque) 204 { 205 ppc4xx_plb_t *plb; 206 207 plb = opaque; 208 plb->acr = 0x00000000; 209 plb->bear = 0x00000000; 210 plb->besr = 0x00000000; 211 } 212 213 void ppc4xx_plb_init(CPUPPCState *env) 214 { 215 ppc4xx_plb_t *plb; 216 217 plb = g_malloc0(sizeof(ppc4xx_plb_t)); 218 ppc_dcr_register(env, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 219 ppc_dcr_register(env, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 220 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 221 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 222 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 223 ppc_dcr_register(env, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 224 qemu_register_reset(ppc4xx_plb_reset, plb); 225 } 226 227 /*****************************************************************************/ 228 /* PLB to OPB bridge */ 229 enum { 230 POB0_BESR0 = 0x0A0, 231 POB0_BESR1 = 0x0A2, 232 POB0_BEAR = 0x0A4, 233 }; 234 235 typedef struct ppc4xx_pob_t ppc4xx_pob_t; 236 struct ppc4xx_pob_t { 237 uint32_t bear; 238 uint32_t besr0; 239 uint32_t besr1; 240 }; 241 242 static uint32_t dcr_read_pob (void *opaque, int dcrn) 243 { 244 ppc4xx_pob_t *pob; 245 uint32_t ret; 246 247 pob = opaque; 248 switch (dcrn) { 249 case POB0_BEAR: 250 ret = pob->bear; 251 break; 252 case POB0_BESR0: 253 ret = pob->besr0; 254 break; 255 case POB0_BESR1: 256 ret = pob->besr1; 257 break; 258 default: 259 /* Avoid gcc warning */ 260 ret = 0; 261 break; 262 } 263 264 return ret; 265 } 266 267 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val) 268 { 269 ppc4xx_pob_t *pob; 270 271 pob = opaque; 272 switch (dcrn) { 273 case POB0_BEAR: 274 /* Read only */ 275 break; 276 case POB0_BESR0: 277 /* Write-clear */ 278 pob->besr0 &= ~val; 279 break; 280 case POB0_BESR1: 281 /* Write-clear */ 282 pob->besr1 &= ~val; 283 break; 284 } 285 } 286 287 static void ppc4xx_pob_reset (void *opaque) 288 { 289 ppc4xx_pob_t *pob; 290 291 pob = opaque; 292 /* No error */ 293 pob->bear = 0x00000000; 294 pob->besr0 = 0x0000000; 295 pob->besr1 = 0x0000000; 296 } 297 298 static void ppc4xx_pob_init(CPUPPCState *env) 299 { 300 ppc4xx_pob_t *pob; 301 302 pob = g_malloc0(sizeof(ppc4xx_pob_t)); 303 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob); 304 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob); 305 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob); 306 qemu_register_reset(ppc4xx_pob_reset, pob); 307 } 308 309 /*****************************************************************************/ 310 /* OPB arbitrer */ 311 typedef struct ppc4xx_opba_t ppc4xx_opba_t; 312 struct ppc4xx_opba_t { 313 MemoryRegion io; 314 uint8_t cr; 315 uint8_t pr; 316 }; 317 318 static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size) 319 { 320 ppc4xx_opba_t *opba = opaque; 321 uint32_t ret; 322 323 switch (addr) { 324 case 0x00: 325 ret = opba->cr; 326 break; 327 case 0x01: 328 ret = opba->pr; 329 break; 330 default: 331 ret = 0x00; 332 break; 333 } 334 335 trace_opba_readb(addr, ret); 336 return ret; 337 } 338 339 static void opba_writeb(void *opaque, hwaddr addr, uint64_t value, 340 unsigned size) 341 { 342 ppc4xx_opba_t *opba = opaque; 343 344 trace_opba_writeb(addr, value); 345 346 switch (addr) { 347 case 0x00: 348 opba->cr = value & 0xF8; 349 break; 350 case 0x01: 351 opba->pr = value & 0xFF; 352 break; 353 default: 354 break; 355 } 356 } 357 static const MemoryRegionOps opba_ops = { 358 .read = opba_readb, 359 .write = opba_writeb, 360 .impl.min_access_size = 1, 361 .impl.max_access_size = 1, 362 .valid.min_access_size = 1, 363 .valid.max_access_size = 4, 364 .endianness = DEVICE_BIG_ENDIAN, 365 }; 366 367 static void ppc4xx_opba_reset (void *opaque) 368 { 369 ppc4xx_opba_t *opba; 370 371 opba = opaque; 372 opba->cr = 0x00; /* No dynamic priorities - park disabled */ 373 opba->pr = 0x11; 374 } 375 376 static void ppc4xx_opba_init(hwaddr base) 377 { 378 ppc4xx_opba_t *opba; 379 380 trace_opba_init(base); 381 382 opba = g_malloc0(sizeof(ppc4xx_opba_t)); 383 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002); 384 memory_region_add_subregion(get_system_memory(), base, &opba->io); 385 qemu_register_reset(ppc4xx_opba_reset, opba); 386 } 387 388 /*****************************************************************************/ 389 /* Code decompression controller */ 390 /* XXX: TODO */ 391 392 /*****************************************************************************/ 393 /* Peripheral controller */ 394 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t; 395 struct ppc4xx_ebc_t { 396 uint32_t addr; 397 uint32_t bcr[8]; 398 uint32_t bap[8]; 399 uint32_t bear; 400 uint32_t besr0; 401 uint32_t besr1; 402 uint32_t cfg; 403 }; 404 405 enum { 406 EBC0_CFGADDR = 0x012, 407 EBC0_CFGDATA = 0x013, 408 }; 409 410 static uint32_t dcr_read_ebc (void *opaque, int dcrn) 411 { 412 ppc4xx_ebc_t *ebc; 413 uint32_t ret; 414 415 ebc = opaque; 416 switch (dcrn) { 417 case EBC0_CFGADDR: 418 ret = ebc->addr; 419 break; 420 case EBC0_CFGDATA: 421 switch (ebc->addr) { 422 case 0x00: /* B0CR */ 423 ret = ebc->bcr[0]; 424 break; 425 case 0x01: /* B1CR */ 426 ret = ebc->bcr[1]; 427 break; 428 case 0x02: /* B2CR */ 429 ret = ebc->bcr[2]; 430 break; 431 case 0x03: /* B3CR */ 432 ret = ebc->bcr[3]; 433 break; 434 case 0x04: /* B4CR */ 435 ret = ebc->bcr[4]; 436 break; 437 case 0x05: /* B5CR */ 438 ret = ebc->bcr[5]; 439 break; 440 case 0x06: /* B6CR */ 441 ret = ebc->bcr[6]; 442 break; 443 case 0x07: /* B7CR */ 444 ret = ebc->bcr[7]; 445 break; 446 case 0x10: /* B0AP */ 447 ret = ebc->bap[0]; 448 break; 449 case 0x11: /* B1AP */ 450 ret = ebc->bap[1]; 451 break; 452 case 0x12: /* B2AP */ 453 ret = ebc->bap[2]; 454 break; 455 case 0x13: /* B3AP */ 456 ret = ebc->bap[3]; 457 break; 458 case 0x14: /* B4AP */ 459 ret = ebc->bap[4]; 460 break; 461 case 0x15: /* B5AP */ 462 ret = ebc->bap[5]; 463 break; 464 case 0x16: /* B6AP */ 465 ret = ebc->bap[6]; 466 break; 467 case 0x17: /* B7AP */ 468 ret = ebc->bap[7]; 469 break; 470 case 0x20: /* BEAR */ 471 ret = ebc->bear; 472 break; 473 case 0x21: /* BESR0 */ 474 ret = ebc->besr0; 475 break; 476 case 0x22: /* BESR1 */ 477 ret = ebc->besr1; 478 break; 479 case 0x23: /* CFG */ 480 ret = ebc->cfg; 481 break; 482 default: 483 ret = 0x00000000; 484 break; 485 } 486 break; 487 default: 488 ret = 0x00000000; 489 break; 490 } 491 492 return ret; 493 } 494 495 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val) 496 { 497 ppc4xx_ebc_t *ebc; 498 499 ebc = opaque; 500 switch (dcrn) { 501 case EBC0_CFGADDR: 502 ebc->addr = val; 503 break; 504 case EBC0_CFGDATA: 505 switch (ebc->addr) { 506 case 0x00: /* B0CR */ 507 break; 508 case 0x01: /* B1CR */ 509 break; 510 case 0x02: /* B2CR */ 511 break; 512 case 0x03: /* B3CR */ 513 break; 514 case 0x04: /* B4CR */ 515 break; 516 case 0x05: /* B5CR */ 517 break; 518 case 0x06: /* B6CR */ 519 break; 520 case 0x07: /* B7CR */ 521 break; 522 case 0x10: /* B0AP */ 523 break; 524 case 0x11: /* B1AP */ 525 break; 526 case 0x12: /* B2AP */ 527 break; 528 case 0x13: /* B3AP */ 529 break; 530 case 0x14: /* B4AP */ 531 break; 532 case 0x15: /* B5AP */ 533 break; 534 case 0x16: /* B6AP */ 535 break; 536 case 0x17: /* B7AP */ 537 break; 538 case 0x20: /* BEAR */ 539 break; 540 case 0x21: /* BESR0 */ 541 break; 542 case 0x22: /* BESR1 */ 543 break; 544 case 0x23: /* CFG */ 545 break; 546 default: 547 break; 548 } 549 break; 550 default: 551 break; 552 } 553 } 554 555 static void ebc_reset (void *opaque) 556 { 557 ppc4xx_ebc_t *ebc; 558 int i; 559 560 ebc = opaque; 561 ebc->addr = 0x00000000; 562 ebc->bap[0] = 0x7F8FFE80; 563 ebc->bcr[0] = 0xFFE28000; 564 for (i = 0; i < 8; i++) { 565 ebc->bap[i] = 0x00000000; 566 ebc->bcr[i] = 0x00000000; 567 } 568 ebc->besr0 = 0x00000000; 569 ebc->besr1 = 0x00000000; 570 ebc->cfg = 0x80400000; 571 } 572 573 void ppc405_ebc_init(CPUPPCState *env) 574 { 575 ppc4xx_ebc_t *ebc; 576 577 ebc = g_malloc0(sizeof(ppc4xx_ebc_t)); 578 qemu_register_reset(&ebc_reset, ebc); 579 ppc_dcr_register(env, EBC0_CFGADDR, 580 ebc, &dcr_read_ebc, &dcr_write_ebc); 581 ppc_dcr_register(env, EBC0_CFGDATA, 582 ebc, &dcr_read_ebc, &dcr_write_ebc); 583 } 584 585 /*****************************************************************************/ 586 /* DMA controller */ 587 enum { 588 DMA0_CR0 = 0x100, 589 DMA0_CT0 = 0x101, 590 DMA0_DA0 = 0x102, 591 DMA0_SA0 = 0x103, 592 DMA0_SG0 = 0x104, 593 DMA0_CR1 = 0x108, 594 DMA0_CT1 = 0x109, 595 DMA0_DA1 = 0x10A, 596 DMA0_SA1 = 0x10B, 597 DMA0_SG1 = 0x10C, 598 DMA0_CR2 = 0x110, 599 DMA0_CT2 = 0x111, 600 DMA0_DA2 = 0x112, 601 DMA0_SA2 = 0x113, 602 DMA0_SG2 = 0x114, 603 DMA0_CR3 = 0x118, 604 DMA0_CT3 = 0x119, 605 DMA0_DA3 = 0x11A, 606 DMA0_SA3 = 0x11B, 607 DMA0_SG3 = 0x11C, 608 DMA0_SR = 0x120, 609 DMA0_SGC = 0x123, 610 DMA0_SLP = 0x125, 611 DMA0_POL = 0x126, 612 }; 613 614 typedef struct ppc405_dma_t ppc405_dma_t; 615 struct ppc405_dma_t { 616 qemu_irq irqs[4]; 617 uint32_t cr[4]; 618 uint32_t ct[4]; 619 uint32_t da[4]; 620 uint32_t sa[4]; 621 uint32_t sg[4]; 622 uint32_t sr; 623 uint32_t sgc; 624 uint32_t slp; 625 uint32_t pol; 626 }; 627 628 static uint32_t dcr_read_dma (void *opaque, int dcrn) 629 { 630 return 0; 631 } 632 633 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val) 634 { 635 } 636 637 static void ppc405_dma_reset (void *opaque) 638 { 639 ppc405_dma_t *dma; 640 int i; 641 642 dma = opaque; 643 for (i = 0; i < 4; i++) { 644 dma->cr[i] = 0x00000000; 645 dma->ct[i] = 0x00000000; 646 dma->da[i] = 0x00000000; 647 dma->sa[i] = 0x00000000; 648 dma->sg[i] = 0x00000000; 649 } 650 dma->sr = 0x00000000; 651 dma->sgc = 0x00000000; 652 dma->slp = 0x7C000000; 653 dma->pol = 0x00000000; 654 } 655 656 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4]) 657 { 658 ppc405_dma_t *dma; 659 660 dma = g_malloc0(sizeof(ppc405_dma_t)); 661 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq)); 662 qemu_register_reset(&ppc405_dma_reset, dma); 663 ppc_dcr_register(env, DMA0_CR0, 664 dma, &dcr_read_dma, &dcr_write_dma); 665 ppc_dcr_register(env, DMA0_CT0, 666 dma, &dcr_read_dma, &dcr_write_dma); 667 ppc_dcr_register(env, DMA0_DA0, 668 dma, &dcr_read_dma, &dcr_write_dma); 669 ppc_dcr_register(env, DMA0_SA0, 670 dma, &dcr_read_dma, &dcr_write_dma); 671 ppc_dcr_register(env, DMA0_SG0, 672 dma, &dcr_read_dma, &dcr_write_dma); 673 ppc_dcr_register(env, DMA0_CR1, 674 dma, &dcr_read_dma, &dcr_write_dma); 675 ppc_dcr_register(env, DMA0_CT1, 676 dma, &dcr_read_dma, &dcr_write_dma); 677 ppc_dcr_register(env, DMA0_DA1, 678 dma, &dcr_read_dma, &dcr_write_dma); 679 ppc_dcr_register(env, DMA0_SA1, 680 dma, &dcr_read_dma, &dcr_write_dma); 681 ppc_dcr_register(env, DMA0_SG1, 682 dma, &dcr_read_dma, &dcr_write_dma); 683 ppc_dcr_register(env, DMA0_CR2, 684 dma, &dcr_read_dma, &dcr_write_dma); 685 ppc_dcr_register(env, DMA0_CT2, 686 dma, &dcr_read_dma, &dcr_write_dma); 687 ppc_dcr_register(env, DMA0_DA2, 688 dma, &dcr_read_dma, &dcr_write_dma); 689 ppc_dcr_register(env, DMA0_SA2, 690 dma, &dcr_read_dma, &dcr_write_dma); 691 ppc_dcr_register(env, DMA0_SG2, 692 dma, &dcr_read_dma, &dcr_write_dma); 693 ppc_dcr_register(env, DMA0_CR3, 694 dma, &dcr_read_dma, &dcr_write_dma); 695 ppc_dcr_register(env, DMA0_CT3, 696 dma, &dcr_read_dma, &dcr_write_dma); 697 ppc_dcr_register(env, DMA0_DA3, 698 dma, &dcr_read_dma, &dcr_write_dma); 699 ppc_dcr_register(env, DMA0_SA3, 700 dma, &dcr_read_dma, &dcr_write_dma); 701 ppc_dcr_register(env, DMA0_SG3, 702 dma, &dcr_read_dma, &dcr_write_dma); 703 ppc_dcr_register(env, DMA0_SR, 704 dma, &dcr_read_dma, &dcr_write_dma); 705 ppc_dcr_register(env, DMA0_SGC, 706 dma, &dcr_read_dma, &dcr_write_dma); 707 ppc_dcr_register(env, DMA0_SLP, 708 dma, &dcr_read_dma, &dcr_write_dma); 709 ppc_dcr_register(env, DMA0_POL, 710 dma, &dcr_read_dma, &dcr_write_dma); 711 } 712 713 /*****************************************************************************/ 714 /* GPIO */ 715 typedef struct ppc405_gpio_t ppc405_gpio_t; 716 struct ppc405_gpio_t { 717 MemoryRegion io; 718 uint32_t or; 719 uint32_t tcr; 720 uint32_t osrh; 721 uint32_t osrl; 722 uint32_t tsrh; 723 uint32_t tsrl; 724 uint32_t odr; 725 uint32_t ir; 726 uint32_t rr1; 727 uint32_t isr1h; 728 uint32_t isr1l; 729 }; 730 731 static uint64_t ppc405_gpio_read(void *opaque, hwaddr addr, unsigned size) 732 { 733 trace_ppc405_gpio_read(addr, size); 734 return 0; 735 } 736 737 static void ppc405_gpio_write(void *opaque, hwaddr addr, uint64_t value, 738 unsigned size) 739 { 740 trace_ppc405_gpio_write(addr, size, value); 741 } 742 743 static const MemoryRegionOps ppc405_gpio_ops = { 744 .read = ppc405_gpio_read, 745 .write = ppc405_gpio_write, 746 .endianness = DEVICE_NATIVE_ENDIAN, 747 }; 748 749 static void ppc405_gpio_reset (void *opaque) 750 { 751 } 752 753 static void ppc405_gpio_init(hwaddr base) 754 { 755 ppc405_gpio_t *gpio; 756 757 trace_ppc405_gpio_init(base); 758 759 gpio = g_malloc0(sizeof(ppc405_gpio_t)); 760 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038); 761 memory_region_add_subregion(get_system_memory(), base, &gpio->io); 762 qemu_register_reset(&ppc405_gpio_reset, gpio); 763 } 764 765 /*****************************************************************************/ 766 /* On Chip Memory */ 767 enum { 768 OCM0_ISARC = 0x018, 769 OCM0_ISACNTL = 0x019, 770 OCM0_DSARC = 0x01A, 771 OCM0_DSACNTL = 0x01B, 772 }; 773 774 typedef struct ppc405_ocm_t ppc405_ocm_t; 775 struct ppc405_ocm_t { 776 MemoryRegion ram; 777 MemoryRegion isarc_ram; 778 MemoryRegion dsarc_ram; 779 uint32_t isarc; 780 uint32_t isacntl; 781 uint32_t dsarc; 782 uint32_t dsacntl; 783 }; 784 785 static void ocm_update_mappings (ppc405_ocm_t *ocm, 786 uint32_t isarc, uint32_t isacntl, 787 uint32_t dsarc, uint32_t dsacntl) 788 { 789 trace_ocm_update_mappings(isarc, isacntl, dsarc, dsacntl, ocm->isarc, 790 ocm->isacntl, ocm->dsarc, ocm->dsacntl); 791 792 if (ocm->isarc != isarc || 793 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 794 if (ocm->isacntl & 0x80000000) { 795 /* Unmap previously assigned memory region */ 796 trace_ocm_unmap("ISA", ocm->isarc); 797 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram); 798 } 799 if (isacntl & 0x80000000) { 800 /* Map new instruction memory region */ 801 trace_ocm_map("ISA", isarc); 802 memory_region_add_subregion(get_system_memory(), isarc, 803 &ocm->isarc_ram); 804 } 805 } 806 if (ocm->dsarc != dsarc || 807 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 808 if (ocm->dsacntl & 0x80000000) { 809 /* Beware not to unmap the region we just mapped */ 810 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) { 811 /* Unmap previously assigned memory region */ 812 trace_ocm_unmap("DSA", ocm->dsarc); 813 memory_region_del_subregion(get_system_memory(), 814 &ocm->dsarc_ram); 815 } 816 } 817 if (dsacntl & 0x80000000) { 818 /* Beware not to remap the region we just mapped */ 819 if (!(isacntl & 0x80000000) || dsarc != isarc) { 820 /* Map new data memory region */ 821 trace_ocm_map("DSA", dsarc); 822 memory_region_add_subregion(get_system_memory(), dsarc, 823 &ocm->dsarc_ram); 824 } 825 } 826 } 827 } 828 829 static uint32_t dcr_read_ocm (void *opaque, int dcrn) 830 { 831 ppc405_ocm_t *ocm; 832 uint32_t ret; 833 834 ocm = opaque; 835 switch (dcrn) { 836 case OCM0_ISARC: 837 ret = ocm->isarc; 838 break; 839 case OCM0_ISACNTL: 840 ret = ocm->isacntl; 841 break; 842 case OCM0_DSARC: 843 ret = ocm->dsarc; 844 break; 845 case OCM0_DSACNTL: 846 ret = ocm->dsacntl; 847 break; 848 default: 849 ret = 0; 850 break; 851 } 852 853 return ret; 854 } 855 856 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val) 857 { 858 ppc405_ocm_t *ocm; 859 uint32_t isarc, dsarc, isacntl, dsacntl; 860 861 ocm = opaque; 862 isarc = ocm->isarc; 863 dsarc = ocm->dsarc; 864 isacntl = ocm->isacntl; 865 dsacntl = ocm->dsacntl; 866 switch (dcrn) { 867 case OCM0_ISARC: 868 isarc = val & 0xFC000000; 869 break; 870 case OCM0_ISACNTL: 871 isacntl = val & 0xC0000000; 872 break; 873 case OCM0_DSARC: 874 isarc = val & 0xFC000000; 875 break; 876 case OCM0_DSACNTL: 877 isacntl = val & 0xC0000000; 878 break; 879 } 880 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 881 ocm->isarc = isarc; 882 ocm->dsarc = dsarc; 883 ocm->isacntl = isacntl; 884 ocm->dsacntl = dsacntl; 885 } 886 887 static void ocm_reset (void *opaque) 888 { 889 ppc405_ocm_t *ocm; 890 uint32_t isarc, dsarc, isacntl, dsacntl; 891 892 ocm = opaque; 893 isarc = 0x00000000; 894 isacntl = 0x00000000; 895 dsarc = 0x00000000; 896 dsacntl = 0x00000000; 897 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl); 898 ocm->isarc = isarc; 899 ocm->dsarc = dsarc; 900 ocm->isacntl = isacntl; 901 ocm->dsacntl = dsacntl; 902 } 903 904 static void ppc405_ocm_init(CPUPPCState *env) 905 { 906 ppc405_ocm_t *ocm; 907 908 ocm = g_malloc0(sizeof(ppc405_ocm_t)); 909 /* XXX: Size is 4096 or 0x04000000 */ 910 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4 * KiB, 911 &error_fatal); 912 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", 913 &ocm->isarc_ram, 0, 4 * KiB); 914 qemu_register_reset(&ocm_reset, ocm); 915 ppc_dcr_register(env, OCM0_ISARC, 916 ocm, &dcr_read_ocm, &dcr_write_ocm); 917 ppc_dcr_register(env, OCM0_ISACNTL, 918 ocm, &dcr_read_ocm, &dcr_write_ocm); 919 ppc_dcr_register(env, OCM0_DSARC, 920 ocm, &dcr_read_ocm, &dcr_write_ocm); 921 ppc_dcr_register(env, OCM0_DSACNTL, 922 ocm, &dcr_read_ocm, &dcr_write_ocm); 923 } 924 925 /*****************************************************************************/ 926 /* General purpose timers */ 927 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t; 928 struct ppc4xx_gpt_t { 929 MemoryRegion iomem; 930 int64_t tb_offset; 931 uint32_t tb_freq; 932 QEMUTimer *timer; 933 qemu_irq irqs[5]; 934 uint32_t oe; 935 uint32_t ol; 936 uint32_t im; 937 uint32_t is; 938 uint32_t ie; 939 uint32_t comp[5]; 940 uint32_t mask[5]; 941 }; 942 943 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n) 944 { 945 /* XXX: TODO */ 946 return 0; 947 } 948 949 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level) 950 { 951 /* XXX: TODO */ 952 } 953 954 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt) 955 { 956 uint32_t mask; 957 int i; 958 959 mask = 0x80000000; 960 for (i = 0; i < 5; i++) { 961 if (gpt->oe & mask) { 962 /* Output is enabled */ 963 if (ppc4xx_gpt_compare(gpt, i)) { 964 /* Comparison is OK */ 965 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask); 966 } else { 967 /* Comparison is KO */ 968 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1); 969 } 970 } 971 mask = mask >> 1; 972 } 973 } 974 975 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) 976 { 977 uint32_t mask; 978 int i; 979 980 mask = 0x00008000; 981 for (i = 0; i < 5; i++) { 982 if (gpt->is & gpt->im & mask) 983 qemu_irq_raise(gpt->irqs[i]); 984 else 985 qemu_irq_lower(gpt->irqs[i]); 986 mask = mask >> 1; 987 } 988 } 989 990 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) 991 { 992 /* XXX: TODO */ 993 } 994 995 static uint64_t ppc4xx_gpt_read(void *opaque, hwaddr addr, unsigned size) 996 { 997 ppc4xx_gpt_t *gpt = opaque; 998 uint32_t ret; 999 int idx; 1000 1001 trace_ppc4xx_gpt_read(addr, size); 1002 1003 switch (addr) { 1004 case 0x00: 1005 /* Time base counter */ 1006 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset, 1007 gpt->tb_freq, NANOSECONDS_PER_SECOND); 1008 break; 1009 case 0x10: 1010 /* Output enable */ 1011 ret = gpt->oe; 1012 break; 1013 case 0x14: 1014 /* Output level */ 1015 ret = gpt->ol; 1016 break; 1017 case 0x18: 1018 /* Interrupt mask */ 1019 ret = gpt->im; 1020 break; 1021 case 0x1C: 1022 case 0x20: 1023 /* Interrupt status */ 1024 ret = gpt->is; 1025 break; 1026 case 0x24: 1027 /* Interrupt enable */ 1028 ret = gpt->ie; 1029 break; 1030 case 0x80 ... 0x90: 1031 /* Compare timer */ 1032 idx = (addr - 0x80) >> 2; 1033 ret = gpt->comp[idx]; 1034 break; 1035 case 0xC0 ... 0xD0: 1036 /* Compare mask */ 1037 idx = (addr - 0xC0) >> 2; 1038 ret = gpt->mask[idx]; 1039 break; 1040 default: 1041 ret = -1; 1042 break; 1043 } 1044 1045 return ret; 1046 } 1047 1048 static void ppc4xx_gpt_write(void *opaque, hwaddr addr, uint64_t value, 1049 unsigned size) 1050 { 1051 ppc4xx_gpt_t *gpt = opaque; 1052 int idx; 1053 1054 trace_ppc4xx_gpt_write(addr, size, value); 1055 1056 switch (addr) { 1057 case 0x00: 1058 /* Time base counter */ 1059 gpt->tb_offset = muldiv64(value, NANOSECONDS_PER_SECOND, gpt->tb_freq) 1060 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1061 ppc4xx_gpt_compute_timer(gpt); 1062 break; 1063 case 0x10: 1064 /* Output enable */ 1065 gpt->oe = value & 0xF8000000; 1066 ppc4xx_gpt_set_outputs(gpt); 1067 break; 1068 case 0x14: 1069 /* Output level */ 1070 gpt->ol = value & 0xF8000000; 1071 ppc4xx_gpt_set_outputs(gpt); 1072 break; 1073 case 0x18: 1074 /* Interrupt mask */ 1075 gpt->im = value & 0x0000F800; 1076 break; 1077 case 0x1C: 1078 /* Interrupt status set */ 1079 gpt->is |= value & 0x0000F800; 1080 ppc4xx_gpt_set_irqs(gpt); 1081 break; 1082 case 0x20: 1083 /* Interrupt status clear */ 1084 gpt->is &= ~(value & 0x0000F800); 1085 ppc4xx_gpt_set_irqs(gpt); 1086 break; 1087 case 0x24: 1088 /* Interrupt enable */ 1089 gpt->ie = value & 0x0000F800; 1090 ppc4xx_gpt_set_irqs(gpt); 1091 break; 1092 case 0x80 ... 0x90: 1093 /* Compare timer */ 1094 idx = (addr - 0x80) >> 2; 1095 gpt->comp[idx] = value & 0xF8000000; 1096 ppc4xx_gpt_compute_timer(gpt); 1097 break; 1098 case 0xC0 ... 0xD0: 1099 /* Compare mask */ 1100 idx = (addr - 0xC0) >> 2; 1101 gpt->mask[idx] = value & 0xF8000000; 1102 ppc4xx_gpt_compute_timer(gpt); 1103 break; 1104 } 1105 } 1106 1107 static const MemoryRegionOps gpt_ops = { 1108 .read = ppc4xx_gpt_read, 1109 .write = ppc4xx_gpt_write, 1110 .valid.min_access_size = 4, 1111 .valid.max_access_size = 4, 1112 .endianness = DEVICE_NATIVE_ENDIAN, 1113 }; 1114 1115 static void ppc4xx_gpt_cb (void *opaque) 1116 { 1117 ppc4xx_gpt_t *gpt; 1118 1119 gpt = opaque; 1120 ppc4xx_gpt_set_irqs(gpt); 1121 ppc4xx_gpt_set_outputs(gpt); 1122 ppc4xx_gpt_compute_timer(gpt); 1123 } 1124 1125 static void ppc4xx_gpt_reset (void *opaque) 1126 { 1127 ppc4xx_gpt_t *gpt; 1128 int i; 1129 1130 gpt = opaque; 1131 timer_del(gpt->timer); 1132 gpt->oe = 0x00000000; 1133 gpt->ol = 0x00000000; 1134 gpt->im = 0x00000000; 1135 gpt->is = 0x00000000; 1136 gpt->ie = 0x00000000; 1137 for (i = 0; i < 5; i++) { 1138 gpt->comp[i] = 0x00000000; 1139 gpt->mask[i] = 0x00000000; 1140 } 1141 } 1142 1143 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5]) 1144 { 1145 ppc4xx_gpt_t *gpt; 1146 int i; 1147 1148 trace_ppc4xx_gpt_init(base); 1149 1150 gpt = g_malloc0(sizeof(ppc4xx_gpt_t)); 1151 for (i = 0; i < 5; i++) { 1152 gpt->irqs[i] = irqs[i]; 1153 } 1154 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt); 1155 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4); 1156 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem); 1157 qemu_register_reset(ppc4xx_gpt_reset, gpt); 1158 } 1159 1160 /*****************************************************************************/ 1161 /* PowerPC 405EP */ 1162 /* CPU control */ 1163 enum { 1164 PPC405EP_CPC0_PLLMR0 = 0x0F0, 1165 PPC405EP_CPC0_BOOT = 0x0F1, 1166 PPC405EP_CPC0_EPCTL = 0x0F3, 1167 PPC405EP_CPC0_PLLMR1 = 0x0F4, 1168 PPC405EP_CPC0_UCR = 0x0F5, 1169 PPC405EP_CPC0_SRR = 0x0F6, 1170 PPC405EP_CPC0_JTAGID = 0x0F7, 1171 PPC405EP_CPC0_PCI = 0x0F9, 1172 #if 0 1173 PPC405EP_CPC0_ER = xxx, 1174 PPC405EP_CPC0_FR = xxx, 1175 PPC405EP_CPC0_SR = xxx, 1176 #endif 1177 }; 1178 1179 enum { 1180 PPC405EP_CPU_CLK = 0, 1181 PPC405EP_PLB_CLK = 1, 1182 PPC405EP_OPB_CLK = 2, 1183 PPC405EP_EBC_CLK = 3, 1184 PPC405EP_MAL_CLK = 4, 1185 PPC405EP_PCI_CLK = 5, 1186 PPC405EP_UART0_CLK = 6, 1187 PPC405EP_UART1_CLK = 7, 1188 PPC405EP_CLK_NB = 8, 1189 }; 1190 1191 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t; 1192 struct ppc405ep_cpc_t { 1193 uint32_t sysclk; 1194 clk_setup_t clk_setup[PPC405EP_CLK_NB]; 1195 uint32_t boot; 1196 uint32_t epctl; 1197 uint32_t pllmr[2]; 1198 uint32_t ucr; 1199 uint32_t srr; 1200 uint32_t jtagid; 1201 uint32_t pci; 1202 /* Clock and power management */ 1203 uint32_t er; 1204 uint32_t fr; 1205 uint32_t sr; 1206 }; 1207 1208 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc) 1209 { 1210 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk; 1211 uint32_t UART0_clk, UART1_clk; 1212 uint64_t VCO_out, PLL_out; 1213 int M, D; 1214 1215 VCO_out = 0; 1216 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) { 1217 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */ 1218 trace_ppc405ep_clocks_compute("FBMUL", (cpc->pllmr[1] >> 20) & 0xF, M); 1219 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */ 1220 trace_ppc405ep_clocks_compute("FWDA", (cpc->pllmr[1] >> 16) & 0x7, D); 1221 VCO_out = (uint64_t)cpc->sysclk * M * D; 1222 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) { 1223 /* Error - unlock the PLL */ 1224 qemu_log_mask(LOG_GUEST_ERROR, "VCO out of range %" PRIu64 "\n", 1225 VCO_out); 1226 #if 0 1227 cpc->pllmr[1] &= ~0x80000000; 1228 goto pll_bypass; 1229 #endif 1230 } 1231 PLL_out = VCO_out / D; 1232 /* Pretend the PLL is locked */ 1233 cpc->boot |= 0x00000001; 1234 } else { 1235 #if 0 1236 pll_bypass: 1237 #endif 1238 PLL_out = cpc->sysclk; 1239 if (cpc->pllmr[1] & 0x40000000) { 1240 /* Pretend the PLL is not locked */ 1241 cpc->boot &= ~0x00000001; 1242 } 1243 } 1244 /* Now, compute all other clocks */ 1245 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */ 1246 trace_ppc405ep_clocks_compute("CCDV", (cpc->pllmr[0] >> 20) & 0x3, D); 1247 CPU_clk = PLL_out / D; 1248 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */ 1249 trace_ppc405ep_clocks_compute("CBDV", (cpc->pllmr[0] >> 16) & 0x3, D); 1250 PLB_clk = CPU_clk / D; 1251 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */ 1252 trace_ppc405ep_clocks_compute("OPDV", (cpc->pllmr[0] >> 12) & 0x3, D); 1253 OPB_clk = PLB_clk / D; 1254 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */ 1255 trace_ppc405ep_clocks_compute("EPDV", (cpc->pllmr[0] >> 8) & 0x3, D); 1256 EBC_clk = PLB_clk / D; 1257 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */ 1258 trace_ppc405ep_clocks_compute("MPDV", (cpc->pllmr[0] >> 4) & 0x3, D); 1259 MAL_clk = PLB_clk / D; 1260 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */ 1261 trace_ppc405ep_clocks_compute("PPDV", cpc->pllmr[0] & 0x3, D); 1262 PCI_clk = PLB_clk / D; 1263 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */ 1264 trace_ppc405ep_clocks_compute("U0DIV", cpc->ucr & 0x7F, D); 1265 UART0_clk = PLL_out / D; 1266 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */ 1267 trace_ppc405ep_clocks_compute("U1DIV", (cpc->ucr >> 8) & 0x7F, D); 1268 UART1_clk = PLL_out / D; 1269 1270 if (trace_event_get_state_backends(TRACE_PPC405EP_CLOCKS_SETUP)) { 1271 g_autofree char *trace = g_strdup_printf( 1272 "Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64 1273 " PLL out %" PRIu64 " Hz\n" 1274 "CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32 1275 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32 1276 " UART1 %" PRIu32 "\n", 1277 cpc->sysclk, VCO_out, PLL_out, 1278 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk, 1279 UART0_clk, UART1_clk); 1280 trace_ppc405ep_clocks_setup(trace); 1281 } 1282 1283 /* Setup CPU clocks */ 1284 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk); 1285 /* Setup PLB clock */ 1286 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk); 1287 /* Setup OPB clock */ 1288 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk); 1289 /* Setup external clock */ 1290 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk); 1291 /* Setup MAL clock */ 1292 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk); 1293 /* Setup PCI clock */ 1294 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk); 1295 /* Setup UART0 clock */ 1296 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk); 1297 /* Setup UART1 clock */ 1298 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk); 1299 } 1300 1301 static uint32_t dcr_read_epcpc (void *opaque, int dcrn) 1302 { 1303 ppc405ep_cpc_t *cpc; 1304 uint32_t ret; 1305 1306 cpc = opaque; 1307 switch (dcrn) { 1308 case PPC405EP_CPC0_BOOT: 1309 ret = cpc->boot; 1310 break; 1311 case PPC405EP_CPC0_EPCTL: 1312 ret = cpc->epctl; 1313 break; 1314 case PPC405EP_CPC0_PLLMR0: 1315 ret = cpc->pllmr[0]; 1316 break; 1317 case PPC405EP_CPC0_PLLMR1: 1318 ret = cpc->pllmr[1]; 1319 break; 1320 case PPC405EP_CPC0_UCR: 1321 ret = cpc->ucr; 1322 break; 1323 case PPC405EP_CPC0_SRR: 1324 ret = cpc->srr; 1325 break; 1326 case PPC405EP_CPC0_JTAGID: 1327 ret = cpc->jtagid; 1328 break; 1329 case PPC405EP_CPC0_PCI: 1330 ret = cpc->pci; 1331 break; 1332 default: 1333 /* Avoid gcc warning */ 1334 ret = 0; 1335 break; 1336 } 1337 1338 return ret; 1339 } 1340 1341 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val) 1342 { 1343 ppc405ep_cpc_t *cpc; 1344 1345 cpc = opaque; 1346 switch (dcrn) { 1347 case PPC405EP_CPC0_BOOT: 1348 /* Read-only register */ 1349 break; 1350 case PPC405EP_CPC0_EPCTL: 1351 /* Don't care for now */ 1352 cpc->epctl = val & 0xC00000F3; 1353 break; 1354 case PPC405EP_CPC0_PLLMR0: 1355 cpc->pllmr[0] = val & 0x00633333; 1356 ppc405ep_compute_clocks(cpc); 1357 break; 1358 case PPC405EP_CPC0_PLLMR1: 1359 cpc->pllmr[1] = val & 0xC0F73FFF; 1360 ppc405ep_compute_clocks(cpc); 1361 break; 1362 case PPC405EP_CPC0_UCR: 1363 /* UART control - don't care for now */ 1364 cpc->ucr = val & 0x003F7F7F; 1365 break; 1366 case PPC405EP_CPC0_SRR: 1367 cpc->srr = val; 1368 break; 1369 case PPC405EP_CPC0_JTAGID: 1370 /* Read-only */ 1371 break; 1372 case PPC405EP_CPC0_PCI: 1373 cpc->pci = val; 1374 break; 1375 } 1376 } 1377 1378 static void ppc405ep_cpc_reset (void *opaque) 1379 { 1380 ppc405ep_cpc_t *cpc = opaque; 1381 1382 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */ 1383 cpc->epctl = 0x00000000; 1384 cpc->pllmr[0] = 0x00011010; 1385 cpc->pllmr[1] = 0x40000000; 1386 cpc->ucr = 0x00000000; 1387 cpc->srr = 0x00040000; 1388 cpc->pci = 0x00000000; 1389 cpc->er = 0x00000000; 1390 cpc->fr = 0x00000000; 1391 cpc->sr = 0x00000000; 1392 ppc405ep_compute_clocks(cpc); 1393 } 1394 1395 /* XXX: sysclk should be between 25 and 100 MHz */ 1396 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8], 1397 uint32_t sysclk) 1398 { 1399 ppc405ep_cpc_t *cpc; 1400 1401 cpc = g_malloc0(sizeof(ppc405ep_cpc_t)); 1402 memcpy(cpc->clk_setup, clk_setup, 1403 PPC405EP_CLK_NB * sizeof(clk_setup_t)); 1404 cpc->jtagid = 0x20267049; 1405 cpc->sysclk = sysclk; 1406 qemu_register_reset(&ppc405ep_cpc_reset, cpc); 1407 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc, 1408 &dcr_read_epcpc, &dcr_write_epcpc); 1409 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc, 1410 &dcr_read_epcpc, &dcr_write_epcpc); 1411 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc, 1412 &dcr_read_epcpc, &dcr_write_epcpc); 1413 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc, 1414 &dcr_read_epcpc, &dcr_write_epcpc); 1415 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc, 1416 &dcr_read_epcpc, &dcr_write_epcpc); 1417 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc, 1418 &dcr_read_epcpc, &dcr_write_epcpc); 1419 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc, 1420 &dcr_read_epcpc, &dcr_write_epcpc); 1421 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc, 1422 &dcr_read_epcpc, &dcr_write_epcpc); 1423 #if 0 1424 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc, 1425 &dcr_read_epcpc, &dcr_write_epcpc); 1426 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc, 1427 &dcr_read_epcpc, &dcr_write_epcpc); 1428 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc, 1429 &dcr_read_epcpc, &dcr_write_epcpc); 1430 #endif 1431 } 1432 1433 PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, 1434 MemoryRegion ram_memories[2], 1435 hwaddr ram_bases[2], 1436 hwaddr ram_sizes[2], 1437 uint32_t sysclk, DeviceState **uicdevp, 1438 int do_init) 1439 { 1440 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; 1441 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; 1442 PowerPCCPU *cpu; 1443 CPUPPCState *env; 1444 DeviceState *uicdev; 1445 SysBusDevice *uicsbd; 1446 1447 memset(clk_setup, 0, sizeof(clk_setup)); 1448 /* init CPUs */ 1449 cpu = ppc4xx_init(POWERPC_CPU_TYPE_NAME("405ep"), 1450 &clk_setup[PPC405EP_CPU_CLK], 1451 &tlb_clk_setup, sysclk); 1452 env = &cpu->env; 1453 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb; 1454 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque; 1455 /* Internal devices init */ 1456 /* Memory mapped devices registers */ 1457 /* PLB arbitrer */ 1458 ppc4xx_plb_init(env); 1459 /* PLB to OPB bridge */ 1460 ppc4xx_pob_init(env); 1461 /* OBP arbitrer */ 1462 ppc4xx_opba_init(0xef600600); 1463 /* Initialize timers */ 1464 ppc_booke_timers_init(cpu, sysclk, 0); 1465 /* Universal interrupt controller */ 1466 uicdev = qdev_new(TYPE_PPC_UIC); 1467 uicsbd = SYS_BUS_DEVICE(uicdev); 1468 1469 object_property_set_link(OBJECT(uicdev), "cpu", OBJECT(cpu), 1470 &error_fatal); 1471 sysbus_realize_and_unref(uicsbd, &error_fatal); 1472 1473 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT, 1474 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]); 1475 sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_CINT, 1476 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]); 1477 1478 *uicdevp = uicdev; 1479 1480 /* SDRAM controller */ 1481 /* XXX 405EP has no ECC interrupt */ 1482 ppc4xx_sdram_init(env, qdev_get_gpio_in(uicdev, 17), 2, ram_memories, 1483 ram_bases, ram_sizes, do_init); 1484 /* External bus controller */ 1485 ppc405_ebc_init(env); 1486 /* DMA controller */ 1487 dma_irqs[0] = qdev_get_gpio_in(uicdev, 5); 1488 dma_irqs[1] = qdev_get_gpio_in(uicdev, 6); 1489 dma_irqs[2] = qdev_get_gpio_in(uicdev, 7); 1490 dma_irqs[3] = qdev_get_gpio_in(uicdev, 8); 1491 ppc405_dma_init(env, dma_irqs); 1492 /* IIC controller */ 1493 sysbus_create_simple(TYPE_PPC4xx_I2C, 0xef600500, 1494 qdev_get_gpio_in(uicdev, 2)); 1495 /* GPIO */ 1496 ppc405_gpio_init(0xef600700); 1497 /* Serial ports */ 1498 if (serial_hd(0) != NULL) { 1499 serial_mm_init(address_space_mem, 0xef600300, 0, 1500 qdev_get_gpio_in(uicdev, 0), 1501 PPC_SERIAL_MM_BAUDBASE, serial_hd(0), 1502 DEVICE_BIG_ENDIAN); 1503 } 1504 if (serial_hd(1) != NULL) { 1505 serial_mm_init(address_space_mem, 0xef600400, 0, 1506 qdev_get_gpio_in(uicdev, 1), 1507 PPC_SERIAL_MM_BAUDBASE, serial_hd(1), 1508 DEVICE_BIG_ENDIAN); 1509 } 1510 /* OCM */ 1511 ppc405_ocm_init(env); 1512 /* GPT */ 1513 gpt_irqs[0] = qdev_get_gpio_in(uicdev, 19); 1514 gpt_irqs[1] = qdev_get_gpio_in(uicdev, 20); 1515 gpt_irqs[2] = qdev_get_gpio_in(uicdev, 21); 1516 gpt_irqs[3] = qdev_get_gpio_in(uicdev, 22); 1517 gpt_irqs[4] = qdev_get_gpio_in(uicdev, 23); 1518 ppc4xx_gpt_init(0xef600000, gpt_irqs); 1519 /* PCI */ 1520 /* Uses UIC IRQs 3, 16, 18 */ 1521 /* MAL */ 1522 mal_irqs[0] = qdev_get_gpio_in(uicdev, 11); 1523 mal_irqs[1] = qdev_get_gpio_in(uicdev, 12); 1524 mal_irqs[2] = qdev_get_gpio_in(uicdev, 13); 1525 mal_irqs[3] = qdev_get_gpio_in(uicdev, 14); 1526 ppc4xx_mal_init(env, 4, 2, mal_irqs); 1527 /* Ethernet */ 1528 /* Uses UIC IRQs 9, 15, 17 */ 1529 /* CPU control */ 1530 ppc405ep_cpc_init(env, clk_setup, sysclk); 1531 1532 return cpu; 1533 } 1534