1 /* 2 * QEMU PowerPC 440 embedded processors emulation 3 * 4 * Copyright (c) 2012 François Revol 5 * Copyright (c) 2016-2018 BALATON Zoltan 6 * 7 * This work is licensed under the GNU GPL license version 2 or later. 8 * 9 */ 10 11 #include "qemu/osdep.h" 12 #include "qemu/units.h" 13 #include "qemu-common.h" 14 #include "qemu/error-report.h" 15 #include "qapi/error.h" 16 #include "qemu/log.h" 17 #include "cpu.h" 18 #include "hw/hw.h" 19 #include "exec/address-spaces.h" 20 #include "exec/memory.h" 21 #include "hw/ppc/ppc.h" 22 #include "hw/pci/pci.h" 23 #include "sysemu/block-backend.h" 24 #include "ppc440.h" 25 26 /*****************************************************************************/ 27 /* L2 Cache as SRAM */ 28 /* FIXME:fix names */ 29 enum { 30 DCR_L2CACHE_BASE = 0x30, 31 DCR_L2CACHE_CFG = DCR_L2CACHE_BASE, 32 DCR_L2CACHE_CMD, 33 DCR_L2CACHE_ADDR, 34 DCR_L2CACHE_DATA, 35 DCR_L2CACHE_STAT, 36 DCR_L2CACHE_CVER, 37 DCR_L2CACHE_SNP0, 38 DCR_L2CACHE_SNP1, 39 DCR_L2CACHE_END = DCR_L2CACHE_SNP1, 40 }; 41 42 /* base is 460ex-specific, cf. U-Boot, ppc4xx-isram.h */ 43 enum { 44 DCR_ISRAM0_BASE = 0x20, 45 DCR_ISRAM0_SB0CR = DCR_ISRAM0_BASE, 46 DCR_ISRAM0_SB1CR, 47 DCR_ISRAM0_SB2CR, 48 DCR_ISRAM0_SB3CR, 49 DCR_ISRAM0_BEAR, 50 DCR_ISRAM0_BESR0, 51 DCR_ISRAM0_BESR1, 52 DCR_ISRAM0_PMEG, 53 DCR_ISRAM0_CID, 54 DCR_ISRAM0_REVID, 55 DCR_ISRAM0_DPC, 56 DCR_ISRAM0_END = DCR_ISRAM0_DPC 57 }; 58 59 enum { 60 DCR_ISRAM1_BASE = 0xb0, 61 DCR_ISRAM1_SB0CR = DCR_ISRAM1_BASE, 62 /* single bank */ 63 DCR_ISRAM1_BEAR = DCR_ISRAM1_BASE + 0x04, 64 DCR_ISRAM1_BESR0, 65 DCR_ISRAM1_BESR1, 66 DCR_ISRAM1_PMEG, 67 DCR_ISRAM1_CID, 68 DCR_ISRAM1_REVID, 69 DCR_ISRAM1_DPC, 70 DCR_ISRAM1_END = DCR_ISRAM1_DPC 71 }; 72 73 typedef struct ppc4xx_l2sram_t { 74 MemoryRegion bank[4]; 75 uint32_t l2cache[8]; 76 uint32_t isram0[11]; 77 } ppc4xx_l2sram_t; 78 79 #ifdef MAP_L2SRAM 80 static void l2sram_update_mappings(ppc4xx_l2sram_t *l2sram, 81 uint32_t isarc, uint32_t isacntl, 82 uint32_t dsarc, uint32_t dsacntl) 83 { 84 if (l2sram->isarc != isarc || 85 (l2sram->isacntl & 0x80000000) != (isacntl & 0x80000000)) { 86 if (l2sram->isacntl & 0x80000000) { 87 /* Unmap previously assigned memory region */ 88 memory_region_del_subregion(get_system_memory(), 89 &l2sram->isarc_ram); 90 } 91 if (isacntl & 0x80000000) { 92 /* Map new instruction memory region */ 93 memory_region_add_subregion(get_system_memory(), isarc, 94 &l2sram->isarc_ram); 95 } 96 } 97 if (l2sram->dsarc != dsarc || 98 (l2sram->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) { 99 if (l2sram->dsacntl & 0x80000000) { 100 /* Beware not to unmap the region we just mapped */ 101 if (!(isacntl & 0x80000000) || l2sram->dsarc != isarc) { 102 /* Unmap previously assigned memory region */ 103 memory_region_del_subregion(get_system_memory(), 104 &l2sram->dsarc_ram); 105 } 106 } 107 if (dsacntl & 0x80000000) { 108 /* Beware not to remap the region we just mapped */ 109 if (!(isacntl & 0x80000000) || dsarc != isarc) { 110 /* Map new data memory region */ 111 memory_region_add_subregion(get_system_memory(), dsarc, 112 &l2sram->dsarc_ram); 113 } 114 } 115 } 116 } 117 #endif 118 119 static uint32_t dcr_read_l2sram(void *opaque, int dcrn) 120 { 121 ppc4xx_l2sram_t *l2sram = opaque; 122 uint32_t ret = 0; 123 124 switch (dcrn) { 125 case DCR_L2CACHE_CFG: 126 case DCR_L2CACHE_CMD: 127 case DCR_L2CACHE_ADDR: 128 case DCR_L2CACHE_DATA: 129 case DCR_L2CACHE_STAT: 130 case DCR_L2CACHE_CVER: 131 case DCR_L2CACHE_SNP0: 132 case DCR_L2CACHE_SNP1: 133 ret = l2sram->l2cache[dcrn - DCR_L2CACHE_BASE]; 134 break; 135 136 case DCR_ISRAM0_SB0CR: 137 case DCR_ISRAM0_SB1CR: 138 case DCR_ISRAM0_SB2CR: 139 case DCR_ISRAM0_SB3CR: 140 case DCR_ISRAM0_BEAR: 141 case DCR_ISRAM0_BESR0: 142 case DCR_ISRAM0_BESR1: 143 case DCR_ISRAM0_PMEG: 144 case DCR_ISRAM0_CID: 145 case DCR_ISRAM0_REVID: 146 case DCR_ISRAM0_DPC: 147 ret = l2sram->isram0[dcrn - DCR_ISRAM0_BASE]; 148 break; 149 150 default: 151 break; 152 } 153 154 return ret; 155 } 156 157 static void dcr_write_l2sram(void *opaque, int dcrn, uint32_t val) 158 { 159 /*ppc4xx_l2sram_t *l2sram = opaque;*/ 160 /* FIXME: Actually handle L2 cache mapping */ 161 162 switch (dcrn) { 163 case DCR_L2CACHE_CFG: 164 case DCR_L2CACHE_CMD: 165 case DCR_L2CACHE_ADDR: 166 case DCR_L2CACHE_DATA: 167 case DCR_L2CACHE_STAT: 168 case DCR_L2CACHE_CVER: 169 case DCR_L2CACHE_SNP0: 170 case DCR_L2CACHE_SNP1: 171 /*l2sram->l2cache[dcrn - DCR_L2CACHE_BASE] = val;*/ 172 break; 173 174 case DCR_ISRAM0_SB0CR: 175 case DCR_ISRAM0_SB1CR: 176 case DCR_ISRAM0_SB2CR: 177 case DCR_ISRAM0_SB3CR: 178 case DCR_ISRAM0_BEAR: 179 case DCR_ISRAM0_BESR0: 180 case DCR_ISRAM0_BESR1: 181 case DCR_ISRAM0_PMEG: 182 case DCR_ISRAM0_CID: 183 case DCR_ISRAM0_REVID: 184 case DCR_ISRAM0_DPC: 185 /*l2sram->isram0[dcrn - DCR_L2CACHE_BASE] = val;*/ 186 break; 187 188 case DCR_ISRAM1_SB0CR: 189 case DCR_ISRAM1_BEAR: 190 case DCR_ISRAM1_BESR0: 191 case DCR_ISRAM1_BESR1: 192 case DCR_ISRAM1_PMEG: 193 case DCR_ISRAM1_CID: 194 case DCR_ISRAM1_REVID: 195 case DCR_ISRAM1_DPC: 196 /*l2sram->isram1[dcrn - DCR_L2CACHE_BASE] = val;*/ 197 break; 198 } 199 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 200 } 201 202 static void l2sram_reset(void *opaque) 203 { 204 ppc4xx_l2sram_t *l2sram = opaque; 205 206 memset(l2sram->l2cache, 0, sizeof(l2sram->l2cache)); 207 l2sram->l2cache[DCR_L2CACHE_STAT - DCR_L2CACHE_BASE] = 0x80000000; 208 memset(l2sram->isram0, 0, sizeof(l2sram->isram0)); 209 /*l2sram_update_mappings(l2sram, isarc, isacntl, dsarc, dsacntl);*/ 210 } 211 212 void ppc4xx_l2sram_init(CPUPPCState *env) 213 { 214 ppc4xx_l2sram_t *l2sram; 215 216 l2sram = g_malloc0(sizeof(*l2sram)); 217 /* XXX: Size is 4*64kB for 460ex, cf. U-Boot, ppc4xx-isram.h */ 218 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", 219 64 * KiB, &error_abort); 220 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", 221 64 * KiB, &error_abort); 222 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", 223 64 * KiB, &error_abort); 224 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", 225 64 * KiB, &error_abort); 226 qemu_register_reset(&l2sram_reset, l2sram); 227 ppc_dcr_register(env, DCR_L2CACHE_CFG, 228 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 229 ppc_dcr_register(env, DCR_L2CACHE_CMD, 230 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 231 ppc_dcr_register(env, DCR_L2CACHE_ADDR, 232 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 233 ppc_dcr_register(env, DCR_L2CACHE_DATA, 234 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 235 ppc_dcr_register(env, DCR_L2CACHE_STAT, 236 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 237 ppc_dcr_register(env, DCR_L2CACHE_CVER, 238 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 239 ppc_dcr_register(env, DCR_L2CACHE_SNP0, 240 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 241 ppc_dcr_register(env, DCR_L2CACHE_SNP1, 242 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 243 244 ppc_dcr_register(env, DCR_ISRAM0_SB0CR, 245 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 246 ppc_dcr_register(env, DCR_ISRAM0_SB1CR, 247 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 248 ppc_dcr_register(env, DCR_ISRAM0_SB2CR, 249 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 250 ppc_dcr_register(env, DCR_ISRAM0_SB3CR, 251 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 252 ppc_dcr_register(env, DCR_ISRAM0_PMEG, 253 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 254 ppc_dcr_register(env, DCR_ISRAM0_DPC, 255 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 256 257 ppc_dcr_register(env, DCR_ISRAM1_SB0CR, 258 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 259 ppc_dcr_register(env, DCR_ISRAM1_PMEG, 260 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 261 ppc_dcr_register(env, DCR_ISRAM1_DPC, 262 l2sram, &dcr_read_l2sram, &dcr_write_l2sram); 263 } 264 265 /*****************************************************************************/ 266 /* Clocking Power on Reset */ 267 enum { 268 CPR0_CFGADDR = 0xC, 269 CPR0_CFGDATA = 0xD, 270 271 CPR0_PLLD = 0x060, 272 CPR0_PLBED = 0x080, 273 CPR0_OPBD = 0x0C0, 274 CPR0_PERD = 0x0E0, 275 CPR0_AHBD = 0x100, 276 }; 277 278 typedef struct ppc4xx_cpr_t { 279 uint32_t addr; 280 } ppc4xx_cpr_t; 281 282 static uint32_t dcr_read_cpr(void *opaque, int dcrn) 283 { 284 ppc4xx_cpr_t *cpr = opaque; 285 uint32_t ret = 0; 286 287 switch (dcrn) { 288 case CPR0_CFGADDR: 289 ret = cpr->addr; 290 break; 291 case CPR0_CFGDATA: 292 switch (cpr->addr) { 293 case CPR0_PLLD: 294 ret = (0xb5 << 24) | (1 << 16) | (9 << 8); 295 break; 296 case CPR0_PLBED: 297 ret = (5 << 24); 298 break; 299 case CPR0_OPBD: 300 ret = (2 << 24); 301 break; 302 case CPR0_PERD: 303 case CPR0_AHBD: 304 ret = (1 << 24); 305 break; 306 default: 307 break; 308 } 309 break; 310 default: 311 break; 312 } 313 314 return ret; 315 } 316 317 static void dcr_write_cpr(void *opaque, int dcrn, uint32_t val) 318 { 319 ppc4xx_cpr_t *cpr = opaque; 320 321 switch (dcrn) { 322 case CPR0_CFGADDR: 323 cpr->addr = val; 324 break; 325 case CPR0_CFGDATA: 326 break; 327 default: 328 break; 329 } 330 } 331 332 static void ppc4xx_cpr_reset(void *opaque) 333 { 334 ppc4xx_cpr_t *cpr = opaque; 335 336 cpr->addr = 0; 337 } 338 339 void ppc4xx_cpr_init(CPUPPCState *env) 340 { 341 ppc4xx_cpr_t *cpr; 342 343 cpr = g_malloc0(sizeof(*cpr)); 344 ppc_dcr_register(env, CPR0_CFGADDR, cpr, &dcr_read_cpr, &dcr_write_cpr); 345 ppc_dcr_register(env, CPR0_CFGDATA, cpr, &dcr_read_cpr, &dcr_write_cpr); 346 qemu_register_reset(ppc4xx_cpr_reset, cpr); 347 } 348 349 /*****************************************************************************/ 350 /* System DCRs */ 351 typedef struct ppc4xx_sdr_t ppc4xx_sdr_t; 352 struct ppc4xx_sdr_t { 353 uint32_t addr; 354 }; 355 356 enum { 357 SDR0_CFGADDR = 0x00e, 358 SDR0_CFGDATA, 359 SDR0_STRP0 = 0x020, 360 SDR0_STRP1, 361 SDR0_102 = 0x66, 362 SDR0_103, 363 SDR0_128 = 0x80, 364 SDR0_ECID3 = 0x083, 365 SDR0_DDR0 = 0x0e1, 366 SDR0_USB0 = 0x320, 367 }; 368 369 enum { 370 PESDR0_LOOP = 0x303, 371 PESDR0_RCSSET, 372 PESDR0_RCSSTS, 373 PESDR0_RSTSTA = 0x310, 374 PESDR1_LOOP = 0x343, 375 PESDR1_RCSSET, 376 PESDR1_RCSSTS, 377 PESDR1_RSTSTA = 0x365, 378 }; 379 380 #define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n)) & 0x03) << 29) 381 #define SDR0_DDR0_DDRM_DDR1 0x20000000 382 #define SDR0_DDR0_DDRM_DDR2 0x40000000 383 384 static uint32_t dcr_read_sdr(void *opaque, int dcrn) 385 { 386 ppc4xx_sdr_t *sdr = opaque; 387 uint32_t ret = 0; 388 389 switch (dcrn) { 390 case SDR0_CFGADDR: 391 ret = sdr->addr; 392 break; 393 case SDR0_CFGDATA: 394 switch (sdr->addr) { 395 case SDR0_STRP0: 396 ret = (0xb5 << 8) | (1 << 4) | 9; 397 break; 398 case SDR0_STRP1: 399 ret = (5 << 29) | (2 << 26) | (1 << 24); 400 break; 401 case SDR0_ECID3: 402 ret = 1 << 20; /* No Security/Kasumi support */ 403 break; 404 case SDR0_DDR0: 405 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 406 break; 407 case PESDR0_RCSSET: 408 case PESDR1_RCSSET: 409 ret = (1 << 24) | (1 << 16); 410 break; 411 case PESDR0_RCSSTS: 412 case PESDR1_RCSSTS: 413 ret = (1 << 16) | (1 << 12); 414 break; 415 case PESDR0_RSTSTA: 416 case PESDR1_RSTSTA: 417 ret = 1; 418 break; 419 case PESDR0_LOOP: 420 case PESDR1_LOOP: 421 ret = 1 << 12; 422 break; 423 default: 424 break; 425 } 426 break; 427 default: 428 break; 429 } 430 431 return ret; 432 } 433 434 static void dcr_write_sdr(void *opaque, int dcrn, uint32_t val) 435 { 436 ppc4xx_sdr_t *sdr = opaque; 437 438 switch (dcrn) { 439 case SDR0_CFGADDR: 440 sdr->addr = val; 441 break; 442 case SDR0_CFGDATA: 443 switch (sdr->addr) { 444 case 0x00: /* B0CR */ 445 break; 446 default: 447 break; 448 } 449 break; 450 default: 451 break; 452 } 453 } 454 455 static void sdr_reset(void *opaque) 456 { 457 ppc4xx_sdr_t *sdr = opaque; 458 459 sdr->addr = 0; 460 } 461 462 void ppc4xx_sdr_init(CPUPPCState *env) 463 { 464 ppc4xx_sdr_t *sdr; 465 466 sdr = g_malloc0(sizeof(*sdr)); 467 qemu_register_reset(&sdr_reset, sdr); 468 ppc_dcr_register(env, SDR0_CFGADDR, 469 sdr, &dcr_read_sdr, &dcr_write_sdr); 470 ppc_dcr_register(env, SDR0_CFGDATA, 471 sdr, &dcr_read_sdr, &dcr_write_sdr); 472 ppc_dcr_register(env, SDR0_102, 473 sdr, &dcr_read_sdr, &dcr_write_sdr); 474 ppc_dcr_register(env, SDR0_103, 475 sdr, &dcr_read_sdr, &dcr_write_sdr); 476 ppc_dcr_register(env, SDR0_128, 477 sdr, &dcr_read_sdr, &dcr_write_sdr); 478 ppc_dcr_register(env, SDR0_USB0, 479 sdr, &dcr_read_sdr, &dcr_write_sdr); 480 } 481 482 /*****************************************************************************/ 483 /* SDRAM controller */ 484 typedef struct ppc4xx_sdram_t { 485 uint32_t addr; 486 int nbanks; 487 MemoryRegion containers[4]; /* used for clipping */ 488 MemoryRegion *ram_memories; 489 hwaddr ram_bases[4]; 490 hwaddr ram_sizes[4]; 491 uint32_t bcr[4]; 492 } ppc4xx_sdram_t; 493 494 enum { 495 SDRAM0_CFGADDR = 0x10, 496 SDRAM0_CFGDATA, 497 SDRAM_R0BAS = 0x40, 498 SDRAM_R1BAS, 499 SDRAM_R2BAS, 500 SDRAM_R3BAS, 501 SDRAM_CONF1HB = 0x45, 502 SDRAM_PLBADDULL = 0x4a, 503 SDRAM_CONF1LL = 0x4b, 504 SDRAM_CONFPATHB = 0x4f, 505 SDRAM_PLBADDUHB = 0x50, 506 }; 507 508 /* XXX: TOFIX: some patches have made this code become inconsistent: 509 * there are type inconsistencies, mixing hwaddr, target_ulong 510 * and uint32_t 511 */ 512 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) 513 { 514 uint32_t bcr; 515 516 switch (ram_size) { 517 case (8 * MiB): 518 bcr = 0xffc0; 519 break; 520 case (16 * MiB): 521 bcr = 0xff80; 522 break; 523 case (32 * MiB): 524 bcr = 0xff00; 525 break; 526 case (64 * MiB): 527 bcr = 0xfe00; 528 break; 529 case (128 * MiB): 530 bcr = 0xfc00; 531 break; 532 case (256 * MiB): 533 bcr = 0xf800; 534 break; 535 case (512 * MiB): 536 bcr = 0xf000; 537 break; 538 case (1 * GiB): 539 bcr = 0xe000; 540 break; 541 default: 542 error_report("invalid RAM size " TARGET_FMT_plx, ram_size); 543 return 0; 544 } 545 bcr |= ram_base & 0xFF800000; 546 bcr |= 1; 547 548 return bcr; 549 } 550 551 static inline hwaddr sdram_base(uint32_t bcr) 552 { 553 return bcr & 0xFF800000; 554 } 555 556 static target_ulong sdram_size(uint32_t bcr) 557 { 558 target_ulong size; 559 int sh; 560 561 sh = 1024 - ((bcr >> 6) & 0x3ff); 562 if (sh == 0) { 563 size = -1; 564 } else { 565 size = 8 * MiB * sh; 566 } 567 568 return size; 569 } 570 571 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, 572 uint32_t *bcrp, uint32_t bcr, int enabled) 573 { 574 unsigned n = bcrp - sdram->bcr; 575 576 if (*bcrp & 1) { 577 /* Unmap RAM */ 578 memory_region_del_subregion(get_system_memory(), 579 &sdram->containers[n]); 580 memory_region_del_subregion(&sdram->containers[n], 581 &sdram->ram_memories[n]); 582 object_unparent(OBJECT(&sdram->containers[n])); 583 } 584 *bcrp = bcr & 0xFFDEE001; 585 if (enabled && (bcr & 1)) { 586 memory_region_init(&sdram->containers[n], NULL, "sdram-containers", 587 sdram_size(bcr)); 588 memory_region_add_subregion(&sdram->containers[n], 0, 589 &sdram->ram_memories[n]); 590 memory_region_add_subregion(get_system_memory(), 591 sdram_base(bcr), 592 &sdram->containers[n]); 593 } 594 } 595 596 static void sdram_map_bcr(ppc4xx_sdram_t *sdram) 597 { 598 int i; 599 600 for (i = 0; i < sdram->nbanks; i++) { 601 if (sdram->ram_sizes[i] != 0) { 602 sdram_set_bcr(sdram, 603 &sdram->bcr[i], 604 sdram_bcr(sdram->ram_bases[i], sdram->ram_sizes[i]), 605 1); 606 } else { 607 sdram_set_bcr(sdram, &sdram->bcr[i], 0, 0); 608 } 609 } 610 } 611 612 static uint32_t dcr_read_sdram(void *opaque, int dcrn) 613 { 614 ppc4xx_sdram_t *sdram = opaque; 615 uint32_t ret = 0; 616 617 switch (dcrn) { 618 case SDRAM_R0BAS: 619 case SDRAM_R1BAS: 620 case SDRAM_R2BAS: 621 case SDRAM_R3BAS: 622 ret = sdram_bcr(sdram->ram_bases[dcrn - SDRAM_R0BAS], 623 sdram->ram_sizes[dcrn - SDRAM_R0BAS]); 624 break; 625 case SDRAM_CONF1HB: 626 case SDRAM_CONF1LL: 627 case SDRAM_CONFPATHB: 628 case SDRAM_PLBADDULL: 629 case SDRAM_PLBADDUHB: 630 break; 631 case SDRAM0_CFGADDR: 632 ret = sdram->addr; 633 break; 634 case SDRAM0_CFGDATA: 635 switch (sdram->addr) { 636 case 0x14: /* SDRAM_MCSTAT (405EX) */ 637 case 0x1F: 638 ret = 0x80000000; 639 break; 640 case 0x21: /* SDRAM_MCOPT2 */ 641 ret = 0x08000000; 642 break; 643 case 0x40: /* SDRAM_MB0CF */ 644 ret = 0x00008001; 645 break; 646 case 0x7A: /* SDRAM_DLCR */ 647 ret = 0x02000000; 648 break; 649 case 0xE1: /* SDR0_DDR0 */ 650 ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1; 651 break; 652 default: 653 break; 654 } 655 break; 656 default: 657 break; 658 } 659 660 return ret; 661 } 662 663 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) 664 { 665 ppc4xx_sdram_t *sdram = opaque; 666 667 switch (dcrn) { 668 case SDRAM_R0BAS: 669 case SDRAM_R1BAS: 670 case SDRAM_R2BAS: 671 case SDRAM_R3BAS: 672 case SDRAM_CONF1HB: 673 case SDRAM_CONF1LL: 674 case SDRAM_CONFPATHB: 675 case SDRAM_PLBADDULL: 676 case SDRAM_PLBADDUHB: 677 break; 678 case SDRAM0_CFGADDR: 679 sdram->addr = val; 680 break; 681 case SDRAM0_CFGDATA: 682 switch (sdram->addr) { 683 case 0x00: /* B0CR */ 684 break; 685 default: 686 break; 687 } 688 break; 689 default: 690 break; 691 } 692 } 693 694 static void sdram_reset(void *opaque) 695 { 696 ppc4xx_sdram_t *sdram = opaque; 697 698 sdram->addr = 0; 699 } 700 701 void ppc440_sdram_init(CPUPPCState *env, int nbanks, 702 MemoryRegion *ram_memories, 703 hwaddr *ram_bases, hwaddr *ram_sizes, 704 int do_init) 705 { 706 ppc4xx_sdram_t *sdram; 707 708 sdram = g_malloc0(sizeof(*sdram)); 709 sdram->nbanks = nbanks; 710 sdram->ram_memories = ram_memories; 711 memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(hwaddr)); 712 memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(hwaddr)); 713 qemu_register_reset(&sdram_reset, sdram); 714 ppc_dcr_register(env, SDRAM0_CFGADDR, 715 sdram, &dcr_read_sdram, &dcr_write_sdram); 716 ppc_dcr_register(env, SDRAM0_CFGDATA, 717 sdram, &dcr_read_sdram, &dcr_write_sdram); 718 if (do_init) { 719 sdram_map_bcr(sdram); 720 } 721 722 ppc_dcr_register(env, SDRAM_R0BAS, 723 sdram, &dcr_read_sdram, &dcr_write_sdram); 724 ppc_dcr_register(env, SDRAM_R1BAS, 725 sdram, &dcr_read_sdram, &dcr_write_sdram); 726 ppc_dcr_register(env, SDRAM_R2BAS, 727 sdram, &dcr_read_sdram, &dcr_write_sdram); 728 ppc_dcr_register(env, SDRAM_R3BAS, 729 sdram, &dcr_read_sdram, &dcr_write_sdram); 730 ppc_dcr_register(env, SDRAM_CONF1HB, 731 sdram, &dcr_read_sdram, &dcr_write_sdram); 732 ppc_dcr_register(env, SDRAM_PLBADDULL, 733 sdram, &dcr_read_sdram, &dcr_write_sdram); 734 ppc_dcr_register(env, SDRAM_CONF1LL, 735 sdram, &dcr_read_sdram, &dcr_write_sdram); 736 ppc_dcr_register(env, SDRAM_CONFPATHB, 737 sdram, &dcr_read_sdram, &dcr_write_sdram); 738 ppc_dcr_register(env, SDRAM_PLBADDUHB, 739 sdram, &dcr_read_sdram, &dcr_write_sdram); 740 } 741 742 /*****************************************************************************/ 743 /* PLB to AHB bridge */ 744 enum { 745 AHB_TOP = 0xA4, 746 AHB_BOT = 0xA5, 747 }; 748 749 typedef struct ppc4xx_ahb_t { 750 uint32_t top; 751 uint32_t bot; 752 } ppc4xx_ahb_t; 753 754 static uint32_t dcr_read_ahb(void *opaque, int dcrn) 755 { 756 ppc4xx_ahb_t *ahb = opaque; 757 uint32_t ret = 0; 758 759 switch (dcrn) { 760 case AHB_TOP: 761 ret = ahb->top; 762 break; 763 case AHB_BOT: 764 ret = ahb->bot; 765 break; 766 default: 767 break; 768 } 769 770 return ret; 771 } 772 773 static void dcr_write_ahb(void *opaque, int dcrn, uint32_t val) 774 { 775 ppc4xx_ahb_t *ahb = opaque; 776 777 switch (dcrn) { 778 case AHB_TOP: 779 ahb->top = val; 780 break; 781 case AHB_BOT: 782 ahb->bot = val; 783 break; 784 } 785 } 786 787 static void ppc4xx_ahb_reset(void *opaque) 788 { 789 ppc4xx_ahb_t *ahb = opaque; 790 791 /* No error */ 792 ahb->top = 0; 793 ahb->bot = 0; 794 } 795 796 void ppc4xx_ahb_init(CPUPPCState *env) 797 { 798 ppc4xx_ahb_t *ahb; 799 800 ahb = g_malloc0(sizeof(*ahb)); 801 ppc_dcr_register(env, AHB_TOP, ahb, &dcr_read_ahb, &dcr_write_ahb); 802 ppc_dcr_register(env, AHB_BOT, ahb, &dcr_read_ahb, &dcr_write_ahb); 803 qemu_register_reset(ppc4xx_ahb_reset, ahb); 804 } 805 806 /*****************************************************************************/ 807 /* DMA controller */ 808 809 #define DMA0_CR_CE (1 << 31) 810 #define DMA0_CR_PW (1 << 26 | 1 << 25) 811 #define DMA0_CR_DAI (1 << 24) 812 #define DMA0_CR_SAI (1 << 23) 813 #define DMA0_CR_DEC (1 << 2) 814 815 enum { 816 DMA0_CR = 0x00, 817 DMA0_CT, 818 DMA0_SAH, 819 DMA0_SAL, 820 DMA0_DAH, 821 DMA0_DAL, 822 DMA0_SGH, 823 DMA0_SGL, 824 825 DMA0_SR = 0x20, 826 DMA0_SGC = 0x23, 827 DMA0_SLP = 0x25, 828 DMA0_POL = 0x26, 829 }; 830 831 typedef struct { 832 uint32_t cr; 833 uint32_t ct; 834 uint64_t sa; 835 uint64_t da; 836 uint64_t sg; 837 } PPC4xxDmaChnl; 838 839 typedef struct { 840 int base; 841 PPC4xxDmaChnl ch[4]; 842 uint32_t sr; 843 } PPC4xxDmaState; 844 845 static uint32_t dcr_read_dma(void *opaque, int dcrn) 846 { 847 PPC4xxDmaState *dma = opaque; 848 uint32_t val = 0; 849 int addr = dcrn - dma->base; 850 int chnl = addr / 8; 851 852 switch (addr) { 853 case 0x00 ... 0x1f: 854 switch (addr % 8) { 855 case DMA0_CR: 856 val = dma->ch[chnl].cr; 857 break; 858 case DMA0_CT: 859 val = dma->ch[chnl].ct; 860 break; 861 case DMA0_SAH: 862 val = dma->ch[chnl].sa >> 32; 863 break; 864 case DMA0_SAL: 865 val = dma->ch[chnl].sa; 866 break; 867 case DMA0_DAH: 868 val = dma->ch[chnl].da >> 32; 869 break; 870 case DMA0_DAL: 871 val = dma->ch[chnl].da; 872 break; 873 case DMA0_SGH: 874 val = dma->ch[chnl].sg >> 32; 875 break; 876 case DMA0_SGL: 877 val = dma->ch[chnl].sg; 878 break; 879 } 880 break; 881 case DMA0_SR: 882 val = dma->sr; 883 break; 884 default: 885 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 886 __func__, dcrn, chnl, addr); 887 } 888 889 return val; 890 } 891 892 static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) 893 { 894 PPC4xxDmaState *dma = opaque; 895 int addr = dcrn - dma->base; 896 int chnl = addr / 8; 897 898 switch (addr) { 899 case 0x00 ... 0x1f: 900 switch (addr % 8) { 901 case DMA0_CR: 902 dma->ch[chnl].cr = val; 903 if (val & DMA0_CR_CE) { 904 int count = dma->ch[chnl].ct & 0xffff; 905 906 if (count) { 907 int width, i, sidx, didx; 908 uint8_t *rptr, *wptr; 909 hwaddr rlen, wlen; 910 911 sidx = didx = 0; 912 width = 1 << ((val & DMA0_CR_PW) >> 25); 913 rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0); 914 wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1); 915 if (rptr && wptr) { 916 if (!(val & DMA0_CR_DEC) && 917 val & DMA0_CR_SAI && val & DMA0_CR_DAI) { 918 /* optimise common case */ 919 memmove(wptr, rptr, count * width); 920 sidx = didx = count * width; 921 } else { 922 /* do it the slow way */ 923 for (sidx = didx = i = 0; i < count; i++) { 924 uint64_t v = ldn_le_p(rptr + sidx, width); 925 stn_le_p(wptr + didx, width, v); 926 if (val & DMA0_CR_SAI) { 927 sidx += width; 928 } 929 if (val & DMA0_CR_DAI) { 930 didx += width; 931 } 932 } 933 } 934 } 935 if (wptr) { 936 cpu_physical_memory_unmap(wptr, wlen, 1, didx); 937 } 938 if (wptr) { 939 cpu_physical_memory_unmap(rptr, rlen, 0, sidx); 940 } 941 } 942 } 943 break; 944 case DMA0_CT: 945 dma->ch[chnl].ct = val; 946 break; 947 case DMA0_SAH: 948 dma->ch[chnl].sa &= 0xffffffffULL; 949 dma->ch[chnl].sa |= (uint64_t)val << 32; 950 break; 951 case DMA0_SAL: 952 dma->ch[chnl].sa &= 0xffffffff00000000ULL; 953 dma->ch[chnl].sa |= val; 954 break; 955 case DMA0_DAH: 956 dma->ch[chnl].da &= 0xffffffffULL; 957 dma->ch[chnl].da |= (uint64_t)val << 32; 958 break; 959 case DMA0_DAL: 960 dma->ch[chnl].da &= 0xffffffff00000000ULL; 961 dma->ch[chnl].da |= val; 962 break; 963 case DMA0_SGH: 964 dma->ch[chnl].sg &= 0xffffffffULL; 965 dma->ch[chnl].sg |= (uint64_t)val << 32; 966 break; 967 case DMA0_SGL: 968 dma->ch[chnl].sg &= 0xffffffff00000000ULL; 969 dma->ch[chnl].sg |= val; 970 break; 971 } 972 break; 973 case DMA0_SR: 974 dma->sr &= ~val; 975 break; 976 default: 977 qemu_log_mask(LOG_UNIMP, "%s: unimplemented register %x (%d, %x)\n", 978 __func__, dcrn, chnl, addr); 979 } 980 } 981 982 static void ppc4xx_dma_reset(void *opaque) 983 { 984 PPC4xxDmaState *dma = opaque; 985 int dma_base = dma->base; 986 987 memset(dma, 0, sizeof(*dma)); 988 dma->base = dma_base; 989 } 990 991 void ppc4xx_dma_init(CPUPPCState *env, int dcr_base) 992 { 993 PPC4xxDmaState *dma; 994 int i; 995 996 dma = g_malloc0(sizeof(*dma)); 997 dma->base = dcr_base; 998 qemu_register_reset(&ppc4xx_dma_reset, dma); 999 for (i = 0; i < 4; i++) { 1000 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CR, 1001 dma, &dcr_read_dma, &dcr_write_dma); 1002 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_CT, 1003 dma, &dcr_read_dma, &dcr_write_dma); 1004 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAH, 1005 dma, &dcr_read_dma, &dcr_write_dma); 1006 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SAL, 1007 dma, &dcr_read_dma, &dcr_write_dma); 1008 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAH, 1009 dma, &dcr_read_dma, &dcr_write_dma); 1010 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_DAL, 1011 dma, &dcr_read_dma, &dcr_write_dma); 1012 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGH, 1013 dma, &dcr_read_dma, &dcr_write_dma); 1014 ppc_dcr_register(env, dcr_base + i * 8 + DMA0_SGL, 1015 dma, &dcr_read_dma, &dcr_write_dma); 1016 } 1017 ppc_dcr_register(env, dcr_base + DMA0_SR, 1018 dma, &dcr_read_dma, &dcr_write_dma); 1019 ppc_dcr_register(env, dcr_base + DMA0_SGC, 1020 dma, &dcr_read_dma, &dcr_write_dma); 1021 ppc_dcr_register(env, dcr_base + DMA0_SLP, 1022 dma, &dcr_read_dma, &dcr_write_dma); 1023 ppc_dcr_register(env, dcr_base + DMA0_POL, 1024 dma, &dcr_read_dma, &dcr_write_dma); 1025 } 1026 1027 /*****************************************************************************/ 1028 /* PCI Express controller */ 1029 /* FIXME: This is not complete and does not work, only implemented partially 1030 * to allow firmware and guests to find an empty bus. Cards should use PCI. 1031 */ 1032 #include "hw/pci/pcie_host.h" 1033 1034 #define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host" 1035 #define PPC460EX_PCIE_HOST(obj) \ 1036 OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST) 1037 1038 typedef struct PPC460EXPCIEState { 1039 PCIExpressHost host; 1040 1041 MemoryRegion iomem; 1042 qemu_irq irq[4]; 1043 int32_t dcrn_base; 1044 1045 uint64_t cfg_base; 1046 uint32_t cfg_mask; 1047 uint64_t msg_base; 1048 uint32_t msg_mask; 1049 uint64_t omr1_base; 1050 uint64_t omr1_mask; 1051 uint64_t omr2_base; 1052 uint64_t omr2_mask; 1053 uint64_t omr3_base; 1054 uint64_t omr3_mask; 1055 uint64_t reg_base; 1056 uint32_t reg_mask; 1057 uint32_t special; 1058 uint32_t cfg; 1059 } PPC460EXPCIEState; 1060 1061 #define DCRN_PCIE0_BASE 0x100 1062 #define DCRN_PCIE1_BASE 0x120 1063 1064 enum { 1065 PEGPL_CFGBAH = 0x0, 1066 PEGPL_CFGBAL, 1067 PEGPL_CFGMSK, 1068 PEGPL_MSGBAH, 1069 PEGPL_MSGBAL, 1070 PEGPL_MSGMSK, 1071 PEGPL_OMR1BAH, 1072 PEGPL_OMR1BAL, 1073 PEGPL_OMR1MSKH, 1074 PEGPL_OMR1MSKL, 1075 PEGPL_OMR2BAH, 1076 PEGPL_OMR2BAL, 1077 PEGPL_OMR2MSKH, 1078 PEGPL_OMR2MSKL, 1079 PEGPL_OMR3BAH, 1080 PEGPL_OMR3BAL, 1081 PEGPL_OMR3MSKH, 1082 PEGPL_OMR3MSKL, 1083 PEGPL_REGBAH, 1084 PEGPL_REGBAL, 1085 PEGPL_REGMSK, 1086 PEGPL_SPECIAL, 1087 PEGPL_CFG, 1088 }; 1089 1090 static uint32_t dcr_read_pcie(void *opaque, int dcrn) 1091 { 1092 PPC460EXPCIEState *state = opaque; 1093 uint32_t ret = 0; 1094 1095 switch (dcrn - state->dcrn_base) { 1096 case PEGPL_CFGBAH: 1097 ret = state->cfg_base >> 32; 1098 break; 1099 case PEGPL_CFGBAL: 1100 ret = state->cfg_base; 1101 break; 1102 case PEGPL_CFGMSK: 1103 ret = state->cfg_mask; 1104 break; 1105 case PEGPL_MSGBAH: 1106 ret = state->msg_base >> 32; 1107 break; 1108 case PEGPL_MSGBAL: 1109 ret = state->msg_base; 1110 break; 1111 case PEGPL_MSGMSK: 1112 ret = state->msg_mask; 1113 break; 1114 case PEGPL_OMR1BAH: 1115 ret = state->omr1_base >> 32; 1116 break; 1117 case PEGPL_OMR1BAL: 1118 ret = state->omr1_base; 1119 break; 1120 case PEGPL_OMR1MSKH: 1121 ret = state->omr1_mask >> 32; 1122 break; 1123 case PEGPL_OMR1MSKL: 1124 ret = state->omr1_mask; 1125 break; 1126 case PEGPL_OMR2BAH: 1127 ret = state->omr2_base >> 32; 1128 break; 1129 case PEGPL_OMR2BAL: 1130 ret = state->omr2_base; 1131 break; 1132 case PEGPL_OMR2MSKH: 1133 ret = state->omr2_mask >> 32; 1134 break; 1135 case PEGPL_OMR2MSKL: 1136 ret = state->omr3_mask; 1137 break; 1138 case PEGPL_OMR3BAH: 1139 ret = state->omr3_base >> 32; 1140 break; 1141 case PEGPL_OMR3BAL: 1142 ret = state->omr3_base; 1143 break; 1144 case PEGPL_OMR3MSKH: 1145 ret = state->omr3_mask >> 32; 1146 break; 1147 case PEGPL_OMR3MSKL: 1148 ret = state->omr3_mask; 1149 break; 1150 case PEGPL_REGBAH: 1151 ret = state->reg_base >> 32; 1152 break; 1153 case PEGPL_REGBAL: 1154 ret = state->reg_base; 1155 break; 1156 case PEGPL_REGMSK: 1157 ret = state->reg_mask; 1158 break; 1159 case PEGPL_SPECIAL: 1160 ret = state->special; 1161 break; 1162 case PEGPL_CFG: 1163 ret = state->cfg; 1164 break; 1165 } 1166 1167 return ret; 1168 } 1169 1170 static void dcr_write_pcie(void *opaque, int dcrn, uint32_t val) 1171 { 1172 PPC460EXPCIEState *s = opaque; 1173 uint64_t size; 1174 1175 switch (dcrn - s->dcrn_base) { 1176 case PEGPL_CFGBAH: 1177 s->cfg_base = ((uint64_t)val << 32) | (s->cfg_base & 0xffffffff); 1178 break; 1179 case PEGPL_CFGBAL: 1180 s->cfg_base = (s->cfg_base & 0xffffffff00000000ULL) | val; 1181 break; 1182 case PEGPL_CFGMSK: 1183 s->cfg_mask = val; 1184 size = ~(val & 0xfffffffe) + 1; 1185 qemu_mutex_lock_iothread(); 1186 pcie_host_mmcfg_update(PCIE_HOST_BRIDGE(s), val & 1, s->cfg_base, size); 1187 qemu_mutex_unlock_iothread(); 1188 break; 1189 case PEGPL_MSGBAH: 1190 s->msg_base = ((uint64_t)val << 32) | (s->msg_base & 0xffffffff); 1191 break; 1192 case PEGPL_MSGBAL: 1193 s->msg_base = (s->msg_base & 0xffffffff00000000ULL) | val; 1194 break; 1195 case PEGPL_MSGMSK: 1196 s->msg_mask = val; 1197 break; 1198 case PEGPL_OMR1BAH: 1199 s->omr1_base = ((uint64_t)val << 32) | (s->omr1_base & 0xffffffff); 1200 break; 1201 case PEGPL_OMR1BAL: 1202 s->omr1_base = (s->omr1_base & 0xffffffff00000000ULL) | val; 1203 break; 1204 case PEGPL_OMR1MSKH: 1205 s->omr1_mask = ((uint64_t)val << 32) | (s->omr1_mask & 0xffffffff); 1206 break; 1207 case PEGPL_OMR1MSKL: 1208 s->omr1_mask = (s->omr1_mask & 0xffffffff00000000ULL) | val; 1209 break; 1210 case PEGPL_OMR2BAH: 1211 s->omr2_base = ((uint64_t)val << 32) | (s->omr2_base & 0xffffffff); 1212 break; 1213 case PEGPL_OMR2BAL: 1214 s->omr2_base = (s->omr2_base & 0xffffffff00000000ULL) | val; 1215 break; 1216 case PEGPL_OMR2MSKH: 1217 s->omr2_mask = ((uint64_t)val << 32) | (s->omr2_mask & 0xffffffff); 1218 break; 1219 case PEGPL_OMR2MSKL: 1220 s->omr2_mask = (s->omr2_mask & 0xffffffff00000000ULL) | val; 1221 break; 1222 case PEGPL_OMR3BAH: 1223 s->omr3_base = ((uint64_t)val << 32) | (s->omr3_base & 0xffffffff); 1224 break; 1225 case PEGPL_OMR3BAL: 1226 s->omr3_base = (s->omr3_base & 0xffffffff00000000ULL) | val; 1227 break; 1228 case PEGPL_OMR3MSKH: 1229 s->omr3_mask = ((uint64_t)val << 32) | (s->omr3_mask & 0xffffffff); 1230 break; 1231 case PEGPL_OMR3MSKL: 1232 s->omr3_mask = (s->omr3_mask & 0xffffffff00000000ULL) | val; 1233 break; 1234 case PEGPL_REGBAH: 1235 s->reg_base = ((uint64_t)val << 32) | (s->reg_base & 0xffffffff); 1236 break; 1237 case PEGPL_REGBAL: 1238 s->reg_base = (s->reg_base & 0xffffffff00000000ULL) | val; 1239 break; 1240 case PEGPL_REGMSK: 1241 s->reg_mask = val; 1242 /* FIXME: how is size encoded? */ 1243 size = (val == 0x7001 ? 4096 : ~(val & 0xfffffffe) + 1); 1244 break; 1245 case PEGPL_SPECIAL: 1246 s->special = val; 1247 break; 1248 case PEGPL_CFG: 1249 s->cfg = val; 1250 break; 1251 } 1252 } 1253 1254 static void ppc460ex_set_irq(void *opaque, int irq_num, int level) 1255 { 1256 PPC460EXPCIEState *s = opaque; 1257 qemu_set_irq(s->irq[irq_num], level); 1258 } 1259 1260 static void ppc460ex_pcie_realize(DeviceState *dev, Error **errp) 1261 { 1262 PPC460EXPCIEState *s = PPC460EX_PCIE_HOST(dev); 1263 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 1264 int i, id; 1265 char buf[16]; 1266 1267 switch (s->dcrn_base) { 1268 case DCRN_PCIE0_BASE: 1269 id = 0; 1270 break; 1271 case DCRN_PCIE1_BASE: 1272 id = 1; 1273 break; 1274 default: 1275 error_setg(errp, "invalid PCIe DCRN base"); 1276 return; 1277 } 1278 snprintf(buf, sizeof(buf), "pcie%d-io", id); 1279 memory_region_init(&s->iomem, OBJECT(s), buf, UINT64_MAX); 1280 for (i = 0; i < 4; i++) { 1281 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); 1282 } 1283 snprintf(buf, sizeof(buf), "pcie.%d", id); 1284 pci->bus = pci_register_root_bus(DEVICE(s), buf, ppc460ex_set_irq, 1285 pci_swizzle_map_irq_fn, s, &s->iomem, 1286 get_system_io(), 0, 4, TYPE_PCIE_BUS); 1287 } 1288 1289 static Property ppc460ex_pcie_props[] = { 1290 DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), 1291 DEFINE_PROP_END_OF_LIST(), 1292 }; 1293 1294 static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) 1295 { 1296 DeviceClass *dc = DEVICE_CLASS(klass); 1297 1298 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1299 dc->realize = ppc460ex_pcie_realize; 1300 dc->props = ppc460ex_pcie_props; 1301 dc->hotpluggable = false; 1302 } 1303 1304 static const TypeInfo ppc460ex_pcie_host_info = { 1305 .name = TYPE_PPC460EX_PCIE_HOST, 1306 .parent = TYPE_PCIE_HOST_BRIDGE, 1307 .instance_size = sizeof(PPC460EXPCIEState), 1308 .class_init = ppc460ex_pcie_class_init, 1309 }; 1310 1311 static void ppc460ex_pcie_register(void) 1312 { 1313 type_register_static(&ppc460ex_pcie_host_info); 1314 } 1315 1316 type_init(ppc460ex_pcie_register) 1317 1318 static void ppc460ex_pcie_register_dcrs(PPC460EXPCIEState *s, CPUPPCState *env) 1319 { 1320 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAH, s, 1321 &dcr_read_pcie, &dcr_write_pcie); 1322 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGBAL, s, 1323 &dcr_read_pcie, &dcr_write_pcie); 1324 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFGMSK, s, 1325 &dcr_read_pcie, &dcr_write_pcie); 1326 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAH, s, 1327 &dcr_read_pcie, &dcr_write_pcie); 1328 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGBAL, s, 1329 &dcr_read_pcie, &dcr_write_pcie); 1330 ppc_dcr_register(env, s->dcrn_base + PEGPL_MSGMSK, s, 1331 &dcr_read_pcie, &dcr_write_pcie); 1332 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAH, s, 1333 &dcr_read_pcie, &dcr_write_pcie); 1334 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1BAL, s, 1335 &dcr_read_pcie, &dcr_write_pcie); 1336 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKH, s, 1337 &dcr_read_pcie, &dcr_write_pcie); 1338 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR1MSKL, s, 1339 &dcr_read_pcie, &dcr_write_pcie); 1340 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAH, s, 1341 &dcr_read_pcie, &dcr_write_pcie); 1342 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2BAL, s, 1343 &dcr_read_pcie, &dcr_write_pcie); 1344 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKH, s, 1345 &dcr_read_pcie, &dcr_write_pcie); 1346 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR2MSKL, s, 1347 &dcr_read_pcie, &dcr_write_pcie); 1348 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAH, s, 1349 &dcr_read_pcie, &dcr_write_pcie); 1350 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3BAL, s, 1351 &dcr_read_pcie, &dcr_write_pcie); 1352 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKH, s, 1353 &dcr_read_pcie, &dcr_write_pcie); 1354 ppc_dcr_register(env, s->dcrn_base + PEGPL_OMR3MSKL, s, 1355 &dcr_read_pcie, &dcr_write_pcie); 1356 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAH, s, 1357 &dcr_read_pcie, &dcr_write_pcie); 1358 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGBAL, s, 1359 &dcr_read_pcie, &dcr_write_pcie); 1360 ppc_dcr_register(env, s->dcrn_base + PEGPL_REGMSK, s, 1361 &dcr_read_pcie, &dcr_write_pcie); 1362 ppc_dcr_register(env, s->dcrn_base + PEGPL_SPECIAL, s, 1363 &dcr_read_pcie, &dcr_write_pcie); 1364 ppc_dcr_register(env, s->dcrn_base + PEGPL_CFG, s, 1365 &dcr_read_pcie, &dcr_write_pcie); 1366 } 1367 1368 void ppc460ex_pcie_init(CPUPPCState *env) 1369 { 1370 DeviceState *dev; 1371 1372 dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); 1373 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE0_BASE); 1374 qdev_init_nofail(dev); 1375 object_property_set_bool(OBJECT(dev), true, "realized", NULL); 1376 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1377 1378 dev = qdev_create(NULL, TYPE_PPC460EX_PCIE_HOST); 1379 qdev_prop_set_int32(dev, "dcrn-base", DCRN_PCIE1_BASE); 1380 qdev_init_nofail(dev); 1381 object_property_set_bool(OBJECT(dev), true, "realized", NULL); 1382 ppc460ex_pcie_register_dcrs(PPC460EX_PCIE_HOST(dev), env); 1383 } 1384