1 /* 2 * QEMU PowerPC 4xx embedded processors shared devices emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "sysemu/reset.h" 28 #include "cpu.h" 29 #include "hw/irq.h" 30 #include "hw/ppc/ppc.h" 31 #include "hw/ppc/ppc4xx.h" 32 #include "hw/qdev-properties.h" 33 #include "qemu/log.h" 34 #include "exec/address-spaces.h" 35 #include "qemu/error-report.h" 36 #include "qapi/error.h" 37 #include "trace.h" 38 39 /*****************************************************************************/ 40 /* SDRAM controller */ 41 typedef struct ppc4xx_sdram_t ppc4xx_sdram_t; 42 struct ppc4xx_sdram_t { 43 uint32_t addr; 44 int nbanks; 45 Ppc4xxSdramBank bank[4]; 46 uint32_t besr0; 47 uint32_t besr1; 48 uint32_t bear; 49 uint32_t cfg; 50 uint32_t status; 51 uint32_t rtr; 52 uint32_t pmit; 53 uint32_t tr; 54 uint32_t ecccfg; 55 uint32_t eccesr; 56 qemu_irq irq; 57 }; 58 59 enum { 60 SDRAM0_CFGADDR = 0x010, 61 SDRAM0_CFGDATA = 0x011, 62 }; 63 64 /* 65 * XXX: TOFIX: some patches have made this code become inconsistent: 66 * there are type inconsistencies, mixing hwaddr, target_ulong 67 * and uint32_t 68 */ 69 static uint32_t sdram_bcr(hwaddr ram_base, hwaddr ram_size) 70 { 71 uint32_t bcr; 72 73 switch (ram_size) { 74 case 4 * MiB: 75 bcr = 0x00000000; 76 break; 77 case 8 * MiB: 78 bcr = 0x00020000; 79 break; 80 case 16 * MiB: 81 bcr = 0x00040000; 82 break; 83 case 32 * MiB: 84 bcr = 0x00060000; 85 break; 86 case 64 * MiB: 87 bcr = 0x00080000; 88 break; 89 case 128 * MiB: 90 bcr = 0x000A0000; 91 break; 92 case 256 * MiB: 93 bcr = 0x000C0000; 94 break; 95 default: 96 qemu_log_mask(LOG_GUEST_ERROR, 97 "%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__, 98 ram_size); 99 return 0x00000000; 100 } 101 bcr |= ram_base & 0xFF800000; 102 bcr |= 1; 103 104 return bcr; 105 } 106 107 static inline hwaddr sdram_base(uint32_t bcr) 108 { 109 return bcr & 0xFF800000; 110 } 111 112 static target_ulong sdram_size(uint32_t bcr) 113 { 114 target_ulong size; 115 int sh; 116 117 sh = (bcr >> 17) & 0x7; 118 if (sh == 7) { 119 size = -1; 120 } else { 121 size = (4 * MiB) << sh; 122 } 123 124 return size; 125 } 126 127 static void sdram_set_bcr(ppc4xx_sdram_t *sdram, int i, 128 uint32_t bcr, int enabled) 129 { 130 if (sdram->bank[i].bcr & 0x00000001) { 131 /* Unmap RAM */ 132 trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), 133 sdram_size(sdram->bank[i].bcr)); 134 memory_region_del_subregion(get_system_memory(), 135 &sdram->bank[i].container); 136 memory_region_del_subregion(&sdram->bank[i].container, 137 &sdram->bank[i].ram); 138 object_unparent(OBJECT(&sdram->bank[i].container)); 139 } 140 sdram->bank[i].bcr = bcr & 0xFFDEE001; 141 if (enabled && (bcr & 0x00000001)) { 142 trace_ppc4xx_sdram_map(sdram_base(bcr), sdram_size(bcr)); 143 memory_region_init(&sdram->bank[i].container, NULL, "sdram-container", 144 sdram_size(bcr)); 145 memory_region_add_subregion(&sdram->bank[i].container, 0, 146 &sdram->bank[i].ram); 147 memory_region_add_subregion(get_system_memory(), 148 sdram_base(bcr), 149 &sdram->bank[i].container); 150 } 151 } 152 153 static void sdram_map_bcr(ppc4xx_sdram_t *sdram) 154 { 155 int i; 156 157 for (i = 0; i < sdram->nbanks; i++) { 158 if (sdram->bank[i].size != 0) { 159 sdram_set_bcr(sdram, i, sdram_bcr(sdram->bank[i].base, 160 sdram->bank[i].size), 1); 161 } else { 162 sdram_set_bcr(sdram, i, 0x00000000, 0); 163 } 164 } 165 } 166 167 static void sdram_unmap_bcr(ppc4xx_sdram_t *sdram) 168 { 169 int i; 170 171 for (i = 0; i < sdram->nbanks; i++) { 172 trace_ppc4xx_sdram_unmap(sdram_base(sdram->bank[i].bcr), 173 sdram_size(sdram->bank[i].bcr)); 174 memory_region_del_subregion(get_system_memory(), 175 &sdram->bank[i].ram); 176 } 177 } 178 179 static uint32_t dcr_read_sdram(void *opaque, int dcrn) 180 { 181 ppc4xx_sdram_t *sdram; 182 uint32_t ret; 183 184 sdram = opaque; 185 switch (dcrn) { 186 case SDRAM0_CFGADDR: 187 ret = sdram->addr; 188 break; 189 case SDRAM0_CFGDATA: 190 switch (sdram->addr) { 191 case 0x00: /* SDRAM_BESR0 */ 192 ret = sdram->besr0; 193 break; 194 case 0x08: /* SDRAM_BESR1 */ 195 ret = sdram->besr1; 196 break; 197 case 0x10: /* SDRAM_BEAR */ 198 ret = sdram->bear; 199 break; 200 case 0x20: /* SDRAM_CFG */ 201 ret = sdram->cfg; 202 break; 203 case 0x24: /* SDRAM_STATUS */ 204 ret = sdram->status; 205 break; 206 case 0x30: /* SDRAM_RTR */ 207 ret = sdram->rtr; 208 break; 209 case 0x34: /* SDRAM_PMIT */ 210 ret = sdram->pmit; 211 break; 212 case 0x40: /* SDRAM_B0CR */ 213 ret = sdram->bank[0].bcr; 214 break; 215 case 0x44: /* SDRAM_B1CR */ 216 ret = sdram->bank[1].bcr; 217 break; 218 case 0x48: /* SDRAM_B2CR */ 219 ret = sdram->bank[2].bcr; 220 break; 221 case 0x4C: /* SDRAM_B3CR */ 222 ret = sdram->bank[3].bcr; 223 break; 224 case 0x80: /* SDRAM_TR */ 225 ret = -1; /* ? */ 226 break; 227 case 0x94: /* SDRAM_ECCCFG */ 228 ret = sdram->ecccfg; 229 break; 230 case 0x98: /* SDRAM_ECCESR */ 231 ret = sdram->eccesr; 232 break; 233 default: /* Error */ 234 ret = -1; 235 break; 236 } 237 break; 238 default: 239 /* Avoid gcc warning */ 240 ret = 0x00000000; 241 break; 242 } 243 244 return ret; 245 } 246 247 static void dcr_write_sdram(void *opaque, int dcrn, uint32_t val) 248 { 249 ppc4xx_sdram_t *sdram; 250 251 sdram = opaque; 252 switch (dcrn) { 253 case SDRAM0_CFGADDR: 254 sdram->addr = val; 255 break; 256 case SDRAM0_CFGDATA: 257 switch (sdram->addr) { 258 case 0x00: /* SDRAM_BESR0 */ 259 sdram->besr0 &= ~val; 260 break; 261 case 0x08: /* SDRAM_BESR1 */ 262 sdram->besr1 &= ~val; 263 break; 264 case 0x10: /* SDRAM_BEAR */ 265 sdram->bear = val; 266 break; 267 case 0x20: /* SDRAM_CFG */ 268 val &= 0xFFE00000; 269 if (!(sdram->cfg & 0x80000000) && (val & 0x80000000)) { 270 trace_ppc4xx_sdram_enable("enable"); 271 /* validate all RAM mappings */ 272 sdram_map_bcr(sdram); 273 sdram->status &= ~0x80000000; 274 } else if ((sdram->cfg & 0x80000000) && !(val & 0x80000000)) { 275 trace_ppc4xx_sdram_enable("disable"); 276 /* invalidate all RAM mappings */ 277 sdram_unmap_bcr(sdram); 278 sdram->status |= 0x80000000; 279 } 280 if (!(sdram->cfg & 0x40000000) && (val & 0x40000000)) { 281 sdram->status |= 0x40000000; 282 } else if ((sdram->cfg & 0x40000000) && !(val & 0x40000000)) { 283 sdram->status &= ~0x40000000; 284 } 285 sdram->cfg = val; 286 break; 287 case 0x24: /* SDRAM_STATUS */ 288 /* Read-only register */ 289 break; 290 case 0x30: /* SDRAM_RTR */ 291 sdram->rtr = val & 0x3FF80000; 292 break; 293 case 0x34: /* SDRAM_PMIT */ 294 sdram->pmit = (val & 0xF8000000) | 0x07C00000; 295 break; 296 case 0x40: /* SDRAM_B0CR */ 297 sdram_set_bcr(sdram, 0, val, sdram->cfg & 0x80000000); 298 break; 299 case 0x44: /* SDRAM_B1CR */ 300 sdram_set_bcr(sdram, 1, val, sdram->cfg & 0x80000000); 301 break; 302 case 0x48: /* SDRAM_B2CR */ 303 sdram_set_bcr(sdram, 2, val, sdram->cfg & 0x80000000); 304 break; 305 case 0x4C: /* SDRAM_B3CR */ 306 sdram_set_bcr(sdram, 3, val, sdram->cfg & 0x80000000); 307 break; 308 case 0x80: /* SDRAM_TR */ 309 sdram->tr = val & 0x018FC01F; 310 break; 311 case 0x94: /* SDRAM_ECCCFG */ 312 sdram->ecccfg = val & 0x00F00000; 313 break; 314 case 0x98: /* SDRAM_ECCESR */ 315 val &= 0xFFF0F000; 316 if (sdram->eccesr == 0 && val != 0) { 317 qemu_irq_raise(sdram->irq); 318 } else if (sdram->eccesr != 0 && val == 0) { 319 qemu_irq_lower(sdram->irq); 320 } 321 sdram->eccesr = val; 322 break; 323 default: /* Error */ 324 break; 325 } 326 break; 327 } 328 } 329 330 static void sdram_reset(void *opaque) 331 { 332 ppc4xx_sdram_t *sdram; 333 334 sdram = opaque; 335 sdram->addr = 0x00000000; 336 sdram->bear = 0x00000000; 337 sdram->besr0 = 0x00000000; /* No error */ 338 sdram->besr1 = 0x00000000; /* No error */ 339 sdram->cfg = 0x00000000; 340 sdram->ecccfg = 0x00000000; /* No ECC */ 341 sdram->eccesr = 0x00000000; /* No error */ 342 sdram->pmit = 0x07C00000; 343 sdram->rtr = 0x05F00000; 344 sdram->tr = 0x00854009; 345 /* We pre-initialize RAM banks */ 346 sdram->status = 0x00000000; 347 sdram->cfg = 0x00800000; 348 } 349 350 void ppc4xx_sdram_init(CPUPPCState *env, qemu_irq irq, int nbanks, 351 MemoryRegion *ram_memories, 352 hwaddr *ram_bases, 353 hwaddr *ram_sizes) 354 { 355 ppc4xx_sdram_t *sdram; 356 int i; 357 358 sdram = g_new0(ppc4xx_sdram_t, 1); 359 sdram->irq = irq; 360 sdram->nbanks = nbanks; 361 for (i = 0; i < nbanks; i++) { 362 sdram->bank[i].ram = ram_memories[i]; 363 sdram->bank[i].base = ram_bases[i]; 364 sdram->bank[i].size = ram_sizes[i]; 365 } 366 qemu_register_reset(&sdram_reset, sdram); 367 ppc_dcr_register(env, SDRAM0_CFGADDR, 368 sdram, &dcr_read_sdram, &dcr_write_sdram); 369 ppc_dcr_register(env, SDRAM0_CFGDATA, 370 sdram, &dcr_read_sdram, &dcr_write_sdram); 371 } 372 373 void ppc4xx_sdram_enable(CPUPPCState *env) 374 { 375 ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x20); 376 ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x80000000); 377 } 378 379 /* 380 * Split RAM between SDRAM banks. 381 * 382 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] 383 * and must be 0-terminated. 384 * 385 * The 4xx SDRAM controller supports a small number of banks, and each bank 386 * must be one of a small set of sizes. The number of banks and the supported 387 * sizes varies by SoC. 388 */ 389 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 390 MemoryRegion ram_memories[], 391 hwaddr ram_bases[], hwaddr ram_sizes[], 392 const ram_addr_t sdram_bank_sizes[]) 393 { 394 ram_addr_t size_left = memory_region_size(ram); 395 ram_addr_t base = 0; 396 ram_addr_t bank_size; 397 int i; 398 int j; 399 400 for (i = 0; i < nr_banks; i++) { 401 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 402 bank_size = sdram_bank_sizes[j]; 403 if (bank_size <= size_left) { 404 char name[32]; 405 406 ram_bases[i] = base; 407 ram_sizes[i] = bank_size; 408 base += bank_size; 409 size_left -= bank_size; 410 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 411 memory_region_init_alias(&ram_memories[i], NULL, name, ram, 412 ram_bases[i], ram_sizes[i]); 413 break; 414 } 415 } 416 if (!size_left) { 417 /* No need to use the remaining banks. */ 418 break; 419 } 420 } 421 422 if (size_left) { 423 ram_addr_t used_size = memory_region_size(ram) - size_left; 424 GString *s = g_string_new(NULL); 425 426 for (i = 0; sdram_bank_sizes[i]; i++) { 427 g_string_append_printf(s, "%" PRIi64 "%s", 428 sdram_bank_sizes[i] / MiB, 429 sdram_bank_sizes[i + 1] ? ", " : ""); 430 } 431 error_report("at most %d bank%s of %s MiB each supported", 432 nr_banks, nr_banks == 1 ? "" : "s", s->str); 433 error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", 434 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); 435 436 g_string_free(s, true); 437 exit(EXIT_FAILURE); 438 } 439 } 440 441 /*****************************************************************************/ 442 /* MAL */ 443 444 enum { 445 MAL0_CFG = 0x180, 446 MAL0_ESR = 0x181, 447 MAL0_IER = 0x182, 448 MAL0_TXCASR = 0x184, 449 MAL0_TXCARR = 0x185, 450 MAL0_TXEOBISR = 0x186, 451 MAL0_TXDEIR = 0x187, 452 MAL0_RXCASR = 0x190, 453 MAL0_RXCARR = 0x191, 454 MAL0_RXEOBISR = 0x192, 455 MAL0_RXDEIR = 0x193, 456 MAL0_TXCTP0R = 0x1A0, 457 MAL0_RXCTP0R = 0x1C0, 458 MAL0_RCBS0 = 0x1E0, 459 MAL0_RCBS1 = 0x1E1, 460 }; 461 462 static void ppc4xx_mal_reset(DeviceState *dev) 463 { 464 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 465 466 mal->cfg = 0x0007C000; 467 mal->esr = 0x00000000; 468 mal->ier = 0x00000000; 469 mal->rxcasr = 0x00000000; 470 mal->rxdeir = 0x00000000; 471 mal->rxeobisr = 0x00000000; 472 mal->txcasr = 0x00000000; 473 mal->txdeir = 0x00000000; 474 mal->txeobisr = 0x00000000; 475 } 476 477 static uint32_t dcr_read_mal(void *opaque, int dcrn) 478 { 479 Ppc4xxMalState *mal = opaque; 480 uint32_t ret; 481 482 switch (dcrn) { 483 case MAL0_CFG: 484 ret = mal->cfg; 485 break; 486 case MAL0_ESR: 487 ret = mal->esr; 488 break; 489 case MAL0_IER: 490 ret = mal->ier; 491 break; 492 case MAL0_TXCASR: 493 ret = mal->txcasr; 494 break; 495 case MAL0_TXCARR: 496 ret = mal->txcarr; 497 break; 498 case MAL0_TXEOBISR: 499 ret = mal->txeobisr; 500 break; 501 case MAL0_TXDEIR: 502 ret = mal->txdeir; 503 break; 504 case MAL0_RXCASR: 505 ret = mal->rxcasr; 506 break; 507 case MAL0_RXCARR: 508 ret = mal->rxcarr; 509 break; 510 case MAL0_RXEOBISR: 511 ret = mal->rxeobisr; 512 break; 513 case MAL0_RXDEIR: 514 ret = mal->rxdeir; 515 break; 516 default: 517 ret = 0; 518 break; 519 } 520 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 521 ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; 522 } 523 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 524 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; 525 } 526 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 527 ret = mal->rcbs[dcrn - MAL0_RCBS0]; 528 } 529 530 return ret; 531 } 532 533 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) 534 { 535 Ppc4xxMalState *mal = opaque; 536 537 switch (dcrn) { 538 case MAL0_CFG: 539 if (val & 0x80000000) { 540 ppc4xx_mal_reset(DEVICE(mal)); 541 } 542 mal->cfg = val & 0x00FFC087; 543 break; 544 case MAL0_ESR: 545 /* Read/clear */ 546 mal->esr &= ~val; 547 break; 548 case MAL0_IER: 549 mal->ier = val & 0x0000001F; 550 break; 551 case MAL0_TXCASR: 552 mal->txcasr = val & 0xF0000000; 553 break; 554 case MAL0_TXCARR: 555 mal->txcarr = val & 0xF0000000; 556 break; 557 case MAL0_TXEOBISR: 558 /* Read/clear */ 559 mal->txeobisr &= ~val; 560 break; 561 case MAL0_TXDEIR: 562 /* Read/clear */ 563 mal->txdeir &= ~val; 564 break; 565 case MAL0_RXCASR: 566 mal->rxcasr = val & 0xC0000000; 567 break; 568 case MAL0_RXCARR: 569 mal->rxcarr = val & 0xC0000000; 570 break; 571 case MAL0_RXEOBISR: 572 /* Read/clear */ 573 mal->rxeobisr &= ~val; 574 break; 575 case MAL0_RXDEIR: 576 /* Read/clear */ 577 mal->rxdeir &= ~val; 578 break; 579 } 580 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 581 mal->txctpr[dcrn - MAL0_TXCTP0R] = val; 582 } 583 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 584 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; 585 } 586 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 587 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; 588 } 589 } 590 591 static void ppc4xx_mal_realize(DeviceState *dev, Error **errp) 592 { 593 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 594 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 595 int i; 596 597 if (mal->txcnum > 32 || mal->rxcnum > 32) { 598 error_setg(errp, "invalid TXC/RXC number"); 599 return; 600 } 601 602 mal->txctpr = g_new0(uint32_t, mal->txcnum); 603 mal->rxctpr = g_new0(uint32_t, mal->rxcnum); 604 mal->rcbs = g_new0(uint32_t, mal->rxcnum); 605 606 for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) { 607 sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]); 608 } 609 610 ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); 611 ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal); 612 ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal); 613 ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal); 614 ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal); 615 ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 616 ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 617 ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal); 618 ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal); 619 ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 620 ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 621 for (i = 0; i < mal->txcnum; i++) { 622 ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i, 623 mal, &dcr_read_mal, &dcr_write_mal); 624 } 625 for (i = 0; i < mal->rxcnum; i++) { 626 ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i, 627 mal, &dcr_read_mal, &dcr_write_mal); 628 } 629 for (i = 0; i < mal->rxcnum; i++) { 630 ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i, 631 mal, &dcr_read_mal, &dcr_write_mal); 632 } 633 } 634 635 static void ppc4xx_mal_finalize(Object *obj) 636 { 637 Ppc4xxMalState *mal = PPC4xx_MAL(obj); 638 639 g_free(mal->rcbs); 640 g_free(mal->rxctpr); 641 g_free(mal->txctpr); 642 } 643 644 static Property ppc4xx_mal_properties[] = { 645 DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), 646 DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), 647 DEFINE_PROP_END_OF_LIST(), 648 }; 649 650 static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) 651 { 652 DeviceClass *dc = DEVICE_CLASS(oc); 653 654 dc->realize = ppc4xx_mal_realize; 655 dc->reset = ppc4xx_mal_reset; 656 /* Reason: only works as function of a ppc4xx SoC */ 657 dc->user_creatable = false; 658 device_class_set_props(dc, ppc4xx_mal_properties); 659 } 660 661 /*****************************************************************************/ 662 /* Peripheral local bus arbitrer */ 663 enum { 664 PLB3A0_ACR = 0x077, 665 PLB4A0_ACR = 0x081, 666 PLB0_BESR = 0x084, 667 PLB0_BEAR = 0x086, 668 PLB0_ACR = 0x087, 669 PLB4A1_ACR = 0x089, 670 }; 671 672 static uint32_t dcr_read_plb(void *opaque, int dcrn) 673 { 674 Ppc4xxPlbState *plb = opaque; 675 uint32_t ret; 676 677 switch (dcrn) { 678 case PLB0_ACR: 679 ret = plb->acr; 680 break; 681 case PLB0_BEAR: 682 ret = plb->bear; 683 break; 684 case PLB0_BESR: 685 ret = plb->besr; 686 break; 687 default: 688 /* Avoid gcc warning */ 689 ret = 0; 690 break; 691 } 692 693 return ret; 694 } 695 696 static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) 697 { 698 Ppc4xxPlbState *plb = opaque; 699 700 switch (dcrn) { 701 case PLB0_ACR: 702 /* 703 * We don't care about the actual parameters written as 704 * we don't manage any priorities on the bus 705 */ 706 plb->acr = val & 0xF8000000; 707 break; 708 case PLB0_BEAR: 709 /* Read only */ 710 break; 711 case PLB0_BESR: 712 /* Write-clear */ 713 plb->besr &= ~val; 714 break; 715 } 716 } 717 718 static void ppc405_plb_reset(DeviceState *dev) 719 { 720 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 721 722 plb->acr = 0x00000000; 723 plb->bear = 0x00000000; 724 plb->besr = 0x00000000; 725 } 726 727 static void ppc405_plb_realize(DeviceState *dev, Error **errp) 728 { 729 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 730 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 731 732 ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 733 ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 734 ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 735 ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 736 ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 737 ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 738 } 739 740 static void ppc405_plb_class_init(ObjectClass *oc, void *data) 741 { 742 DeviceClass *dc = DEVICE_CLASS(oc); 743 744 dc->realize = ppc405_plb_realize; 745 dc->reset = ppc405_plb_reset; 746 /* Reason: only works as function of a ppc4xx SoC */ 747 dc->user_creatable = false; 748 } 749 750 /*****************************************************************************/ 751 /* Peripheral controller */ 752 enum { 753 EBC0_CFGADDR = 0x012, 754 EBC0_CFGDATA = 0x013, 755 }; 756 757 static uint32_t dcr_read_ebc(void *opaque, int dcrn) 758 { 759 Ppc4xxEbcState *ebc = opaque; 760 uint32_t ret; 761 762 switch (dcrn) { 763 case EBC0_CFGADDR: 764 ret = ebc->addr; 765 break; 766 case EBC0_CFGDATA: 767 switch (ebc->addr) { 768 case 0x00: /* B0CR */ 769 ret = ebc->bcr[0]; 770 break; 771 case 0x01: /* B1CR */ 772 ret = ebc->bcr[1]; 773 break; 774 case 0x02: /* B2CR */ 775 ret = ebc->bcr[2]; 776 break; 777 case 0x03: /* B3CR */ 778 ret = ebc->bcr[3]; 779 break; 780 case 0x04: /* B4CR */ 781 ret = ebc->bcr[4]; 782 break; 783 case 0x05: /* B5CR */ 784 ret = ebc->bcr[5]; 785 break; 786 case 0x06: /* B6CR */ 787 ret = ebc->bcr[6]; 788 break; 789 case 0x07: /* B7CR */ 790 ret = ebc->bcr[7]; 791 break; 792 case 0x10: /* B0AP */ 793 ret = ebc->bap[0]; 794 break; 795 case 0x11: /* B1AP */ 796 ret = ebc->bap[1]; 797 break; 798 case 0x12: /* B2AP */ 799 ret = ebc->bap[2]; 800 break; 801 case 0x13: /* B3AP */ 802 ret = ebc->bap[3]; 803 break; 804 case 0x14: /* B4AP */ 805 ret = ebc->bap[4]; 806 break; 807 case 0x15: /* B5AP */ 808 ret = ebc->bap[5]; 809 break; 810 case 0x16: /* B6AP */ 811 ret = ebc->bap[6]; 812 break; 813 case 0x17: /* B7AP */ 814 ret = ebc->bap[7]; 815 break; 816 case 0x20: /* BEAR */ 817 ret = ebc->bear; 818 break; 819 case 0x21: /* BESR0 */ 820 ret = ebc->besr0; 821 break; 822 case 0x22: /* BESR1 */ 823 ret = ebc->besr1; 824 break; 825 case 0x23: /* CFG */ 826 ret = ebc->cfg; 827 break; 828 default: 829 ret = 0x00000000; 830 break; 831 } 832 break; 833 default: 834 ret = 0x00000000; 835 break; 836 } 837 838 return ret; 839 } 840 841 static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) 842 { 843 Ppc4xxEbcState *ebc = opaque; 844 845 switch (dcrn) { 846 case EBC0_CFGADDR: 847 ebc->addr = val; 848 break; 849 case EBC0_CFGDATA: 850 switch (ebc->addr) { 851 case 0x00: /* B0CR */ 852 break; 853 case 0x01: /* B1CR */ 854 break; 855 case 0x02: /* B2CR */ 856 break; 857 case 0x03: /* B3CR */ 858 break; 859 case 0x04: /* B4CR */ 860 break; 861 case 0x05: /* B5CR */ 862 break; 863 case 0x06: /* B6CR */ 864 break; 865 case 0x07: /* B7CR */ 866 break; 867 case 0x10: /* B0AP */ 868 break; 869 case 0x11: /* B1AP */ 870 break; 871 case 0x12: /* B2AP */ 872 break; 873 case 0x13: /* B3AP */ 874 break; 875 case 0x14: /* B4AP */ 876 break; 877 case 0x15: /* B5AP */ 878 break; 879 case 0x16: /* B6AP */ 880 break; 881 case 0x17: /* B7AP */ 882 break; 883 case 0x20: /* BEAR */ 884 break; 885 case 0x21: /* BESR0 */ 886 break; 887 case 0x22: /* BESR1 */ 888 break; 889 case 0x23: /* CFG */ 890 break; 891 default: 892 break; 893 } 894 break; 895 default: 896 break; 897 } 898 } 899 900 static void ppc405_ebc_reset(DeviceState *dev) 901 { 902 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 903 int i; 904 905 ebc->addr = 0x00000000; 906 ebc->bap[0] = 0x7F8FFE80; 907 ebc->bcr[0] = 0xFFE28000; 908 for (i = 0; i < 8; i++) { 909 ebc->bap[i] = 0x00000000; 910 ebc->bcr[i] = 0x00000000; 911 } 912 ebc->besr0 = 0x00000000; 913 ebc->besr1 = 0x00000000; 914 ebc->cfg = 0x80400000; 915 } 916 917 static void ppc405_ebc_realize(DeviceState *dev, Error **errp) 918 { 919 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 920 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 921 922 ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); 923 ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc); 924 } 925 926 static void ppc405_ebc_class_init(ObjectClass *oc, void *data) 927 { 928 DeviceClass *dc = DEVICE_CLASS(oc); 929 930 dc->realize = ppc405_ebc_realize; 931 dc->reset = ppc405_ebc_reset; 932 /* Reason: only works as function of a ppc4xx SoC */ 933 dc->user_creatable = false; 934 } 935 936 /* PPC4xx_DCR_DEVICE */ 937 938 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 939 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 940 { 941 assert(dev->cpu); 942 ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write); 943 } 944 945 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 946 Error **errp) 947 { 948 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 949 return sysbus_realize(SYS_BUS_DEVICE(dev), errp); 950 } 951 952 static Property ppc4xx_dcr_properties[] = { 953 DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU, 954 PowerPCCPU *), 955 DEFINE_PROP_END_OF_LIST(), 956 }; 957 958 static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data) 959 { 960 DeviceClass *dc = DEVICE_CLASS(oc); 961 962 device_class_set_props(dc, ppc4xx_dcr_properties); 963 } 964 965 static const TypeInfo ppc4xx_types[] = { 966 { 967 .name = TYPE_PPC4xx_MAL, 968 .parent = TYPE_PPC4xx_DCR_DEVICE, 969 .instance_size = sizeof(Ppc4xxMalState), 970 .instance_finalize = ppc4xx_mal_finalize, 971 .class_init = ppc4xx_mal_class_init, 972 }, { 973 .name = TYPE_PPC4xx_PLB, 974 .parent = TYPE_PPC4xx_DCR_DEVICE, 975 .instance_size = sizeof(Ppc4xxPlbState), 976 .class_init = ppc405_plb_class_init, 977 }, { 978 .name = TYPE_PPC4xx_EBC, 979 .parent = TYPE_PPC4xx_DCR_DEVICE, 980 .instance_size = sizeof(Ppc4xxEbcState), 981 .class_init = ppc405_ebc_class_init, 982 }, { 983 .name = TYPE_PPC4xx_DCR_DEVICE, 984 .parent = TYPE_SYS_BUS_DEVICE, 985 .instance_size = sizeof(Ppc4xxDcrDeviceState), 986 .class_init = ppc4xx_dcr_class_init, 987 .abstract = true, 988 } 989 }; 990 991 DEFINE_TYPES(ppc4xx_types) 992