1 /* 2 * QEMU PowerPC 4xx embedded processors shared devices emulation 3 * 4 * Copyright (c) 2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "cpu.h" 28 #include "hw/ppc/ppc4xx.h" 29 #include "hw/qdev-properties.h" 30 #include "qapi/error.h" 31 32 /* 33 * Split RAM between SDRAM banks. 34 * 35 * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] 36 * and must be 0-terminated. 37 * 38 * The 4xx SDRAM controller supports a small number of banks, and each bank 39 * must be one of a small set of sizes. The number of banks and the supported 40 * sizes varies by SoC. 41 */ 42 void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, 43 Ppc4xxSdramBank ram_banks[], 44 const ram_addr_t sdram_bank_sizes[]) 45 { 46 ram_addr_t size_left = memory_region_size(ram); 47 ram_addr_t base = 0; 48 ram_addr_t bank_size; 49 int i; 50 int j; 51 52 for (i = 0; i < nr_banks; i++) { 53 for (j = 0; sdram_bank_sizes[j] != 0; j++) { 54 bank_size = sdram_bank_sizes[j]; 55 if (bank_size <= size_left) { 56 char name[32]; 57 58 ram_banks[i].base = base; 59 ram_banks[i].size = bank_size; 60 base += bank_size; 61 size_left -= bank_size; 62 snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); 63 memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram, 64 ram_banks[i].base, ram_banks[i].size); 65 break; 66 } 67 } 68 if (!size_left) { 69 /* No need to use the remaining banks. */ 70 break; 71 } 72 } 73 74 if (size_left) { 75 ram_addr_t used_size = memory_region_size(ram) - size_left; 76 GString *s = g_string_new(NULL); 77 78 for (i = 0; sdram_bank_sizes[i]; i++) { 79 g_string_append_printf(s, "%" PRIi64 "%s", 80 sdram_bank_sizes[i] / MiB, 81 sdram_bank_sizes[i + 1] ? ", " : ""); 82 } 83 error_report("at most %d bank%s of %s MiB each supported", 84 nr_banks, nr_banks == 1 ? "" : "s", s->str); 85 error_printf("Possible valid RAM size: %" PRIi64 " MiB\n", 86 used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); 87 88 g_string_free(s, true); 89 exit(EXIT_FAILURE); 90 } 91 } 92 93 /*****************************************************************************/ 94 /* MAL */ 95 96 enum { 97 MAL0_CFG = 0x180, 98 MAL0_ESR = 0x181, 99 MAL0_IER = 0x182, 100 MAL0_TXCASR = 0x184, 101 MAL0_TXCARR = 0x185, 102 MAL0_TXEOBISR = 0x186, 103 MAL0_TXDEIR = 0x187, 104 MAL0_RXCASR = 0x190, 105 MAL0_RXCARR = 0x191, 106 MAL0_RXEOBISR = 0x192, 107 MAL0_RXDEIR = 0x193, 108 MAL0_TXCTP0R = 0x1A0, 109 MAL0_RXCTP0R = 0x1C0, 110 MAL0_RCBS0 = 0x1E0, 111 MAL0_RCBS1 = 0x1E1, 112 }; 113 114 static void ppc4xx_mal_reset(DeviceState *dev) 115 { 116 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 117 118 mal->cfg = 0x0007C000; 119 mal->esr = 0x00000000; 120 mal->ier = 0x00000000; 121 mal->rxcasr = 0x00000000; 122 mal->rxdeir = 0x00000000; 123 mal->rxeobisr = 0x00000000; 124 mal->txcasr = 0x00000000; 125 mal->txdeir = 0x00000000; 126 mal->txeobisr = 0x00000000; 127 } 128 129 static uint32_t dcr_read_mal(void *opaque, int dcrn) 130 { 131 Ppc4xxMalState *mal = opaque; 132 uint32_t ret; 133 134 switch (dcrn) { 135 case MAL0_CFG: 136 ret = mal->cfg; 137 break; 138 case MAL0_ESR: 139 ret = mal->esr; 140 break; 141 case MAL0_IER: 142 ret = mal->ier; 143 break; 144 case MAL0_TXCASR: 145 ret = mal->txcasr; 146 break; 147 case MAL0_TXCARR: 148 ret = mal->txcarr; 149 break; 150 case MAL0_TXEOBISR: 151 ret = mal->txeobisr; 152 break; 153 case MAL0_TXDEIR: 154 ret = mal->txdeir; 155 break; 156 case MAL0_RXCASR: 157 ret = mal->rxcasr; 158 break; 159 case MAL0_RXCARR: 160 ret = mal->rxcarr; 161 break; 162 case MAL0_RXEOBISR: 163 ret = mal->rxeobisr; 164 break; 165 case MAL0_RXDEIR: 166 ret = mal->rxdeir; 167 break; 168 default: 169 ret = 0; 170 break; 171 } 172 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 173 ret = mal->txctpr[dcrn - MAL0_TXCTP0R]; 174 } 175 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 176 ret = mal->rxctpr[dcrn - MAL0_RXCTP0R]; 177 } 178 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 179 ret = mal->rcbs[dcrn - MAL0_RCBS0]; 180 } 181 182 return ret; 183 } 184 185 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) 186 { 187 Ppc4xxMalState *mal = opaque; 188 189 switch (dcrn) { 190 case MAL0_CFG: 191 if (val & 0x80000000) { 192 ppc4xx_mal_reset(DEVICE(mal)); 193 } 194 mal->cfg = val & 0x00FFC087; 195 break; 196 case MAL0_ESR: 197 /* Read/clear */ 198 mal->esr &= ~val; 199 break; 200 case MAL0_IER: 201 mal->ier = val & 0x0000001F; 202 break; 203 case MAL0_TXCASR: 204 mal->txcasr = val & 0xF0000000; 205 break; 206 case MAL0_TXCARR: 207 mal->txcarr = val & 0xF0000000; 208 break; 209 case MAL0_TXEOBISR: 210 /* Read/clear */ 211 mal->txeobisr &= ~val; 212 break; 213 case MAL0_TXDEIR: 214 /* Read/clear */ 215 mal->txdeir &= ~val; 216 break; 217 case MAL0_RXCASR: 218 mal->rxcasr = val & 0xC0000000; 219 break; 220 case MAL0_RXCARR: 221 mal->rxcarr = val & 0xC0000000; 222 break; 223 case MAL0_RXEOBISR: 224 /* Read/clear */ 225 mal->rxeobisr &= ~val; 226 break; 227 case MAL0_RXDEIR: 228 /* Read/clear */ 229 mal->rxdeir &= ~val; 230 break; 231 } 232 if (dcrn >= MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { 233 mal->txctpr[dcrn - MAL0_TXCTP0R] = val; 234 } 235 if (dcrn >= MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { 236 mal->rxctpr[dcrn - MAL0_RXCTP0R] = val; 237 } 238 if (dcrn >= MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { 239 mal->rcbs[dcrn - MAL0_RCBS0] = val & 0x000000FF; 240 } 241 } 242 243 static void ppc4xx_mal_realize(DeviceState *dev, Error **errp) 244 { 245 Ppc4xxMalState *mal = PPC4xx_MAL(dev); 246 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 247 int i; 248 249 if (mal->txcnum > 32 || mal->rxcnum > 32) { 250 error_setg(errp, "invalid TXC/RXC number"); 251 return; 252 } 253 254 mal->txctpr = g_new0(uint32_t, mal->txcnum); 255 mal->rxctpr = g_new0(uint32_t, mal->rxcnum); 256 mal->rcbs = g_new0(uint32_t, mal->rxcnum); 257 258 for (i = 0; i < ARRAY_SIZE(mal->irqs); i++) { 259 sysbus_init_irq(SYS_BUS_DEVICE(dev), &mal->irqs[i]); 260 } 261 262 ppc4xx_dcr_register(dcr, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); 263 ppc4xx_dcr_register(dcr, MAL0_ESR, mal, &dcr_read_mal, &dcr_write_mal); 264 ppc4xx_dcr_register(dcr, MAL0_IER, mal, &dcr_read_mal, &dcr_write_mal); 265 ppc4xx_dcr_register(dcr, MAL0_TXCASR, mal, &dcr_read_mal, &dcr_write_mal); 266 ppc4xx_dcr_register(dcr, MAL0_TXCARR, mal, &dcr_read_mal, &dcr_write_mal); 267 ppc4xx_dcr_register(dcr, MAL0_TXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 268 ppc4xx_dcr_register(dcr, MAL0_TXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 269 ppc4xx_dcr_register(dcr, MAL0_RXCASR, mal, &dcr_read_mal, &dcr_write_mal); 270 ppc4xx_dcr_register(dcr, MAL0_RXCARR, mal, &dcr_read_mal, &dcr_write_mal); 271 ppc4xx_dcr_register(dcr, MAL0_RXEOBISR, mal, &dcr_read_mal, &dcr_write_mal); 272 ppc4xx_dcr_register(dcr, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal); 273 for (i = 0; i < mal->txcnum; i++) { 274 ppc4xx_dcr_register(dcr, MAL0_TXCTP0R + i, 275 mal, &dcr_read_mal, &dcr_write_mal); 276 } 277 for (i = 0; i < mal->rxcnum; i++) { 278 ppc4xx_dcr_register(dcr, MAL0_RXCTP0R + i, 279 mal, &dcr_read_mal, &dcr_write_mal); 280 } 281 for (i = 0; i < mal->rxcnum; i++) { 282 ppc4xx_dcr_register(dcr, MAL0_RCBS0 + i, 283 mal, &dcr_read_mal, &dcr_write_mal); 284 } 285 } 286 287 static void ppc4xx_mal_finalize(Object *obj) 288 { 289 Ppc4xxMalState *mal = PPC4xx_MAL(obj); 290 291 g_free(mal->rcbs); 292 g_free(mal->rxctpr); 293 g_free(mal->txctpr); 294 } 295 296 static Property ppc4xx_mal_properties[] = { 297 DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), 298 DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), 299 DEFINE_PROP_END_OF_LIST(), 300 }; 301 302 static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) 303 { 304 DeviceClass *dc = DEVICE_CLASS(oc); 305 306 dc->realize = ppc4xx_mal_realize; 307 dc->reset = ppc4xx_mal_reset; 308 /* Reason: only works as function of a ppc4xx SoC */ 309 dc->user_creatable = false; 310 device_class_set_props(dc, ppc4xx_mal_properties); 311 } 312 313 /*****************************************************************************/ 314 /* Peripheral local bus arbitrer */ 315 enum { 316 PLB3A0_ACR = 0x077, 317 PLB4A0_ACR = 0x081, 318 PLB0_BESR = 0x084, 319 PLB0_BEAR = 0x086, 320 PLB0_ACR = 0x087, 321 PLB4A1_ACR = 0x089, 322 }; 323 324 static uint32_t dcr_read_plb(void *opaque, int dcrn) 325 { 326 Ppc4xxPlbState *plb = opaque; 327 uint32_t ret; 328 329 switch (dcrn) { 330 case PLB0_ACR: 331 ret = plb->acr; 332 break; 333 case PLB0_BEAR: 334 ret = plb->bear; 335 break; 336 case PLB0_BESR: 337 ret = plb->besr; 338 break; 339 default: 340 /* Avoid gcc warning */ 341 ret = 0; 342 break; 343 } 344 345 return ret; 346 } 347 348 static void dcr_write_plb(void *opaque, int dcrn, uint32_t val) 349 { 350 Ppc4xxPlbState *plb = opaque; 351 352 switch (dcrn) { 353 case PLB0_ACR: 354 /* 355 * We don't care about the actual parameters written as 356 * we don't manage any priorities on the bus 357 */ 358 plb->acr = val & 0xF8000000; 359 break; 360 case PLB0_BEAR: 361 /* Read only */ 362 break; 363 case PLB0_BESR: 364 /* Write-clear */ 365 plb->besr &= ~val; 366 break; 367 } 368 } 369 370 static void ppc405_plb_reset(DeviceState *dev) 371 { 372 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 373 374 plb->acr = 0x00000000; 375 plb->bear = 0x00000000; 376 plb->besr = 0x00000000; 377 } 378 379 static void ppc405_plb_realize(DeviceState *dev, Error **errp) 380 { 381 Ppc4xxPlbState *plb = PPC4xx_PLB(dev); 382 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 383 384 ppc4xx_dcr_register(dcr, PLB3A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 385 ppc4xx_dcr_register(dcr, PLB4A0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 386 ppc4xx_dcr_register(dcr, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb); 387 ppc4xx_dcr_register(dcr, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb); 388 ppc4xx_dcr_register(dcr, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb); 389 ppc4xx_dcr_register(dcr, PLB4A1_ACR, plb, &dcr_read_plb, &dcr_write_plb); 390 } 391 392 static void ppc405_plb_class_init(ObjectClass *oc, void *data) 393 { 394 DeviceClass *dc = DEVICE_CLASS(oc); 395 396 dc->realize = ppc405_plb_realize; 397 dc->reset = ppc405_plb_reset; 398 /* Reason: only works as function of a ppc4xx SoC */ 399 dc->user_creatable = false; 400 } 401 402 /*****************************************************************************/ 403 /* Peripheral controller */ 404 enum { 405 EBC0_CFGADDR = 0x012, 406 EBC0_CFGDATA = 0x013, 407 }; 408 409 static uint32_t dcr_read_ebc(void *opaque, int dcrn) 410 { 411 Ppc4xxEbcState *ebc = opaque; 412 uint32_t ret; 413 414 switch (dcrn) { 415 case EBC0_CFGADDR: 416 ret = ebc->addr; 417 break; 418 case EBC0_CFGDATA: 419 switch (ebc->addr) { 420 case 0x00: /* B0CR */ 421 ret = ebc->bcr[0]; 422 break; 423 case 0x01: /* B1CR */ 424 ret = ebc->bcr[1]; 425 break; 426 case 0x02: /* B2CR */ 427 ret = ebc->bcr[2]; 428 break; 429 case 0x03: /* B3CR */ 430 ret = ebc->bcr[3]; 431 break; 432 case 0x04: /* B4CR */ 433 ret = ebc->bcr[4]; 434 break; 435 case 0x05: /* B5CR */ 436 ret = ebc->bcr[5]; 437 break; 438 case 0x06: /* B6CR */ 439 ret = ebc->bcr[6]; 440 break; 441 case 0x07: /* B7CR */ 442 ret = ebc->bcr[7]; 443 break; 444 case 0x10: /* B0AP */ 445 ret = ebc->bap[0]; 446 break; 447 case 0x11: /* B1AP */ 448 ret = ebc->bap[1]; 449 break; 450 case 0x12: /* B2AP */ 451 ret = ebc->bap[2]; 452 break; 453 case 0x13: /* B3AP */ 454 ret = ebc->bap[3]; 455 break; 456 case 0x14: /* B4AP */ 457 ret = ebc->bap[4]; 458 break; 459 case 0x15: /* B5AP */ 460 ret = ebc->bap[5]; 461 break; 462 case 0x16: /* B6AP */ 463 ret = ebc->bap[6]; 464 break; 465 case 0x17: /* B7AP */ 466 ret = ebc->bap[7]; 467 break; 468 case 0x20: /* BEAR */ 469 ret = ebc->bear; 470 break; 471 case 0x21: /* BESR0 */ 472 ret = ebc->besr0; 473 break; 474 case 0x22: /* BESR1 */ 475 ret = ebc->besr1; 476 break; 477 case 0x23: /* CFG */ 478 ret = ebc->cfg; 479 break; 480 default: 481 ret = 0x00000000; 482 break; 483 } 484 break; 485 default: 486 ret = 0x00000000; 487 break; 488 } 489 490 return ret; 491 } 492 493 static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val) 494 { 495 Ppc4xxEbcState *ebc = opaque; 496 497 switch (dcrn) { 498 case EBC0_CFGADDR: 499 ebc->addr = val; 500 break; 501 case EBC0_CFGDATA: 502 switch (ebc->addr) { 503 case 0x00: /* B0CR */ 504 break; 505 case 0x01: /* B1CR */ 506 break; 507 case 0x02: /* B2CR */ 508 break; 509 case 0x03: /* B3CR */ 510 break; 511 case 0x04: /* B4CR */ 512 break; 513 case 0x05: /* B5CR */ 514 break; 515 case 0x06: /* B6CR */ 516 break; 517 case 0x07: /* B7CR */ 518 break; 519 case 0x10: /* B0AP */ 520 break; 521 case 0x11: /* B1AP */ 522 break; 523 case 0x12: /* B2AP */ 524 break; 525 case 0x13: /* B3AP */ 526 break; 527 case 0x14: /* B4AP */ 528 break; 529 case 0x15: /* B5AP */ 530 break; 531 case 0x16: /* B6AP */ 532 break; 533 case 0x17: /* B7AP */ 534 break; 535 case 0x20: /* BEAR */ 536 break; 537 case 0x21: /* BESR0 */ 538 break; 539 case 0x22: /* BESR1 */ 540 break; 541 case 0x23: /* CFG */ 542 break; 543 default: 544 break; 545 } 546 break; 547 default: 548 break; 549 } 550 } 551 552 static void ppc405_ebc_reset(DeviceState *dev) 553 { 554 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 555 int i; 556 557 ebc->addr = 0x00000000; 558 ebc->bap[0] = 0x7F8FFE80; 559 ebc->bcr[0] = 0xFFE28000; 560 for (i = 0; i < 8; i++) { 561 ebc->bap[i] = 0x00000000; 562 ebc->bcr[i] = 0x00000000; 563 } 564 ebc->besr0 = 0x00000000; 565 ebc->besr1 = 0x00000000; 566 ebc->cfg = 0x80400000; 567 } 568 569 static void ppc405_ebc_realize(DeviceState *dev, Error **errp) 570 { 571 Ppc4xxEbcState *ebc = PPC4xx_EBC(dev); 572 Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev); 573 574 ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc); 575 ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc); 576 } 577 578 static void ppc405_ebc_class_init(ObjectClass *oc, void *data) 579 { 580 DeviceClass *dc = DEVICE_CLASS(oc); 581 582 dc->realize = ppc405_ebc_realize; 583 dc->reset = ppc405_ebc_reset; 584 /* Reason: only works as function of a ppc4xx SoC */ 585 dc->user_creatable = false; 586 } 587 588 /* PPC4xx_DCR_DEVICE */ 589 590 void ppc4xx_dcr_register(Ppc4xxDcrDeviceState *dev, int dcrn, void *opaque, 591 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 592 { 593 assert(dev->cpu); 594 ppc_dcr_register(&dev->cpu->env, dcrn, opaque, dcr_read, dcr_write); 595 } 596 597 bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, 598 Error **errp) 599 { 600 object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_abort); 601 return sysbus_realize(SYS_BUS_DEVICE(dev), errp); 602 } 603 604 static Property ppc4xx_dcr_properties[] = { 605 DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU, 606 PowerPCCPU *), 607 DEFINE_PROP_END_OF_LIST(), 608 }; 609 610 static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data) 611 { 612 DeviceClass *dc = DEVICE_CLASS(oc); 613 614 device_class_set_props(dc, ppc4xx_dcr_properties); 615 } 616 617 static const TypeInfo ppc4xx_types[] = { 618 { 619 .name = TYPE_PPC4xx_MAL, 620 .parent = TYPE_PPC4xx_DCR_DEVICE, 621 .instance_size = sizeof(Ppc4xxMalState), 622 .instance_finalize = ppc4xx_mal_finalize, 623 .class_init = ppc4xx_mal_class_init, 624 }, { 625 .name = TYPE_PPC4xx_PLB, 626 .parent = TYPE_PPC4xx_DCR_DEVICE, 627 .instance_size = sizeof(Ppc4xxPlbState), 628 .class_init = ppc405_plb_class_init, 629 }, { 630 .name = TYPE_PPC4xx_EBC, 631 .parent = TYPE_PPC4xx_DCR_DEVICE, 632 .instance_size = sizeof(Ppc4xxEbcState), 633 .class_init = ppc405_ebc_class_init, 634 }, { 635 .name = TYPE_PPC4xx_DCR_DEVICE, 636 .parent = TYPE_SYS_BUS_DEVICE, 637 .instance_size = sizeof(Ppc4xxDcrDeviceState), 638 .class_init = ppc4xx_dcr_class_init, 639 .abstract = true, 640 } 641 }; 642 643 DEFINE_TYPES(ppc4xx_types) 644