1 /* 2 * QEMU PowerPC e500v2 ePAPR spinning code 3 * 4 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Alexander Graf, <agraf@suse.de> 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 * 21 * This code is not really a device, but models an interface that usually 22 * firmware takes care of. It's used when QEMU plays the role of firmware. 23 * 24 * Specification: 25 * 26 * https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf 27 * 28 */ 29 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/sysbus.h" 34 #include "sysemu/kvm.h" 35 #include "e500.h" 36 37 #define MAX_CPUS 32 38 39 typedef struct spin_info { 40 uint64_t addr; 41 uint64_t r3; 42 uint32_t resv; 43 uint32_t pir; 44 uint64_t reserved; 45 } QEMU_PACKED SpinInfo; 46 47 #define TYPE_E500_SPIN "e500-spin" 48 #define E500_SPIN(obj) OBJECT_CHECK(SpinState, (obj), TYPE_E500_SPIN) 49 50 typedef struct SpinState { 51 SysBusDevice parent_obj; 52 53 MemoryRegion iomem; 54 SpinInfo spin[MAX_CPUS]; 55 } SpinState; 56 57 typedef struct spin_kick { 58 PowerPCCPU *cpu; 59 SpinInfo *spin; 60 } SpinKick; 61 62 static void spin_reset(void *opaque) 63 { 64 SpinState *s = opaque; 65 int i; 66 67 for (i = 0; i < MAX_CPUS; i++) { 68 SpinInfo *info = &s->spin[i]; 69 70 stl_p(&info->pir, i); 71 stq_p(&info->r3, i); 72 stq_p(&info->addr, 1); 73 } 74 } 75 76 static void mmubooke_create_initial_mapping(CPUPPCState *env, 77 target_ulong va, 78 hwaddr pa, 79 hwaddr len) 80 { 81 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1); 82 hwaddr size; 83 84 size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT); 85 tlb->mas1 = MAS1_VALID | size; 86 tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M; 87 tlb->mas7_3 = pa & TARGET_PAGE_MASK; 88 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX; 89 env->tlb_dirty = true; 90 } 91 92 static void spin_kick(void *data) 93 { 94 SpinKick *kick = data; 95 CPUState *cpu = CPU(kick->cpu); 96 CPUPPCState *env = &kick->cpu->env; 97 SpinInfo *curspin = kick->spin; 98 hwaddr map_size = 64 * 1024 * 1024; 99 hwaddr map_start; 100 101 cpu_synchronize_state(cpu); 102 stl_p(&curspin->pir, env->spr[SPR_BOOKE_PIR]); 103 env->nip = ldq_p(&curspin->addr) & (map_size - 1); 104 env->gpr[3] = ldq_p(&curspin->r3); 105 env->gpr[4] = 0; 106 env->gpr[5] = 0; 107 env->gpr[6] = 0; 108 env->gpr[7] = map_size; 109 env->gpr[8] = 0; 110 env->gpr[9] = 0; 111 112 map_start = ldq_p(&curspin->addr) & ~(map_size - 1); 113 mmubooke_create_initial_mapping(env, 0, map_start, map_size); 114 115 cpu->halted = 0; 116 cpu->exception_index = -1; 117 cpu->stopped = false; 118 qemu_cpu_kick(cpu); 119 } 120 121 static void spin_write(void *opaque, hwaddr addr, uint64_t value, 122 unsigned len) 123 { 124 SpinState *s = opaque; 125 int env_idx = addr / sizeof(SpinInfo); 126 CPUState *cpu; 127 SpinInfo *curspin = &s->spin[env_idx]; 128 uint8_t *curspin_p = (uint8_t*)curspin; 129 130 cpu = qemu_get_cpu(env_idx); 131 if (cpu == NULL) { 132 /* Unknown CPU */ 133 return; 134 } 135 136 if (cpu->cpu_index == 0) { 137 /* primary CPU doesn't spin */ 138 return; 139 } 140 141 curspin_p = &curspin_p[addr % sizeof(SpinInfo)]; 142 switch (len) { 143 case 1: 144 stb_p(curspin_p, value); 145 break; 146 case 2: 147 stw_p(curspin_p, value); 148 break; 149 case 4: 150 stl_p(curspin_p, value); 151 break; 152 } 153 154 if (!(ldq_p(&curspin->addr) & 1)) { 155 /* run CPU */ 156 SpinKick kick = { 157 .cpu = POWERPC_CPU(cpu), 158 .spin = curspin, 159 }; 160 161 run_on_cpu(cpu, spin_kick, &kick); 162 } 163 } 164 165 static uint64_t spin_read(void *opaque, hwaddr addr, unsigned len) 166 { 167 SpinState *s = opaque; 168 uint8_t *spin_p = &((uint8_t*)s->spin)[addr]; 169 170 switch (len) { 171 case 1: 172 return ldub_p(spin_p); 173 case 2: 174 return lduw_p(spin_p); 175 case 4: 176 return ldl_p(spin_p); 177 default: 178 hw_error("ppce500: unexpected %s with len = %u", __func__, len); 179 } 180 } 181 182 static const MemoryRegionOps spin_rw_ops = { 183 .read = spin_read, 184 .write = spin_write, 185 .endianness = DEVICE_BIG_ENDIAN, 186 }; 187 188 static int ppce500_spin_initfn(SysBusDevice *dev) 189 { 190 SpinState *s = E500_SPIN(dev); 191 192 memory_region_init_io(&s->iomem, OBJECT(s), &spin_rw_ops, s, 193 "e500 spin pv device", sizeof(SpinInfo) * MAX_CPUS); 194 sysbus_init_mmio(dev, &s->iomem); 195 196 qemu_register_reset(spin_reset, s); 197 198 return 0; 199 } 200 201 static void ppce500_spin_class_init(ObjectClass *klass, void *data) 202 { 203 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 204 205 k->init = ppce500_spin_initfn; 206 } 207 208 static const TypeInfo ppce500_spin_info = { 209 .name = TYPE_E500_SPIN, 210 .parent = TYPE_SYS_BUS_DEVICE, 211 .instance_size = sizeof(SpinState), 212 .class_init = ppce500_spin_class_init, 213 }; 214 215 static void ppce500_spin_register_types(void) 216 { 217 type_register_static(&ppce500_spin_info); 218 } 219 220 type_init(ppce500_spin_register_types) 221