1 /* 2 * QEMU PPC PREP hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright (c) 2017 Hervé Poussineau 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "hw/hw.h" 28 #include "hw/timer/m48t59.h" 29 #include "hw/i386/pc.h" 30 #include "hw/char/serial.h" 31 #include "hw/block/fdc.h" 32 #include "net/net.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/isa/isa.h" 35 #include "hw/pci/pci.h" 36 #include "hw/pci/pci_host.h" 37 #include "hw/ppc/ppc.h" 38 #include "hw/boards.h" 39 #include "qemu/error-report.h" 40 #include "qemu/log.h" 41 #include "hw/ide.h" 42 #include "hw/loader.h" 43 #include "hw/timer/mc146818rtc.h" 44 #include "hw/input/i8042.h" 45 #include "hw/isa/pc87312.h" 46 #include "hw/net/ne2000-isa.h" 47 #include "sysemu/arch_init.h" 48 #include "sysemu/kvm.h" 49 #include "sysemu/qtest.h" 50 #include "exec/address-spaces.h" 51 #include "trace.h" 52 #include "elf.h" 53 #include "qemu/units.h" 54 #include "kvm_ppc.h" 55 56 /* SMP is not enabled, for now */ 57 #define MAX_CPUS 1 58 59 #define MAX_IDE_BUS 2 60 61 #define CFG_ADDR 0xf0000510 62 63 #define BIOS_SIZE (1 * MiB) 64 #define BIOS_FILENAME "ppc_rom.bin" 65 #define KERNEL_LOAD_ADDR 0x01000000 66 #define INITRD_LOAD_ADDR 0x01800000 67 68 /* Constants for devices init */ 69 static const int ide_iobase[2] = { 0x1f0, 0x170 }; 70 static const int ide_iobase2[2] = { 0x3f6, 0x376 }; 71 static const int ide_irq[2] = { 13, 13 }; 72 73 #define NE2000_NB_MAX 6 74 75 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; 76 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; 77 78 /* ISA IO ports bridge */ 79 #define PPC_IO_BASE 0x80000000 80 81 /* PowerPC control and status registers */ 82 #if 0 // Not used 83 static struct { 84 /* IDs */ 85 uint32_t veni_devi; 86 uint32_t revi; 87 /* Control and status */ 88 uint32_t gcsr; 89 uint32_t xcfr; 90 uint32_t ct32; 91 uint32_t mcsr; 92 /* General purpose registers */ 93 uint32_t gprg[6]; 94 /* Exceptions */ 95 uint32_t feen; 96 uint32_t fest; 97 uint32_t fema; 98 uint32_t fecl; 99 uint32_t eeen; 100 uint32_t eest; 101 uint32_t eecl; 102 uint32_t eeint; 103 uint32_t eemck0; 104 uint32_t eemck1; 105 /* Error diagnostic */ 106 } XCSR; 107 108 static void PPC_XCSR_writeb (void *opaque, 109 hwaddr addr, uint32_t value) 110 { 111 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 112 value); 113 } 114 115 static void PPC_XCSR_writew (void *opaque, 116 hwaddr addr, uint32_t value) 117 { 118 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 119 value); 120 } 121 122 static void PPC_XCSR_writel (void *opaque, 123 hwaddr addr, uint32_t value) 124 { 125 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, 126 value); 127 } 128 129 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr) 130 { 131 uint32_t retval = 0; 132 133 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 134 retval); 135 136 return retval; 137 } 138 139 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr) 140 { 141 uint32_t retval = 0; 142 143 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 144 retval); 145 146 return retval; 147 } 148 149 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr) 150 { 151 uint32_t retval = 0; 152 153 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, 154 retval); 155 156 return retval; 157 } 158 159 static const MemoryRegionOps PPC_XCSR_ops = { 160 .old_mmio = { 161 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, 162 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, 163 }, 164 .endianness = DEVICE_LITTLE_ENDIAN, 165 }; 166 167 #endif 168 169 /* Fake super-io ports for PREP platform (Intel 82378ZB) */ 170 typedef struct sysctrl_t { 171 qemu_irq reset_irq; 172 Nvram *nvram; 173 uint8_t state; 174 uint8_t syscontrol; 175 int contiguous_map; 176 qemu_irq contiguous_map_irq; 177 int endian; 178 } sysctrl_t; 179 180 enum { 181 STATE_HARDFILE = 0x01, 182 }; 183 184 static sysctrl_t *sysctrl; 185 186 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) 187 { 188 sysctrl_t *sysctrl = opaque; 189 190 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val); 191 switch (addr) { 192 case 0x0092: 193 /* Special port 92 */ 194 /* Check soft reset asked */ 195 if (val & 0x01) { 196 qemu_irq_raise(sysctrl->reset_irq); 197 } else { 198 qemu_irq_lower(sysctrl->reset_irq); 199 } 200 /* Check LE mode */ 201 if (val & 0x02) { 202 sysctrl->endian = 1; 203 } else { 204 sysctrl->endian = 0; 205 } 206 break; 207 case 0x0800: 208 /* Motorola CPU configuration register : read-only */ 209 break; 210 case 0x0802: 211 /* Motorola base module feature register : read-only */ 212 break; 213 case 0x0803: 214 /* Motorola base module status register : read-only */ 215 break; 216 case 0x0808: 217 /* Hardfile light register */ 218 if (val & 1) 219 sysctrl->state |= STATE_HARDFILE; 220 else 221 sysctrl->state &= ~STATE_HARDFILE; 222 break; 223 case 0x0810: 224 /* Password protect 1 register */ 225 if (sysctrl->nvram != NULL) { 226 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 227 (k->toggle_lock)(sysctrl->nvram, 1); 228 } 229 break; 230 case 0x0812: 231 /* Password protect 2 register */ 232 if (sysctrl->nvram != NULL) { 233 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram); 234 (k->toggle_lock)(sysctrl->nvram, 2); 235 } 236 break; 237 case 0x0814: 238 /* L2 invalidate register */ 239 // tlb_flush(first_cpu, 1); 240 break; 241 case 0x081C: 242 /* system control register */ 243 sysctrl->syscontrol = val & 0x0F; 244 break; 245 case 0x0850: 246 /* I/O map type register */ 247 sysctrl->contiguous_map = val & 0x01; 248 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map); 249 break; 250 default: 251 printf("ERROR: unaffected IO port write: %04" PRIx32 252 " => %02" PRIx32"\n", addr, val); 253 break; 254 } 255 } 256 257 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) 258 { 259 sysctrl_t *sysctrl = opaque; 260 uint32_t retval = 0xFF; 261 262 switch (addr) { 263 case 0x0092: 264 /* Special port 92 */ 265 retval = sysctrl->endian << 1; 266 break; 267 case 0x0800: 268 /* Motorola CPU configuration register */ 269 retval = 0xEF; /* MPC750 */ 270 break; 271 case 0x0802: 272 /* Motorola Base module feature register */ 273 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ 274 break; 275 case 0x0803: 276 /* Motorola base module status register */ 277 retval = 0xE0; /* Standard MPC750 */ 278 break; 279 case 0x080C: 280 /* Equipment present register: 281 * no L2 cache 282 * no upgrade processor 283 * no cards in PCI slots 284 * SCSI fuse is bad 285 */ 286 retval = 0x3C; 287 break; 288 case 0x0810: 289 /* Motorola base module extended feature register */ 290 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ 291 break; 292 case 0x0814: 293 /* L2 invalidate: don't care */ 294 break; 295 case 0x0818: 296 /* Keylock */ 297 retval = 0x00; 298 break; 299 case 0x081C: 300 /* system control register 301 * 7 - 6 / 1 - 0: L2 cache enable 302 */ 303 retval = sysctrl->syscontrol; 304 break; 305 case 0x0823: 306 /* */ 307 retval = 0x03; /* no L2 cache */ 308 break; 309 case 0x0850: 310 /* I/O map type register */ 311 retval = sysctrl->contiguous_map; 312 break; 313 default: 314 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr); 315 break; 316 } 317 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval); 318 319 return retval; 320 } 321 322 323 #define NVRAM_SIZE 0x2000 324 325 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 326 Error **errp) 327 { 328 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 329 } 330 331 static void ppc_prep_reset(void *opaque) 332 { 333 PowerPCCPU *cpu = opaque; 334 335 cpu_reset(CPU(cpu)); 336 } 337 338 static const MemoryRegionPortio prep_portio_list[] = { 339 /* System control ports */ 340 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 341 { 0x0800, 0x52, 1, 342 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, }, 343 /* Special port to get debug messages from Open-Firmware */ 344 { 0x0F00, 4, 1, .write = PPC_debug_write, }, 345 PORTIO_END_OF_LIST(), 346 }; 347 348 static PortioList prep_port_list; 349 350 /*****************************************************************************/ 351 /* NVRAM helpers */ 352 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr) 353 { 354 NvramClass *k = NVRAM_GET_CLASS(nvram); 355 return (k->read)(nvram, addr); 356 } 357 358 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val) 359 { 360 NvramClass *k = NVRAM_GET_CLASS(nvram); 361 (k->write)(nvram, addr, val); 362 } 363 364 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value) 365 { 366 nvram_write(nvram, addr, value); 367 } 368 369 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr) 370 { 371 return nvram_read(nvram, addr); 372 } 373 374 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value) 375 { 376 nvram_write(nvram, addr, value >> 8); 377 nvram_write(nvram, addr + 1, value & 0xFF); 378 } 379 380 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr) 381 { 382 uint16_t tmp; 383 384 tmp = nvram_read(nvram, addr) << 8; 385 tmp |= nvram_read(nvram, addr + 1); 386 387 return tmp; 388 } 389 390 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value) 391 { 392 nvram_write(nvram, addr, value >> 24); 393 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); 394 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); 395 nvram_write(nvram, addr + 3, value & 0xFF); 396 } 397 398 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str, 399 uint32_t max) 400 { 401 int i; 402 403 for (i = 0; i < max && str[i] != '\0'; i++) { 404 nvram_write(nvram, addr + i, str[i]); 405 } 406 nvram_write(nvram, addr + i, str[i]); 407 nvram_write(nvram, addr + max - 1, '\0'); 408 } 409 410 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value) 411 { 412 uint16_t tmp; 413 uint16_t pd, pd1, pd2; 414 415 tmp = prev >> 8; 416 pd = prev ^ value; 417 pd1 = pd & 0x000F; 418 pd2 = ((pd >> 4) & 0x000F) ^ pd1; 419 tmp ^= (pd1 << 3) | (pd1 << 8); 420 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); 421 422 return tmp; 423 } 424 425 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count) 426 { 427 uint32_t i; 428 uint16_t crc = 0xFFFF; 429 int odd; 430 431 odd = count & 1; 432 count &= ~1; 433 for (i = 0; i != count; i++) { 434 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); 435 } 436 if (odd) { 437 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8); 438 } 439 440 return crc; 441 } 442 443 #define CMDLINE_ADDR 0x017ff000 444 445 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size, 446 const char *arch, 447 uint32_t RAM_size, int boot_device, 448 uint32_t kernel_image, uint32_t kernel_size, 449 const char *cmdline, 450 uint32_t initrd_image, uint32_t initrd_size, 451 uint32_t NVRAM_image, 452 int width, int height, int depth) 453 { 454 uint16_t crc; 455 456 /* Set parameters for Open Hack'Ware BIOS */ 457 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); 458 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ 459 NVRAM_set_word(nvram, 0x14, NVRAM_size); 460 NVRAM_set_string(nvram, 0x20, arch, 16); 461 NVRAM_set_lword(nvram, 0x30, RAM_size); 462 NVRAM_set_byte(nvram, 0x34, boot_device); 463 NVRAM_set_lword(nvram, 0x38, kernel_image); 464 NVRAM_set_lword(nvram, 0x3C, kernel_size); 465 if (cmdline) { 466 /* XXX: put the cmdline in NVRAM too ? */ 467 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, 468 cmdline); 469 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); 470 NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); 471 } else { 472 NVRAM_set_lword(nvram, 0x40, 0); 473 NVRAM_set_lword(nvram, 0x44, 0); 474 } 475 NVRAM_set_lword(nvram, 0x48, initrd_image); 476 NVRAM_set_lword(nvram, 0x4C, initrd_size); 477 NVRAM_set_lword(nvram, 0x50, NVRAM_image); 478 479 NVRAM_set_word(nvram, 0x54, width); 480 NVRAM_set_word(nvram, 0x56, height); 481 NVRAM_set_word(nvram, 0x58, depth); 482 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); 483 NVRAM_set_word(nvram, 0xFC, crc); 484 485 return 0; 486 } 487 488 /* PowerPC PREP hardware initialisation */ 489 static void ppc_prep_init(MachineState *machine) 490 { 491 ram_addr_t ram_size = machine->ram_size; 492 const char *kernel_filename = machine->kernel_filename; 493 const char *kernel_cmdline = machine->kernel_cmdline; 494 const char *initrd_filename = machine->initrd_filename; 495 const char *boot_device = machine->boot_order; 496 MemoryRegion *sysmem = get_system_memory(); 497 PowerPCCPU *cpu = NULL; 498 CPUPPCState *env = NULL; 499 Nvram *m48t59; 500 #if 0 501 MemoryRegion *xcsr = g_new(MemoryRegion, 1); 502 #endif 503 int linux_boot, i, nb_nics1; 504 MemoryRegion *ram = g_new(MemoryRegion, 1); 505 uint32_t kernel_base, initrd_base; 506 long kernel_size, initrd_size; 507 DeviceState *dev; 508 PCIHostState *pcihost; 509 PCIBus *pci_bus; 510 PCIDevice *pci; 511 ISABus *isa_bus; 512 ISADevice *isa; 513 int ppc_boot_device; 514 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 515 516 sysctrl = g_malloc0(sizeof(sysctrl_t)); 517 518 linux_boot = (kernel_filename != NULL); 519 520 /* init CPUs */ 521 for (i = 0; i < smp_cpus; i++) { 522 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 523 env = &cpu->env; 524 525 if (env->flags & POWERPC_FLAG_RTC_CLK) { 526 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 527 cpu_ppc_tb_init(env, 7812500UL); 528 } else { 529 /* Set time-base frequency to 100 Mhz */ 530 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 531 } 532 qemu_register_reset(ppc_prep_reset, cpu); 533 } 534 535 /* allocate RAM */ 536 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size); 537 memory_region_add_subregion(sysmem, 0, ram); 538 539 if (linux_boot) { 540 kernel_base = KERNEL_LOAD_ADDR; 541 /* now we can load the kernel */ 542 kernel_size = load_image_targphys(kernel_filename, kernel_base, 543 ram_size - kernel_base); 544 if (kernel_size < 0) { 545 error_report("could not load kernel '%s'", kernel_filename); 546 exit(1); 547 } 548 /* load initrd */ 549 if (initrd_filename) { 550 initrd_base = INITRD_LOAD_ADDR; 551 initrd_size = load_image_targphys(initrd_filename, initrd_base, 552 ram_size - initrd_base); 553 if (initrd_size < 0) { 554 error_report("could not load initial ram disk '%s'", 555 initrd_filename); 556 exit(1); 557 } 558 } else { 559 initrd_base = 0; 560 initrd_size = 0; 561 } 562 ppc_boot_device = 'm'; 563 } else { 564 kernel_base = 0; 565 kernel_size = 0; 566 initrd_base = 0; 567 initrd_size = 0; 568 ppc_boot_device = '\0'; 569 /* For now, OHW cannot boot from the network. */ 570 for (i = 0; boot_device[i] != '\0'; i++) { 571 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') { 572 ppc_boot_device = boot_device[i]; 573 break; 574 } 575 } 576 if (ppc_boot_device == '\0') { 577 error_report("No valid boot device for Mac99 machine"); 578 exit(1); 579 } 580 } 581 582 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 583 error_report("Only 6xx bus is supported on PREP machine"); 584 exit(1); 585 } 586 587 dev = qdev_create(NULL, "raven-pcihost"); 588 if (bios_name == NULL) { 589 bios_name = BIOS_FILENAME; 590 } 591 qdev_prop_set_string(dev, "bios-name", bios_name); 592 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 593 pcihost = PCI_HOST_BRIDGE(dev); 594 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 595 qdev_init_nofail(dev); 596 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0"); 597 if (pci_bus == NULL) { 598 error_report("Couldn't create PCI host controller"); 599 exit(1); 600 } 601 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0); 602 603 /* PCI -> ISA bridge */ 604 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); 605 cpu = POWERPC_CPU(first_cpu); 606 qdev_connect_gpio_out(&pci->qdev, 0, 607 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 608 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9)); 609 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11)); 610 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9)); 611 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11)); 612 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0")); 613 614 /* Super I/O (parallel + serial ports) */ 615 isa = isa_create(isa_bus, TYPE_PC87312_SUPERIO); 616 dev = DEVICE(isa); 617 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ 618 qdev_init_nofail(dev); 619 620 /* init basic PC hardware */ 621 pci_vga_init(pci_bus); 622 623 nb_nics1 = nb_nics; 624 if (nb_nics1 > NE2000_NB_MAX) 625 nb_nics1 = NE2000_NB_MAX; 626 for(i = 0; i < nb_nics1; i++) { 627 if (nd_table[i].model == NULL) { 628 nd_table[i].model = g_strdup("ne2k_isa"); 629 } 630 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) { 631 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i], 632 &nd_table[i]); 633 } else { 634 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 635 } 636 } 637 638 ide_drive_get(hd, ARRAY_SIZE(hd)); 639 for(i = 0; i < MAX_IDE_BUS; i++) { 640 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i], 641 hd[2 * i], 642 hd[2 * i + 1]); 643 } 644 645 cpu = POWERPC_CPU(first_cpu); 646 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET]; 647 648 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep"); 649 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0); 650 651 /* PowerPC control and status register group */ 652 #if 0 653 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); 654 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); 655 #endif 656 657 if (machine_usb(machine)) { 658 pci_create_simple(pci_bus, -1, "pci-ohci"); 659 } 660 661 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59); 662 if (m48t59 == NULL) 663 return; 664 sysctrl->nvram = m48t59; 665 666 /* Initialise NVRAM */ 667 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 668 ppc_boot_device, 669 kernel_base, kernel_size, 670 kernel_cmdline, 671 initrd_base, initrd_size, 672 /* XXX: need an option to load a NVRAM image */ 673 0, 674 graphic_width, graphic_height, graphic_depth); 675 } 676 677 static void prep_machine_init(MachineClass *mc) 678 { 679 mc->desc = "PowerPC PREP platform"; 680 mc->init = ppc_prep_init; 681 mc->block_default_type = IF_IDE; 682 mc->max_cpus = MAX_CPUS; 683 mc->default_boot_order = "cad"; 684 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("602"); 685 mc->default_display = "std"; 686 } 687 688 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque) 689 { 690 uint16_t checksum = *(uint16_t *)opaque; 691 ISADevice *rtc; 692 693 if (object_dynamic_cast(OBJECT(dev), "mc146818rtc")) { 694 rtc = ISA_DEVICE(dev); 695 rtc_set_memory(rtc, 0x2e, checksum & 0xff); 696 rtc_set_memory(rtc, 0x3e, checksum & 0xff); 697 rtc_set_memory(rtc, 0x2f, checksum >> 8); 698 rtc_set_memory(rtc, 0x3f, checksum >> 8); 699 } 700 return 0; 701 } 702 703 static void ibm_40p_init(MachineState *machine) 704 { 705 CPUPPCState *env = NULL; 706 uint16_t cmos_checksum; 707 PowerPCCPU *cpu; 708 DeviceState *dev; 709 SysBusDevice *pcihost; 710 Nvram *m48t59 = NULL; 711 PCIBus *pci_bus; 712 ISABus *isa_bus; 713 void *fw_cfg; 714 int i; 715 uint32_t kernel_base = 0, initrd_base = 0; 716 long kernel_size = 0, initrd_size = 0; 717 char boot_device; 718 719 /* init CPU */ 720 cpu = POWERPC_CPU(cpu_create(machine->cpu_type)); 721 env = &cpu->env; 722 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) { 723 error_report("only 6xx bus is supported on this machine"); 724 exit(1); 725 } 726 727 if (env->flags & POWERPC_FLAG_RTC_CLK) { 728 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ 729 cpu_ppc_tb_init(env, 7812500UL); 730 } else { 731 /* Set time-base frequency to 100 Mhz */ 732 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); 733 } 734 qemu_register_reset(ppc_prep_reset, cpu); 735 736 /* PCI host */ 737 dev = qdev_create(NULL, "raven-pcihost"); 738 if (!bios_name) { 739 bios_name = BIOS_FILENAME; 740 } 741 qdev_prop_set_string(dev, "bios-name", bios_name); 742 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE); 743 pcihost = SYS_BUS_DEVICE(dev); 744 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL); 745 qdev_init_nofail(dev); 746 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0")); 747 if (!pci_bus) { 748 error_report("could not create PCI host controller"); 749 exit(1); 750 } 751 752 /* PCI -> ISA bridge */ 753 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378")); 754 qdev_connect_gpio_out(dev, 0, 755 cpu->env.irq_inputs[PPC6xx_INPUT_INT]); 756 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(dev, 15)); 757 sysbus_connect_irq(pcihost, 1, qdev_get_gpio_in(dev, 13)); 758 sysbus_connect_irq(pcihost, 2, qdev_get_gpio_in(dev, 15)); 759 sysbus_connect_irq(pcihost, 3, qdev_get_gpio_in(dev, 13)); 760 isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); 761 762 /* Memory controller */ 763 dev = DEVICE(isa_create(isa_bus, "rs6000-mc")); 764 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size); 765 qdev_init_nofail(dev); 766 767 /* initialize CMOS checksums */ 768 cmos_checksum = 0x6aa9; 769 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL, 770 &cmos_checksum); 771 772 /* add some more devices */ 773 if (defaults_enabled()) { 774 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59")); 775 776 dev = DEVICE(isa_create(isa_bus, "cs4231a")); 777 qdev_prop_set_uint32(dev, "iobase", 0x830); 778 qdev_prop_set_uint32(dev, "irq", 10); 779 qdev_init_nofail(dev); 780 781 dev = DEVICE(isa_create(isa_bus, "pc87312")); 782 qdev_prop_set_uint32(dev, "config", 12); 783 qdev_init_nofail(dev); 784 785 dev = DEVICE(isa_create(isa_bus, "prep-systemio")); 786 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc); 787 qdev_prop_set_uint32(dev, "equipment", 0xc0); 788 qdev_init_nofail(dev); 789 790 lsi53c810_create(pci_bus, PCI_DEVFN(1, 0)); 791 792 /* XXX: s3-trio at PCI_DEVFN(2, 0) */ 793 pci_vga_init(pci_bus); 794 795 for (i = 0; i < nb_nics; i++) { 796 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet", 797 i == 0 ? "3" : NULL); 798 } 799 } 800 801 /* Prepare firmware configuration for OpenBIOS */ 802 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); 803 804 if (machine->kernel_filename) { 805 /* load kernel */ 806 kernel_base = KERNEL_LOAD_ADDR; 807 kernel_size = load_image_targphys(machine->kernel_filename, 808 kernel_base, 809 machine->ram_size - kernel_base); 810 if (kernel_size < 0) { 811 error_report("could not load kernel '%s'", 812 machine->kernel_filename); 813 exit(1); 814 } 815 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); 816 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 817 /* load initrd */ 818 if (machine->initrd_filename) { 819 initrd_base = INITRD_LOAD_ADDR; 820 initrd_size = load_image_targphys(machine->initrd_filename, 821 initrd_base, 822 machine->ram_size - initrd_base); 823 if (initrd_size < 0) { 824 error_report("could not load initial ram disk '%s'", 825 machine->initrd_filename); 826 exit(1); 827 } 828 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base); 829 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 830 } 831 if (machine->kernel_cmdline && *machine->kernel_cmdline) { 832 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 833 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 834 machine->kernel_cmdline); 835 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 836 machine->kernel_cmdline); 837 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 838 strlen(machine->kernel_cmdline) + 1); 839 } 840 boot_device = 'm'; 841 } else { 842 boot_device = machine->boot_order[0]; 843 } 844 845 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 846 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 847 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP); 848 849 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width); 850 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height); 851 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth); 852 853 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled()); 854 if (kvm_enabled()) { 855 #ifdef CONFIG_KVM 856 uint8_t *hypercall; 857 858 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq()); 859 hypercall = g_malloc(16); 860 kvmppc_get_hypercall(env, hypercall, 16); 861 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16); 862 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid()); 863 #endif 864 } else { 865 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND); 866 } 867 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device); 868 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 869 870 /* Prepare firmware configuration for Open Hack'Ware */ 871 if (m48t59) { 872 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size, 873 boot_device, 874 kernel_base, kernel_size, 875 machine->kernel_cmdline, 876 initrd_base, initrd_size, 877 /* XXX: need an option to load a NVRAM image */ 878 0, 879 graphic_width, graphic_height, graphic_depth); 880 } 881 } 882 883 static void ibm_40p_machine_init(MachineClass *mc) 884 { 885 mc->desc = "IBM RS/6000 7020 (40p)", 886 mc->init = ibm_40p_init; 887 mc->max_cpus = 1; 888 mc->default_ram_size = 128 * MiB; 889 mc->block_default_type = IF_SCSI; 890 mc->default_boot_order = "c"; 891 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604"); 892 mc->default_display = "std"; 893 } 894 895 DEFINE_MACHINE("40p", ibm_40p_machine_init) 896 DEFINE_MACHINE("prep", prep_machine_init) 897