1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "sysemu/sysemu.h" 29 #include "sysemu/numa.h" 30 #include "hw/hw.h" 31 #include "hw/fw-path-provider.h" 32 #include "elf.h" 33 #include "net/net.h" 34 #include "sysemu/device_tree.h" 35 #include "sysemu/block-backend.h" 36 #include "sysemu/cpus.h" 37 #include "sysemu/kvm.h" 38 #include "sysemu/device_tree.h" 39 #include "kvm_ppc.h" 40 #include "migration/migration.h" 41 #include "mmu-hash64.h" 42 #include "qom/cpu.h" 43 44 #include "hw/boards.h" 45 #include "hw/ppc/ppc.h" 46 #include "hw/loader.h" 47 48 #include "hw/ppc/spapr.h" 49 #include "hw/ppc/spapr_vio.h" 50 #include "hw/pci-host/spapr.h" 51 #include "hw/ppc/xics.h" 52 #include "hw/pci/msi.h" 53 54 #include "hw/pci/pci.h" 55 #include "hw/scsi/scsi.h" 56 #include "hw/virtio/virtio-scsi.h" 57 58 #include "exec/address-spaces.h" 59 #include "hw/usb.h" 60 #include "qemu/config-file.h" 61 #include "qemu/error-report.h" 62 #include "trace.h" 63 #include "hw/nmi.h" 64 65 #include "hw/compat.h" 66 #include "qemu-common.h" 67 68 #include <libfdt.h> 69 70 /* SLOF memory layout: 71 * 72 * SLOF raw image loaded at 0, copies its romfs right below the flat 73 * device-tree, then position SLOF itself 31M below that 74 * 75 * So we set FW_OVERHEAD to 40MB which should account for all of that 76 * and more 77 * 78 * We load our kernel at 4M, leaving space for SLOF initial image 79 */ 80 #define FDT_MAX_SIZE 0x100000 81 #define RTAS_MAX_SIZE 0x10000 82 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 83 #define FW_MAX_SIZE 0x400000 84 #define FW_FILE_NAME "slof.bin" 85 #define FW_OVERHEAD 0x2800000 86 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 87 88 #define MIN_RMA_SLOF 128UL 89 90 #define TIMEBASE_FREQ 512000000ULL 91 92 #define PHANDLE_XICP 0x00001111 93 94 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 95 96 static XICSState *try_create_xics(const char *type, int nr_servers, 97 int nr_irqs, Error **errp) 98 { 99 Error *err = NULL; 100 DeviceState *dev; 101 102 dev = qdev_create(NULL, type); 103 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 104 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 105 object_property_set_bool(OBJECT(dev), true, "realized", &err); 106 if (err) { 107 error_propagate(errp, err); 108 object_unparent(OBJECT(dev)); 109 return NULL; 110 } 111 return XICS_COMMON(dev); 112 } 113 114 static XICSState *xics_system_init(MachineState *machine, 115 int nr_servers, int nr_irqs, Error **errp) 116 { 117 XICSState *icp = NULL; 118 119 if (kvm_enabled()) { 120 Error *err = NULL; 121 122 if (machine_kernel_irqchip_allowed(machine)) { 123 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 124 } 125 if (machine_kernel_irqchip_required(machine) && !icp) { 126 error_reportf_err(err, 127 "kernel_irqchip requested but unavailable: "); 128 } else { 129 error_free(err); 130 } 131 } 132 133 if (!icp) { 134 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp); 135 } 136 137 return icp; 138 } 139 140 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 141 int smt_threads) 142 { 143 int i, ret = 0; 144 uint32_t servers_prop[smt_threads]; 145 uint32_t gservers_prop[smt_threads * 2]; 146 int index = ppc_get_vcpu_dt_id(cpu); 147 148 if (cpu->cpu_version) { 149 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 150 if (ret < 0) { 151 return ret; 152 } 153 } 154 155 /* Build interrupt servers and gservers properties */ 156 for (i = 0; i < smt_threads; i++) { 157 servers_prop[i] = cpu_to_be32(index + i); 158 /* Hack, direct the group queues back to cpu 0 */ 159 gservers_prop[i*2] = cpu_to_be32(index + i); 160 gservers_prop[i*2 + 1] = 0; 161 } 162 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 163 servers_prop, sizeof(servers_prop)); 164 if (ret < 0) { 165 return ret; 166 } 167 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 168 gservers_prop, sizeof(gservers_prop)); 169 170 return ret; 171 } 172 173 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 174 { 175 int ret = 0; 176 PowerPCCPU *cpu = POWERPC_CPU(cs); 177 int index = ppc_get_vcpu_dt_id(cpu); 178 uint32_t associativity[] = {cpu_to_be32(0x5), 179 cpu_to_be32(0x0), 180 cpu_to_be32(0x0), 181 cpu_to_be32(0x0), 182 cpu_to_be32(cs->numa_node), 183 cpu_to_be32(index)}; 184 185 /* Advertise NUMA via ibm,associativity */ 186 if (nb_numa_nodes > 1) { 187 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 188 sizeof(associativity)); 189 } 190 191 return ret; 192 } 193 194 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 195 { 196 int ret = 0, offset, cpus_offset; 197 CPUState *cs; 198 char cpu_model[32]; 199 int smt = kvmppc_smt_threads(); 200 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 201 202 CPU_FOREACH(cs) { 203 PowerPCCPU *cpu = POWERPC_CPU(cs); 204 DeviceClass *dc = DEVICE_GET_CLASS(cs); 205 int index = ppc_get_vcpu_dt_id(cpu); 206 207 if ((index % smt) != 0) { 208 continue; 209 } 210 211 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 212 213 cpus_offset = fdt_path_offset(fdt, "/cpus"); 214 if (cpus_offset < 0) { 215 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 216 "cpus"); 217 if (cpus_offset < 0) { 218 return cpus_offset; 219 } 220 } 221 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 222 if (offset < 0) { 223 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 224 if (offset < 0) { 225 return offset; 226 } 227 } 228 229 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 230 pft_size_prop, sizeof(pft_size_prop)); 231 if (ret < 0) { 232 return ret; 233 } 234 235 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 236 if (ret < 0) { 237 return ret; 238 } 239 240 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 241 ppc_get_compat_smt_threads(cpu)); 242 if (ret < 0) { 243 return ret; 244 } 245 } 246 return ret; 247 } 248 249 250 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 251 size_t maxsize) 252 { 253 size_t maxcells = maxsize / sizeof(uint32_t); 254 int i, j, count; 255 uint32_t *p = prop; 256 257 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 258 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 259 260 if (!sps->page_shift) { 261 break; 262 } 263 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 264 if (sps->enc[count].page_shift == 0) { 265 break; 266 } 267 } 268 if ((p - prop) >= (maxcells - 3 - count * 2)) { 269 break; 270 } 271 *(p++) = cpu_to_be32(sps->page_shift); 272 *(p++) = cpu_to_be32(sps->slb_enc); 273 *(p++) = cpu_to_be32(count); 274 for (j = 0; j < count; j++) { 275 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 276 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 277 } 278 } 279 280 return (p - prop) * sizeof(uint32_t); 281 } 282 283 static hwaddr spapr_node0_size(void) 284 { 285 MachineState *machine = MACHINE(qdev_get_machine()); 286 287 if (nb_numa_nodes) { 288 int i; 289 for (i = 0; i < nb_numa_nodes; ++i) { 290 if (numa_info[i].node_mem) { 291 return MIN(pow2floor(numa_info[i].node_mem), 292 machine->ram_size); 293 } 294 } 295 } 296 return machine->ram_size; 297 } 298 299 #define _FDT(exp) \ 300 do { \ 301 int ret = (exp); \ 302 if (ret < 0) { \ 303 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 304 #exp, fdt_strerror(ret)); \ 305 exit(1); \ 306 } \ 307 } while (0) 308 309 static void add_str(GString *s, const gchar *s1) 310 { 311 g_string_append_len(s, s1, strlen(s1) + 1); 312 } 313 314 static void *spapr_create_fdt_skel(hwaddr initrd_base, 315 hwaddr initrd_size, 316 hwaddr kernel_size, 317 bool little_endian, 318 const char *kernel_cmdline, 319 uint32_t epow_irq) 320 { 321 void *fdt; 322 uint32_t start_prop = cpu_to_be32(initrd_base); 323 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 324 GString *hypertas = g_string_sized_new(256); 325 GString *qemu_hypertas = g_string_sized_new(256); 326 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 327 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 328 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 329 char *buf; 330 331 add_str(hypertas, "hcall-pft"); 332 add_str(hypertas, "hcall-term"); 333 add_str(hypertas, "hcall-dabr"); 334 add_str(hypertas, "hcall-interrupt"); 335 add_str(hypertas, "hcall-tce"); 336 add_str(hypertas, "hcall-vio"); 337 add_str(hypertas, "hcall-splpar"); 338 add_str(hypertas, "hcall-bulk"); 339 add_str(hypertas, "hcall-set-mode"); 340 add_str(qemu_hypertas, "hcall-memop1"); 341 342 fdt = g_malloc0(FDT_MAX_SIZE); 343 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 344 345 if (kernel_size) { 346 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 347 } 348 if (initrd_size) { 349 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 350 } 351 _FDT((fdt_finish_reservemap(fdt))); 352 353 /* Root node */ 354 _FDT((fdt_begin_node(fdt, ""))); 355 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 356 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 357 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 358 359 /* 360 * Add info to guest to indentify which host is it being run on 361 * and what is the uuid of the guest 362 */ 363 if (kvmppc_get_host_model(&buf)) { 364 _FDT((fdt_property_string(fdt, "host-model", buf))); 365 g_free(buf); 366 } 367 if (kvmppc_get_host_serial(&buf)) { 368 _FDT((fdt_property_string(fdt, "host-serial", buf))); 369 g_free(buf); 370 } 371 372 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 373 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 374 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 375 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 376 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 377 qemu_uuid[14], qemu_uuid[15]); 378 379 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 380 if (qemu_uuid_set) { 381 _FDT((fdt_property_string(fdt, "system-id", buf))); 382 } 383 g_free(buf); 384 385 if (qemu_get_vm_name()) { 386 _FDT((fdt_property_string(fdt, "ibm,partition-name", 387 qemu_get_vm_name()))); 388 } 389 390 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 391 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 392 393 /* /chosen */ 394 _FDT((fdt_begin_node(fdt, "chosen"))); 395 396 /* Set Form1_affinity */ 397 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 398 399 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 400 _FDT((fdt_property(fdt, "linux,initrd-start", 401 &start_prop, sizeof(start_prop)))); 402 _FDT((fdt_property(fdt, "linux,initrd-end", 403 &end_prop, sizeof(end_prop)))); 404 if (kernel_size) { 405 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 406 cpu_to_be64(kernel_size) }; 407 408 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 409 if (little_endian) { 410 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 411 } 412 } 413 if (boot_menu) { 414 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 415 } 416 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 417 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 418 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 419 420 _FDT((fdt_end_node(fdt))); 421 422 /* RTAS */ 423 _FDT((fdt_begin_node(fdt, "rtas"))); 424 425 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 426 add_str(hypertas, "hcall-multi-tce"); 427 } 428 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 429 hypertas->len))); 430 g_string_free(hypertas, TRUE); 431 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 432 qemu_hypertas->len))); 433 g_string_free(qemu_hypertas, TRUE); 434 435 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 436 refpoints, sizeof(refpoints)))); 437 438 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 439 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 440 RTAS_EVENT_SCAN_RATE))); 441 442 if (msi_supported) { 443 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 444 } 445 446 /* 447 * According to PAPR, rtas ibm,os-term does not guarantee a return 448 * back to the guest cpu. 449 * 450 * While an additional ibm,extended-os-term property indicates that 451 * rtas call return will always occur. Set this property. 452 */ 453 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 454 455 _FDT((fdt_end_node(fdt))); 456 457 /* interrupt controller */ 458 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 459 460 _FDT((fdt_property_string(fdt, "device_type", 461 "PowerPC-External-Interrupt-Presentation"))); 462 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 463 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 464 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 465 interrupt_server_ranges_prop, 466 sizeof(interrupt_server_ranges_prop)))); 467 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 468 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 469 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 470 471 _FDT((fdt_end_node(fdt))); 472 473 /* vdevice */ 474 _FDT((fdt_begin_node(fdt, "vdevice"))); 475 476 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 477 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 478 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 479 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 480 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 481 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 482 483 _FDT((fdt_end_node(fdt))); 484 485 /* event-sources */ 486 spapr_events_fdt_skel(fdt, epow_irq); 487 488 /* /hypervisor node */ 489 if (kvm_enabled()) { 490 uint8_t hypercall[16]; 491 492 /* indicate KVM hypercall interface */ 493 _FDT((fdt_begin_node(fdt, "hypervisor"))); 494 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 495 if (kvmppc_has_cap_fixup_hcalls()) { 496 /* 497 * Older KVM versions with older guest kernels were broken with the 498 * magic page, don't allow the guest to map it. 499 */ 500 kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 501 sizeof(hypercall)); 502 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 503 sizeof(hypercall)))); 504 } 505 _FDT((fdt_end_node(fdt))); 506 } 507 508 _FDT((fdt_end_node(fdt))); /* close root node */ 509 _FDT((fdt_finish(fdt))); 510 511 return fdt; 512 } 513 514 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 515 hwaddr size) 516 { 517 uint32_t associativity[] = { 518 cpu_to_be32(0x4), /* length */ 519 cpu_to_be32(0x0), cpu_to_be32(0x0), 520 cpu_to_be32(0x0), cpu_to_be32(nodeid) 521 }; 522 char mem_name[32]; 523 uint64_t mem_reg_property[2]; 524 int off; 525 526 mem_reg_property[0] = cpu_to_be64(start); 527 mem_reg_property[1] = cpu_to_be64(size); 528 529 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 530 off = fdt_add_subnode(fdt, 0, mem_name); 531 _FDT(off); 532 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 533 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 534 sizeof(mem_reg_property)))); 535 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 536 sizeof(associativity)))); 537 return off; 538 } 539 540 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 541 { 542 MachineState *machine = MACHINE(spapr); 543 hwaddr mem_start, node_size; 544 int i, nb_nodes = nb_numa_nodes; 545 NodeInfo *nodes = numa_info; 546 NodeInfo ramnode; 547 548 /* No NUMA nodes, assume there is just one node with whole RAM */ 549 if (!nb_numa_nodes) { 550 nb_nodes = 1; 551 ramnode.node_mem = machine->ram_size; 552 nodes = &ramnode; 553 } 554 555 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 556 if (!nodes[i].node_mem) { 557 continue; 558 } 559 if (mem_start >= machine->ram_size) { 560 node_size = 0; 561 } else { 562 node_size = nodes[i].node_mem; 563 if (node_size > machine->ram_size - mem_start) { 564 node_size = machine->ram_size - mem_start; 565 } 566 } 567 if (!mem_start) { 568 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 569 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 570 mem_start += spapr->rma_size; 571 node_size -= spapr->rma_size; 572 } 573 for ( ; node_size; ) { 574 hwaddr sizetmp = pow2floor(node_size); 575 576 /* mem_start != 0 here */ 577 if (ctzl(mem_start) < ctzl(sizetmp)) { 578 sizetmp = 1ULL << ctzl(mem_start); 579 } 580 581 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 582 node_size -= sizetmp; 583 mem_start += sizetmp; 584 } 585 } 586 587 return 0; 588 } 589 590 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 591 sPAPRMachineState *spapr) 592 { 593 PowerPCCPU *cpu = POWERPC_CPU(cs); 594 CPUPPCState *env = &cpu->env; 595 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 596 int index = ppc_get_vcpu_dt_id(cpu); 597 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 598 0xffffffff, 0xffffffff}; 599 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 600 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 601 uint32_t page_sizes_prop[64]; 602 size_t page_sizes_prop_size; 603 uint32_t vcpus_per_socket = smp_threads * smp_cores; 604 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 605 606 /* Note: we keep CI large pages off for now because a 64K capable guest 607 * provisioned with large pages might otherwise try to map a qemu 608 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 609 * even if that qemu runs on a 4k host. 610 * 611 * We can later add this bit back when we are confident this is not 612 * an issue (!HV KVM or 64K host) 613 */ 614 uint8_t pa_features_206[] = { 6, 0, 615 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 616 uint8_t pa_features_207[] = { 24, 0, 617 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 618 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 619 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 620 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 621 uint8_t *pa_features; 622 size_t pa_size; 623 624 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 625 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 626 627 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 628 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 629 env->dcache_line_size))); 630 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 631 env->dcache_line_size))); 632 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 633 env->icache_line_size))); 634 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 635 env->icache_line_size))); 636 637 if (pcc->l1_dcache_size) { 638 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 639 pcc->l1_dcache_size))); 640 } else { 641 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 642 } 643 if (pcc->l1_icache_size) { 644 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 645 pcc->l1_icache_size))); 646 } else { 647 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 648 } 649 650 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 651 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 652 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 653 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 654 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 655 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 656 657 if (env->spr_cb[SPR_PURR].oea_read) { 658 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 659 } 660 661 if (env->mmu_model & POWERPC_MMU_1TSEG) { 662 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 663 segs, sizeof(segs)))); 664 } 665 666 /* Advertise VMX/VSX (vector extensions) if available 667 * 0 / no property == no vector extensions 668 * 1 == VMX / Altivec available 669 * 2 == VSX available */ 670 if (env->insns_flags & PPC_ALTIVEC) { 671 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 672 673 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 674 } 675 676 /* Advertise DFP (Decimal Floating Point) if available 677 * 0 / no property == no DFP 678 * 1 == DFP available */ 679 if (env->insns_flags2 & PPC2_DFP) { 680 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 681 } 682 683 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 684 sizeof(page_sizes_prop)); 685 if (page_sizes_prop_size) { 686 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 687 page_sizes_prop, page_sizes_prop_size))); 688 } 689 690 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 691 if (env->mmu_model == POWERPC_MMU_2_06) { 692 pa_features = pa_features_206; 693 pa_size = sizeof(pa_features_206); 694 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 695 pa_features = pa_features_207; 696 pa_size = sizeof(pa_features_207); 697 } 698 if (env->ci_large_pages) { 699 pa_features[3] |= 0x20; 700 } 701 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 702 703 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 704 cs->cpu_index / vcpus_per_socket))); 705 706 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 707 pft_size_prop, sizeof(pft_size_prop)))); 708 709 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 710 711 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 712 ppc_get_compat_smt_threads(cpu))); 713 } 714 715 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 716 { 717 CPUState *cs; 718 int cpus_offset; 719 char *nodename; 720 int smt = kvmppc_smt_threads(); 721 722 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 723 _FDT(cpus_offset); 724 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 725 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 726 727 /* 728 * We walk the CPUs in reverse order to ensure that CPU DT nodes 729 * created by fdt_add_subnode() end up in the right order in FDT 730 * for the guest kernel the enumerate the CPUs correctly. 731 */ 732 CPU_FOREACH_REVERSE(cs) { 733 PowerPCCPU *cpu = POWERPC_CPU(cs); 734 int index = ppc_get_vcpu_dt_id(cpu); 735 DeviceClass *dc = DEVICE_GET_CLASS(cs); 736 int offset; 737 738 if ((index % smt) != 0) { 739 continue; 740 } 741 742 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 743 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 744 g_free(nodename); 745 _FDT(offset); 746 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 747 } 748 749 } 750 751 /* 752 * Adds ibm,dynamic-reconfiguration-memory node. 753 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 754 * of this device tree node. 755 */ 756 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 757 { 758 MachineState *machine = MACHINE(spapr); 759 int ret, i, offset; 760 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 761 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 762 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 763 uint32_t *int_buf, *cur_index, buf_len; 764 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 765 766 /* 767 * Don't create the node if there are no DR LMBs. 768 */ 769 if (!nr_lmbs) { 770 return 0; 771 } 772 773 /* 774 * Allocate enough buffer size to fit in ibm,dynamic-memory 775 * or ibm,associativity-lookup-arrays 776 */ 777 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 778 * sizeof(uint32_t); 779 cur_index = int_buf = g_malloc0(buf_len); 780 781 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 782 783 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 784 sizeof(prop_lmb_size)); 785 if (ret < 0) { 786 goto out; 787 } 788 789 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 790 if (ret < 0) { 791 goto out; 792 } 793 794 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 795 if (ret < 0) { 796 goto out; 797 } 798 799 /* ibm,dynamic-memory */ 800 int_buf[0] = cpu_to_be32(nr_lmbs); 801 cur_index++; 802 for (i = 0; i < nr_lmbs; i++) { 803 sPAPRDRConnector *drc; 804 sPAPRDRConnectorClass *drck; 805 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;; 806 uint32_t *dynamic_memory = cur_index; 807 808 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 809 addr/lmb_size); 810 g_assert(drc); 811 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 812 813 dynamic_memory[0] = cpu_to_be32(addr >> 32); 814 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 815 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 816 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 817 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 818 if (addr < machine->ram_size || 819 memory_region_present(get_system_memory(), addr)) { 820 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 821 } else { 822 dynamic_memory[5] = cpu_to_be32(0); 823 } 824 825 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 826 } 827 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 828 if (ret < 0) { 829 goto out; 830 } 831 832 /* ibm,associativity-lookup-arrays */ 833 cur_index = int_buf; 834 int_buf[0] = cpu_to_be32(nr_nodes); 835 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 836 cur_index += 2; 837 for (i = 0; i < nr_nodes; i++) { 838 uint32_t associativity[] = { 839 cpu_to_be32(0x0), 840 cpu_to_be32(0x0), 841 cpu_to_be32(0x0), 842 cpu_to_be32(i) 843 }; 844 memcpy(cur_index, associativity, sizeof(associativity)); 845 cur_index += 4; 846 } 847 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 848 (cur_index - int_buf) * sizeof(uint32_t)); 849 out: 850 g_free(int_buf); 851 return ret; 852 } 853 854 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 855 target_ulong addr, target_ulong size, 856 bool cpu_update, bool memory_update) 857 { 858 void *fdt, *fdt_skel; 859 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 860 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 861 862 size -= sizeof(hdr); 863 864 /* Create sceleton */ 865 fdt_skel = g_malloc0(size); 866 _FDT((fdt_create(fdt_skel, size))); 867 _FDT((fdt_begin_node(fdt_skel, ""))); 868 _FDT((fdt_end_node(fdt_skel))); 869 _FDT((fdt_finish(fdt_skel))); 870 fdt = g_malloc0(size); 871 _FDT((fdt_open_into(fdt_skel, fdt, size))); 872 g_free(fdt_skel); 873 874 /* Fixup cpu nodes */ 875 if (cpu_update) { 876 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 877 } 878 879 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 880 if (memory_update && smc->dr_lmb_enabled) { 881 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 882 } 883 884 /* Pack resulting tree */ 885 _FDT((fdt_pack(fdt))); 886 887 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 888 trace_spapr_cas_failed(size); 889 return -1; 890 } 891 892 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 893 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 894 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 895 g_free(fdt); 896 897 return 0; 898 } 899 900 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 901 hwaddr fdt_addr, 902 hwaddr rtas_addr, 903 hwaddr rtas_size) 904 { 905 MachineState *machine = MACHINE(qdev_get_machine()); 906 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 907 const char *boot_device = machine->boot_order; 908 int ret, i; 909 size_t cb = 0; 910 char *bootlist; 911 void *fdt; 912 sPAPRPHBState *phb; 913 914 fdt = g_malloc(FDT_MAX_SIZE); 915 916 /* open out the base tree into a temp buffer for the final tweaks */ 917 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 918 919 ret = spapr_populate_memory(spapr, fdt); 920 if (ret < 0) { 921 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 922 exit(1); 923 } 924 925 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 926 if (ret < 0) { 927 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 928 exit(1); 929 } 930 931 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 932 ret = spapr_rng_populate_dt(fdt); 933 if (ret < 0) { 934 fprintf(stderr, "could not set up rng device in the fdt\n"); 935 exit(1); 936 } 937 } 938 939 QLIST_FOREACH(phb, &spapr->phbs, list) { 940 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 941 } 942 943 if (ret < 0) { 944 fprintf(stderr, "couldn't setup PCI devices in fdt\n"); 945 exit(1); 946 } 947 948 /* RTAS */ 949 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 950 if (ret < 0) { 951 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 952 } 953 954 /* cpus */ 955 spapr_populate_cpus_dt_node(fdt, spapr); 956 957 bootlist = get_boot_devices_list(&cb, true); 958 if (cb && bootlist) { 959 int offset = fdt_path_offset(fdt, "/chosen"); 960 if (offset < 0) { 961 exit(1); 962 } 963 for (i = 0; i < cb; i++) { 964 if (bootlist[i] == '\n') { 965 bootlist[i] = ' '; 966 } 967 968 } 969 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 970 } 971 972 if (boot_device && strlen(boot_device)) { 973 int offset = fdt_path_offset(fdt, "/chosen"); 974 975 if (offset < 0) { 976 exit(1); 977 } 978 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 979 } 980 981 if (!spapr->has_graphics) { 982 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 983 } 984 985 if (smc->dr_lmb_enabled) { 986 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 987 } 988 989 _FDT((fdt_pack(fdt))); 990 991 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 992 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 993 fdt_totalsize(fdt), FDT_MAX_SIZE); 994 exit(1); 995 } 996 997 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 998 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 999 1000 g_free(bootlist); 1001 g_free(fdt); 1002 } 1003 1004 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1005 { 1006 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1007 } 1008 1009 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 1010 { 1011 CPUPPCState *env = &cpu->env; 1012 1013 if (msr_pr) { 1014 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1015 env->gpr[3] = H_PRIVILEGE; 1016 } else { 1017 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1018 } 1019 } 1020 1021 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1022 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1023 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1024 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1025 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1026 1027 /* 1028 * Get the fd to access the kernel htab, re-opening it if necessary 1029 */ 1030 static int get_htab_fd(sPAPRMachineState *spapr) 1031 { 1032 if (spapr->htab_fd >= 0) { 1033 return spapr->htab_fd; 1034 } 1035 1036 spapr->htab_fd = kvmppc_get_htab_fd(false); 1037 if (spapr->htab_fd < 0) { 1038 error_report("Unable to open fd for reading hash table from KVM: %s", 1039 strerror(errno)); 1040 } 1041 1042 return spapr->htab_fd; 1043 } 1044 1045 static void close_htab_fd(sPAPRMachineState *spapr) 1046 { 1047 if (spapr->htab_fd >= 0) { 1048 close(spapr->htab_fd); 1049 } 1050 spapr->htab_fd = -1; 1051 } 1052 1053 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1054 { 1055 int shift; 1056 1057 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1058 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1059 * that's much more than is needed for Linux guests */ 1060 shift = ctz64(pow2ceil(ramsize)) - 7; 1061 shift = MAX(shift, 18); /* Minimum architected size */ 1062 shift = MIN(shift, 46); /* Maximum architected size */ 1063 return shift; 1064 } 1065 1066 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1067 Error **errp) 1068 { 1069 long rc; 1070 1071 /* Clean up any HPT info from a previous boot */ 1072 g_free(spapr->htab); 1073 spapr->htab = NULL; 1074 spapr->htab_shift = 0; 1075 close_htab_fd(spapr); 1076 1077 rc = kvmppc_reset_htab(shift); 1078 if (rc < 0) { 1079 /* kernel-side HPT needed, but couldn't allocate one */ 1080 error_setg_errno(errp, errno, 1081 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1082 shift); 1083 /* This is almost certainly fatal, but if the caller really 1084 * wants to carry on with shift == 0, it's welcome to try */ 1085 } else if (rc > 0) { 1086 /* kernel-side HPT allocated */ 1087 if (rc != shift) { 1088 error_setg(errp, 1089 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1090 shift, rc); 1091 } 1092 1093 spapr->htab_shift = shift; 1094 kvmppc_kern_htab = true; 1095 } else { 1096 /* kernel-side HPT not needed, allocate in userspace instead */ 1097 size_t size = 1ULL << shift; 1098 int i; 1099 1100 spapr->htab = qemu_memalign(size, size); 1101 if (!spapr->htab) { 1102 error_setg_errno(errp, errno, 1103 "Could not allocate HPT of order %d", shift); 1104 return; 1105 } 1106 1107 memset(spapr->htab, 0, size); 1108 spapr->htab_shift = shift; 1109 kvmppc_kern_htab = false; 1110 1111 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1112 DIRTY_HPTE(HPTE(spapr->htab, i)); 1113 } 1114 } 1115 } 1116 1117 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1118 { 1119 bool matched = false; 1120 1121 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1122 matched = true; 1123 } 1124 1125 if (!matched) { 1126 error_report("Device %s is not supported by this machine yet.", 1127 qdev_fw_name(DEVICE(sbdev))); 1128 exit(1); 1129 } 1130 1131 return 0; 1132 } 1133 1134 static void ppc_spapr_reset(void) 1135 { 1136 MachineState *machine = MACHINE(qdev_get_machine()); 1137 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1138 PowerPCCPU *first_ppc_cpu; 1139 uint32_t rtas_limit; 1140 1141 /* Check for unknown sysbus devices */ 1142 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1143 1144 /* Allocate and/or reset the hash page table */ 1145 spapr_reallocate_hpt(spapr, 1146 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1147 &error_fatal); 1148 1149 /* Update the RMA size if necessary */ 1150 if (spapr->vrma_adjust) { 1151 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1152 spapr->htab_shift); 1153 } 1154 1155 qemu_devices_reset(); 1156 1157 /* 1158 * We place the device tree and RTAS just below either the top of the RMA, 1159 * or just below 2GB, whichever is lowere, so that it can be 1160 * processed with 32-bit real mode code if necessary 1161 */ 1162 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1163 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1164 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1165 1166 /* Load the fdt */ 1167 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1168 spapr->rtas_size); 1169 1170 /* Copy RTAS over */ 1171 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1172 spapr->rtas_size); 1173 1174 /* Set up the entry state */ 1175 first_ppc_cpu = POWERPC_CPU(first_cpu); 1176 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1177 first_ppc_cpu->env.gpr[5] = 0; 1178 first_cpu->halted = 0; 1179 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1180 1181 } 1182 1183 static void spapr_cpu_reset(void *opaque) 1184 { 1185 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1186 PowerPCCPU *cpu = opaque; 1187 CPUState *cs = CPU(cpu); 1188 CPUPPCState *env = &cpu->env; 1189 1190 cpu_reset(cs); 1191 1192 /* All CPUs start halted. CPU0 is unhalted from the machine level 1193 * reset code and the rest are explicitly started up by the guest 1194 * using an RTAS call */ 1195 cs->halted = 1; 1196 1197 env->spr[SPR_HIOR] = 0; 1198 1199 env->external_htab = (uint8_t *)spapr->htab; 1200 env->htab_base = -1; 1201 /* 1202 * htab_mask is the mask used to normalize hash value to PTEG index. 1203 * htab_shift is log2 of hash table size. 1204 * We have 8 hpte per group, and each hpte is 16 bytes. 1205 * ie have 128 bytes per hpte entry. 1206 */ 1207 env->htab_mask = (1ULL << (spapr->htab_shift - 7)) - 1; 1208 env->spr[SPR_SDR1] = (target_ulong)(uintptr_t)spapr->htab | 1209 (spapr->htab_shift - 18); 1210 } 1211 1212 static void spapr_create_nvram(sPAPRMachineState *spapr) 1213 { 1214 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1215 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1216 1217 if (dinfo) { 1218 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1219 &error_fatal); 1220 } 1221 1222 qdev_init_nofail(dev); 1223 1224 spapr->nvram = (struct sPAPRNVRAM *)dev; 1225 } 1226 1227 static void spapr_rtc_create(sPAPRMachineState *spapr) 1228 { 1229 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1230 1231 qdev_init_nofail(dev); 1232 spapr->rtc = dev; 1233 1234 object_property_add_alias(qdev_get_machine(), "rtc-time", 1235 OBJECT(spapr->rtc), "date", NULL); 1236 } 1237 1238 /* Returns whether we want to use VGA or not */ 1239 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1240 { 1241 switch (vga_interface_type) { 1242 case VGA_NONE: 1243 return false; 1244 case VGA_DEVICE: 1245 return true; 1246 case VGA_STD: 1247 case VGA_VIRTIO: 1248 return pci_vga_init(pci_bus) != NULL; 1249 default: 1250 error_setg(errp, 1251 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1252 return false; 1253 } 1254 } 1255 1256 static int spapr_post_load(void *opaque, int version_id) 1257 { 1258 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1259 int err = 0; 1260 1261 /* In earlier versions, there was no separate qdev for the PAPR 1262 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1263 * So when migrating from those versions, poke the incoming offset 1264 * value into the RTC device */ 1265 if (version_id < 3) { 1266 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1267 } 1268 1269 return err; 1270 } 1271 1272 static bool version_before_3(void *opaque, int version_id) 1273 { 1274 return version_id < 3; 1275 } 1276 1277 static const VMStateDescription vmstate_spapr = { 1278 .name = "spapr", 1279 .version_id = 3, 1280 .minimum_version_id = 1, 1281 .post_load = spapr_post_load, 1282 .fields = (VMStateField[]) { 1283 /* used to be @next_irq */ 1284 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1285 1286 /* RTC offset */ 1287 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1288 1289 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1290 VMSTATE_END_OF_LIST() 1291 }, 1292 }; 1293 1294 static int htab_save_setup(QEMUFile *f, void *opaque) 1295 { 1296 sPAPRMachineState *spapr = opaque; 1297 1298 /* "Iteration" header */ 1299 qemu_put_be32(f, spapr->htab_shift); 1300 1301 if (spapr->htab) { 1302 spapr->htab_save_index = 0; 1303 spapr->htab_first_pass = true; 1304 } else { 1305 assert(kvm_enabled()); 1306 } 1307 1308 1309 return 0; 1310 } 1311 1312 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1313 int64_t max_ns) 1314 { 1315 bool has_timeout = max_ns != -1; 1316 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1317 int index = spapr->htab_save_index; 1318 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1319 1320 assert(spapr->htab_first_pass); 1321 1322 do { 1323 int chunkstart; 1324 1325 /* Consume invalid HPTEs */ 1326 while ((index < htabslots) 1327 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1328 index++; 1329 CLEAN_HPTE(HPTE(spapr->htab, index)); 1330 } 1331 1332 /* Consume valid HPTEs */ 1333 chunkstart = index; 1334 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1335 && HPTE_VALID(HPTE(spapr->htab, index))) { 1336 index++; 1337 CLEAN_HPTE(HPTE(spapr->htab, index)); 1338 } 1339 1340 if (index > chunkstart) { 1341 int n_valid = index - chunkstart; 1342 1343 qemu_put_be32(f, chunkstart); 1344 qemu_put_be16(f, n_valid); 1345 qemu_put_be16(f, 0); 1346 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1347 HASH_PTE_SIZE_64 * n_valid); 1348 1349 if (has_timeout && 1350 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1351 break; 1352 } 1353 } 1354 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1355 1356 if (index >= htabslots) { 1357 assert(index == htabslots); 1358 index = 0; 1359 spapr->htab_first_pass = false; 1360 } 1361 spapr->htab_save_index = index; 1362 } 1363 1364 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1365 int64_t max_ns) 1366 { 1367 bool final = max_ns < 0; 1368 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1369 int examined = 0, sent = 0; 1370 int index = spapr->htab_save_index; 1371 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1372 1373 assert(!spapr->htab_first_pass); 1374 1375 do { 1376 int chunkstart, invalidstart; 1377 1378 /* Consume non-dirty HPTEs */ 1379 while ((index < htabslots) 1380 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1381 index++; 1382 examined++; 1383 } 1384 1385 chunkstart = index; 1386 /* Consume valid dirty HPTEs */ 1387 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1388 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1389 && HPTE_VALID(HPTE(spapr->htab, index))) { 1390 CLEAN_HPTE(HPTE(spapr->htab, index)); 1391 index++; 1392 examined++; 1393 } 1394 1395 invalidstart = index; 1396 /* Consume invalid dirty HPTEs */ 1397 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1398 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1399 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1400 CLEAN_HPTE(HPTE(spapr->htab, index)); 1401 index++; 1402 examined++; 1403 } 1404 1405 if (index > chunkstart) { 1406 int n_valid = invalidstart - chunkstart; 1407 int n_invalid = index - invalidstart; 1408 1409 qemu_put_be32(f, chunkstart); 1410 qemu_put_be16(f, n_valid); 1411 qemu_put_be16(f, n_invalid); 1412 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1413 HASH_PTE_SIZE_64 * n_valid); 1414 sent += index - chunkstart; 1415 1416 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1417 break; 1418 } 1419 } 1420 1421 if (examined >= htabslots) { 1422 break; 1423 } 1424 1425 if (index >= htabslots) { 1426 assert(index == htabslots); 1427 index = 0; 1428 } 1429 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1430 1431 if (index >= htabslots) { 1432 assert(index == htabslots); 1433 index = 0; 1434 } 1435 1436 spapr->htab_save_index = index; 1437 1438 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1439 } 1440 1441 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1442 #define MAX_KVM_BUF_SIZE 2048 1443 1444 static int htab_save_iterate(QEMUFile *f, void *opaque) 1445 { 1446 sPAPRMachineState *spapr = opaque; 1447 int fd; 1448 int rc = 0; 1449 1450 /* Iteration header */ 1451 qemu_put_be32(f, 0); 1452 1453 if (!spapr->htab) { 1454 assert(kvm_enabled()); 1455 1456 fd = get_htab_fd(spapr); 1457 if (fd < 0) { 1458 return fd; 1459 } 1460 1461 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1462 if (rc < 0) { 1463 return rc; 1464 } 1465 } else if (spapr->htab_first_pass) { 1466 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1467 } else { 1468 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1469 } 1470 1471 /* End marker */ 1472 qemu_put_be32(f, 0); 1473 qemu_put_be16(f, 0); 1474 qemu_put_be16(f, 0); 1475 1476 return rc; 1477 } 1478 1479 static int htab_save_complete(QEMUFile *f, void *opaque) 1480 { 1481 sPAPRMachineState *spapr = opaque; 1482 int fd; 1483 1484 /* Iteration header */ 1485 qemu_put_be32(f, 0); 1486 1487 if (!spapr->htab) { 1488 int rc; 1489 1490 assert(kvm_enabled()); 1491 1492 fd = get_htab_fd(spapr); 1493 if (fd < 0) { 1494 return fd; 1495 } 1496 1497 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1498 if (rc < 0) { 1499 return rc; 1500 } 1501 close_htab_fd(spapr); 1502 } else { 1503 if (spapr->htab_first_pass) { 1504 htab_save_first_pass(f, spapr, -1); 1505 } 1506 htab_save_later_pass(f, spapr, -1); 1507 } 1508 1509 /* End marker */ 1510 qemu_put_be32(f, 0); 1511 qemu_put_be16(f, 0); 1512 qemu_put_be16(f, 0); 1513 1514 return 0; 1515 } 1516 1517 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1518 { 1519 sPAPRMachineState *spapr = opaque; 1520 uint32_t section_hdr; 1521 int fd = -1; 1522 1523 if (version_id < 1 || version_id > 1) { 1524 error_report("htab_load() bad version"); 1525 return -EINVAL; 1526 } 1527 1528 section_hdr = qemu_get_be32(f); 1529 1530 if (section_hdr) { 1531 Error *local_err = NULL; 1532 1533 /* First section gives the htab size */ 1534 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1535 if (local_err) { 1536 error_report_err(local_err); 1537 return -EINVAL; 1538 } 1539 return 0; 1540 } 1541 1542 if (!spapr->htab) { 1543 assert(kvm_enabled()); 1544 1545 fd = kvmppc_get_htab_fd(true); 1546 if (fd < 0) { 1547 error_report("Unable to open fd to restore KVM hash table: %s", 1548 strerror(errno)); 1549 } 1550 } 1551 1552 while (true) { 1553 uint32_t index; 1554 uint16_t n_valid, n_invalid; 1555 1556 index = qemu_get_be32(f); 1557 n_valid = qemu_get_be16(f); 1558 n_invalid = qemu_get_be16(f); 1559 1560 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1561 /* End of Stream */ 1562 break; 1563 } 1564 1565 if ((index + n_valid + n_invalid) > 1566 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1567 /* Bad index in stream */ 1568 error_report( 1569 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1570 index, n_valid, n_invalid, spapr->htab_shift); 1571 return -EINVAL; 1572 } 1573 1574 if (spapr->htab) { 1575 if (n_valid) { 1576 qemu_get_buffer(f, HPTE(spapr->htab, index), 1577 HASH_PTE_SIZE_64 * n_valid); 1578 } 1579 if (n_invalid) { 1580 memset(HPTE(spapr->htab, index + n_valid), 0, 1581 HASH_PTE_SIZE_64 * n_invalid); 1582 } 1583 } else { 1584 int rc; 1585 1586 assert(fd >= 0); 1587 1588 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1589 if (rc < 0) { 1590 return rc; 1591 } 1592 } 1593 } 1594 1595 if (!spapr->htab) { 1596 assert(fd >= 0); 1597 close(fd); 1598 } 1599 1600 return 0; 1601 } 1602 1603 static SaveVMHandlers savevm_htab_handlers = { 1604 .save_live_setup = htab_save_setup, 1605 .save_live_iterate = htab_save_iterate, 1606 .save_live_complete_precopy = htab_save_complete, 1607 .load_state = htab_load, 1608 }; 1609 1610 static void spapr_boot_set(void *opaque, const char *boot_device, 1611 Error **errp) 1612 { 1613 MachineState *machine = MACHINE(qdev_get_machine()); 1614 machine->boot_order = g_strdup(boot_device); 1615 } 1616 1617 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1618 Error **errp) 1619 { 1620 CPUPPCState *env = &cpu->env; 1621 1622 /* Set time-base frequency to 512 MHz */ 1623 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1624 1625 /* PAPR always has exception vectors in RAM not ROM. To ensure this, 1626 * MSR[IP] should never be set. 1627 */ 1628 env->msr_mask &= ~(1 << 6); 1629 1630 /* Tell KVM that we're in PAPR mode */ 1631 if (kvm_enabled()) { 1632 kvmppc_set_papr(cpu); 1633 } 1634 1635 if (cpu->max_compat) { 1636 Error *local_err = NULL; 1637 1638 ppc_set_compat(cpu, cpu->max_compat, &local_err); 1639 if (local_err) { 1640 error_propagate(errp, local_err); 1641 return; 1642 } 1643 } 1644 1645 xics_cpu_setup(spapr->icp, cpu); 1646 1647 qemu_register_reset(spapr_cpu_reset, cpu); 1648 } 1649 1650 /* 1651 * Reset routine for LMB DR devices. 1652 * 1653 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1654 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1655 * when it walks all its children devices. LMB devices reset occurs 1656 * as part of spapr_ppc_reset(). 1657 */ 1658 static void spapr_drc_reset(void *opaque) 1659 { 1660 sPAPRDRConnector *drc = opaque; 1661 DeviceState *d = DEVICE(drc); 1662 1663 if (d) { 1664 device_reset(d); 1665 } 1666 } 1667 1668 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1669 { 1670 MachineState *machine = MACHINE(spapr); 1671 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1672 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1673 int i; 1674 1675 for (i = 0; i < nr_lmbs; i++) { 1676 sPAPRDRConnector *drc; 1677 uint64_t addr; 1678 1679 addr = i * lmb_size + spapr->hotplug_memory.base; 1680 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1681 addr/lmb_size); 1682 qemu_register_reset(spapr_drc_reset, drc); 1683 } 1684 } 1685 1686 /* 1687 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1688 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1689 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1690 */ 1691 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1692 { 1693 int i; 1694 1695 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1696 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1697 " is not aligned to %llu MiB", 1698 machine->ram_size, 1699 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1700 return; 1701 } 1702 1703 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1704 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1705 " is not aligned to %llu MiB", 1706 machine->ram_size, 1707 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1708 return; 1709 } 1710 1711 for (i = 0; i < nb_numa_nodes; i++) { 1712 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1713 error_setg(errp, 1714 "Node %d memory size 0x%" PRIx64 1715 " is not aligned to %llu MiB", 1716 i, numa_info[i].node_mem, 1717 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1718 return; 1719 } 1720 } 1721 } 1722 1723 /* pSeries LPAR / sPAPR hardware init */ 1724 static void ppc_spapr_init(MachineState *machine) 1725 { 1726 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1727 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1728 const char *kernel_filename = machine->kernel_filename; 1729 const char *kernel_cmdline = machine->kernel_cmdline; 1730 const char *initrd_filename = machine->initrd_filename; 1731 PowerPCCPU *cpu; 1732 PCIHostState *phb; 1733 int i; 1734 MemoryRegion *sysmem = get_system_memory(); 1735 MemoryRegion *ram = g_new(MemoryRegion, 1); 1736 MemoryRegion *rma_region; 1737 void *rma = NULL; 1738 hwaddr rma_alloc_size; 1739 hwaddr node0_size = spapr_node0_size(); 1740 uint32_t initrd_base = 0; 1741 long kernel_size = 0, initrd_size = 0; 1742 long load_limit, fw_size; 1743 bool kernel_le = false; 1744 char *filename; 1745 1746 msi_supported = true; 1747 1748 QLIST_INIT(&spapr->phbs); 1749 1750 cpu_ppc_hypercall = emulate_spapr_hypercall; 1751 1752 /* Allocate RMA if necessary */ 1753 rma_alloc_size = kvmppc_alloc_rma(&rma); 1754 1755 if (rma_alloc_size == -1) { 1756 error_report("Unable to create RMA"); 1757 exit(1); 1758 } 1759 1760 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1761 spapr->rma_size = rma_alloc_size; 1762 } else { 1763 spapr->rma_size = node0_size; 1764 1765 /* With KVM, we don't actually know whether KVM supports an 1766 * unbounded RMA (PR KVM) or is limited by the hash table size 1767 * (HV KVM using VRMA), so we always assume the latter 1768 * 1769 * In that case, we also limit the initial allocations for RTAS 1770 * etc... to 256M since we have no way to know what the VRMA size 1771 * is going to be as it depends on the size of the hash table 1772 * isn't determined yet. 1773 */ 1774 if (kvm_enabled()) { 1775 spapr->vrma_adjust = 1; 1776 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1777 } 1778 } 1779 1780 if (spapr->rma_size > node0_size) { 1781 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1782 spapr->rma_size); 1783 exit(1); 1784 } 1785 1786 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1787 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1788 1789 /* Set up Interrupt Controller before we create the VCPUs */ 1790 spapr->icp = xics_system_init(machine, 1791 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1792 smp_threads), 1793 XICS_IRQS, &error_fatal); 1794 1795 if (smc->dr_lmb_enabled) { 1796 spapr_validate_node_memory(machine, &error_fatal); 1797 } 1798 1799 /* init CPUs */ 1800 if (machine->cpu_model == NULL) { 1801 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1802 } 1803 for (i = 0; i < smp_cpus; i++) { 1804 cpu = cpu_ppc_init(machine->cpu_model); 1805 if (cpu == NULL) { 1806 error_report("Unable to find PowerPC CPU definition"); 1807 exit(1); 1808 } 1809 spapr_cpu_init(spapr, cpu, &error_fatal); 1810 } 1811 1812 if (kvm_enabled()) { 1813 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1814 kvmppc_enable_logical_ci_hcalls(); 1815 kvmppc_enable_set_mode_hcall(); 1816 } 1817 1818 /* allocate RAM */ 1819 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1820 machine->ram_size); 1821 memory_region_add_subregion(sysmem, 0, ram); 1822 1823 if (rma_alloc_size && rma) { 1824 rma_region = g_new(MemoryRegion, 1); 1825 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1826 rma_alloc_size, rma); 1827 vmstate_register_ram_global(rma_region); 1828 memory_region_add_subregion(sysmem, 0, rma_region); 1829 } 1830 1831 /* initialize hotplug memory address space */ 1832 if (machine->ram_size < machine->maxram_size) { 1833 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1834 1835 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) { 1836 error_report("Specified number of memory slots %" 1837 PRIu64" exceeds max supported %d", 1838 machine->ram_slots, SPAPR_MAX_RAM_SLOTS); 1839 exit(1); 1840 } 1841 1842 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1843 SPAPR_HOTPLUG_MEM_ALIGN); 1844 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1845 "hotplug-memory", hotplug_mem_size); 1846 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1847 &spapr->hotplug_memory.mr); 1848 } 1849 1850 if (smc->dr_lmb_enabled) { 1851 spapr_create_lmb_dr_connectors(spapr); 1852 } 1853 1854 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1855 if (!filename) { 1856 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1857 exit(1); 1858 } 1859 spapr->rtas_size = get_image_size(filename); 1860 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1861 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1862 error_report("Could not load LPAR rtas '%s'", filename); 1863 exit(1); 1864 } 1865 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1866 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1867 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1868 exit(1); 1869 } 1870 g_free(filename); 1871 1872 /* Set up EPOW events infrastructure */ 1873 spapr_events_init(spapr); 1874 1875 /* Set up the RTC RTAS interfaces */ 1876 spapr_rtc_create(spapr); 1877 1878 /* Set up VIO bus */ 1879 spapr->vio_bus = spapr_vio_bus_init(); 1880 1881 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1882 if (serial_hds[i]) { 1883 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1884 } 1885 } 1886 1887 /* We always have at least the nvram device on VIO */ 1888 spapr_create_nvram(spapr); 1889 1890 /* Set up PCI */ 1891 spapr_pci_rtas_init(); 1892 1893 phb = spapr_create_phb(spapr, 0); 1894 1895 for (i = 0; i < nb_nics; i++) { 1896 NICInfo *nd = &nd_table[i]; 1897 1898 if (!nd->model) { 1899 nd->model = g_strdup("ibmveth"); 1900 } 1901 1902 if (strcmp(nd->model, "ibmveth") == 0) { 1903 spapr_vlan_create(spapr->vio_bus, nd); 1904 } else { 1905 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1906 } 1907 } 1908 1909 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1910 spapr_vscsi_create(spapr->vio_bus); 1911 } 1912 1913 /* Graphics */ 1914 if (spapr_vga_init(phb->bus, &error_fatal)) { 1915 spapr->has_graphics = true; 1916 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1917 } 1918 1919 if (machine->usb) { 1920 if (smc->use_ohci_by_default) { 1921 pci_create_simple(phb->bus, -1, "pci-ohci"); 1922 } else { 1923 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 1924 } 1925 1926 if (spapr->has_graphics) { 1927 USBBus *usb_bus = usb_bus_find(-1); 1928 1929 usb_create_simple(usb_bus, "usb-kbd"); 1930 usb_create_simple(usb_bus, "usb-mouse"); 1931 } 1932 } 1933 1934 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1935 error_report( 1936 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 1937 MIN_RMA_SLOF); 1938 exit(1); 1939 } 1940 1941 if (kernel_filename) { 1942 uint64_t lowaddr = 0; 1943 1944 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1945 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 1946 0, 0); 1947 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1948 kernel_size = load_elf(kernel_filename, 1949 translate_kernel_address, NULL, 1950 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 1951 0, 0); 1952 kernel_le = kernel_size > 0; 1953 } 1954 if (kernel_size < 0) { 1955 error_report("error loading %s: %s", 1956 kernel_filename, load_elf_strerror(kernel_size)); 1957 exit(1); 1958 } 1959 1960 /* load initrd */ 1961 if (initrd_filename) { 1962 /* Try to locate the initrd in the gap between the kernel 1963 * and the firmware. Add a bit of space just in case 1964 */ 1965 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1966 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1967 load_limit - initrd_base); 1968 if (initrd_size < 0) { 1969 error_report("could not load initial ram disk '%s'", 1970 initrd_filename); 1971 exit(1); 1972 } 1973 } else { 1974 initrd_base = 0; 1975 initrd_size = 0; 1976 } 1977 } 1978 1979 if (bios_name == NULL) { 1980 bios_name = FW_FILE_NAME; 1981 } 1982 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1983 if (!filename) { 1984 error_report("Could not find LPAR firmware '%s'", bios_name); 1985 exit(1); 1986 } 1987 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 1988 if (fw_size <= 0) { 1989 error_report("Could not load LPAR firmware '%s'", filename); 1990 exit(1); 1991 } 1992 g_free(filename); 1993 1994 /* FIXME: Should register things through the MachineState's qdev 1995 * interface, this is a legacy from the sPAPREnvironment structure 1996 * which predated MachineState but had a similar function */ 1997 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 1998 register_savevm_live(NULL, "spapr/htab", -1, 1, 1999 &savevm_htab_handlers, spapr); 2000 2001 /* Prepare the device tree */ 2002 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 2003 kernel_size, kernel_le, 2004 kernel_cmdline, 2005 spapr->check_exception_irq); 2006 assert(spapr->fdt_skel != NULL); 2007 2008 /* used by RTAS */ 2009 QTAILQ_INIT(&spapr->ccs_list); 2010 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2011 2012 qemu_register_boot_set(spapr_boot_set, spapr); 2013 } 2014 2015 static int spapr_kvm_type(const char *vm_type) 2016 { 2017 if (!vm_type) { 2018 return 0; 2019 } 2020 2021 if (!strcmp(vm_type, "HV")) { 2022 return 1; 2023 } 2024 2025 if (!strcmp(vm_type, "PR")) { 2026 return 2; 2027 } 2028 2029 error_report("Unknown kvm-type specified '%s'", vm_type); 2030 exit(1); 2031 } 2032 2033 /* 2034 * Implementation of an interface to adjust firmware path 2035 * for the bootindex property handling. 2036 */ 2037 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2038 DeviceState *dev) 2039 { 2040 #define CAST(type, obj, name) \ 2041 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2042 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2043 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2044 2045 if (d) { 2046 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2047 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2048 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2049 2050 if (spapr) { 2051 /* 2052 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2053 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2054 * in the top 16 bits of the 64-bit LUN 2055 */ 2056 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2057 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2058 (uint64_t)id << 48); 2059 } else if (virtio) { 2060 /* 2061 * We use SRP luns of the form 01000000 | (target << 8) | lun 2062 * in the top 32 bits of the 64-bit LUN 2063 * Note: the quote above is from SLOF and it is wrong, 2064 * the actual binding is: 2065 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2066 */ 2067 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2068 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2069 (uint64_t)id << 32); 2070 } else if (usb) { 2071 /* 2072 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2073 * in the top 32 bits of the 64-bit LUN 2074 */ 2075 unsigned usb_port = atoi(usb->port->path); 2076 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2077 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2078 (uint64_t)id << 32); 2079 } 2080 } 2081 2082 if (phb) { 2083 /* Replace "pci" with "pci@800000020000000" */ 2084 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2085 } 2086 2087 return NULL; 2088 } 2089 2090 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2091 { 2092 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2093 2094 return g_strdup(spapr->kvm_type); 2095 } 2096 2097 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2098 { 2099 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2100 2101 g_free(spapr->kvm_type); 2102 spapr->kvm_type = g_strdup(value); 2103 } 2104 2105 static void spapr_machine_initfn(Object *obj) 2106 { 2107 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2108 2109 spapr->htab_fd = -1; 2110 object_property_add_str(obj, "kvm-type", 2111 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2112 object_property_set_description(obj, "kvm-type", 2113 "Specifies the KVM virtualization mode (HV, PR)", 2114 NULL); 2115 } 2116 2117 static void spapr_machine_finalizefn(Object *obj) 2118 { 2119 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2120 2121 g_free(spapr->kvm_type); 2122 } 2123 2124 static void ppc_cpu_do_nmi_on_cpu(void *arg) 2125 { 2126 CPUState *cs = arg; 2127 2128 cpu_synchronize_state(cs); 2129 ppc_cpu_do_system_reset(cs); 2130 } 2131 2132 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2133 { 2134 CPUState *cs; 2135 2136 CPU_FOREACH(cs) { 2137 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 2138 } 2139 } 2140 2141 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2142 uint32_t node, Error **errp) 2143 { 2144 sPAPRDRConnector *drc; 2145 sPAPRDRConnectorClass *drck; 2146 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2147 int i, fdt_offset, fdt_size; 2148 void *fdt; 2149 2150 /* 2151 * Check for DRC connectors and send hotplug notification to the 2152 * guest only in case of hotplugged memory. This allows cold plugged 2153 * memory to be specified at boot time. 2154 */ 2155 if (!dev->hotplugged) { 2156 return; 2157 } 2158 2159 for (i = 0; i < nr_lmbs; i++) { 2160 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2161 addr/SPAPR_MEMORY_BLOCK_SIZE); 2162 g_assert(drc); 2163 2164 fdt = create_device_tree(&fdt_size); 2165 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2166 SPAPR_MEMORY_BLOCK_SIZE); 2167 2168 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2169 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2170 addr += SPAPR_MEMORY_BLOCK_SIZE; 2171 } 2172 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2173 } 2174 2175 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2176 uint32_t node, Error **errp) 2177 { 2178 Error *local_err = NULL; 2179 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2180 PCDIMMDevice *dimm = PC_DIMM(dev); 2181 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2182 MemoryRegion *mr = ddc->get_memory_region(dimm); 2183 uint64_t align = memory_region_get_alignment(mr); 2184 uint64_t size = memory_region_size(mr); 2185 uint64_t addr; 2186 2187 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2188 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2189 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2190 goto out; 2191 } 2192 2193 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2194 if (local_err) { 2195 goto out; 2196 } 2197 2198 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2199 if (local_err) { 2200 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2201 goto out; 2202 } 2203 2204 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2205 2206 out: 2207 error_propagate(errp, local_err); 2208 } 2209 2210 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2211 DeviceState *dev, Error **errp) 2212 { 2213 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2214 2215 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2216 int node; 2217 2218 if (!smc->dr_lmb_enabled) { 2219 error_setg(errp, "Memory hotplug not supported for this machine"); 2220 return; 2221 } 2222 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2223 if (*errp) { 2224 return; 2225 } 2226 2227 /* 2228 * Currently PowerPC kernel doesn't allow hot-adding memory to 2229 * memory-less node, but instead will silently add the memory 2230 * to the first node that has some memory. This causes two 2231 * unexpected behaviours for the user. 2232 * 2233 * - Memory gets hotplugged to a different node than what the user 2234 * specified. 2235 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2236 * to memory-less node, a reboot will set things accordingly 2237 * and the previously hotplugged memory now ends in the right node. 2238 * This appears as if some memory moved from one node to another. 2239 * 2240 * So until kernel starts supporting memory hotplug to memory-less 2241 * nodes, just prevent such attempts upfront in QEMU. 2242 */ 2243 if (nb_numa_nodes && !numa_info[node].node_mem) { 2244 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2245 node); 2246 return; 2247 } 2248 2249 spapr_memory_plug(hotplug_dev, dev, node, errp); 2250 } 2251 } 2252 2253 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2254 DeviceState *dev, Error **errp) 2255 { 2256 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2257 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2258 } 2259 } 2260 2261 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, 2262 DeviceState *dev) 2263 { 2264 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2265 return HOTPLUG_HANDLER(machine); 2266 } 2267 return NULL; 2268 } 2269 2270 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2271 { 2272 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2273 * socket means much for the paravirtualized PAPR platform) */ 2274 return cpu_index / smp_threads / smp_cores; 2275 } 2276 2277 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2278 { 2279 MachineClass *mc = MACHINE_CLASS(oc); 2280 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2281 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2282 NMIClass *nc = NMI_CLASS(oc); 2283 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2284 2285 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2286 2287 /* 2288 * We set up the default / latest behaviour here. The class_init 2289 * functions for the specific versioned machine types can override 2290 * these details for backwards compatibility 2291 */ 2292 mc->init = ppc_spapr_init; 2293 mc->reset = ppc_spapr_reset; 2294 mc->block_default_type = IF_SCSI; 2295 mc->max_cpus = MAX_CPUMASK_BITS; 2296 mc->no_parallel = 1; 2297 mc->default_boot_order = ""; 2298 mc->default_ram_size = 512 * M_BYTE; 2299 mc->kvm_type = spapr_kvm_type; 2300 mc->has_dynamic_sysbus = true; 2301 mc->pci_allow_0_address = true; 2302 mc->get_hotplug_handler = spapr_get_hotpug_handler; 2303 hc->plug = spapr_machine_device_plug; 2304 hc->unplug = spapr_machine_device_unplug; 2305 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2306 2307 smc->dr_lmb_enabled = true; 2308 fwc->get_dev_path = spapr_get_fw_dev_path; 2309 nc->nmi_monitor_handler = spapr_nmi; 2310 } 2311 2312 static const TypeInfo spapr_machine_info = { 2313 .name = TYPE_SPAPR_MACHINE, 2314 .parent = TYPE_MACHINE, 2315 .abstract = true, 2316 .instance_size = sizeof(sPAPRMachineState), 2317 .instance_init = spapr_machine_initfn, 2318 .instance_finalize = spapr_machine_finalizefn, 2319 .class_size = sizeof(sPAPRMachineClass), 2320 .class_init = spapr_machine_class_init, 2321 .interfaces = (InterfaceInfo[]) { 2322 { TYPE_FW_PATH_PROVIDER }, 2323 { TYPE_NMI }, 2324 { TYPE_HOTPLUG_HANDLER }, 2325 { } 2326 }, 2327 }; 2328 2329 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2330 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2331 void *data) \ 2332 { \ 2333 MachineClass *mc = MACHINE_CLASS(oc); \ 2334 spapr_machine_##suffix##_class_options(mc); \ 2335 if (latest) { \ 2336 mc->alias = "pseries"; \ 2337 mc->is_default = 1; \ 2338 } \ 2339 } \ 2340 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2341 { \ 2342 MachineState *machine = MACHINE(obj); \ 2343 spapr_machine_##suffix##_instance_options(machine); \ 2344 } \ 2345 static const TypeInfo spapr_machine_##suffix##_info = { \ 2346 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2347 .parent = TYPE_SPAPR_MACHINE, \ 2348 .class_init = spapr_machine_##suffix##_class_init, \ 2349 .instance_init = spapr_machine_##suffix##_instance_init, \ 2350 }; \ 2351 static void spapr_machine_register_##suffix(void) \ 2352 { \ 2353 type_register(&spapr_machine_##suffix##_info); \ 2354 } \ 2355 machine_init(spapr_machine_register_##suffix) 2356 2357 /* 2358 * pseries-2.6 2359 */ 2360 static void spapr_machine_2_6_instance_options(MachineState *machine) 2361 { 2362 } 2363 2364 static void spapr_machine_2_6_class_options(MachineClass *mc) 2365 { 2366 /* Defaults for the latest behaviour inherited from the base class */ 2367 } 2368 2369 DEFINE_SPAPR_MACHINE(2_6, "2.6", true); 2370 2371 /* 2372 * pseries-2.5 2373 */ 2374 #define SPAPR_COMPAT_2_5 \ 2375 HW_COMPAT_2_5 2376 2377 static void spapr_machine_2_5_instance_options(MachineState *machine) 2378 { 2379 } 2380 2381 static void spapr_machine_2_5_class_options(MachineClass *mc) 2382 { 2383 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2384 2385 spapr_machine_2_6_class_options(mc); 2386 smc->use_ohci_by_default = true; 2387 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2388 } 2389 2390 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2391 2392 /* 2393 * pseries-2.4 2394 */ 2395 #define SPAPR_COMPAT_2_4 \ 2396 SPAPR_COMPAT_2_5 \ 2397 HW_COMPAT_2_4 2398 2399 static void spapr_machine_2_4_instance_options(MachineState *machine) 2400 { 2401 spapr_machine_2_5_instance_options(machine); 2402 } 2403 2404 static void spapr_machine_2_4_class_options(MachineClass *mc) 2405 { 2406 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2407 2408 spapr_machine_2_5_class_options(mc); 2409 smc->dr_lmb_enabled = false; 2410 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2411 } 2412 2413 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2414 2415 /* 2416 * pseries-2.3 2417 */ 2418 #define SPAPR_COMPAT_2_3 \ 2419 SPAPR_COMPAT_2_4 \ 2420 HW_COMPAT_2_3 \ 2421 {\ 2422 .driver = "spapr-pci-host-bridge",\ 2423 .property = "dynamic-reconfiguration",\ 2424 .value = "off",\ 2425 }, 2426 2427 static void spapr_machine_2_3_instance_options(MachineState *machine) 2428 { 2429 spapr_machine_2_4_instance_options(machine); 2430 savevm_skip_section_footers(); 2431 global_state_set_optional(); 2432 savevm_skip_configuration(); 2433 } 2434 2435 static void spapr_machine_2_3_class_options(MachineClass *mc) 2436 { 2437 spapr_machine_2_4_class_options(mc); 2438 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 2439 } 2440 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 2441 2442 /* 2443 * pseries-2.2 2444 */ 2445 2446 #define SPAPR_COMPAT_2_2 \ 2447 SPAPR_COMPAT_2_3 \ 2448 HW_COMPAT_2_2 \ 2449 {\ 2450 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2451 .property = "mem_win_size",\ 2452 .value = "0x20000000",\ 2453 }, 2454 2455 static void spapr_machine_2_2_instance_options(MachineState *machine) 2456 { 2457 spapr_machine_2_3_instance_options(machine); 2458 machine->suppress_vmdesc = true; 2459 } 2460 2461 static void spapr_machine_2_2_class_options(MachineClass *mc) 2462 { 2463 spapr_machine_2_3_class_options(mc); 2464 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 2465 } 2466 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 2467 2468 /* 2469 * pseries-2.1 2470 */ 2471 #define SPAPR_COMPAT_2_1 \ 2472 SPAPR_COMPAT_2_2 \ 2473 HW_COMPAT_2_1 2474 2475 static void spapr_machine_2_1_instance_options(MachineState *machine) 2476 { 2477 spapr_machine_2_2_instance_options(machine); 2478 } 2479 2480 static void spapr_machine_2_1_class_options(MachineClass *mc) 2481 { 2482 spapr_machine_2_2_class_options(mc); 2483 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 2484 } 2485 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 2486 2487 static void spapr_machine_register_types(void) 2488 { 2489 type_register_static(&spapr_machine_info); 2490 } 2491 2492 type_init(spapr_machine_register_types) 2493