1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/kvm.h" 40 #include "sysemu/device_tree.h" 41 #include "kvm_ppc.h" 42 #include "migration/migration.h" 43 #include "mmu-hash64.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 70 #include <libfdt.h> 71 72 /* SLOF memory layout: 73 * 74 * SLOF raw image loaded at 0, copies its romfs right below the flat 75 * device-tree, then position SLOF itself 31M below that 76 * 77 * So we set FW_OVERHEAD to 40MB which should account for all of that 78 * and more 79 * 80 * We load our kernel at 4M, leaving space for SLOF initial image 81 */ 82 #define FDT_MAX_SIZE 0x100000 83 #define RTAS_MAX_SIZE 0x10000 84 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 85 #define FW_MAX_SIZE 0x400000 86 #define FW_FILE_NAME "slof.bin" 87 #define FW_OVERHEAD 0x2800000 88 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 89 90 #define MIN_RMA_SLOF 128UL 91 92 #define TIMEBASE_FREQ 512000000ULL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(const char *type, int nr_servers, 99 int nr_irqs, Error **errp) 100 { 101 Error *err = NULL; 102 DeviceState *dev; 103 104 dev = qdev_create(NULL, type); 105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 107 object_property_set_bool(OBJECT(dev), true, "realized", &err); 108 if (err) { 109 error_propagate(errp, err); 110 object_unparent(OBJECT(dev)); 111 return NULL; 112 } 113 return XICS_COMMON(dev); 114 } 115 116 static XICSState *xics_system_init(MachineState *machine, 117 int nr_servers, int nr_irqs, Error **errp) 118 { 119 XICSState *icp = NULL; 120 121 if (kvm_enabled()) { 122 Error *err = NULL; 123 124 if (machine_kernel_irqchip_allowed(machine)) { 125 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err); 126 } 127 if (machine_kernel_irqchip_required(machine) && !icp) { 128 error_reportf_err(err, 129 "kernel_irqchip requested but unavailable: "); 130 } else { 131 error_free(err); 132 } 133 } 134 135 if (!icp) { 136 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp); 137 } 138 139 return icp; 140 } 141 142 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 143 int smt_threads) 144 { 145 int i, ret = 0; 146 uint32_t servers_prop[smt_threads]; 147 uint32_t gservers_prop[smt_threads * 2]; 148 int index = ppc_get_vcpu_dt_id(cpu); 149 150 if (cpu->cpu_version) { 151 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 152 if (ret < 0) { 153 return ret; 154 } 155 } 156 157 /* Build interrupt servers and gservers properties */ 158 for (i = 0; i < smt_threads; i++) { 159 servers_prop[i] = cpu_to_be32(index + i); 160 /* Hack, direct the group queues back to cpu 0 */ 161 gservers_prop[i*2] = cpu_to_be32(index + i); 162 gservers_prop[i*2 + 1] = 0; 163 } 164 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 165 servers_prop, sizeof(servers_prop)); 166 if (ret < 0) { 167 return ret; 168 } 169 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 170 gservers_prop, sizeof(gservers_prop)); 171 172 return ret; 173 } 174 175 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 176 { 177 int ret = 0; 178 PowerPCCPU *cpu = POWERPC_CPU(cs); 179 int index = ppc_get_vcpu_dt_id(cpu); 180 uint32_t associativity[] = {cpu_to_be32(0x5), 181 cpu_to_be32(0x0), 182 cpu_to_be32(0x0), 183 cpu_to_be32(0x0), 184 cpu_to_be32(cs->numa_node), 185 cpu_to_be32(index)}; 186 187 /* Advertise NUMA via ibm,associativity */ 188 if (nb_numa_nodes > 1) { 189 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 190 sizeof(associativity)); 191 } 192 193 return ret; 194 } 195 196 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 197 { 198 int ret = 0, offset, cpus_offset; 199 CPUState *cs; 200 char cpu_model[32]; 201 int smt = kvmppc_smt_threads(); 202 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 203 204 CPU_FOREACH(cs) { 205 PowerPCCPU *cpu = POWERPC_CPU(cs); 206 DeviceClass *dc = DEVICE_GET_CLASS(cs); 207 int index = ppc_get_vcpu_dt_id(cpu); 208 209 if ((index % smt) != 0) { 210 continue; 211 } 212 213 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 214 215 cpus_offset = fdt_path_offset(fdt, "/cpus"); 216 if (cpus_offset < 0) { 217 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 218 "cpus"); 219 if (cpus_offset < 0) { 220 return cpus_offset; 221 } 222 } 223 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 224 if (offset < 0) { 225 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 226 if (offset < 0) { 227 return offset; 228 } 229 } 230 231 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 232 pft_size_prop, sizeof(pft_size_prop)); 233 if (ret < 0) { 234 return ret; 235 } 236 237 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 238 if (ret < 0) { 239 return ret; 240 } 241 242 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 243 ppc_get_compat_smt_threads(cpu)); 244 if (ret < 0) { 245 return ret; 246 } 247 } 248 return ret; 249 } 250 251 252 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 253 size_t maxsize) 254 { 255 size_t maxcells = maxsize / sizeof(uint32_t); 256 int i, j, count; 257 uint32_t *p = prop; 258 259 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 260 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 261 262 if (!sps->page_shift) { 263 break; 264 } 265 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 266 if (sps->enc[count].page_shift == 0) { 267 break; 268 } 269 } 270 if ((p - prop) >= (maxcells - 3 - count * 2)) { 271 break; 272 } 273 *(p++) = cpu_to_be32(sps->page_shift); 274 *(p++) = cpu_to_be32(sps->slb_enc); 275 *(p++) = cpu_to_be32(count); 276 for (j = 0; j < count; j++) { 277 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 278 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 279 } 280 } 281 282 return (p - prop) * sizeof(uint32_t); 283 } 284 285 static hwaddr spapr_node0_size(void) 286 { 287 MachineState *machine = MACHINE(qdev_get_machine()); 288 289 if (nb_numa_nodes) { 290 int i; 291 for (i = 0; i < nb_numa_nodes; ++i) { 292 if (numa_info[i].node_mem) { 293 return MIN(pow2floor(numa_info[i].node_mem), 294 machine->ram_size); 295 } 296 } 297 } 298 return machine->ram_size; 299 } 300 301 #define _FDT(exp) \ 302 do { \ 303 int ret = (exp); \ 304 if (ret < 0) { \ 305 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 306 #exp, fdt_strerror(ret)); \ 307 exit(1); \ 308 } \ 309 } while (0) 310 311 static void add_str(GString *s, const gchar *s1) 312 { 313 g_string_append_len(s, s1, strlen(s1) + 1); 314 } 315 316 static void *spapr_create_fdt_skel(hwaddr initrd_base, 317 hwaddr initrd_size, 318 hwaddr kernel_size, 319 bool little_endian, 320 const char *kernel_cmdline, 321 uint32_t epow_irq) 322 { 323 void *fdt; 324 uint32_t start_prop = cpu_to_be32(initrd_base); 325 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 326 GString *hypertas = g_string_sized_new(256); 327 GString *qemu_hypertas = g_string_sized_new(256); 328 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 329 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 330 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 331 char *buf; 332 333 add_str(hypertas, "hcall-pft"); 334 add_str(hypertas, "hcall-term"); 335 add_str(hypertas, "hcall-dabr"); 336 add_str(hypertas, "hcall-interrupt"); 337 add_str(hypertas, "hcall-tce"); 338 add_str(hypertas, "hcall-vio"); 339 add_str(hypertas, "hcall-splpar"); 340 add_str(hypertas, "hcall-bulk"); 341 add_str(hypertas, "hcall-set-mode"); 342 add_str(qemu_hypertas, "hcall-memop1"); 343 344 fdt = g_malloc0(FDT_MAX_SIZE); 345 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 346 347 if (kernel_size) { 348 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 349 } 350 if (initrd_size) { 351 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 352 } 353 _FDT((fdt_finish_reservemap(fdt))); 354 355 /* Root node */ 356 _FDT((fdt_begin_node(fdt, ""))); 357 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 358 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 359 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 360 361 /* 362 * Add info to guest to indentify which host is it being run on 363 * and what is the uuid of the guest 364 */ 365 if (kvmppc_get_host_model(&buf)) { 366 _FDT((fdt_property_string(fdt, "host-model", buf))); 367 g_free(buf); 368 } 369 if (kvmppc_get_host_serial(&buf)) { 370 _FDT((fdt_property_string(fdt, "host-serial", buf))); 371 g_free(buf); 372 } 373 374 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 375 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 376 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 377 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 378 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 379 qemu_uuid[14], qemu_uuid[15]); 380 381 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 382 if (qemu_uuid_set) { 383 _FDT((fdt_property_string(fdt, "system-id", buf))); 384 } 385 g_free(buf); 386 387 if (qemu_get_vm_name()) { 388 _FDT((fdt_property_string(fdt, "ibm,partition-name", 389 qemu_get_vm_name()))); 390 } 391 392 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 393 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 394 395 /* /chosen */ 396 _FDT((fdt_begin_node(fdt, "chosen"))); 397 398 /* Set Form1_affinity */ 399 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 400 401 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 402 _FDT((fdt_property(fdt, "linux,initrd-start", 403 &start_prop, sizeof(start_prop)))); 404 _FDT((fdt_property(fdt, "linux,initrd-end", 405 &end_prop, sizeof(end_prop)))); 406 if (kernel_size) { 407 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 408 cpu_to_be64(kernel_size) }; 409 410 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 411 if (little_endian) { 412 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 413 } 414 } 415 if (boot_menu) { 416 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 417 } 418 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 419 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 420 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 421 422 _FDT((fdt_end_node(fdt))); 423 424 /* RTAS */ 425 _FDT((fdt_begin_node(fdt, "rtas"))); 426 427 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 428 add_str(hypertas, "hcall-multi-tce"); 429 } 430 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 431 hypertas->len))); 432 g_string_free(hypertas, TRUE); 433 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 434 qemu_hypertas->len))); 435 g_string_free(qemu_hypertas, TRUE); 436 437 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 438 refpoints, sizeof(refpoints)))); 439 440 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 441 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 442 RTAS_EVENT_SCAN_RATE))); 443 444 if (msi_nonbroken) { 445 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 446 } 447 448 /* 449 * According to PAPR, rtas ibm,os-term does not guarantee a return 450 * back to the guest cpu. 451 * 452 * While an additional ibm,extended-os-term property indicates that 453 * rtas call return will always occur. Set this property. 454 */ 455 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 456 457 _FDT((fdt_end_node(fdt))); 458 459 /* interrupt controller */ 460 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 461 462 _FDT((fdt_property_string(fdt, "device_type", 463 "PowerPC-External-Interrupt-Presentation"))); 464 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 465 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 466 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 467 interrupt_server_ranges_prop, 468 sizeof(interrupt_server_ranges_prop)))); 469 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 470 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 471 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 472 473 _FDT((fdt_end_node(fdt))); 474 475 /* vdevice */ 476 _FDT((fdt_begin_node(fdt, "vdevice"))); 477 478 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 479 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 480 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 481 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 482 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 483 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 484 485 _FDT((fdt_end_node(fdt))); 486 487 /* event-sources */ 488 spapr_events_fdt_skel(fdt, epow_irq); 489 490 /* /hypervisor node */ 491 if (kvm_enabled()) { 492 uint8_t hypercall[16]; 493 494 /* indicate KVM hypercall interface */ 495 _FDT((fdt_begin_node(fdt, "hypervisor"))); 496 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 497 if (kvmppc_has_cap_fixup_hcalls()) { 498 /* 499 * Older KVM versions with older guest kernels were broken with the 500 * magic page, don't allow the guest to map it. 501 */ 502 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 503 sizeof(hypercall))) { 504 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 505 sizeof(hypercall)))); 506 } 507 } 508 _FDT((fdt_end_node(fdt))); 509 } 510 511 _FDT((fdt_end_node(fdt))); /* close root node */ 512 _FDT((fdt_finish(fdt))); 513 514 return fdt; 515 } 516 517 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 518 hwaddr size) 519 { 520 uint32_t associativity[] = { 521 cpu_to_be32(0x4), /* length */ 522 cpu_to_be32(0x0), cpu_to_be32(0x0), 523 cpu_to_be32(0x0), cpu_to_be32(nodeid) 524 }; 525 char mem_name[32]; 526 uint64_t mem_reg_property[2]; 527 int off; 528 529 mem_reg_property[0] = cpu_to_be64(start); 530 mem_reg_property[1] = cpu_to_be64(size); 531 532 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 533 off = fdt_add_subnode(fdt, 0, mem_name); 534 _FDT(off); 535 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 536 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 537 sizeof(mem_reg_property)))); 538 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 539 sizeof(associativity)))); 540 return off; 541 } 542 543 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 544 { 545 MachineState *machine = MACHINE(spapr); 546 hwaddr mem_start, node_size; 547 int i, nb_nodes = nb_numa_nodes; 548 NodeInfo *nodes = numa_info; 549 NodeInfo ramnode; 550 551 /* No NUMA nodes, assume there is just one node with whole RAM */ 552 if (!nb_numa_nodes) { 553 nb_nodes = 1; 554 ramnode.node_mem = machine->ram_size; 555 nodes = &ramnode; 556 } 557 558 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 559 if (!nodes[i].node_mem) { 560 continue; 561 } 562 if (mem_start >= machine->ram_size) { 563 node_size = 0; 564 } else { 565 node_size = nodes[i].node_mem; 566 if (node_size > machine->ram_size - mem_start) { 567 node_size = machine->ram_size - mem_start; 568 } 569 } 570 if (!mem_start) { 571 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 572 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 573 mem_start += spapr->rma_size; 574 node_size -= spapr->rma_size; 575 } 576 for ( ; node_size; ) { 577 hwaddr sizetmp = pow2floor(node_size); 578 579 /* mem_start != 0 here */ 580 if (ctzl(mem_start) < ctzl(sizetmp)) { 581 sizetmp = 1ULL << ctzl(mem_start); 582 } 583 584 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 585 node_size -= sizetmp; 586 mem_start += sizetmp; 587 } 588 } 589 590 return 0; 591 } 592 593 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 594 sPAPRMachineState *spapr) 595 { 596 PowerPCCPU *cpu = POWERPC_CPU(cs); 597 CPUPPCState *env = &cpu->env; 598 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 599 int index = ppc_get_vcpu_dt_id(cpu); 600 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 601 0xffffffff, 0xffffffff}; 602 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ; 603 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 604 uint32_t page_sizes_prop[64]; 605 size_t page_sizes_prop_size; 606 uint32_t vcpus_per_socket = smp_threads * smp_cores; 607 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 608 609 /* Note: we keep CI large pages off for now because a 64K capable guest 610 * provisioned with large pages might otherwise try to map a qemu 611 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 612 * even if that qemu runs on a 4k host. 613 * 614 * We can later add this bit back when we are confident this is not 615 * an issue (!HV KVM or 64K host) 616 */ 617 uint8_t pa_features_206[] = { 6, 0, 618 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 619 uint8_t pa_features_207[] = { 24, 0, 620 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 621 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 622 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 623 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 624 uint8_t *pa_features; 625 size_t pa_size; 626 627 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 628 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 629 630 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 631 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 632 env->dcache_line_size))); 633 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 634 env->dcache_line_size))); 635 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 636 env->icache_line_size))); 637 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 638 env->icache_line_size))); 639 640 if (pcc->l1_dcache_size) { 641 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 642 pcc->l1_dcache_size))); 643 } else { 644 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 645 } 646 if (pcc->l1_icache_size) { 647 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 648 pcc->l1_icache_size))); 649 } else { 650 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 651 } 652 653 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 654 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 655 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 656 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 657 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 658 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 659 660 if (env->spr_cb[SPR_PURR].oea_read) { 661 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 662 } 663 664 if (env->mmu_model & POWERPC_MMU_1TSEG) { 665 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 666 segs, sizeof(segs)))); 667 } 668 669 /* Advertise VMX/VSX (vector extensions) if available 670 * 0 / no property == no vector extensions 671 * 1 == VMX / Altivec available 672 * 2 == VSX available */ 673 if (env->insns_flags & PPC_ALTIVEC) { 674 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 675 676 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 677 } 678 679 /* Advertise DFP (Decimal Floating Point) if available 680 * 0 / no property == no DFP 681 * 1 == DFP available */ 682 if (env->insns_flags2 & PPC2_DFP) { 683 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 684 } 685 686 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 687 sizeof(page_sizes_prop)); 688 if (page_sizes_prop_size) { 689 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 690 page_sizes_prop, page_sizes_prop_size))); 691 } 692 693 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 694 if (env->mmu_model == POWERPC_MMU_2_06) { 695 pa_features = pa_features_206; 696 pa_size = sizeof(pa_features_206); 697 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 698 pa_features = pa_features_207; 699 pa_size = sizeof(pa_features_207); 700 } 701 if (env->ci_large_pages) { 702 pa_features[3] |= 0x20; 703 } 704 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 705 706 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 707 cs->cpu_index / vcpus_per_socket))); 708 709 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 710 pft_size_prop, sizeof(pft_size_prop)))); 711 712 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 713 714 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 715 ppc_get_compat_smt_threads(cpu))); 716 } 717 718 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 719 { 720 CPUState *cs; 721 int cpus_offset; 722 char *nodename; 723 int smt = kvmppc_smt_threads(); 724 725 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 726 _FDT(cpus_offset); 727 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 728 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 729 730 /* 731 * We walk the CPUs in reverse order to ensure that CPU DT nodes 732 * created by fdt_add_subnode() end up in the right order in FDT 733 * for the guest kernel the enumerate the CPUs correctly. 734 */ 735 CPU_FOREACH_REVERSE(cs) { 736 PowerPCCPU *cpu = POWERPC_CPU(cs); 737 int index = ppc_get_vcpu_dt_id(cpu); 738 DeviceClass *dc = DEVICE_GET_CLASS(cs); 739 int offset; 740 741 if ((index % smt) != 0) { 742 continue; 743 } 744 745 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 746 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 747 g_free(nodename); 748 _FDT(offset); 749 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 750 } 751 752 } 753 754 /* 755 * Adds ibm,dynamic-reconfiguration-memory node. 756 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 757 * of this device tree node. 758 */ 759 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 760 { 761 MachineState *machine = MACHINE(spapr); 762 int ret, i, offset; 763 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 764 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 765 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 766 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 767 memory_region_size(&spapr->hotplug_memory.mr)) / 768 lmb_size; 769 uint32_t *int_buf, *cur_index, buf_len; 770 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 771 772 /* 773 * Don't create the node if there is no hotpluggable memory 774 */ 775 if (machine->ram_size == machine->maxram_size) { 776 return 0; 777 } 778 779 /* 780 * Allocate enough buffer size to fit in ibm,dynamic-memory 781 * or ibm,associativity-lookup-arrays 782 */ 783 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 784 * sizeof(uint32_t); 785 cur_index = int_buf = g_malloc0(buf_len); 786 787 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 788 789 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 790 sizeof(prop_lmb_size)); 791 if (ret < 0) { 792 goto out; 793 } 794 795 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 796 if (ret < 0) { 797 goto out; 798 } 799 800 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 801 if (ret < 0) { 802 goto out; 803 } 804 805 /* ibm,dynamic-memory */ 806 int_buf[0] = cpu_to_be32(nr_lmbs); 807 cur_index++; 808 for (i = 0; i < nr_lmbs; i++) { 809 uint64_t addr = i * lmb_size; 810 uint32_t *dynamic_memory = cur_index; 811 812 if (i >= hotplug_lmb_start) { 813 sPAPRDRConnector *drc; 814 sPAPRDRConnectorClass *drck; 815 816 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 817 g_assert(drc); 818 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 819 820 dynamic_memory[0] = cpu_to_be32(addr >> 32); 821 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 822 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 823 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 824 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 825 if (memory_region_present(get_system_memory(), addr)) { 826 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 827 } else { 828 dynamic_memory[5] = cpu_to_be32(0); 829 } 830 } else { 831 /* 832 * LMB information for RMA, boot time RAM and gap b/n RAM and 833 * hotplug memory region -- all these are marked as reserved 834 * and as having no valid DRC. 835 */ 836 dynamic_memory[0] = cpu_to_be32(addr >> 32); 837 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 838 dynamic_memory[2] = cpu_to_be32(0); 839 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 840 dynamic_memory[4] = cpu_to_be32(-1); 841 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 842 SPAPR_LMB_FLAGS_DRC_INVALID); 843 } 844 845 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 846 } 847 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 848 if (ret < 0) { 849 goto out; 850 } 851 852 /* ibm,associativity-lookup-arrays */ 853 cur_index = int_buf; 854 int_buf[0] = cpu_to_be32(nr_nodes); 855 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 856 cur_index += 2; 857 for (i = 0; i < nr_nodes; i++) { 858 uint32_t associativity[] = { 859 cpu_to_be32(0x0), 860 cpu_to_be32(0x0), 861 cpu_to_be32(0x0), 862 cpu_to_be32(i) 863 }; 864 memcpy(cur_index, associativity, sizeof(associativity)); 865 cur_index += 4; 866 } 867 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 868 (cur_index - int_buf) * sizeof(uint32_t)); 869 out: 870 g_free(int_buf); 871 return ret; 872 } 873 874 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 875 target_ulong addr, target_ulong size, 876 bool cpu_update, bool memory_update) 877 { 878 void *fdt, *fdt_skel; 879 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 880 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 881 882 size -= sizeof(hdr); 883 884 /* Create sceleton */ 885 fdt_skel = g_malloc0(size); 886 _FDT((fdt_create(fdt_skel, size))); 887 _FDT((fdt_begin_node(fdt_skel, ""))); 888 _FDT((fdt_end_node(fdt_skel))); 889 _FDT((fdt_finish(fdt_skel))); 890 fdt = g_malloc0(size); 891 _FDT((fdt_open_into(fdt_skel, fdt, size))); 892 g_free(fdt_skel); 893 894 /* Fixup cpu nodes */ 895 if (cpu_update) { 896 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 897 } 898 899 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 900 if (memory_update && smc->dr_lmb_enabled) { 901 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 902 } 903 904 /* Pack resulting tree */ 905 _FDT((fdt_pack(fdt))); 906 907 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 908 trace_spapr_cas_failed(size); 909 return -1; 910 } 911 912 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 913 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 914 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 915 g_free(fdt); 916 917 return 0; 918 } 919 920 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 921 hwaddr fdt_addr, 922 hwaddr rtas_addr, 923 hwaddr rtas_size) 924 { 925 MachineState *machine = MACHINE(qdev_get_machine()); 926 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 927 const char *boot_device = machine->boot_order; 928 int ret, i; 929 size_t cb = 0; 930 char *bootlist; 931 void *fdt; 932 sPAPRPHBState *phb; 933 934 fdt = g_malloc(FDT_MAX_SIZE); 935 936 /* open out the base tree into a temp buffer for the final tweaks */ 937 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 938 939 ret = spapr_populate_memory(spapr, fdt); 940 if (ret < 0) { 941 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 942 exit(1); 943 } 944 945 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 946 if (ret < 0) { 947 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 948 exit(1); 949 } 950 951 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 952 ret = spapr_rng_populate_dt(fdt); 953 if (ret < 0) { 954 fprintf(stderr, "could not set up rng device in the fdt\n"); 955 exit(1); 956 } 957 } 958 959 QLIST_FOREACH(phb, &spapr->phbs, list) { 960 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 961 if (ret < 0) { 962 error_report("couldn't setup PCI devices in fdt"); 963 exit(1); 964 } 965 } 966 967 /* RTAS */ 968 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 969 if (ret < 0) { 970 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 971 } 972 973 /* cpus */ 974 spapr_populate_cpus_dt_node(fdt, spapr); 975 976 bootlist = get_boot_devices_list(&cb, true); 977 if (cb && bootlist) { 978 int offset = fdt_path_offset(fdt, "/chosen"); 979 if (offset < 0) { 980 exit(1); 981 } 982 for (i = 0; i < cb; i++) { 983 if (bootlist[i] == '\n') { 984 bootlist[i] = ' '; 985 } 986 987 } 988 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 989 } 990 991 if (boot_device && strlen(boot_device)) { 992 int offset = fdt_path_offset(fdt, "/chosen"); 993 994 if (offset < 0) { 995 exit(1); 996 } 997 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 998 } 999 1000 if (!spapr->has_graphics) { 1001 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 1002 } 1003 1004 if (smc->dr_lmb_enabled) { 1005 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1006 } 1007 1008 _FDT((fdt_pack(fdt))); 1009 1010 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1011 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1012 fdt_totalsize(fdt), FDT_MAX_SIZE); 1013 exit(1); 1014 } 1015 1016 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1017 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1018 1019 g_free(bootlist); 1020 g_free(fdt); 1021 } 1022 1023 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1024 { 1025 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1026 } 1027 1028 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 1029 { 1030 CPUPPCState *env = &cpu->env; 1031 1032 if (msr_pr) { 1033 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1034 env->gpr[3] = H_PRIVILEGE; 1035 } else { 1036 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1037 } 1038 } 1039 1040 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1041 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1042 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1043 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1044 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1045 1046 /* 1047 * Get the fd to access the kernel htab, re-opening it if necessary 1048 */ 1049 static int get_htab_fd(sPAPRMachineState *spapr) 1050 { 1051 if (spapr->htab_fd >= 0) { 1052 return spapr->htab_fd; 1053 } 1054 1055 spapr->htab_fd = kvmppc_get_htab_fd(false); 1056 if (spapr->htab_fd < 0) { 1057 error_report("Unable to open fd for reading hash table from KVM: %s", 1058 strerror(errno)); 1059 } 1060 1061 return spapr->htab_fd; 1062 } 1063 1064 static void close_htab_fd(sPAPRMachineState *spapr) 1065 { 1066 if (spapr->htab_fd >= 0) { 1067 close(spapr->htab_fd); 1068 } 1069 spapr->htab_fd = -1; 1070 } 1071 1072 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1073 { 1074 int shift; 1075 1076 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1077 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1078 * that's much more than is needed for Linux guests */ 1079 shift = ctz64(pow2ceil(ramsize)) - 7; 1080 shift = MAX(shift, 18); /* Minimum architected size */ 1081 shift = MIN(shift, 46); /* Maximum architected size */ 1082 return shift; 1083 } 1084 1085 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1086 Error **errp) 1087 { 1088 long rc; 1089 1090 /* Clean up any HPT info from a previous boot */ 1091 g_free(spapr->htab); 1092 spapr->htab = NULL; 1093 spapr->htab_shift = 0; 1094 close_htab_fd(spapr); 1095 1096 rc = kvmppc_reset_htab(shift); 1097 if (rc < 0) { 1098 /* kernel-side HPT needed, but couldn't allocate one */ 1099 error_setg_errno(errp, errno, 1100 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1101 shift); 1102 /* This is almost certainly fatal, but if the caller really 1103 * wants to carry on with shift == 0, it's welcome to try */ 1104 } else if (rc > 0) { 1105 /* kernel-side HPT allocated */ 1106 if (rc != shift) { 1107 error_setg(errp, 1108 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1109 shift, rc); 1110 } 1111 1112 spapr->htab_shift = shift; 1113 spapr->htab = NULL; 1114 } else { 1115 /* kernel-side HPT not needed, allocate in userspace instead */ 1116 size_t size = 1ULL << shift; 1117 int i; 1118 1119 spapr->htab = qemu_memalign(size, size); 1120 if (!spapr->htab) { 1121 error_setg_errno(errp, errno, 1122 "Could not allocate HPT of order %d", shift); 1123 return; 1124 } 1125 1126 memset(spapr->htab, 0, size); 1127 spapr->htab_shift = shift; 1128 1129 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1130 DIRTY_HPTE(HPTE(spapr->htab, i)); 1131 } 1132 } 1133 } 1134 1135 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1136 { 1137 bool matched = false; 1138 1139 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1140 matched = true; 1141 } 1142 1143 if (!matched) { 1144 error_report("Device %s is not supported by this machine yet.", 1145 qdev_fw_name(DEVICE(sbdev))); 1146 exit(1); 1147 } 1148 1149 return 0; 1150 } 1151 1152 static void ppc_spapr_reset(void) 1153 { 1154 MachineState *machine = MACHINE(qdev_get_machine()); 1155 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1156 PowerPCCPU *first_ppc_cpu; 1157 uint32_t rtas_limit; 1158 1159 /* Check for unknown sysbus devices */ 1160 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1161 1162 /* Allocate and/or reset the hash page table */ 1163 spapr_reallocate_hpt(spapr, 1164 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1165 &error_fatal); 1166 1167 /* Update the RMA size if necessary */ 1168 if (spapr->vrma_adjust) { 1169 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1170 spapr->htab_shift); 1171 } 1172 1173 qemu_devices_reset(); 1174 1175 /* 1176 * We place the device tree and RTAS just below either the top of the RMA, 1177 * or just below 2GB, whichever is lowere, so that it can be 1178 * processed with 32-bit real mode code if necessary 1179 */ 1180 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1181 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1182 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1183 1184 /* Load the fdt */ 1185 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1186 spapr->rtas_size); 1187 1188 /* Copy RTAS over */ 1189 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1190 spapr->rtas_size); 1191 1192 /* Set up the entry state */ 1193 first_ppc_cpu = POWERPC_CPU(first_cpu); 1194 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1195 first_ppc_cpu->env.gpr[5] = 0; 1196 first_cpu->halted = 0; 1197 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1198 1199 } 1200 1201 static void spapr_cpu_reset(void *opaque) 1202 { 1203 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1204 PowerPCCPU *cpu = opaque; 1205 CPUState *cs = CPU(cpu); 1206 CPUPPCState *env = &cpu->env; 1207 1208 cpu_reset(cs); 1209 1210 /* All CPUs start halted. CPU0 is unhalted from the machine level 1211 * reset code and the rest are explicitly started up by the guest 1212 * using an RTAS call */ 1213 cs->halted = 1; 1214 1215 env->spr[SPR_HIOR] = 0; 1216 1217 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift, 1218 &error_fatal); 1219 } 1220 1221 static void spapr_create_nvram(sPAPRMachineState *spapr) 1222 { 1223 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1224 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1225 1226 if (dinfo) { 1227 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1228 &error_fatal); 1229 } 1230 1231 qdev_init_nofail(dev); 1232 1233 spapr->nvram = (struct sPAPRNVRAM *)dev; 1234 } 1235 1236 static void spapr_rtc_create(sPAPRMachineState *spapr) 1237 { 1238 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1239 1240 qdev_init_nofail(dev); 1241 spapr->rtc = dev; 1242 1243 object_property_add_alias(qdev_get_machine(), "rtc-time", 1244 OBJECT(spapr->rtc), "date", NULL); 1245 } 1246 1247 /* Returns whether we want to use VGA or not */ 1248 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1249 { 1250 switch (vga_interface_type) { 1251 case VGA_NONE: 1252 return false; 1253 case VGA_DEVICE: 1254 return true; 1255 case VGA_STD: 1256 case VGA_VIRTIO: 1257 return pci_vga_init(pci_bus) != NULL; 1258 default: 1259 error_setg(errp, 1260 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1261 return false; 1262 } 1263 } 1264 1265 static int spapr_post_load(void *opaque, int version_id) 1266 { 1267 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1268 int err = 0; 1269 1270 /* In earlier versions, there was no separate qdev for the PAPR 1271 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1272 * So when migrating from those versions, poke the incoming offset 1273 * value into the RTC device */ 1274 if (version_id < 3) { 1275 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1276 } 1277 1278 return err; 1279 } 1280 1281 static bool version_before_3(void *opaque, int version_id) 1282 { 1283 return version_id < 3; 1284 } 1285 1286 static const VMStateDescription vmstate_spapr = { 1287 .name = "spapr", 1288 .version_id = 3, 1289 .minimum_version_id = 1, 1290 .post_load = spapr_post_load, 1291 .fields = (VMStateField[]) { 1292 /* used to be @next_irq */ 1293 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1294 1295 /* RTC offset */ 1296 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1297 1298 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1299 VMSTATE_END_OF_LIST() 1300 }, 1301 }; 1302 1303 static int htab_save_setup(QEMUFile *f, void *opaque) 1304 { 1305 sPAPRMachineState *spapr = opaque; 1306 1307 /* "Iteration" header */ 1308 qemu_put_be32(f, spapr->htab_shift); 1309 1310 if (spapr->htab) { 1311 spapr->htab_save_index = 0; 1312 spapr->htab_first_pass = true; 1313 } else { 1314 assert(kvm_enabled()); 1315 } 1316 1317 1318 return 0; 1319 } 1320 1321 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1322 int64_t max_ns) 1323 { 1324 bool has_timeout = max_ns != -1; 1325 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1326 int index = spapr->htab_save_index; 1327 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1328 1329 assert(spapr->htab_first_pass); 1330 1331 do { 1332 int chunkstart; 1333 1334 /* Consume invalid HPTEs */ 1335 while ((index < htabslots) 1336 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1337 index++; 1338 CLEAN_HPTE(HPTE(spapr->htab, index)); 1339 } 1340 1341 /* Consume valid HPTEs */ 1342 chunkstart = index; 1343 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1344 && HPTE_VALID(HPTE(spapr->htab, index))) { 1345 index++; 1346 CLEAN_HPTE(HPTE(spapr->htab, index)); 1347 } 1348 1349 if (index > chunkstart) { 1350 int n_valid = index - chunkstart; 1351 1352 qemu_put_be32(f, chunkstart); 1353 qemu_put_be16(f, n_valid); 1354 qemu_put_be16(f, 0); 1355 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1356 HASH_PTE_SIZE_64 * n_valid); 1357 1358 if (has_timeout && 1359 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1360 break; 1361 } 1362 } 1363 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1364 1365 if (index >= htabslots) { 1366 assert(index == htabslots); 1367 index = 0; 1368 spapr->htab_first_pass = false; 1369 } 1370 spapr->htab_save_index = index; 1371 } 1372 1373 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1374 int64_t max_ns) 1375 { 1376 bool final = max_ns < 0; 1377 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1378 int examined = 0, sent = 0; 1379 int index = spapr->htab_save_index; 1380 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1381 1382 assert(!spapr->htab_first_pass); 1383 1384 do { 1385 int chunkstart, invalidstart; 1386 1387 /* Consume non-dirty HPTEs */ 1388 while ((index < htabslots) 1389 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1390 index++; 1391 examined++; 1392 } 1393 1394 chunkstart = index; 1395 /* Consume valid dirty HPTEs */ 1396 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1397 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1398 && HPTE_VALID(HPTE(spapr->htab, index))) { 1399 CLEAN_HPTE(HPTE(spapr->htab, index)); 1400 index++; 1401 examined++; 1402 } 1403 1404 invalidstart = index; 1405 /* Consume invalid dirty HPTEs */ 1406 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1407 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1408 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1409 CLEAN_HPTE(HPTE(spapr->htab, index)); 1410 index++; 1411 examined++; 1412 } 1413 1414 if (index > chunkstart) { 1415 int n_valid = invalidstart - chunkstart; 1416 int n_invalid = index - invalidstart; 1417 1418 qemu_put_be32(f, chunkstart); 1419 qemu_put_be16(f, n_valid); 1420 qemu_put_be16(f, n_invalid); 1421 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1422 HASH_PTE_SIZE_64 * n_valid); 1423 sent += index - chunkstart; 1424 1425 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1426 break; 1427 } 1428 } 1429 1430 if (examined >= htabslots) { 1431 break; 1432 } 1433 1434 if (index >= htabslots) { 1435 assert(index == htabslots); 1436 index = 0; 1437 } 1438 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1439 1440 if (index >= htabslots) { 1441 assert(index == htabslots); 1442 index = 0; 1443 } 1444 1445 spapr->htab_save_index = index; 1446 1447 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1448 } 1449 1450 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1451 #define MAX_KVM_BUF_SIZE 2048 1452 1453 static int htab_save_iterate(QEMUFile *f, void *opaque) 1454 { 1455 sPAPRMachineState *spapr = opaque; 1456 int fd; 1457 int rc = 0; 1458 1459 /* Iteration header */ 1460 qemu_put_be32(f, 0); 1461 1462 if (!spapr->htab) { 1463 assert(kvm_enabled()); 1464 1465 fd = get_htab_fd(spapr); 1466 if (fd < 0) { 1467 return fd; 1468 } 1469 1470 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1471 if (rc < 0) { 1472 return rc; 1473 } 1474 } else if (spapr->htab_first_pass) { 1475 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1476 } else { 1477 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1478 } 1479 1480 /* End marker */ 1481 qemu_put_be32(f, 0); 1482 qemu_put_be16(f, 0); 1483 qemu_put_be16(f, 0); 1484 1485 return rc; 1486 } 1487 1488 static int htab_save_complete(QEMUFile *f, void *opaque) 1489 { 1490 sPAPRMachineState *spapr = opaque; 1491 int fd; 1492 1493 /* Iteration header */ 1494 qemu_put_be32(f, 0); 1495 1496 if (!spapr->htab) { 1497 int rc; 1498 1499 assert(kvm_enabled()); 1500 1501 fd = get_htab_fd(spapr); 1502 if (fd < 0) { 1503 return fd; 1504 } 1505 1506 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1507 if (rc < 0) { 1508 return rc; 1509 } 1510 close_htab_fd(spapr); 1511 } else { 1512 if (spapr->htab_first_pass) { 1513 htab_save_first_pass(f, spapr, -1); 1514 } 1515 htab_save_later_pass(f, spapr, -1); 1516 } 1517 1518 /* End marker */ 1519 qemu_put_be32(f, 0); 1520 qemu_put_be16(f, 0); 1521 qemu_put_be16(f, 0); 1522 1523 return 0; 1524 } 1525 1526 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1527 { 1528 sPAPRMachineState *spapr = opaque; 1529 uint32_t section_hdr; 1530 int fd = -1; 1531 1532 if (version_id < 1 || version_id > 1) { 1533 error_report("htab_load() bad version"); 1534 return -EINVAL; 1535 } 1536 1537 section_hdr = qemu_get_be32(f); 1538 1539 if (section_hdr) { 1540 Error *local_err = NULL; 1541 1542 /* First section gives the htab size */ 1543 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1544 if (local_err) { 1545 error_report_err(local_err); 1546 return -EINVAL; 1547 } 1548 return 0; 1549 } 1550 1551 if (!spapr->htab) { 1552 assert(kvm_enabled()); 1553 1554 fd = kvmppc_get_htab_fd(true); 1555 if (fd < 0) { 1556 error_report("Unable to open fd to restore KVM hash table: %s", 1557 strerror(errno)); 1558 } 1559 } 1560 1561 while (true) { 1562 uint32_t index; 1563 uint16_t n_valid, n_invalid; 1564 1565 index = qemu_get_be32(f); 1566 n_valid = qemu_get_be16(f); 1567 n_invalid = qemu_get_be16(f); 1568 1569 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1570 /* End of Stream */ 1571 break; 1572 } 1573 1574 if ((index + n_valid + n_invalid) > 1575 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1576 /* Bad index in stream */ 1577 error_report( 1578 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1579 index, n_valid, n_invalid, spapr->htab_shift); 1580 return -EINVAL; 1581 } 1582 1583 if (spapr->htab) { 1584 if (n_valid) { 1585 qemu_get_buffer(f, HPTE(spapr->htab, index), 1586 HASH_PTE_SIZE_64 * n_valid); 1587 } 1588 if (n_invalid) { 1589 memset(HPTE(spapr->htab, index + n_valid), 0, 1590 HASH_PTE_SIZE_64 * n_invalid); 1591 } 1592 } else { 1593 int rc; 1594 1595 assert(fd >= 0); 1596 1597 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1598 if (rc < 0) { 1599 return rc; 1600 } 1601 } 1602 } 1603 1604 if (!spapr->htab) { 1605 assert(fd >= 0); 1606 close(fd); 1607 } 1608 1609 return 0; 1610 } 1611 1612 static SaveVMHandlers savevm_htab_handlers = { 1613 .save_live_setup = htab_save_setup, 1614 .save_live_iterate = htab_save_iterate, 1615 .save_live_complete_precopy = htab_save_complete, 1616 .load_state = htab_load, 1617 }; 1618 1619 static void spapr_boot_set(void *opaque, const char *boot_device, 1620 Error **errp) 1621 { 1622 MachineState *machine = MACHINE(qdev_get_machine()); 1623 machine->boot_order = g_strdup(boot_device); 1624 } 1625 1626 static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1627 Error **errp) 1628 { 1629 CPUPPCState *env = &cpu->env; 1630 1631 /* Set time-base frequency to 512 MHz */ 1632 cpu_ppc_tb_init(env, TIMEBASE_FREQ); 1633 1634 /* Enable PAPR mode in TCG or KVM */ 1635 cpu_ppc_set_papr(cpu); 1636 1637 if (cpu->max_compat) { 1638 Error *local_err = NULL; 1639 1640 ppc_set_compat(cpu, cpu->max_compat, &local_err); 1641 if (local_err) { 1642 error_propagate(errp, local_err); 1643 return; 1644 } 1645 } 1646 1647 xics_cpu_setup(spapr->icp, cpu); 1648 1649 qemu_register_reset(spapr_cpu_reset, cpu); 1650 } 1651 1652 /* 1653 * Reset routine for LMB DR devices. 1654 * 1655 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1656 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1657 * when it walks all its children devices. LMB devices reset occurs 1658 * as part of spapr_ppc_reset(). 1659 */ 1660 static void spapr_drc_reset(void *opaque) 1661 { 1662 sPAPRDRConnector *drc = opaque; 1663 DeviceState *d = DEVICE(drc); 1664 1665 if (d) { 1666 device_reset(d); 1667 } 1668 } 1669 1670 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1671 { 1672 MachineState *machine = MACHINE(spapr); 1673 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1674 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1675 int i; 1676 1677 for (i = 0; i < nr_lmbs; i++) { 1678 sPAPRDRConnector *drc; 1679 uint64_t addr; 1680 1681 addr = i * lmb_size + spapr->hotplug_memory.base; 1682 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1683 addr/lmb_size); 1684 qemu_register_reset(spapr_drc_reset, drc); 1685 } 1686 } 1687 1688 /* 1689 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1690 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1691 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1692 */ 1693 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1694 { 1695 int i; 1696 1697 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1698 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1699 " is not aligned to %llu MiB", 1700 machine->ram_size, 1701 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1702 return; 1703 } 1704 1705 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1706 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1707 " is not aligned to %llu MiB", 1708 machine->ram_size, 1709 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1710 return; 1711 } 1712 1713 for (i = 0; i < nb_numa_nodes; i++) { 1714 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1715 error_setg(errp, 1716 "Node %d memory size 0x%" PRIx64 1717 " is not aligned to %llu MiB", 1718 i, numa_info[i].node_mem, 1719 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1720 return; 1721 } 1722 } 1723 } 1724 1725 /* pSeries LPAR / sPAPR hardware init */ 1726 static void ppc_spapr_init(MachineState *machine) 1727 { 1728 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1729 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1730 const char *kernel_filename = machine->kernel_filename; 1731 const char *kernel_cmdline = machine->kernel_cmdline; 1732 const char *initrd_filename = machine->initrd_filename; 1733 PowerPCCPU *cpu; 1734 PCIHostState *phb; 1735 int i; 1736 MemoryRegion *sysmem = get_system_memory(); 1737 MemoryRegion *ram = g_new(MemoryRegion, 1); 1738 MemoryRegion *rma_region; 1739 void *rma = NULL; 1740 hwaddr rma_alloc_size; 1741 hwaddr node0_size = spapr_node0_size(); 1742 uint32_t initrd_base = 0; 1743 long kernel_size = 0, initrd_size = 0; 1744 long load_limit, fw_size; 1745 bool kernel_le = false; 1746 char *filename; 1747 1748 msi_nonbroken = true; 1749 1750 QLIST_INIT(&spapr->phbs); 1751 1752 cpu_ppc_hypercall = emulate_spapr_hypercall; 1753 1754 /* Allocate RMA if necessary */ 1755 rma_alloc_size = kvmppc_alloc_rma(&rma); 1756 1757 if (rma_alloc_size == -1) { 1758 error_report("Unable to create RMA"); 1759 exit(1); 1760 } 1761 1762 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1763 spapr->rma_size = rma_alloc_size; 1764 } else { 1765 spapr->rma_size = node0_size; 1766 1767 /* With KVM, we don't actually know whether KVM supports an 1768 * unbounded RMA (PR KVM) or is limited by the hash table size 1769 * (HV KVM using VRMA), so we always assume the latter 1770 * 1771 * In that case, we also limit the initial allocations for RTAS 1772 * etc... to 256M since we have no way to know what the VRMA size 1773 * is going to be as it depends on the size of the hash table 1774 * isn't determined yet. 1775 */ 1776 if (kvm_enabled()) { 1777 spapr->vrma_adjust = 1; 1778 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1779 } 1780 } 1781 1782 if (spapr->rma_size > node0_size) { 1783 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1784 spapr->rma_size); 1785 exit(1); 1786 } 1787 1788 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1789 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1790 1791 /* Set up Interrupt Controller before we create the VCPUs */ 1792 spapr->icp = xics_system_init(machine, 1793 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), 1794 smp_threads), 1795 XICS_IRQS, &error_fatal); 1796 1797 if (smc->dr_lmb_enabled) { 1798 spapr_validate_node_memory(machine, &error_fatal); 1799 } 1800 1801 /* init CPUs */ 1802 if (machine->cpu_model == NULL) { 1803 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1804 } 1805 for (i = 0; i < smp_cpus; i++) { 1806 cpu = cpu_ppc_init(machine->cpu_model); 1807 if (cpu == NULL) { 1808 error_report("Unable to find PowerPC CPU definition"); 1809 exit(1); 1810 } 1811 spapr_cpu_init(spapr, cpu, &error_fatal); 1812 } 1813 1814 if (kvm_enabled()) { 1815 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1816 kvmppc_enable_logical_ci_hcalls(); 1817 kvmppc_enable_set_mode_hcall(); 1818 } 1819 1820 /* allocate RAM */ 1821 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1822 machine->ram_size); 1823 memory_region_add_subregion(sysmem, 0, ram); 1824 1825 if (rma_alloc_size && rma) { 1826 rma_region = g_new(MemoryRegion, 1); 1827 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1828 rma_alloc_size, rma); 1829 vmstate_register_ram_global(rma_region); 1830 memory_region_add_subregion(sysmem, 0, rma_region); 1831 } 1832 1833 /* initialize hotplug memory address space */ 1834 if (machine->ram_size < machine->maxram_size) { 1835 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1836 /* 1837 * Limit the number of hotpluggable memory slots to half the number 1838 * slots that KVM supports, leaving the other half for PCI and other 1839 * devices. However ensure that number of slots doesn't drop below 32. 1840 */ 1841 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 1842 SPAPR_MAX_RAM_SLOTS; 1843 1844 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 1845 max_memslots = SPAPR_MAX_RAM_SLOTS; 1846 } 1847 if (machine->ram_slots > max_memslots) { 1848 error_report("Specified number of memory slots %" 1849 PRIu64" exceeds max supported %d", 1850 machine->ram_slots, max_memslots); 1851 exit(1); 1852 } 1853 1854 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1855 SPAPR_HOTPLUG_MEM_ALIGN); 1856 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1857 "hotplug-memory", hotplug_mem_size); 1858 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1859 &spapr->hotplug_memory.mr); 1860 } 1861 1862 if (smc->dr_lmb_enabled) { 1863 spapr_create_lmb_dr_connectors(spapr); 1864 } 1865 1866 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1867 if (!filename) { 1868 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1869 exit(1); 1870 } 1871 spapr->rtas_size = get_image_size(filename); 1872 if (spapr->rtas_size < 0) { 1873 error_report("Could not get size of LPAR rtas '%s'", filename); 1874 exit(1); 1875 } 1876 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1877 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1878 error_report("Could not load LPAR rtas '%s'", filename); 1879 exit(1); 1880 } 1881 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1882 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1883 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1884 exit(1); 1885 } 1886 g_free(filename); 1887 1888 /* Set up EPOW events infrastructure */ 1889 spapr_events_init(spapr); 1890 1891 /* Set up the RTC RTAS interfaces */ 1892 spapr_rtc_create(spapr); 1893 1894 /* Set up VIO bus */ 1895 spapr->vio_bus = spapr_vio_bus_init(); 1896 1897 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1898 if (serial_hds[i]) { 1899 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1900 } 1901 } 1902 1903 /* We always have at least the nvram device on VIO */ 1904 spapr_create_nvram(spapr); 1905 1906 /* Set up PCI */ 1907 spapr_pci_rtas_init(); 1908 1909 phb = spapr_create_phb(spapr, 0); 1910 1911 for (i = 0; i < nb_nics; i++) { 1912 NICInfo *nd = &nd_table[i]; 1913 1914 if (!nd->model) { 1915 nd->model = g_strdup("ibmveth"); 1916 } 1917 1918 if (strcmp(nd->model, "ibmveth") == 0) { 1919 spapr_vlan_create(spapr->vio_bus, nd); 1920 } else { 1921 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1922 } 1923 } 1924 1925 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1926 spapr_vscsi_create(spapr->vio_bus); 1927 } 1928 1929 /* Graphics */ 1930 if (spapr_vga_init(phb->bus, &error_fatal)) { 1931 spapr->has_graphics = true; 1932 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1933 } 1934 1935 if (machine->usb) { 1936 if (smc->use_ohci_by_default) { 1937 pci_create_simple(phb->bus, -1, "pci-ohci"); 1938 } else { 1939 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 1940 } 1941 1942 if (spapr->has_graphics) { 1943 USBBus *usb_bus = usb_bus_find(-1); 1944 1945 usb_create_simple(usb_bus, "usb-kbd"); 1946 usb_create_simple(usb_bus, "usb-mouse"); 1947 } 1948 } 1949 1950 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1951 error_report( 1952 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 1953 MIN_RMA_SLOF); 1954 exit(1); 1955 } 1956 1957 if (kernel_filename) { 1958 uint64_t lowaddr = 0; 1959 1960 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1961 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 1962 0, 0); 1963 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1964 kernel_size = load_elf(kernel_filename, 1965 translate_kernel_address, NULL, 1966 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 1967 0, 0); 1968 kernel_le = kernel_size > 0; 1969 } 1970 if (kernel_size < 0) { 1971 error_report("error loading %s: %s", 1972 kernel_filename, load_elf_strerror(kernel_size)); 1973 exit(1); 1974 } 1975 1976 /* load initrd */ 1977 if (initrd_filename) { 1978 /* Try to locate the initrd in the gap between the kernel 1979 * and the firmware. Add a bit of space just in case 1980 */ 1981 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1982 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1983 load_limit - initrd_base); 1984 if (initrd_size < 0) { 1985 error_report("could not load initial ram disk '%s'", 1986 initrd_filename); 1987 exit(1); 1988 } 1989 } else { 1990 initrd_base = 0; 1991 initrd_size = 0; 1992 } 1993 } 1994 1995 if (bios_name == NULL) { 1996 bios_name = FW_FILE_NAME; 1997 } 1998 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 1999 if (!filename) { 2000 error_report("Could not find LPAR firmware '%s'", bios_name); 2001 exit(1); 2002 } 2003 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2004 if (fw_size <= 0) { 2005 error_report("Could not load LPAR firmware '%s'", filename); 2006 exit(1); 2007 } 2008 g_free(filename); 2009 2010 /* FIXME: Should register things through the MachineState's qdev 2011 * interface, this is a legacy from the sPAPREnvironment structure 2012 * which predated MachineState but had a similar function */ 2013 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2014 register_savevm_live(NULL, "spapr/htab", -1, 1, 2015 &savevm_htab_handlers, spapr); 2016 2017 /* Prepare the device tree */ 2018 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 2019 kernel_size, kernel_le, 2020 kernel_cmdline, 2021 spapr->check_exception_irq); 2022 assert(spapr->fdt_skel != NULL); 2023 2024 /* used by RTAS */ 2025 QTAILQ_INIT(&spapr->ccs_list); 2026 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2027 2028 qemu_register_boot_set(spapr_boot_set, spapr); 2029 } 2030 2031 static int spapr_kvm_type(const char *vm_type) 2032 { 2033 if (!vm_type) { 2034 return 0; 2035 } 2036 2037 if (!strcmp(vm_type, "HV")) { 2038 return 1; 2039 } 2040 2041 if (!strcmp(vm_type, "PR")) { 2042 return 2; 2043 } 2044 2045 error_report("Unknown kvm-type specified '%s'", vm_type); 2046 exit(1); 2047 } 2048 2049 /* 2050 * Implementation of an interface to adjust firmware path 2051 * for the bootindex property handling. 2052 */ 2053 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2054 DeviceState *dev) 2055 { 2056 #define CAST(type, obj, name) \ 2057 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2058 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2059 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2060 2061 if (d) { 2062 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2063 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2064 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2065 2066 if (spapr) { 2067 /* 2068 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2069 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2070 * in the top 16 bits of the 64-bit LUN 2071 */ 2072 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2073 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2074 (uint64_t)id << 48); 2075 } else if (virtio) { 2076 /* 2077 * We use SRP luns of the form 01000000 | (target << 8) | lun 2078 * in the top 32 bits of the 64-bit LUN 2079 * Note: the quote above is from SLOF and it is wrong, 2080 * the actual binding is: 2081 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2082 */ 2083 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2084 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2085 (uint64_t)id << 32); 2086 } else if (usb) { 2087 /* 2088 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2089 * in the top 32 bits of the 64-bit LUN 2090 */ 2091 unsigned usb_port = atoi(usb->port->path); 2092 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2093 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2094 (uint64_t)id << 32); 2095 } 2096 } 2097 2098 if (phb) { 2099 /* Replace "pci" with "pci@800000020000000" */ 2100 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2101 } 2102 2103 return NULL; 2104 } 2105 2106 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2107 { 2108 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2109 2110 return g_strdup(spapr->kvm_type); 2111 } 2112 2113 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2114 { 2115 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2116 2117 g_free(spapr->kvm_type); 2118 spapr->kvm_type = g_strdup(value); 2119 } 2120 2121 static void spapr_machine_initfn(Object *obj) 2122 { 2123 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2124 2125 spapr->htab_fd = -1; 2126 object_property_add_str(obj, "kvm-type", 2127 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2128 object_property_set_description(obj, "kvm-type", 2129 "Specifies the KVM virtualization mode (HV, PR)", 2130 NULL); 2131 } 2132 2133 static void spapr_machine_finalizefn(Object *obj) 2134 { 2135 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2136 2137 g_free(spapr->kvm_type); 2138 } 2139 2140 static void ppc_cpu_do_nmi_on_cpu(void *arg) 2141 { 2142 CPUState *cs = arg; 2143 2144 cpu_synchronize_state(cs); 2145 ppc_cpu_do_system_reset(cs); 2146 } 2147 2148 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2149 { 2150 CPUState *cs; 2151 2152 CPU_FOREACH(cs) { 2153 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 2154 } 2155 } 2156 2157 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2158 uint32_t node, Error **errp) 2159 { 2160 sPAPRDRConnector *drc; 2161 sPAPRDRConnectorClass *drck; 2162 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2163 int i, fdt_offset, fdt_size; 2164 void *fdt; 2165 2166 for (i = 0; i < nr_lmbs; i++) { 2167 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2168 addr/SPAPR_MEMORY_BLOCK_SIZE); 2169 g_assert(drc); 2170 2171 fdt = create_device_tree(&fdt_size); 2172 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2173 SPAPR_MEMORY_BLOCK_SIZE); 2174 2175 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2176 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2177 addr += SPAPR_MEMORY_BLOCK_SIZE; 2178 } 2179 /* send hotplug notification to the 2180 * guest only in case of hotplugged memory 2181 */ 2182 if (dev->hotplugged) { 2183 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2184 } 2185 } 2186 2187 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2188 uint32_t node, Error **errp) 2189 { 2190 Error *local_err = NULL; 2191 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2192 PCDIMMDevice *dimm = PC_DIMM(dev); 2193 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2194 MemoryRegion *mr = ddc->get_memory_region(dimm); 2195 uint64_t align = memory_region_get_alignment(mr); 2196 uint64_t size = memory_region_size(mr); 2197 uint64_t addr; 2198 2199 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2200 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2201 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2202 goto out; 2203 } 2204 2205 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2206 if (local_err) { 2207 goto out; 2208 } 2209 2210 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2211 if (local_err) { 2212 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2213 goto out; 2214 } 2215 2216 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2217 2218 out: 2219 error_propagate(errp, local_err); 2220 } 2221 2222 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2223 DeviceState *dev, Error **errp) 2224 { 2225 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2226 2227 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2228 int node; 2229 2230 if (!smc->dr_lmb_enabled) { 2231 error_setg(errp, "Memory hotplug not supported for this machine"); 2232 return; 2233 } 2234 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2235 if (*errp) { 2236 return; 2237 } 2238 if (node < 0 || node >= MAX_NODES) { 2239 error_setg(errp, "Invaild node %d", node); 2240 return; 2241 } 2242 2243 /* 2244 * Currently PowerPC kernel doesn't allow hot-adding memory to 2245 * memory-less node, but instead will silently add the memory 2246 * to the first node that has some memory. This causes two 2247 * unexpected behaviours for the user. 2248 * 2249 * - Memory gets hotplugged to a different node than what the user 2250 * specified. 2251 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2252 * to memory-less node, a reboot will set things accordingly 2253 * and the previously hotplugged memory now ends in the right node. 2254 * This appears as if some memory moved from one node to another. 2255 * 2256 * So until kernel starts supporting memory hotplug to memory-less 2257 * nodes, just prevent such attempts upfront in QEMU. 2258 */ 2259 if (nb_numa_nodes && !numa_info[node].node_mem) { 2260 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2261 node); 2262 return; 2263 } 2264 2265 spapr_memory_plug(hotplug_dev, dev, node, errp); 2266 } 2267 } 2268 2269 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2270 DeviceState *dev, Error **errp) 2271 { 2272 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2273 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2274 } 2275 } 2276 2277 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, 2278 DeviceState *dev) 2279 { 2280 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2281 return HOTPLUG_HANDLER(machine); 2282 } 2283 return NULL; 2284 } 2285 2286 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2287 { 2288 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2289 * socket means much for the paravirtualized PAPR platform) */ 2290 return cpu_index / smp_threads / smp_cores; 2291 } 2292 2293 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2294 { 2295 MachineClass *mc = MACHINE_CLASS(oc); 2296 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2297 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2298 NMIClass *nc = NMI_CLASS(oc); 2299 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2300 2301 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2302 2303 /* 2304 * We set up the default / latest behaviour here. The class_init 2305 * functions for the specific versioned machine types can override 2306 * these details for backwards compatibility 2307 */ 2308 mc->init = ppc_spapr_init; 2309 mc->reset = ppc_spapr_reset; 2310 mc->block_default_type = IF_SCSI; 2311 mc->max_cpus = MAX_CPUMASK_BITS; 2312 mc->no_parallel = 1; 2313 mc->default_boot_order = ""; 2314 mc->default_ram_size = 512 * M_BYTE; 2315 mc->kvm_type = spapr_kvm_type; 2316 mc->has_dynamic_sysbus = true; 2317 mc->pci_allow_0_address = true; 2318 mc->get_hotplug_handler = spapr_get_hotpug_handler; 2319 hc->plug = spapr_machine_device_plug; 2320 hc->unplug = spapr_machine_device_unplug; 2321 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2322 2323 smc->dr_lmb_enabled = true; 2324 fwc->get_dev_path = spapr_get_fw_dev_path; 2325 nc->nmi_monitor_handler = spapr_nmi; 2326 } 2327 2328 static const TypeInfo spapr_machine_info = { 2329 .name = TYPE_SPAPR_MACHINE, 2330 .parent = TYPE_MACHINE, 2331 .abstract = true, 2332 .instance_size = sizeof(sPAPRMachineState), 2333 .instance_init = spapr_machine_initfn, 2334 .instance_finalize = spapr_machine_finalizefn, 2335 .class_size = sizeof(sPAPRMachineClass), 2336 .class_init = spapr_machine_class_init, 2337 .interfaces = (InterfaceInfo[]) { 2338 { TYPE_FW_PATH_PROVIDER }, 2339 { TYPE_NMI }, 2340 { TYPE_HOTPLUG_HANDLER }, 2341 { } 2342 }, 2343 }; 2344 2345 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2346 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2347 void *data) \ 2348 { \ 2349 MachineClass *mc = MACHINE_CLASS(oc); \ 2350 spapr_machine_##suffix##_class_options(mc); \ 2351 if (latest) { \ 2352 mc->alias = "pseries"; \ 2353 mc->is_default = 1; \ 2354 } \ 2355 } \ 2356 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2357 { \ 2358 MachineState *machine = MACHINE(obj); \ 2359 spapr_machine_##suffix##_instance_options(machine); \ 2360 } \ 2361 static const TypeInfo spapr_machine_##suffix##_info = { \ 2362 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2363 .parent = TYPE_SPAPR_MACHINE, \ 2364 .class_init = spapr_machine_##suffix##_class_init, \ 2365 .instance_init = spapr_machine_##suffix##_instance_init, \ 2366 }; \ 2367 static void spapr_machine_register_##suffix(void) \ 2368 { \ 2369 type_register(&spapr_machine_##suffix##_info); \ 2370 } \ 2371 type_init(spapr_machine_register_##suffix) 2372 2373 /* 2374 * pseries-2.7 2375 */ 2376 static void spapr_machine_2_7_instance_options(MachineState *machine) 2377 { 2378 } 2379 2380 static void spapr_machine_2_7_class_options(MachineClass *mc) 2381 { 2382 /* Defaults for the latest behaviour inherited from the base class */ 2383 } 2384 2385 DEFINE_SPAPR_MACHINE(2_7, "2.7", true); 2386 2387 /* 2388 * pseries-2.6 2389 */ 2390 #define SPAPR_COMPAT_2_6 \ 2391 HW_COMPAT_2_6 2392 2393 static void spapr_machine_2_6_instance_options(MachineState *machine) 2394 { 2395 } 2396 2397 static void spapr_machine_2_6_class_options(MachineClass *mc) 2398 { 2399 spapr_machine_2_7_class_options(mc); 2400 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 2401 } 2402 2403 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 2404 2405 /* 2406 * pseries-2.5 2407 */ 2408 #define SPAPR_COMPAT_2_5 \ 2409 HW_COMPAT_2_5 \ 2410 { \ 2411 .driver = "spapr-vlan", \ 2412 .property = "use-rx-buffer-pools", \ 2413 .value = "off", \ 2414 }, 2415 2416 static void spapr_machine_2_5_instance_options(MachineState *machine) 2417 { 2418 } 2419 2420 static void spapr_machine_2_5_class_options(MachineClass *mc) 2421 { 2422 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2423 2424 spapr_machine_2_6_class_options(mc); 2425 smc->use_ohci_by_default = true; 2426 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2427 } 2428 2429 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2430 2431 /* 2432 * pseries-2.4 2433 */ 2434 #define SPAPR_COMPAT_2_4 \ 2435 HW_COMPAT_2_4 2436 2437 static void spapr_machine_2_4_instance_options(MachineState *machine) 2438 { 2439 spapr_machine_2_5_instance_options(machine); 2440 } 2441 2442 static void spapr_machine_2_4_class_options(MachineClass *mc) 2443 { 2444 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2445 2446 spapr_machine_2_5_class_options(mc); 2447 smc->dr_lmb_enabled = false; 2448 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2449 } 2450 2451 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2452 2453 /* 2454 * pseries-2.3 2455 */ 2456 #define SPAPR_COMPAT_2_3 \ 2457 HW_COMPAT_2_3 \ 2458 {\ 2459 .driver = "spapr-pci-host-bridge",\ 2460 .property = "dynamic-reconfiguration",\ 2461 .value = "off",\ 2462 }, 2463 2464 static void spapr_machine_2_3_instance_options(MachineState *machine) 2465 { 2466 spapr_machine_2_4_instance_options(machine); 2467 savevm_skip_section_footers(); 2468 global_state_set_optional(); 2469 savevm_skip_configuration(); 2470 } 2471 2472 static void spapr_machine_2_3_class_options(MachineClass *mc) 2473 { 2474 spapr_machine_2_4_class_options(mc); 2475 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 2476 } 2477 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 2478 2479 /* 2480 * pseries-2.2 2481 */ 2482 2483 #define SPAPR_COMPAT_2_2 \ 2484 HW_COMPAT_2_2 \ 2485 {\ 2486 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2487 .property = "mem_win_size",\ 2488 .value = "0x20000000",\ 2489 }, 2490 2491 static void spapr_machine_2_2_instance_options(MachineState *machine) 2492 { 2493 spapr_machine_2_3_instance_options(machine); 2494 machine->suppress_vmdesc = true; 2495 } 2496 2497 static void spapr_machine_2_2_class_options(MachineClass *mc) 2498 { 2499 spapr_machine_2_3_class_options(mc); 2500 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 2501 } 2502 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 2503 2504 /* 2505 * pseries-2.1 2506 */ 2507 #define SPAPR_COMPAT_2_1 \ 2508 HW_COMPAT_2_1 2509 2510 static void spapr_machine_2_1_instance_options(MachineState *machine) 2511 { 2512 spapr_machine_2_2_instance_options(machine); 2513 } 2514 2515 static void spapr_machine_2_1_class_options(MachineClass *mc) 2516 { 2517 spapr_machine_2_2_class_options(mc); 2518 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 2519 } 2520 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 2521 2522 static void spapr_machine_register_types(void) 2523 { 2524 type_register_static(&spapr_machine_info); 2525 } 2526 2527 type_init(spapr_machine_register_types) 2528