1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/ppc/xics.h" 58 #include "hw/pci/msi.h" 59 60 #include "hw/pci/pci.h" 61 #include "hw/scsi/scsi.h" 62 #include "hw/virtio/virtio-scsi.h" 63 #include "hw/virtio/vhost-scsi-common.h" 64 65 #include "exec/address-spaces.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "hw/compat.h" 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "qmp-commands.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 103 const char *type_ics, 104 int nr_irqs, Error **errp) 105 { 106 Error *local_err = NULL; 107 Object *obj; 108 109 obj = object_new(type_ics); 110 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 111 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 112 &error_abort); 113 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 114 if (local_err) { 115 goto error; 116 } 117 object_property_set_bool(obj, true, "realized", &local_err); 118 if (local_err) { 119 goto error; 120 } 121 122 return ICS_SIMPLE(obj); 123 124 error: 125 error_propagate(errp, local_err); 126 return NULL; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 static inline int xics_max_server_number(void) 164 { 165 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); 166 } 167 168 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 169 { 170 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 171 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 172 173 if (kvm_enabled()) { 174 if (machine_kernel_irqchip_allowed(machine) && 175 !xics_kvm_init(spapr, errp)) { 176 spapr->icp_type = TYPE_KVM_ICP; 177 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 178 } 179 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 180 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 181 return; 182 } 183 } 184 185 if (!spapr->ics) { 186 xics_spapr_init(spapr); 187 spapr->icp_type = TYPE_ICP; 188 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 189 if (!spapr->ics) { 190 return; 191 } 192 } 193 194 if (smc->pre_2_10_has_unused_icps) { 195 int i; 196 197 for (i = 0; i < xics_max_server_number(); i++) { 198 /* Dummy entries get deregistered when real ICPState objects 199 * are registered during CPU core hotplug. 200 */ 201 pre_2_10_vmstate_register_dummy_icp(i); 202 } 203 } 204 } 205 206 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 207 int smt_threads) 208 { 209 int i, ret = 0; 210 uint32_t servers_prop[smt_threads]; 211 uint32_t gservers_prop[smt_threads * 2]; 212 int index = spapr_vcpu_id(cpu); 213 214 if (cpu->compat_pvr) { 215 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 216 if (ret < 0) { 217 return ret; 218 } 219 } 220 221 /* Build interrupt servers and gservers properties */ 222 for (i = 0; i < smt_threads; i++) { 223 servers_prop[i] = cpu_to_be32(index + i); 224 /* Hack, direct the group queues back to cpu 0 */ 225 gservers_prop[i*2] = cpu_to_be32(index + i); 226 gservers_prop[i*2 + 1] = 0; 227 } 228 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 229 servers_prop, sizeof(servers_prop)); 230 if (ret < 0) { 231 return ret; 232 } 233 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 234 gservers_prop, sizeof(gservers_prop)); 235 236 return ret; 237 } 238 239 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 240 { 241 int index = spapr_vcpu_id(cpu); 242 uint32_t associativity[] = {cpu_to_be32(0x5), 243 cpu_to_be32(0x0), 244 cpu_to_be32(0x0), 245 cpu_to_be32(0x0), 246 cpu_to_be32(cpu->node_id), 247 cpu_to_be32(index)}; 248 249 /* Advertise NUMA via ibm,associativity */ 250 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 251 sizeof(associativity)); 252 } 253 254 /* Populate the "ibm,pa-features" property */ 255 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 256 bool legacy_guest) 257 { 258 uint8_t pa_features_206[] = { 6, 0, 259 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 260 uint8_t pa_features_207[] = { 24, 0, 261 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 262 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 263 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 264 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 265 uint8_t pa_features_300[] = { 66, 0, 266 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 267 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 268 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 269 /* 6: DS207 */ 270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 271 /* 16: Vector */ 272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 273 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 274 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 275 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 276 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 277 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 278 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 279 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 280 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 281 /* 42: PM, 44: PC RA, 46: SC vec'd */ 282 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 283 /* 48: SIMD, 50: QP BFP, 52: String */ 284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 285 /* 54: DecFP, 56: DecI, 58: SHA */ 286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 287 /* 60: NM atomic, 62: RNG */ 288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 289 }; 290 uint8_t *pa_features; 291 size_t pa_size; 292 293 switch (POWERPC_MMU_VER(env->mmu_model)) { 294 case POWERPC_MMU_VER_2_06: 295 pa_features = pa_features_206; 296 pa_size = sizeof(pa_features_206); 297 break; 298 case POWERPC_MMU_VER_2_07: 299 pa_features = pa_features_207; 300 pa_size = sizeof(pa_features_207); 301 break; 302 case POWERPC_MMU_VER_3_00: 303 pa_features = pa_features_300; 304 pa_size = sizeof(pa_features_300); 305 break; 306 default: 307 return; 308 } 309 310 if (env->ci_large_pages) { 311 /* 312 * Note: we keep CI large pages off by default because a 64K capable 313 * guest provisioned with large pages might otherwise try to map a qemu 314 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 315 * even if that qemu runs on a 4k host. 316 * We dd this bit back here if we are confident this is not an issue 317 */ 318 pa_features[3] |= 0x20; 319 } 320 if (kvmppc_has_cap_htm() && pa_size > 24) { 321 pa_features[24] |= 0x80; /* Transactional memory support */ 322 } 323 if (legacy_guest && pa_size > 40) { 324 /* Workaround for broken kernels that attempt (guest) radix 325 * mode when they can't handle it, if they see the radix bit set 326 * in pa-features. So hide it from them. */ 327 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 328 } 329 330 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 331 } 332 333 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 334 { 335 int ret = 0, offset, cpus_offset; 336 CPUState *cs; 337 char cpu_model[32]; 338 int smt = kvmppc_smt_threads(); 339 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 340 341 CPU_FOREACH(cs) { 342 PowerPCCPU *cpu = POWERPC_CPU(cs); 343 CPUPPCState *env = &cpu->env; 344 DeviceClass *dc = DEVICE_GET_CLASS(cs); 345 int index = spapr_vcpu_id(cpu); 346 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 347 348 if ((index % smt) != 0) { 349 continue; 350 } 351 352 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 353 354 cpus_offset = fdt_path_offset(fdt, "/cpus"); 355 if (cpus_offset < 0) { 356 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 357 "cpus"); 358 if (cpus_offset < 0) { 359 return cpus_offset; 360 } 361 } 362 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 363 if (offset < 0) { 364 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 365 if (offset < 0) { 366 return offset; 367 } 368 } 369 370 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 371 pft_size_prop, sizeof(pft_size_prop)); 372 if (ret < 0) { 373 return ret; 374 } 375 376 if (nb_numa_nodes > 1) { 377 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 378 if (ret < 0) { 379 return ret; 380 } 381 } 382 383 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 384 if (ret < 0) { 385 return ret; 386 } 387 388 spapr_populate_pa_features(env, fdt, offset, 389 spapr->cas_legacy_guest_workaround); 390 } 391 return ret; 392 } 393 394 static hwaddr spapr_node0_size(MachineState *machine) 395 { 396 if (nb_numa_nodes) { 397 int i; 398 for (i = 0; i < nb_numa_nodes; ++i) { 399 if (numa_info[i].node_mem) { 400 return MIN(pow2floor(numa_info[i].node_mem), 401 machine->ram_size); 402 } 403 } 404 } 405 return machine->ram_size; 406 } 407 408 static void add_str(GString *s, const gchar *s1) 409 { 410 g_string_append_len(s, s1, strlen(s1) + 1); 411 } 412 413 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 414 hwaddr size) 415 { 416 uint32_t associativity[] = { 417 cpu_to_be32(0x4), /* length */ 418 cpu_to_be32(0x0), cpu_to_be32(0x0), 419 cpu_to_be32(0x0), cpu_to_be32(nodeid) 420 }; 421 char mem_name[32]; 422 uint64_t mem_reg_property[2]; 423 int off; 424 425 mem_reg_property[0] = cpu_to_be64(start); 426 mem_reg_property[1] = cpu_to_be64(size); 427 428 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 429 off = fdt_add_subnode(fdt, 0, mem_name); 430 _FDT(off); 431 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 432 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 433 sizeof(mem_reg_property)))); 434 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 435 sizeof(associativity)))); 436 return off; 437 } 438 439 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 440 { 441 MachineState *machine = MACHINE(spapr); 442 hwaddr mem_start, node_size; 443 int i, nb_nodes = nb_numa_nodes; 444 NodeInfo *nodes = numa_info; 445 NodeInfo ramnode; 446 447 /* No NUMA nodes, assume there is just one node with whole RAM */ 448 if (!nb_numa_nodes) { 449 nb_nodes = 1; 450 ramnode.node_mem = machine->ram_size; 451 nodes = &ramnode; 452 } 453 454 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 455 if (!nodes[i].node_mem) { 456 continue; 457 } 458 if (mem_start >= machine->ram_size) { 459 node_size = 0; 460 } else { 461 node_size = nodes[i].node_mem; 462 if (node_size > machine->ram_size - mem_start) { 463 node_size = machine->ram_size - mem_start; 464 } 465 } 466 if (!mem_start) { 467 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 468 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 469 mem_start += spapr->rma_size; 470 node_size -= spapr->rma_size; 471 } 472 for ( ; node_size; ) { 473 hwaddr sizetmp = pow2floor(node_size); 474 475 /* mem_start != 0 here */ 476 if (ctzl(mem_start) < ctzl(sizetmp)) { 477 sizetmp = 1ULL << ctzl(mem_start); 478 } 479 480 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 481 node_size -= sizetmp; 482 mem_start += sizetmp; 483 } 484 } 485 486 return 0; 487 } 488 489 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 490 sPAPRMachineState *spapr) 491 { 492 PowerPCCPU *cpu = POWERPC_CPU(cs); 493 CPUPPCState *env = &cpu->env; 494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 495 int index = spapr_vcpu_id(cpu); 496 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 497 0xffffffff, 0xffffffff}; 498 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 499 : SPAPR_TIMEBASE_FREQ; 500 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 501 uint32_t page_sizes_prop[64]; 502 size_t page_sizes_prop_size; 503 uint32_t vcpus_per_socket = smp_threads * smp_cores; 504 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 505 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 506 sPAPRDRConnector *drc; 507 int drc_index; 508 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 509 int i; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 512 if (drc) { 513 drc_index = spapr_drc_index(drc); 514 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 515 } 516 517 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 518 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 519 520 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 521 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 522 env->dcache_line_size))); 523 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 524 env->dcache_line_size))); 525 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 526 env->icache_line_size))); 527 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 528 env->icache_line_size))); 529 530 if (pcc->l1_dcache_size) { 531 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 532 pcc->l1_dcache_size))); 533 } else { 534 warn_report("Unknown L1 dcache size for cpu"); 535 } 536 if (pcc->l1_icache_size) { 537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 538 pcc->l1_icache_size))); 539 } else { 540 warn_report("Unknown L1 icache size for cpu"); 541 } 542 543 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 544 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 545 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 546 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 547 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 548 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 549 550 if (env->spr_cb[SPR_PURR].oea_read) { 551 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 552 } 553 554 if (env->mmu_model & POWERPC_MMU_1TSEG) { 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 556 segs, sizeof(segs)))); 557 } 558 559 /* Advertise VMX/VSX (vector extensions) if available 560 * 0 / no property == no vector extensions 561 * 1 == VMX / Altivec available 562 * 2 == VSX available */ 563 if (env->insns_flags & PPC_ALTIVEC) { 564 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 565 566 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 567 } 568 569 /* Advertise DFP (Decimal Floating Point) if available 570 * 0 / no property == no DFP 571 * 1 == DFP available */ 572 if (env->insns_flags2 & PPC2_DFP) { 573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 574 } 575 576 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 577 sizeof(page_sizes_prop)); 578 if (page_sizes_prop_size) { 579 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 580 page_sizes_prop, page_sizes_prop_size))); 581 } 582 583 spapr_populate_pa_features(env, fdt, offset, false); 584 585 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 586 cs->cpu_index / vcpus_per_socket))); 587 588 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 589 pft_size_prop, sizeof(pft_size_prop)))); 590 591 if (nb_numa_nodes > 1) { 592 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 593 } 594 595 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 596 597 if (pcc->radix_page_info) { 598 for (i = 0; i < pcc->radix_page_info->count; i++) { 599 radix_AP_encodings[i] = 600 cpu_to_be32(pcc->radix_page_info->entries[i]); 601 } 602 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 603 radix_AP_encodings, 604 pcc->radix_page_info->count * 605 sizeof(radix_AP_encodings[0])))); 606 } 607 } 608 609 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 610 { 611 CPUState *cs; 612 int cpus_offset; 613 char *nodename; 614 int smt = kvmppc_smt_threads(); 615 616 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 617 _FDT(cpus_offset); 618 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 619 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 620 621 /* 622 * We walk the CPUs in reverse order to ensure that CPU DT nodes 623 * created by fdt_add_subnode() end up in the right order in FDT 624 * for the guest kernel the enumerate the CPUs correctly. 625 */ 626 CPU_FOREACH_REVERSE(cs) { 627 PowerPCCPU *cpu = POWERPC_CPU(cs); 628 int index = spapr_vcpu_id(cpu); 629 DeviceClass *dc = DEVICE_GET_CLASS(cs); 630 int offset; 631 632 if ((index % smt) != 0) { 633 continue; 634 } 635 636 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 637 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 638 g_free(nodename); 639 _FDT(offset); 640 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 641 } 642 643 } 644 645 /* 646 * Adds ibm,dynamic-reconfiguration-memory node. 647 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 648 * of this device tree node. 649 */ 650 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 651 { 652 MachineState *machine = MACHINE(spapr); 653 int ret, i, offset; 654 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 655 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 656 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 657 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 658 memory_region_size(&spapr->hotplug_memory.mr)) / 659 lmb_size; 660 uint32_t *int_buf, *cur_index, buf_len; 661 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 662 663 /* 664 * Don't create the node if there is no hotpluggable memory 665 */ 666 if (machine->ram_size == machine->maxram_size) { 667 return 0; 668 } 669 670 /* 671 * Allocate enough buffer size to fit in ibm,dynamic-memory 672 * or ibm,associativity-lookup-arrays 673 */ 674 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 675 * sizeof(uint32_t); 676 cur_index = int_buf = g_malloc0(buf_len); 677 678 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 679 680 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 681 sizeof(prop_lmb_size)); 682 if (ret < 0) { 683 goto out; 684 } 685 686 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 687 if (ret < 0) { 688 goto out; 689 } 690 691 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 692 if (ret < 0) { 693 goto out; 694 } 695 696 /* ibm,dynamic-memory */ 697 int_buf[0] = cpu_to_be32(nr_lmbs); 698 cur_index++; 699 for (i = 0; i < nr_lmbs; i++) { 700 uint64_t addr = i * lmb_size; 701 uint32_t *dynamic_memory = cur_index; 702 703 if (i >= hotplug_lmb_start) { 704 sPAPRDRConnector *drc; 705 706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 707 g_assert(drc); 708 709 dynamic_memory[0] = cpu_to_be32(addr >> 32); 710 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 711 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 712 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 713 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 714 if (memory_region_present(get_system_memory(), addr)) { 715 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 716 } else { 717 dynamic_memory[5] = cpu_to_be32(0); 718 } 719 } else { 720 /* 721 * LMB information for RMA, boot time RAM and gap b/n RAM and 722 * hotplug memory region -- all these are marked as reserved 723 * and as having no valid DRC. 724 */ 725 dynamic_memory[0] = cpu_to_be32(addr >> 32); 726 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 727 dynamic_memory[2] = cpu_to_be32(0); 728 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 729 dynamic_memory[4] = cpu_to_be32(-1); 730 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 731 SPAPR_LMB_FLAGS_DRC_INVALID); 732 } 733 734 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 735 } 736 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 737 if (ret < 0) { 738 goto out; 739 } 740 741 /* ibm,associativity-lookup-arrays */ 742 cur_index = int_buf; 743 int_buf[0] = cpu_to_be32(nr_nodes); 744 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 745 cur_index += 2; 746 for (i = 0; i < nr_nodes; i++) { 747 uint32_t associativity[] = { 748 cpu_to_be32(0x0), 749 cpu_to_be32(0x0), 750 cpu_to_be32(0x0), 751 cpu_to_be32(i) 752 }; 753 memcpy(cur_index, associativity, sizeof(associativity)); 754 cur_index += 4; 755 } 756 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 757 (cur_index - int_buf) * sizeof(uint32_t)); 758 out: 759 g_free(int_buf); 760 return ret; 761 } 762 763 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 764 sPAPROptionVector *ov5_updates) 765 { 766 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 767 int ret = 0, offset; 768 769 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 770 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 771 g_assert(smc->dr_lmb_enabled); 772 ret = spapr_populate_drconf_memory(spapr, fdt); 773 if (ret) { 774 goto out; 775 } 776 } 777 778 offset = fdt_path_offset(fdt, "/chosen"); 779 if (offset < 0) { 780 offset = fdt_add_subnode(fdt, 0, "chosen"); 781 if (offset < 0) { 782 return offset; 783 } 784 } 785 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 786 "ibm,architecture-vec-5"); 787 788 out: 789 return ret; 790 } 791 792 static bool spapr_hotplugged_dev_before_cas(void) 793 { 794 Object *drc_container, *obj; 795 ObjectProperty *prop; 796 ObjectPropertyIterator iter; 797 798 drc_container = container_get(object_get_root(), "/dr-connector"); 799 object_property_iter_init(&iter, drc_container); 800 while ((prop = object_property_iter_next(&iter))) { 801 if (!strstart(prop->type, "link<", NULL)) { 802 continue; 803 } 804 obj = object_property_get_link(drc_container, prop->name, NULL); 805 if (spapr_drc_needed(obj)) { 806 return true; 807 } 808 } 809 return false; 810 } 811 812 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 813 target_ulong addr, target_ulong size, 814 sPAPROptionVector *ov5_updates) 815 { 816 void *fdt, *fdt_skel; 817 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 818 819 if (spapr_hotplugged_dev_before_cas()) { 820 return 1; 821 } 822 823 size -= sizeof(hdr); 824 825 /* Create skeleton */ 826 fdt_skel = g_malloc0(size); 827 _FDT((fdt_create(fdt_skel, size))); 828 _FDT((fdt_begin_node(fdt_skel, ""))); 829 _FDT((fdt_end_node(fdt_skel))); 830 _FDT((fdt_finish(fdt_skel))); 831 fdt = g_malloc0(size); 832 _FDT((fdt_open_into(fdt_skel, fdt, size))); 833 g_free(fdt_skel); 834 835 /* Fixup cpu nodes */ 836 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 837 838 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 839 return -1; 840 } 841 842 /* Pack resulting tree */ 843 _FDT((fdt_pack(fdt))); 844 845 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 846 trace_spapr_cas_failed(size); 847 return -1; 848 } 849 850 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 851 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 852 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 853 g_free(fdt); 854 855 return 0; 856 } 857 858 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 859 { 860 int rtas; 861 GString *hypertas = g_string_sized_new(256); 862 GString *qemu_hypertas = g_string_sized_new(256); 863 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 864 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 865 memory_region_size(&spapr->hotplug_memory.mr); 866 uint32_t lrdr_capacity[] = { 867 cpu_to_be32(max_hotplug_addr >> 32), 868 cpu_to_be32(max_hotplug_addr & 0xffffffff), 869 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 870 cpu_to_be32(max_cpus / smp_threads), 871 }; 872 873 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 874 875 /* hypertas */ 876 add_str(hypertas, "hcall-pft"); 877 add_str(hypertas, "hcall-term"); 878 add_str(hypertas, "hcall-dabr"); 879 add_str(hypertas, "hcall-interrupt"); 880 add_str(hypertas, "hcall-tce"); 881 add_str(hypertas, "hcall-vio"); 882 add_str(hypertas, "hcall-splpar"); 883 add_str(hypertas, "hcall-bulk"); 884 add_str(hypertas, "hcall-set-mode"); 885 add_str(hypertas, "hcall-sprg0"); 886 add_str(hypertas, "hcall-copy"); 887 add_str(hypertas, "hcall-debug"); 888 add_str(qemu_hypertas, "hcall-memop1"); 889 890 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 891 add_str(hypertas, "hcall-multi-tce"); 892 } 893 894 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 895 add_str(hypertas, "hcall-hpt-resize"); 896 } 897 898 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 899 hypertas->str, hypertas->len)); 900 g_string_free(hypertas, TRUE); 901 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 902 qemu_hypertas->str, qemu_hypertas->len)); 903 g_string_free(qemu_hypertas, TRUE); 904 905 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 906 refpoints, sizeof(refpoints))); 907 908 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 909 RTAS_ERROR_LOG_MAX)); 910 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 911 RTAS_EVENT_SCAN_RATE)); 912 913 if (msi_nonbroken) { 914 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 915 } 916 917 /* 918 * According to PAPR, rtas ibm,os-term does not guarantee a return 919 * back to the guest cpu. 920 * 921 * While an additional ibm,extended-os-term property indicates 922 * that rtas call return will always occur. Set this property. 923 */ 924 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 925 926 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 927 lrdr_capacity, sizeof(lrdr_capacity))); 928 929 spapr_dt_rtas_tokens(fdt, rtas); 930 } 931 932 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 933 * that the guest may request and thus the valid values for bytes 24..26 of 934 * option vector 5: */ 935 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 936 { 937 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 938 939 char val[2 * 4] = { 940 23, 0x00, /* Xive mode, filled in below. */ 941 24, 0x00, /* Hash/Radix, filled in below. */ 942 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 943 26, 0x40, /* Radix options: GTSE == yes. */ 944 }; 945 946 if (kvm_enabled()) { 947 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 948 val[3] = 0x80; /* OV5_MMU_BOTH */ 949 } else if (kvmppc_has_cap_mmu_radix()) { 950 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 951 } else { 952 val[3] = 0x00; /* Hash */ 953 } 954 } else { 955 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 956 /* V3 MMU supports both hash and radix (with dynamic switching) */ 957 val[3] = 0xC0; 958 } else { 959 /* Otherwise we can only do hash */ 960 val[3] = 0x00; 961 } 962 } 963 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 964 val, sizeof(val))); 965 } 966 967 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 968 { 969 MachineState *machine = MACHINE(spapr); 970 int chosen; 971 const char *boot_device = machine->boot_order; 972 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 973 size_t cb = 0; 974 char *bootlist = get_boot_devices_list(&cb, true); 975 976 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 977 978 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 979 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 980 spapr->initrd_base)); 981 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 982 spapr->initrd_base + spapr->initrd_size)); 983 984 if (spapr->kernel_size) { 985 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 986 cpu_to_be64(spapr->kernel_size) }; 987 988 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 989 &kprop, sizeof(kprop))); 990 if (spapr->kernel_le) { 991 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 992 } 993 } 994 if (boot_menu) { 995 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 996 } 997 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 998 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 999 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1000 1001 if (cb && bootlist) { 1002 int i; 1003 1004 for (i = 0; i < cb; i++) { 1005 if (bootlist[i] == '\n') { 1006 bootlist[i] = ' '; 1007 } 1008 } 1009 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1010 } 1011 1012 if (boot_device && strlen(boot_device)) { 1013 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1014 } 1015 1016 if (!spapr->has_graphics && stdout_path) { 1017 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1018 } 1019 1020 spapr_dt_ov5_platform_support(fdt, chosen); 1021 1022 g_free(stdout_path); 1023 g_free(bootlist); 1024 } 1025 1026 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1027 { 1028 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1029 * KVM to work under pHyp with some guest co-operation */ 1030 int hypervisor; 1031 uint8_t hypercall[16]; 1032 1033 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1034 /* indicate KVM hypercall interface */ 1035 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1036 if (kvmppc_has_cap_fixup_hcalls()) { 1037 /* 1038 * Older KVM versions with older guest kernels were broken 1039 * with the magic page, don't allow the guest to map it. 1040 */ 1041 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1042 sizeof(hypercall))) { 1043 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1044 hypercall, sizeof(hypercall))); 1045 } 1046 } 1047 } 1048 1049 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1050 hwaddr rtas_addr, 1051 hwaddr rtas_size) 1052 { 1053 MachineState *machine = MACHINE(spapr); 1054 MachineClass *mc = MACHINE_GET_CLASS(machine); 1055 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1056 int ret; 1057 void *fdt; 1058 sPAPRPHBState *phb; 1059 char *buf; 1060 1061 fdt = g_malloc0(FDT_MAX_SIZE); 1062 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1063 1064 /* Root node */ 1065 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1066 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1067 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1068 1069 /* 1070 * Add info to guest to indentify which host is it being run on 1071 * and what is the uuid of the guest 1072 */ 1073 if (kvmppc_get_host_model(&buf)) { 1074 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1075 g_free(buf); 1076 } 1077 if (kvmppc_get_host_serial(&buf)) { 1078 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1079 g_free(buf); 1080 } 1081 1082 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1083 1084 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1085 if (qemu_uuid_set) { 1086 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1087 } 1088 g_free(buf); 1089 1090 if (qemu_get_vm_name()) { 1091 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1092 qemu_get_vm_name())); 1093 } 1094 1095 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1096 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1097 1098 /* /interrupt controller */ 1099 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); 1100 1101 ret = spapr_populate_memory(spapr, fdt); 1102 if (ret < 0) { 1103 error_report("couldn't setup memory nodes in fdt"); 1104 exit(1); 1105 } 1106 1107 /* /vdevice */ 1108 spapr_dt_vdevice(spapr->vio_bus, fdt); 1109 1110 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1111 ret = spapr_rng_populate_dt(fdt); 1112 if (ret < 0) { 1113 error_report("could not set up rng device in the fdt"); 1114 exit(1); 1115 } 1116 } 1117 1118 QLIST_FOREACH(phb, &spapr->phbs, list) { 1119 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1120 if (ret < 0) { 1121 error_report("couldn't setup PCI devices in fdt"); 1122 exit(1); 1123 } 1124 } 1125 1126 /* cpus */ 1127 spapr_populate_cpus_dt_node(fdt, spapr); 1128 1129 if (smc->dr_lmb_enabled) { 1130 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1131 } 1132 1133 if (mc->has_hotpluggable_cpus) { 1134 int offset = fdt_path_offset(fdt, "/cpus"); 1135 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1136 SPAPR_DR_CONNECTOR_TYPE_CPU); 1137 if (ret < 0) { 1138 error_report("Couldn't set up CPU DR device tree properties"); 1139 exit(1); 1140 } 1141 } 1142 1143 /* /event-sources */ 1144 spapr_dt_events(spapr, fdt); 1145 1146 /* /rtas */ 1147 spapr_dt_rtas(spapr, fdt); 1148 1149 /* /chosen */ 1150 spapr_dt_chosen(spapr, fdt); 1151 1152 /* /hypervisor */ 1153 if (kvm_enabled()) { 1154 spapr_dt_hypervisor(spapr, fdt); 1155 } 1156 1157 /* Build memory reserve map */ 1158 if (spapr->kernel_size) { 1159 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1160 } 1161 if (spapr->initrd_size) { 1162 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1163 } 1164 1165 /* ibm,client-architecture-support updates */ 1166 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1167 if (ret < 0) { 1168 error_report("couldn't setup CAS properties fdt"); 1169 exit(1); 1170 } 1171 1172 return fdt; 1173 } 1174 1175 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1176 { 1177 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1178 } 1179 1180 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1181 PowerPCCPU *cpu) 1182 { 1183 CPUPPCState *env = &cpu->env; 1184 1185 /* The TCG path should also be holding the BQL at this point */ 1186 g_assert(qemu_mutex_iothread_locked()); 1187 1188 if (msr_pr) { 1189 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1190 env->gpr[3] = H_PRIVILEGE; 1191 } else { 1192 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1193 } 1194 } 1195 1196 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1197 { 1198 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1199 1200 return spapr->patb_entry; 1201 } 1202 1203 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1204 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1205 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1206 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1207 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1208 1209 /* 1210 * Get the fd to access the kernel htab, re-opening it if necessary 1211 */ 1212 static int get_htab_fd(sPAPRMachineState *spapr) 1213 { 1214 if (spapr->htab_fd >= 0) { 1215 return spapr->htab_fd; 1216 } 1217 1218 spapr->htab_fd = kvmppc_get_htab_fd(false); 1219 if (spapr->htab_fd < 0) { 1220 error_report("Unable to open fd for reading hash table from KVM: %s", 1221 strerror(errno)); 1222 } 1223 1224 return spapr->htab_fd; 1225 } 1226 1227 void close_htab_fd(sPAPRMachineState *spapr) 1228 { 1229 if (spapr->htab_fd >= 0) { 1230 close(spapr->htab_fd); 1231 } 1232 spapr->htab_fd = -1; 1233 } 1234 1235 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1236 { 1237 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1238 1239 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1240 } 1241 1242 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1243 hwaddr ptex, int n) 1244 { 1245 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1246 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1247 1248 if (!spapr->htab) { 1249 /* 1250 * HTAB is controlled by KVM. Fetch into temporary buffer 1251 */ 1252 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1253 kvmppc_read_hptes(hptes, ptex, n); 1254 return hptes; 1255 } 1256 1257 /* 1258 * HTAB is controlled by QEMU. Just point to the internally 1259 * accessible PTEG. 1260 */ 1261 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1262 } 1263 1264 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1265 const ppc_hash_pte64_t *hptes, 1266 hwaddr ptex, int n) 1267 { 1268 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1269 1270 if (!spapr->htab) { 1271 g_free((void *)hptes); 1272 } 1273 1274 /* Nothing to do for qemu managed HPT */ 1275 } 1276 1277 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1278 uint64_t pte0, uint64_t pte1) 1279 { 1280 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1281 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1282 1283 if (!spapr->htab) { 1284 kvmppc_write_hpte(ptex, pte0, pte1); 1285 } else { 1286 stq_p(spapr->htab + offset, pte0); 1287 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1288 } 1289 } 1290 1291 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1292 { 1293 int shift; 1294 1295 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1296 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1297 * that's much more than is needed for Linux guests */ 1298 shift = ctz64(pow2ceil(ramsize)) - 7; 1299 shift = MAX(shift, 18); /* Minimum architected size */ 1300 shift = MIN(shift, 46); /* Maximum architected size */ 1301 return shift; 1302 } 1303 1304 void spapr_free_hpt(sPAPRMachineState *spapr) 1305 { 1306 g_free(spapr->htab); 1307 spapr->htab = NULL; 1308 spapr->htab_shift = 0; 1309 close_htab_fd(spapr); 1310 } 1311 1312 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1313 Error **errp) 1314 { 1315 long rc; 1316 1317 /* Clean up any HPT info from a previous boot */ 1318 spapr_free_hpt(spapr); 1319 1320 rc = kvmppc_reset_htab(shift); 1321 if (rc < 0) { 1322 /* kernel-side HPT needed, but couldn't allocate one */ 1323 error_setg_errno(errp, errno, 1324 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1325 shift); 1326 /* This is almost certainly fatal, but if the caller really 1327 * wants to carry on with shift == 0, it's welcome to try */ 1328 } else if (rc > 0) { 1329 /* kernel-side HPT allocated */ 1330 if (rc != shift) { 1331 error_setg(errp, 1332 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1333 shift, rc); 1334 } 1335 1336 spapr->htab_shift = shift; 1337 spapr->htab = NULL; 1338 } else { 1339 /* kernel-side HPT not needed, allocate in userspace instead */ 1340 size_t size = 1ULL << shift; 1341 int i; 1342 1343 spapr->htab = qemu_memalign(size, size); 1344 if (!spapr->htab) { 1345 error_setg_errno(errp, errno, 1346 "Could not allocate HPT of order %d", shift); 1347 return; 1348 } 1349 1350 memset(spapr->htab, 0, size); 1351 spapr->htab_shift = shift; 1352 1353 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1354 DIRTY_HPTE(HPTE(spapr->htab, i)); 1355 } 1356 } 1357 } 1358 1359 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1360 { 1361 int hpt_shift; 1362 1363 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1364 || (spapr->cas_reboot 1365 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1366 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1367 } else { 1368 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size); 1369 } 1370 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1371 1372 if (spapr->vrma_adjust) { 1373 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1374 spapr->htab_shift); 1375 } 1376 /* We're setting up a hash table, so that means we're not radix */ 1377 spapr->patb_entry = 0; 1378 } 1379 1380 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1381 { 1382 bool matched = false; 1383 1384 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1385 matched = true; 1386 } 1387 1388 if (!matched) { 1389 error_report("Device %s is not supported by this machine yet.", 1390 qdev_fw_name(DEVICE(sbdev))); 1391 exit(1); 1392 } 1393 } 1394 1395 static void ppc_spapr_reset(void) 1396 { 1397 MachineState *machine = MACHINE(qdev_get_machine()); 1398 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1399 PowerPCCPU *first_ppc_cpu; 1400 uint32_t rtas_limit; 1401 hwaddr rtas_addr, fdt_addr; 1402 void *fdt; 1403 int rc; 1404 1405 /* Check for unknown sysbus devices */ 1406 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1407 1408 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1409 /* If using KVM with radix mode available, VCPUs can be started 1410 * without a HPT because KVM will start them in radix mode. 1411 * Set the GR bit in PATB so that we know there is no HPT. */ 1412 spapr->patb_entry = PATBE1_GR; 1413 } else { 1414 spapr_setup_hpt_and_vrma(spapr); 1415 } 1416 1417 qemu_devices_reset(); 1418 spapr_clear_pending_events(spapr); 1419 1420 /* 1421 * We place the device tree and RTAS just below either the top of the RMA, 1422 * or just below 2GB, whichever is lowere, so that it can be 1423 * processed with 32-bit real mode code if necessary 1424 */ 1425 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1426 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1427 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1428 1429 /* if this reset wasn't generated by CAS, we should reset our 1430 * negotiated options and start from scratch */ 1431 if (!spapr->cas_reboot) { 1432 spapr_ovec_cleanup(spapr->ov5_cas); 1433 spapr->ov5_cas = spapr_ovec_new(); 1434 1435 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1436 } 1437 1438 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1439 1440 spapr_load_rtas(spapr, fdt, rtas_addr); 1441 1442 rc = fdt_pack(fdt); 1443 1444 /* Should only fail if we've built a corrupted tree */ 1445 assert(rc == 0); 1446 1447 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1448 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1449 fdt_totalsize(fdt), FDT_MAX_SIZE); 1450 exit(1); 1451 } 1452 1453 /* Load the fdt */ 1454 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1455 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1456 g_free(fdt); 1457 1458 /* Set up the entry state */ 1459 first_ppc_cpu = POWERPC_CPU(first_cpu); 1460 first_ppc_cpu->env.gpr[3] = fdt_addr; 1461 first_ppc_cpu->env.gpr[5] = 0; 1462 first_cpu->halted = 0; 1463 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1464 1465 spapr->cas_reboot = false; 1466 } 1467 1468 static void spapr_create_nvram(sPAPRMachineState *spapr) 1469 { 1470 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1471 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1472 1473 if (dinfo) { 1474 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1475 &error_fatal); 1476 } 1477 1478 qdev_init_nofail(dev); 1479 1480 spapr->nvram = (struct sPAPRNVRAM *)dev; 1481 } 1482 1483 static void spapr_rtc_create(sPAPRMachineState *spapr) 1484 { 1485 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1486 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1487 &error_fatal); 1488 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1489 &error_fatal); 1490 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1491 "date", &error_fatal); 1492 } 1493 1494 /* Returns whether we want to use VGA or not */ 1495 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1496 { 1497 switch (vga_interface_type) { 1498 case VGA_NONE: 1499 return false; 1500 case VGA_DEVICE: 1501 return true; 1502 case VGA_STD: 1503 case VGA_VIRTIO: 1504 return pci_vga_init(pci_bus) != NULL; 1505 default: 1506 error_setg(errp, 1507 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1508 return false; 1509 } 1510 } 1511 1512 static int spapr_post_load(void *opaque, int version_id) 1513 { 1514 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1515 int err = 0; 1516 1517 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1518 CPUState *cs; 1519 CPU_FOREACH(cs) { 1520 PowerPCCPU *cpu = POWERPC_CPU(cs); 1521 icp_resend(ICP(cpu->intc)); 1522 } 1523 } 1524 1525 /* In earlier versions, there was no separate qdev for the PAPR 1526 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1527 * So when migrating from those versions, poke the incoming offset 1528 * value into the RTC device */ 1529 if (version_id < 3) { 1530 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1531 } 1532 1533 if (spapr->patb_entry) { 1534 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1535 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1536 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1537 1538 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1539 if (err) { 1540 error_report("Process table config unsupported by the host"); 1541 return -EINVAL; 1542 } 1543 } 1544 1545 return err; 1546 } 1547 1548 static bool version_before_3(void *opaque, int version_id) 1549 { 1550 return version_id < 3; 1551 } 1552 1553 static bool spapr_pending_events_needed(void *opaque) 1554 { 1555 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1556 return !QTAILQ_EMPTY(&spapr->pending_events); 1557 } 1558 1559 static const VMStateDescription vmstate_spapr_event_entry = { 1560 .name = "spapr_event_log_entry", 1561 .version_id = 1, 1562 .minimum_version_id = 1, 1563 .fields = (VMStateField[]) { 1564 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1565 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1566 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1567 NULL, extended_length), 1568 VMSTATE_END_OF_LIST() 1569 }, 1570 }; 1571 1572 static const VMStateDescription vmstate_spapr_pending_events = { 1573 .name = "spapr_pending_events", 1574 .version_id = 1, 1575 .minimum_version_id = 1, 1576 .needed = spapr_pending_events_needed, 1577 .fields = (VMStateField[]) { 1578 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1579 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1580 VMSTATE_END_OF_LIST() 1581 }, 1582 }; 1583 1584 static bool spapr_ov5_cas_needed(void *opaque) 1585 { 1586 sPAPRMachineState *spapr = opaque; 1587 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1588 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1589 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1590 bool cas_needed; 1591 1592 /* Prior to the introduction of sPAPROptionVector, we had two option 1593 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1594 * Both of these options encode machine topology into the device-tree 1595 * in such a way that the now-booted OS should still be able to interact 1596 * appropriately with QEMU regardless of what options were actually 1597 * negotiatied on the source side. 1598 * 1599 * As such, we can avoid migrating the CAS-negotiated options if these 1600 * are the only options available on the current machine/platform. 1601 * Since these are the only options available for pseries-2.7 and 1602 * earlier, this allows us to maintain old->new/new->old migration 1603 * compatibility. 1604 * 1605 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1606 * via default pseries-2.8 machines and explicit command-line parameters. 1607 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1608 * of the actual CAS-negotiated values to continue working properly. For 1609 * example, availability of memory unplug depends on knowing whether 1610 * OV5_HP_EVT was negotiated via CAS. 1611 * 1612 * Thus, for any cases where the set of available CAS-negotiatable 1613 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1614 * include the CAS-negotiated options in the migration stream. 1615 */ 1616 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1617 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1618 1619 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1620 * the mask itself since in the future it's possible "legacy" bits may be 1621 * removed via machine options, which could generate a false positive 1622 * that breaks migration. 1623 */ 1624 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1625 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1626 1627 spapr_ovec_cleanup(ov5_mask); 1628 spapr_ovec_cleanup(ov5_legacy); 1629 spapr_ovec_cleanup(ov5_removed); 1630 1631 return cas_needed; 1632 } 1633 1634 static const VMStateDescription vmstate_spapr_ov5_cas = { 1635 .name = "spapr_option_vector_ov5_cas", 1636 .version_id = 1, 1637 .minimum_version_id = 1, 1638 .needed = spapr_ov5_cas_needed, 1639 .fields = (VMStateField[]) { 1640 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1641 vmstate_spapr_ovec, sPAPROptionVector), 1642 VMSTATE_END_OF_LIST() 1643 }, 1644 }; 1645 1646 static bool spapr_patb_entry_needed(void *opaque) 1647 { 1648 sPAPRMachineState *spapr = opaque; 1649 1650 return !!spapr->patb_entry; 1651 } 1652 1653 static const VMStateDescription vmstate_spapr_patb_entry = { 1654 .name = "spapr_patb_entry", 1655 .version_id = 1, 1656 .minimum_version_id = 1, 1657 .needed = spapr_patb_entry_needed, 1658 .fields = (VMStateField[]) { 1659 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1660 VMSTATE_END_OF_LIST() 1661 }, 1662 }; 1663 1664 static const VMStateDescription vmstate_spapr = { 1665 .name = "spapr", 1666 .version_id = 3, 1667 .minimum_version_id = 1, 1668 .post_load = spapr_post_load, 1669 .fields = (VMStateField[]) { 1670 /* used to be @next_irq */ 1671 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1672 1673 /* RTC offset */ 1674 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1675 1676 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1677 VMSTATE_END_OF_LIST() 1678 }, 1679 .subsections = (const VMStateDescription*[]) { 1680 &vmstate_spapr_ov5_cas, 1681 &vmstate_spapr_patb_entry, 1682 &vmstate_spapr_pending_events, 1683 NULL 1684 } 1685 }; 1686 1687 static int htab_save_setup(QEMUFile *f, void *opaque) 1688 { 1689 sPAPRMachineState *spapr = opaque; 1690 1691 /* "Iteration" header */ 1692 if (!spapr->htab_shift) { 1693 qemu_put_be32(f, -1); 1694 } else { 1695 qemu_put_be32(f, spapr->htab_shift); 1696 } 1697 1698 if (spapr->htab) { 1699 spapr->htab_save_index = 0; 1700 spapr->htab_first_pass = true; 1701 } else { 1702 if (spapr->htab_shift) { 1703 assert(kvm_enabled()); 1704 } 1705 } 1706 1707 1708 return 0; 1709 } 1710 1711 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1712 int64_t max_ns) 1713 { 1714 bool has_timeout = max_ns != -1; 1715 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1716 int index = spapr->htab_save_index; 1717 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1718 1719 assert(spapr->htab_first_pass); 1720 1721 do { 1722 int chunkstart; 1723 1724 /* Consume invalid HPTEs */ 1725 while ((index < htabslots) 1726 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1727 CLEAN_HPTE(HPTE(spapr->htab, index)); 1728 index++; 1729 } 1730 1731 /* Consume valid HPTEs */ 1732 chunkstart = index; 1733 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1734 && HPTE_VALID(HPTE(spapr->htab, index))) { 1735 CLEAN_HPTE(HPTE(spapr->htab, index)); 1736 index++; 1737 } 1738 1739 if (index > chunkstart) { 1740 int n_valid = index - chunkstart; 1741 1742 qemu_put_be32(f, chunkstart); 1743 qemu_put_be16(f, n_valid); 1744 qemu_put_be16(f, 0); 1745 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1746 HASH_PTE_SIZE_64 * n_valid); 1747 1748 if (has_timeout && 1749 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1750 break; 1751 } 1752 } 1753 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1754 1755 if (index >= htabslots) { 1756 assert(index == htabslots); 1757 index = 0; 1758 spapr->htab_first_pass = false; 1759 } 1760 spapr->htab_save_index = index; 1761 } 1762 1763 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1764 int64_t max_ns) 1765 { 1766 bool final = max_ns < 0; 1767 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1768 int examined = 0, sent = 0; 1769 int index = spapr->htab_save_index; 1770 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1771 1772 assert(!spapr->htab_first_pass); 1773 1774 do { 1775 int chunkstart, invalidstart; 1776 1777 /* Consume non-dirty HPTEs */ 1778 while ((index < htabslots) 1779 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1780 index++; 1781 examined++; 1782 } 1783 1784 chunkstart = index; 1785 /* Consume valid dirty HPTEs */ 1786 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1787 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1788 && HPTE_VALID(HPTE(spapr->htab, index))) { 1789 CLEAN_HPTE(HPTE(spapr->htab, index)); 1790 index++; 1791 examined++; 1792 } 1793 1794 invalidstart = index; 1795 /* Consume invalid dirty HPTEs */ 1796 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1797 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1798 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1799 CLEAN_HPTE(HPTE(spapr->htab, index)); 1800 index++; 1801 examined++; 1802 } 1803 1804 if (index > chunkstart) { 1805 int n_valid = invalidstart - chunkstart; 1806 int n_invalid = index - invalidstart; 1807 1808 qemu_put_be32(f, chunkstart); 1809 qemu_put_be16(f, n_valid); 1810 qemu_put_be16(f, n_invalid); 1811 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1812 HASH_PTE_SIZE_64 * n_valid); 1813 sent += index - chunkstart; 1814 1815 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1816 break; 1817 } 1818 } 1819 1820 if (examined >= htabslots) { 1821 break; 1822 } 1823 1824 if (index >= htabslots) { 1825 assert(index == htabslots); 1826 index = 0; 1827 } 1828 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1829 1830 if (index >= htabslots) { 1831 assert(index == htabslots); 1832 index = 0; 1833 } 1834 1835 spapr->htab_save_index = index; 1836 1837 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1838 } 1839 1840 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1841 #define MAX_KVM_BUF_SIZE 2048 1842 1843 static int htab_save_iterate(QEMUFile *f, void *opaque) 1844 { 1845 sPAPRMachineState *spapr = opaque; 1846 int fd; 1847 int rc = 0; 1848 1849 /* Iteration header */ 1850 if (!spapr->htab_shift) { 1851 qemu_put_be32(f, -1); 1852 return 1; 1853 } else { 1854 qemu_put_be32(f, 0); 1855 } 1856 1857 if (!spapr->htab) { 1858 assert(kvm_enabled()); 1859 1860 fd = get_htab_fd(spapr); 1861 if (fd < 0) { 1862 return fd; 1863 } 1864 1865 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1866 if (rc < 0) { 1867 return rc; 1868 } 1869 } else if (spapr->htab_first_pass) { 1870 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1871 } else { 1872 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1873 } 1874 1875 /* End marker */ 1876 qemu_put_be32(f, 0); 1877 qemu_put_be16(f, 0); 1878 qemu_put_be16(f, 0); 1879 1880 return rc; 1881 } 1882 1883 static int htab_save_complete(QEMUFile *f, void *opaque) 1884 { 1885 sPAPRMachineState *spapr = opaque; 1886 int fd; 1887 1888 /* Iteration header */ 1889 if (!spapr->htab_shift) { 1890 qemu_put_be32(f, -1); 1891 return 0; 1892 } else { 1893 qemu_put_be32(f, 0); 1894 } 1895 1896 if (!spapr->htab) { 1897 int rc; 1898 1899 assert(kvm_enabled()); 1900 1901 fd = get_htab_fd(spapr); 1902 if (fd < 0) { 1903 return fd; 1904 } 1905 1906 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1907 if (rc < 0) { 1908 return rc; 1909 } 1910 } else { 1911 if (spapr->htab_first_pass) { 1912 htab_save_first_pass(f, spapr, -1); 1913 } 1914 htab_save_later_pass(f, spapr, -1); 1915 } 1916 1917 /* End marker */ 1918 qemu_put_be32(f, 0); 1919 qemu_put_be16(f, 0); 1920 qemu_put_be16(f, 0); 1921 1922 return 0; 1923 } 1924 1925 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1926 { 1927 sPAPRMachineState *spapr = opaque; 1928 uint32_t section_hdr; 1929 int fd = -1; 1930 1931 if (version_id < 1 || version_id > 1) { 1932 error_report("htab_load() bad version"); 1933 return -EINVAL; 1934 } 1935 1936 section_hdr = qemu_get_be32(f); 1937 1938 if (section_hdr == -1) { 1939 spapr_free_hpt(spapr); 1940 return 0; 1941 } 1942 1943 if (section_hdr) { 1944 Error *local_err = NULL; 1945 1946 /* First section gives the htab size */ 1947 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1948 if (local_err) { 1949 error_report_err(local_err); 1950 return -EINVAL; 1951 } 1952 return 0; 1953 } 1954 1955 if (!spapr->htab) { 1956 assert(kvm_enabled()); 1957 1958 fd = kvmppc_get_htab_fd(true); 1959 if (fd < 0) { 1960 error_report("Unable to open fd to restore KVM hash table: %s", 1961 strerror(errno)); 1962 } 1963 } 1964 1965 while (true) { 1966 uint32_t index; 1967 uint16_t n_valid, n_invalid; 1968 1969 index = qemu_get_be32(f); 1970 n_valid = qemu_get_be16(f); 1971 n_invalid = qemu_get_be16(f); 1972 1973 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1974 /* End of Stream */ 1975 break; 1976 } 1977 1978 if ((index + n_valid + n_invalid) > 1979 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1980 /* Bad index in stream */ 1981 error_report( 1982 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1983 index, n_valid, n_invalid, spapr->htab_shift); 1984 return -EINVAL; 1985 } 1986 1987 if (spapr->htab) { 1988 if (n_valid) { 1989 qemu_get_buffer(f, HPTE(spapr->htab, index), 1990 HASH_PTE_SIZE_64 * n_valid); 1991 } 1992 if (n_invalid) { 1993 memset(HPTE(spapr->htab, index + n_valid), 0, 1994 HASH_PTE_SIZE_64 * n_invalid); 1995 } 1996 } else { 1997 int rc; 1998 1999 assert(fd >= 0); 2000 2001 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2002 if (rc < 0) { 2003 return rc; 2004 } 2005 } 2006 } 2007 2008 if (!spapr->htab) { 2009 assert(fd >= 0); 2010 close(fd); 2011 } 2012 2013 return 0; 2014 } 2015 2016 static void htab_save_cleanup(void *opaque) 2017 { 2018 sPAPRMachineState *spapr = opaque; 2019 2020 close_htab_fd(spapr); 2021 } 2022 2023 static SaveVMHandlers savevm_htab_handlers = { 2024 .save_setup = htab_save_setup, 2025 .save_live_iterate = htab_save_iterate, 2026 .save_live_complete_precopy = htab_save_complete, 2027 .save_cleanup = htab_save_cleanup, 2028 .load_state = htab_load, 2029 }; 2030 2031 static void spapr_boot_set(void *opaque, const char *boot_device, 2032 Error **errp) 2033 { 2034 MachineState *machine = MACHINE(opaque); 2035 machine->boot_order = g_strdup(boot_device); 2036 } 2037 2038 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2039 { 2040 MachineState *machine = MACHINE(spapr); 2041 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2042 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2043 int i; 2044 2045 for (i = 0; i < nr_lmbs; i++) { 2046 uint64_t addr; 2047 2048 addr = i * lmb_size + spapr->hotplug_memory.base; 2049 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2050 addr / lmb_size); 2051 } 2052 } 2053 2054 /* 2055 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2056 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2057 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2058 */ 2059 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2060 { 2061 int i; 2062 2063 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2064 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2065 " is not aligned to %llu MiB", 2066 machine->ram_size, 2067 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2068 return; 2069 } 2070 2071 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2072 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2073 " is not aligned to %llu MiB", 2074 machine->ram_size, 2075 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2076 return; 2077 } 2078 2079 for (i = 0; i < nb_numa_nodes; i++) { 2080 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2081 error_setg(errp, 2082 "Node %d memory size 0x%" PRIx64 2083 " is not aligned to %llu MiB", 2084 i, numa_info[i].node_mem, 2085 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2086 return; 2087 } 2088 } 2089 } 2090 2091 /* find cpu slot in machine->possible_cpus by core_id */ 2092 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2093 { 2094 int index = id / smp_threads; 2095 2096 if (index >= ms->possible_cpus->len) { 2097 return NULL; 2098 } 2099 if (idx) { 2100 *idx = index; 2101 } 2102 return &ms->possible_cpus->cpus[index]; 2103 } 2104 2105 static void spapr_init_cpus(sPAPRMachineState *spapr) 2106 { 2107 MachineState *machine = MACHINE(spapr); 2108 MachineClass *mc = MACHINE_GET_CLASS(machine); 2109 char *type = spapr_get_cpu_core_type(machine->cpu_model); 2110 int smt = kvmppc_smt_threads(); 2111 const CPUArchIdList *possible_cpus; 2112 int boot_cores_nr = smp_cpus / smp_threads; 2113 int i; 2114 2115 if (!type) { 2116 error_report("Unable to find sPAPR CPU Core definition"); 2117 exit(1); 2118 } 2119 2120 possible_cpus = mc->possible_cpu_arch_ids(machine); 2121 if (mc->has_hotpluggable_cpus) { 2122 if (smp_cpus % smp_threads) { 2123 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2124 smp_cpus, smp_threads); 2125 exit(1); 2126 } 2127 if (max_cpus % smp_threads) { 2128 error_report("max_cpus (%u) must be multiple of threads (%u)", 2129 max_cpus, smp_threads); 2130 exit(1); 2131 } 2132 } else { 2133 if (max_cpus != smp_cpus) { 2134 error_report("This machine version does not support CPU hotplug"); 2135 exit(1); 2136 } 2137 boot_cores_nr = possible_cpus->len; 2138 } 2139 2140 for (i = 0; i < possible_cpus->len; i++) { 2141 int core_id = i * smp_threads; 2142 2143 if (mc->has_hotpluggable_cpus) { 2144 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2145 (core_id / smp_threads) * smt); 2146 } 2147 2148 if (i < boot_cores_nr) { 2149 Object *core = object_new(type); 2150 int nr_threads = smp_threads; 2151 2152 /* Handle the partially filled core for older machine types */ 2153 if ((i + 1) * smp_threads >= smp_cpus) { 2154 nr_threads = smp_cpus - i * smp_threads; 2155 } 2156 2157 object_property_set_int(core, nr_threads, "nr-threads", 2158 &error_fatal); 2159 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2160 &error_fatal); 2161 object_property_set_bool(core, true, "realized", &error_fatal); 2162 } 2163 } 2164 g_free(type); 2165 } 2166 2167 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2168 { 2169 Error *local_err = NULL; 2170 bool vsmt_user = !!spapr->vsmt; 2171 int kvm_smt = kvmppc_smt_threads(); 2172 int ret; 2173 2174 if (!kvm_enabled() && (smp_threads > 1)) { 2175 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2176 "on a pseries machine"); 2177 goto out; 2178 } 2179 if (!is_power_of_2(smp_threads)) { 2180 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2181 "machine because it must be a power of 2", smp_threads); 2182 goto out; 2183 } 2184 2185 /* Detemine the VSMT mode to use: */ 2186 if (vsmt_user) { 2187 if (spapr->vsmt < smp_threads) { 2188 error_setg(&local_err, "Cannot support VSMT mode %d" 2189 " because it must be >= threads/core (%d)", 2190 spapr->vsmt, smp_threads); 2191 goto out; 2192 } 2193 /* In this case, spapr->vsmt has been set by the command line */ 2194 } else { 2195 /* Choose a VSMT mode that may be higher than necessary but is 2196 * likely to be compatible with hosts that don't have VSMT. */ 2197 spapr->vsmt = MAX(kvm_smt, smp_threads); 2198 } 2199 2200 /* KVM: If necessary, set the SMT mode: */ 2201 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2202 ret = kvmppc_set_smt_threads(spapr->vsmt); 2203 if (ret) { 2204 error_setg(&local_err, 2205 "Failed to set KVM's VSMT mode to %d (errno %d)", 2206 spapr->vsmt, ret); 2207 if (!vsmt_user) { 2208 error_append_hint(&local_err, "On PPC, a VM with %d threads/" 2209 "core on a host with %d threads/core requires " 2210 " the use of VSMT mode %d.\n", 2211 smp_threads, kvm_smt, spapr->vsmt); 2212 } 2213 kvmppc_hint_smt_possible(&local_err); 2214 goto out; 2215 } 2216 } 2217 /* else TCG: nothing to do currently */ 2218 out: 2219 error_propagate(errp, local_err); 2220 } 2221 2222 /* pSeries LPAR / sPAPR hardware init */ 2223 static void ppc_spapr_init(MachineState *machine) 2224 { 2225 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2226 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2227 const char *kernel_filename = machine->kernel_filename; 2228 const char *initrd_filename = machine->initrd_filename; 2229 PCIHostState *phb; 2230 int i; 2231 MemoryRegion *sysmem = get_system_memory(); 2232 MemoryRegion *ram = g_new(MemoryRegion, 1); 2233 MemoryRegion *rma_region; 2234 void *rma = NULL; 2235 hwaddr rma_alloc_size; 2236 hwaddr node0_size = spapr_node0_size(machine); 2237 long load_limit, fw_size; 2238 char *filename; 2239 Error *resize_hpt_err = NULL; 2240 2241 msi_nonbroken = true; 2242 2243 QLIST_INIT(&spapr->phbs); 2244 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2245 2246 /* Check HPT resizing availability */ 2247 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2248 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2249 /* 2250 * If the user explicitly requested a mode we should either 2251 * supply it, or fail completely (which we do below). But if 2252 * it's not set explicitly, we reset our mode to something 2253 * that works 2254 */ 2255 if (resize_hpt_err) { 2256 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2257 error_free(resize_hpt_err); 2258 resize_hpt_err = NULL; 2259 } else { 2260 spapr->resize_hpt = smc->resize_hpt_default; 2261 } 2262 } 2263 2264 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2265 2266 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2267 /* 2268 * User requested HPT resize, but this host can't supply it. Bail out 2269 */ 2270 error_report_err(resize_hpt_err); 2271 exit(1); 2272 } 2273 2274 /* Allocate RMA if necessary */ 2275 rma_alloc_size = kvmppc_alloc_rma(&rma); 2276 2277 if (rma_alloc_size == -1) { 2278 error_report("Unable to create RMA"); 2279 exit(1); 2280 } 2281 2282 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2283 spapr->rma_size = rma_alloc_size; 2284 } else { 2285 spapr->rma_size = node0_size; 2286 2287 /* With KVM, we don't actually know whether KVM supports an 2288 * unbounded RMA (PR KVM) or is limited by the hash table size 2289 * (HV KVM using VRMA), so we always assume the latter 2290 * 2291 * In that case, we also limit the initial allocations for RTAS 2292 * etc... to 256M since we have no way to know what the VRMA size 2293 * is going to be as it depends on the size of the hash table 2294 * isn't determined yet. 2295 */ 2296 if (kvm_enabled()) { 2297 spapr->vrma_adjust = 1; 2298 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2299 } 2300 2301 /* Actually we don't support unbounded RMA anymore since we 2302 * added proper emulation of HV mode. The max we can get is 2303 * 16G which also happens to be what we configure for PAPR 2304 * mode so make sure we don't do anything bigger than that 2305 */ 2306 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2307 } 2308 2309 if (spapr->rma_size > node0_size) { 2310 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2311 spapr->rma_size); 2312 exit(1); 2313 } 2314 2315 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2316 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2317 2318 /* Set up Interrupt Controller before we create the VCPUs */ 2319 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2320 2321 /* Set up containers for ibm,client-set-architecture negotiated options */ 2322 spapr->ov5 = spapr_ovec_new(); 2323 spapr->ov5_cas = spapr_ovec_new(); 2324 2325 if (smc->dr_lmb_enabled) { 2326 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2327 spapr_validate_node_memory(machine, &error_fatal); 2328 } 2329 2330 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2331 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2332 /* KVM and TCG always allow GTSE with radix... */ 2333 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2334 } 2335 /* ... but not with hash (currently). */ 2336 2337 /* advertise support for dedicated HP event source to guests */ 2338 if (spapr->use_hotplug_event_source) { 2339 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2340 } 2341 2342 /* advertise support for HPT resizing */ 2343 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2344 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2345 } 2346 2347 /* init CPUs */ 2348 if (machine->cpu_model == NULL) { 2349 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2350 } 2351 2352 spapr_cpu_parse_features(spapr); 2353 2354 spapr_set_vsmt_mode(spapr, &error_fatal); 2355 2356 spapr_init_cpus(spapr); 2357 2358 if (kvm_enabled()) { 2359 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2360 kvmppc_enable_logical_ci_hcalls(); 2361 kvmppc_enable_set_mode_hcall(); 2362 2363 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2364 kvmppc_enable_clear_ref_mod_hcalls(); 2365 } 2366 2367 /* allocate RAM */ 2368 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2369 machine->ram_size); 2370 memory_region_add_subregion(sysmem, 0, ram); 2371 2372 if (rma_alloc_size && rma) { 2373 rma_region = g_new(MemoryRegion, 1); 2374 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2375 rma_alloc_size, rma); 2376 vmstate_register_ram_global(rma_region); 2377 memory_region_add_subregion(sysmem, 0, rma_region); 2378 } 2379 2380 /* initialize hotplug memory address space */ 2381 if (machine->ram_size < machine->maxram_size) { 2382 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2383 /* 2384 * Limit the number of hotpluggable memory slots to half the number 2385 * slots that KVM supports, leaving the other half for PCI and other 2386 * devices. However ensure that number of slots doesn't drop below 32. 2387 */ 2388 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2389 SPAPR_MAX_RAM_SLOTS; 2390 2391 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2392 max_memslots = SPAPR_MAX_RAM_SLOTS; 2393 } 2394 if (machine->ram_slots > max_memslots) { 2395 error_report("Specified number of memory slots %" 2396 PRIu64" exceeds max supported %d", 2397 machine->ram_slots, max_memslots); 2398 exit(1); 2399 } 2400 2401 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2402 SPAPR_HOTPLUG_MEM_ALIGN); 2403 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2404 "hotplug-memory", hotplug_mem_size); 2405 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2406 &spapr->hotplug_memory.mr); 2407 } 2408 2409 if (smc->dr_lmb_enabled) { 2410 spapr_create_lmb_dr_connectors(spapr); 2411 } 2412 2413 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2414 if (!filename) { 2415 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2416 exit(1); 2417 } 2418 spapr->rtas_size = get_image_size(filename); 2419 if (spapr->rtas_size < 0) { 2420 error_report("Could not get size of LPAR rtas '%s'", filename); 2421 exit(1); 2422 } 2423 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2424 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2425 error_report("Could not load LPAR rtas '%s'", filename); 2426 exit(1); 2427 } 2428 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2429 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2430 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2431 exit(1); 2432 } 2433 g_free(filename); 2434 2435 /* Set up RTAS event infrastructure */ 2436 spapr_events_init(spapr); 2437 2438 /* Set up the RTC RTAS interfaces */ 2439 spapr_rtc_create(spapr); 2440 2441 /* Set up VIO bus */ 2442 spapr->vio_bus = spapr_vio_bus_init(); 2443 2444 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2445 if (serial_hds[i]) { 2446 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2447 } 2448 } 2449 2450 /* We always have at least the nvram device on VIO */ 2451 spapr_create_nvram(spapr); 2452 2453 /* Set up PCI */ 2454 spapr_pci_rtas_init(); 2455 2456 phb = spapr_create_phb(spapr, 0); 2457 2458 for (i = 0; i < nb_nics; i++) { 2459 NICInfo *nd = &nd_table[i]; 2460 2461 if (!nd->model) { 2462 nd->model = g_strdup("ibmveth"); 2463 } 2464 2465 if (strcmp(nd->model, "ibmveth") == 0) { 2466 spapr_vlan_create(spapr->vio_bus, nd); 2467 } else { 2468 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2469 } 2470 } 2471 2472 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2473 spapr_vscsi_create(spapr->vio_bus); 2474 } 2475 2476 /* Graphics */ 2477 if (spapr_vga_init(phb->bus, &error_fatal)) { 2478 spapr->has_graphics = true; 2479 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2480 } 2481 2482 if (machine->usb) { 2483 if (smc->use_ohci_by_default) { 2484 pci_create_simple(phb->bus, -1, "pci-ohci"); 2485 } else { 2486 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2487 } 2488 2489 if (spapr->has_graphics) { 2490 USBBus *usb_bus = usb_bus_find(-1); 2491 2492 usb_create_simple(usb_bus, "usb-kbd"); 2493 usb_create_simple(usb_bus, "usb-mouse"); 2494 } 2495 } 2496 2497 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2498 error_report( 2499 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2500 MIN_RMA_SLOF); 2501 exit(1); 2502 } 2503 2504 if (kernel_filename) { 2505 uint64_t lowaddr = 0; 2506 2507 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2508 NULL, NULL, &lowaddr, NULL, 1, 2509 PPC_ELF_MACHINE, 0, 0); 2510 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2511 spapr->kernel_size = load_elf(kernel_filename, 2512 translate_kernel_address, NULL, NULL, 2513 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2514 0, 0); 2515 spapr->kernel_le = spapr->kernel_size > 0; 2516 } 2517 if (spapr->kernel_size < 0) { 2518 error_report("error loading %s: %s", kernel_filename, 2519 load_elf_strerror(spapr->kernel_size)); 2520 exit(1); 2521 } 2522 2523 /* load initrd */ 2524 if (initrd_filename) { 2525 /* Try to locate the initrd in the gap between the kernel 2526 * and the firmware. Add a bit of space just in case 2527 */ 2528 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2529 + 0x1ffff) & ~0xffff; 2530 spapr->initrd_size = load_image_targphys(initrd_filename, 2531 spapr->initrd_base, 2532 load_limit 2533 - spapr->initrd_base); 2534 if (spapr->initrd_size < 0) { 2535 error_report("could not load initial ram disk '%s'", 2536 initrd_filename); 2537 exit(1); 2538 } 2539 } 2540 } 2541 2542 if (bios_name == NULL) { 2543 bios_name = FW_FILE_NAME; 2544 } 2545 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2546 if (!filename) { 2547 error_report("Could not find LPAR firmware '%s'", bios_name); 2548 exit(1); 2549 } 2550 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2551 if (fw_size <= 0) { 2552 error_report("Could not load LPAR firmware '%s'", filename); 2553 exit(1); 2554 } 2555 g_free(filename); 2556 2557 /* FIXME: Should register things through the MachineState's qdev 2558 * interface, this is a legacy from the sPAPREnvironment structure 2559 * which predated MachineState but had a similar function */ 2560 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2561 register_savevm_live(NULL, "spapr/htab", -1, 1, 2562 &savevm_htab_handlers, spapr); 2563 2564 qemu_register_boot_set(spapr_boot_set, spapr); 2565 2566 if (kvm_enabled()) { 2567 /* to stop and start vmclock */ 2568 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2569 &spapr->tb); 2570 2571 kvmppc_spapr_enable_inkernel_multitce(); 2572 } 2573 } 2574 2575 static int spapr_kvm_type(const char *vm_type) 2576 { 2577 if (!vm_type) { 2578 return 0; 2579 } 2580 2581 if (!strcmp(vm_type, "HV")) { 2582 return 1; 2583 } 2584 2585 if (!strcmp(vm_type, "PR")) { 2586 return 2; 2587 } 2588 2589 error_report("Unknown kvm-type specified '%s'", vm_type); 2590 exit(1); 2591 } 2592 2593 /* 2594 * Implementation of an interface to adjust firmware path 2595 * for the bootindex property handling. 2596 */ 2597 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2598 DeviceState *dev) 2599 { 2600 #define CAST(type, obj, name) \ 2601 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2602 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2603 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2604 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2605 2606 if (d) { 2607 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2608 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2609 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2610 2611 if (spapr) { 2612 /* 2613 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2614 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2615 * in the top 16 bits of the 64-bit LUN 2616 */ 2617 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2618 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2619 (uint64_t)id << 48); 2620 } else if (virtio) { 2621 /* 2622 * We use SRP luns of the form 01000000 | (target << 8) | lun 2623 * in the top 32 bits of the 64-bit LUN 2624 * Note: the quote above is from SLOF and it is wrong, 2625 * the actual binding is: 2626 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2627 */ 2628 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2629 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2630 (uint64_t)id << 32); 2631 } else if (usb) { 2632 /* 2633 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2634 * in the top 32 bits of the 64-bit LUN 2635 */ 2636 unsigned usb_port = atoi(usb->port->path); 2637 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2638 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2639 (uint64_t)id << 32); 2640 } 2641 } 2642 2643 /* 2644 * SLOF probes the USB devices, and if it recognizes that the device is a 2645 * storage device, it changes its name to "storage" instead of "usb-host", 2646 * and additionally adds a child node for the SCSI LUN, so the correct 2647 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2648 */ 2649 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2650 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2651 if (usb_host_dev_is_scsi_storage(usbdev)) { 2652 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2653 } 2654 } 2655 2656 if (phb) { 2657 /* Replace "pci" with "pci@800000020000000" */ 2658 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2659 } 2660 2661 if (vsc) { 2662 /* Same logic as virtio above */ 2663 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2664 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2665 } 2666 2667 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2668 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2669 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2670 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2671 } 2672 2673 return NULL; 2674 } 2675 2676 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2677 { 2678 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2679 2680 return g_strdup(spapr->kvm_type); 2681 } 2682 2683 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2684 { 2685 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2686 2687 g_free(spapr->kvm_type); 2688 spapr->kvm_type = g_strdup(value); 2689 } 2690 2691 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2692 { 2693 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2694 2695 return spapr->use_hotplug_event_source; 2696 } 2697 2698 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2699 Error **errp) 2700 { 2701 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2702 2703 spapr->use_hotplug_event_source = value; 2704 } 2705 2706 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2707 { 2708 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2709 2710 switch (spapr->resize_hpt) { 2711 case SPAPR_RESIZE_HPT_DEFAULT: 2712 return g_strdup("default"); 2713 case SPAPR_RESIZE_HPT_DISABLED: 2714 return g_strdup("disabled"); 2715 case SPAPR_RESIZE_HPT_ENABLED: 2716 return g_strdup("enabled"); 2717 case SPAPR_RESIZE_HPT_REQUIRED: 2718 return g_strdup("required"); 2719 } 2720 g_assert_not_reached(); 2721 } 2722 2723 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2724 { 2725 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2726 2727 if (strcmp(value, "default") == 0) { 2728 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2729 } else if (strcmp(value, "disabled") == 0) { 2730 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2731 } else if (strcmp(value, "enabled") == 0) { 2732 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2733 } else if (strcmp(value, "required") == 0) { 2734 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2735 } else { 2736 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2737 } 2738 } 2739 2740 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2741 void *opaque, Error **errp) 2742 { 2743 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2744 } 2745 2746 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 2747 void *opaque, Error **errp) 2748 { 2749 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2750 } 2751 2752 static void spapr_machine_initfn(Object *obj) 2753 { 2754 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2755 2756 spapr->htab_fd = -1; 2757 spapr->use_hotplug_event_source = true; 2758 object_property_add_str(obj, "kvm-type", 2759 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2760 object_property_set_description(obj, "kvm-type", 2761 "Specifies the KVM virtualization mode (HV, PR)", 2762 NULL); 2763 object_property_add_bool(obj, "modern-hotplug-events", 2764 spapr_get_modern_hotplug_events, 2765 spapr_set_modern_hotplug_events, 2766 NULL); 2767 object_property_set_description(obj, "modern-hotplug-events", 2768 "Use dedicated hotplug event mechanism in" 2769 " place of standard EPOW events when possible" 2770 " (required for memory hot-unplug support)", 2771 NULL); 2772 2773 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2774 "Maximum permitted CPU compatibility mode", 2775 &error_fatal); 2776 2777 object_property_add_str(obj, "resize-hpt", 2778 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 2779 object_property_set_description(obj, "resize-hpt", 2780 "Resizing of the Hash Page Table (enabled, disabled, required)", 2781 NULL); 2782 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 2783 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 2784 object_property_set_description(obj, "vsmt", 2785 "Virtual SMT: KVM behaves as if this were" 2786 " the host's SMT mode", &error_abort); 2787 } 2788 2789 static void spapr_machine_finalizefn(Object *obj) 2790 { 2791 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2792 2793 g_free(spapr->kvm_type); 2794 } 2795 2796 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2797 { 2798 cpu_synchronize_state(cs); 2799 ppc_cpu_do_system_reset(cs); 2800 } 2801 2802 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2803 { 2804 CPUState *cs; 2805 2806 CPU_FOREACH(cs) { 2807 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2808 } 2809 } 2810 2811 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2812 uint32_t node, bool dedicated_hp_event_source, 2813 Error **errp) 2814 { 2815 sPAPRDRConnector *drc; 2816 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2817 int i, fdt_offset, fdt_size; 2818 void *fdt; 2819 uint64_t addr = addr_start; 2820 bool hotplugged = spapr_drc_hotplugged(dev); 2821 Error *local_err = NULL; 2822 2823 for (i = 0; i < nr_lmbs; i++) { 2824 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2825 addr / SPAPR_MEMORY_BLOCK_SIZE); 2826 g_assert(drc); 2827 2828 fdt = create_device_tree(&fdt_size); 2829 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2830 SPAPR_MEMORY_BLOCK_SIZE); 2831 2832 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2833 if (local_err) { 2834 while (addr > addr_start) { 2835 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2836 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2837 addr / SPAPR_MEMORY_BLOCK_SIZE); 2838 spapr_drc_detach(drc); 2839 } 2840 g_free(fdt); 2841 error_propagate(errp, local_err); 2842 return; 2843 } 2844 if (!hotplugged) { 2845 spapr_drc_reset(drc); 2846 } 2847 addr += SPAPR_MEMORY_BLOCK_SIZE; 2848 } 2849 /* send hotplug notification to the 2850 * guest only in case of hotplugged memory 2851 */ 2852 if (hotplugged) { 2853 if (dedicated_hp_event_source) { 2854 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2855 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2856 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2857 nr_lmbs, 2858 spapr_drc_index(drc)); 2859 } else { 2860 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2861 nr_lmbs); 2862 } 2863 } 2864 } 2865 2866 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2867 uint32_t node, Error **errp) 2868 { 2869 Error *local_err = NULL; 2870 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2871 PCDIMMDevice *dimm = PC_DIMM(dev); 2872 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2873 MemoryRegion *mr; 2874 uint64_t align, size, addr; 2875 2876 mr = ddc->get_memory_region(dimm, &local_err); 2877 if (local_err) { 2878 goto out; 2879 } 2880 align = memory_region_get_alignment(mr); 2881 size = memory_region_size(mr); 2882 2883 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2884 if (local_err) { 2885 goto out; 2886 } 2887 2888 addr = object_property_get_uint(OBJECT(dimm), 2889 PC_DIMM_ADDR_PROP, &local_err); 2890 if (local_err) { 2891 goto out_unplug; 2892 } 2893 2894 spapr_add_lmbs(dev, addr, size, node, 2895 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2896 &local_err); 2897 if (local_err) { 2898 goto out_unplug; 2899 } 2900 2901 return; 2902 2903 out_unplug: 2904 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2905 out: 2906 error_propagate(errp, local_err); 2907 } 2908 2909 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2910 Error **errp) 2911 { 2912 PCDIMMDevice *dimm = PC_DIMM(dev); 2913 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2914 MemoryRegion *mr; 2915 uint64_t size; 2916 char *mem_dev; 2917 2918 mr = ddc->get_memory_region(dimm, errp); 2919 if (!mr) { 2920 return; 2921 } 2922 size = memory_region_size(mr); 2923 2924 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2925 error_setg(errp, "Hotplugged memory size must be a multiple of " 2926 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2927 return; 2928 } 2929 2930 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2931 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2932 error_setg(errp, "Memory backend has bad page size. " 2933 "Use 'memory-backend-file' with correct mem-path."); 2934 goto out; 2935 } 2936 2937 out: 2938 g_free(mem_dev); 2939 } 2940 2941 struct sPAPRDIMMState { 2942 PCDIMMDevice *dimm; 2943 uint32_t nr_lmbs; 2944 QTAILQ_ENTRY(sPAPRDIMMState) next; 2945 }; 2946 2947 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2948 PCDIMMDevice *dimm) 2949 { 2950 sPAPRDIMMState *dimm_state = NULL; 2951 2952 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2953 if (dimm_state->dimm == dimm) { 2954 break; 2955 } 2956 } 2957 return dimm_state; 2958 } 2959 2960 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2961 uint32_t nr_lmbs, 2962 PCDIMMDevice *dimm) 2963 { 2964 sPAPRDIMMState *ds = NULL; 2965 2966 /* 2967 * If this request is for a DIMM whose removal had failed earlier 2968 * (due to guest's refusal to remove the LMBs), we would have this 2969 * dimm already in the pending_dimm_unplugs list. In that 2970 * case don't add again. 2971 */ 2972 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 2973 if (!ds) { 2974 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2975 ds->nr_lmbs = nr_lmbs; 2976 ds->dimm = dimm; 2977 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 2978 } 2979 return ds; 2980 } 2981 2982 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 2983 sPAPRDIMMState *dimm_state) 2984 { 2985 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 2986 g_free(dimm_state); 2987 } 2988 2989 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 2990 PCDIMMDevice *dimm) 2991 { 2992 sPAPRDRConnector *drc; 2993 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2994 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 2995 uint64_t size = memory_region_size(mr); 2996 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2997 uint32_t avail_lmbs = 0; 2998 uint64_t addr_start, addr; 2999 int i; 3000 3001 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3002 &error_abort); 3003 3004 addr = addr_start; 3005 for (i = 0; i < nr_lmbs; i++) { 3006 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3007 addr / SPAPR_MEMORY_BLOCK_SIZE); 3008 g_assert(drc); 3009 if (drc->dev) { 3010 avail_lmbs++; 3011 } 3012 addr += SPAPR_MEMORY_BLOCK_SIZE; 3013 } 3014 3015 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3016 } 3017 3018 /* Callback to be called during DRC release. */ 3019 void spapr_lmb_release(DeviceState *dev) 3020 { 3021 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3022 PCDIMMDevice *dimm = PC_DIMM(dev); 3023 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3024 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3025 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3026 3027 /* This information will get lost if a migration occurs 3028 * during the unplug process. In this case recover it. */ 3029 if (ds == NULL) { 3030 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3031 g_assert(ds); 3032 /* The DRC being examined by the caller at least must be counted */ 3033 g_assert(ds->nr_lmbs); 3034 } 3035 3036 if (--ds->nr_lmbs) { 3037 return; 3038 } 3039 3040 spapr_pending_dimm_unplugs_remove(spapr, ds); 3041 3042 /* 3043 * Now that all the LMBs have been removed by the guest, call the 3044 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3045 */ 3046 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3047 object_unparent(OBJECT(dev)); 3048 } 3049 3050 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3051 DeviceState *dev, Error **errp) 3052 { 3053 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3054 Error *local_err = NULL; 3055 PCDIMMDevice *dimm = PC_DIMM(dev); 3056 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3057 MemoryRegion *mr; 3058 uint32_t nr_lmbs; 3059 uint64_t size, addr_start, addr; 3060 int i; 3061 sPAPRDRConnector *drc; 3062 3063 mr = ddc->get_memory_region(dimm, &local_err); 3064 if (local_err) { 3065 goto out; 3066 } 3067 size = memory_region_size(mr); 3068 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3069 3070 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3071 &local_err); 3072 if (local_err) { 3073 goto out; 3074 } 3075 3076 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3077 3078 addr = addr_start; 3079 for (i = 0; i < nr_lmbs; i++) { 3080 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3081 addr / SPAPR_MEMORY_BLOCK_SIZE); 3082 g_assert(drc); 3083 3084 spapr_drc_detach(drc); 3085 addr += SPAPR_MEMORY_BLOCK_SIZE; 3086 } 3087 3088 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3089 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3090 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3091 nr_lmbs, spapr_drc_index(drc)); 3092 out: 3093 error_propagate(errp, local_err); 3094 } 3095 3096 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3097 sPAPRMachineState *spapr) 3098 { 3099 PowerPCCPU *cpu = POWERPC_CPU(cs); 3100 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3101 int id = spapr_vcpu_id(cpu); 3102 void *fdt; 3103 int offset, fdt_size; 3104 char *nodename; 3105 3106 fdt = create_device_tree(&fdt_size); 3107 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3108 offset = fdt_add_subnode(fdt, 0, nodename); 3109 3110 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3111 g_free(nodename); 3112 3113 *fdt_offset = offset; 3114 return fdt; 3115 } 3116 3117 /* Callback to be called during DRC release. */ 3118 void spapr_core_release(DeviceState *dev) 3119 { 3120 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3121 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3122 CPUCore *cc = CPU_CORE(dev); 3123 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3124 3125 if (smc->pre_2_10_has_unused_icps) { 3126 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3127 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3128 const char *typename = object_class_get_name(scc->cpu_class); 3129 size_t size = object_type_get_instance_size(typename); 3130 int i; 3131 3132 for (i = 0; i < cc->nr_threads; i++) { 3133 CPUState *cs = CPU(sc->threads + i * size); 3134 3135 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3136 } 3137 } 3138 3139 assert(core_slot); 3140 core_slot->cpu = NULL; 3141 object_unparent(OBJECT(dev)); 3142 } 3143 3144 static 3145 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3146 Error **errp) 3147 { 3148 int index; 3149 sPAPRDRConnector *drc; 3150 CPUCore *cc = CPU_CORE(dev); 3151 int smt = kvmppc_smt_threads(); 3152 3153 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3154 error_setg(errp, "Unable to find CPU core with core-id: %d", 3155 cc->core_id); 3156 return; 3157 } 3158 if (index == 0) { 3159 error_setg(errp, "Boot CPU core may not be unplugged"); 3160 return; 3161 } 3162 3163 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3164 g_assert(drc); 3165 3166 spapr_drc_detach(drc); 3167 3168 spapr_hotplug_req_remove_by_index(drc); 3169 } 3170 3171 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3172 Error **errp) 3173 { 3174 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3175 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3176 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3177 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3178 CPUCore *cc = CPU_CORE(dev); 3179 CPUState *cs = CPU(core->threads); 3180 sPAPRDRConnector *drc; 3181 Error *local_err = NULL; 3182 int smt = kvmppc_smt_threads(); 3183 CPUArchId *core_slot; 3184 int index; 3185 bool hotplugged = spapr_drc_hotplugged(dev); 3186 3187 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3188 if (!core_slot) { 3189 error_setg(errp, "Unable to find CPU core with core-id: %d", 3190 cc->core_id); 3191 return; 3192 } 3193 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3194 3195 g_assert(drc || !mc->has_hotpluggable_cpus); 3196 3197 if (drc) { 3198 void *fdt; 3199 int fdt_offset; 3200 3201 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3202 3203 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3204 if (local_err) { 3205 g_free(fdt); 3206 error_propagate(errp, local_err); 3207 return; 3208 } 3209 3210 if (hotplugged) { 3211 /* 3212 * Send hotplug notification interrupt to the guest only 3213 * in case of hotplugged CPUs. 3214 */ 3215 spapr_hotplug_req_add_by_index(drc); 3216 } else { 3217 spapr_drc_reset(drc); 3218 } 3219 } 3220 3221 core_slot->cpu = OBJECT(dev); 3222 3223 if (smc->pre_2_10_has_unused_icps) { 3224 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3225 const char *typename = object_class_get_name(scc->cpu_class); 3226 size_t size = object_type_get_instance_size(typename); 3227 int i; 3228 3229 for (i = 0; i < cc->nr_threads; i++) { 3230 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 3231 void *obj = sc->threads + i * size; 3232 3233 cs = CPU(obj); 3234 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3235 } 3236 } 3237 } 3238 3239 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3240 Error **errp) 3241 { 3242 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3243 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3244 Error *local_err = NULL; 3245 CPUCore *cc = CPU_CORE(dev); 3246 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 3247 const char *type = object_get_typename(OBJECT(dev)); 3248 CPUArchId *core_slot; 3249 int index; 3250 3251 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3252 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3253 goto out; 3254 } 3255 3256 if (strcmp(base_core_type, type)) { 3257 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3258 goto out; 3259 } 3260 3261 if (cc->core_id % smp_threads) { 3262 error_setg(&local_err, "invalid core id %d", cc->core_id); 3263 goto out; 3264 } 3265 3266 /* 3267 * In general we should have homogeneous threads-per-core, but old 3268 * (pre hotplug support) machine types allow the last core to have 3269 * reduced threads as a compatibility hack for when we allowed 3270 * total vcpus not a multiple of threads-per-core. 3271 */ 3272 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3273 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3274 cc->nr_threads, smp_threads); 3275 goto out; 3276 } 3277 3278 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3279 if (!core_slot) { 3280 error_setg(&local_err, "core id %d out of range", cc->core_id); 3281 goto out; 3282 } 3283 3284 if (core_slot->cpu) { 3285 error_setg(&local_err, "core %d already populated", cc->core_id); 3286 goto out; 3287 } 3288 3289 numa_cpu_pre_plug(core_slot, dev, &local_err); 3290 3291 out: 3292 g_free(base_core_type); 3293 error_propagate(errp, local_err); 3294 } 3295 3296 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3297 DeviceState *dev, Error **errp) 3298 { 3299 MachineState *ms = MACHINE(hotplug_dev); 3300 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3301 3302 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3303 int node; 3304 3305 if (!smc->dr_lmb_enabled) { 3306 error_setg(errp, "Memory hotplug not supported for this machine"); 3307 return; 3308 } 3309 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3310 if (*errp) { 3311 return; 3312 } 3313 if (node < 0 || node >= MAX_NODES) { 3314 error_setg(errp, "Invaild node %d", node); 3315 return; 3316 } 3317 3318 /* 3319 * Currently PowerPC kernel doesn't allow hot-adding memory to 3320 * memory-less node, but instead will silently add the memory 3321 * to the first node that has some memory. This causes two 3322 * unexpected behaviours for the user. 3323 * 3324 * - Memory gets hotplugged to a different node than what the user 3325 * specified. 3326 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3327 * to memory-less node, a reboot will set things accordingly 3328 * and the previously hotplugged memory now ends in the right node. 3329 * This appears as if some memory moved from one node to another. 3330 * 3331 * So until kernel starts supporting memory hotplug to memory-less 3332 * nodes, just prevent such attempts upfront in QEMU. 3333 */ 3334 if (nb_numa_nodes && !numa_info[node].node_mem) { 3335 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3336 node); 3337 return; 3338 } 3339 3340 spapr_memory_plug(hotplug_dev, dev, node, errp); 3341 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3342 spapr_core_plug(hotplug_dev, dev, errp); 3343 } 3344 } 3345 3346 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3347 DeviceState *dev, Error **errp) 3348 { 3349 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3350 MachineClass *mc = MACHINE_GET_CLASS(sms); 3351 3352 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3353 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3354 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3355 } else { 3356 /* NOTE: this means there is a window after guest reset, prior to 3357 * CAS negotiation, where unplug requests will fail due to the 3358 * capability not being detected yet. This is a bit different than 3359 * the case with PCI unplug, where the events will be queued and 3360 * eventually handled by the guest after boot 3361 */ 3362 error_setg(errp, "Memory hot unplug not supported for this guest"); 3363 } 3364 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3365 if (!mc->has_hotpluggable_cpus) { 3366 error_setg(errp, "CPU hot unplug not supported on this machine"); 3367 return; 3368 } 3369 spapr_core_unplug_request(hotplug_dev, dev, errp); 3370 } 3371 } 3372 3373 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3374 DeviceState *dev, Error **errp) 3375 { 3376 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3377 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3378 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3379 spapr_core_pre_plug(hotplug_dev, dev, errp); 3380 } 3381 } 3382 3383 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3384 DeviceState *dev) 3385 { 3386 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3387 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3388 return HOTPLUG_HANDLER(machine); 3389 } 3390 return NULL; 3391 } 3392 3393 static CpuInstanceProperties 3394 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3395 { 3396 CPUArchId *core_slot; 3397 MachineClass *mc = MACHINE_GET_CLASS(machine); 3398 3399 /* make sure possible_cpu are intialized */ 3400 mc->possible_cpu_arch_ids(machine); 3401 /* get CPU core slot containing thread that matches cpu_index */ 3402 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3403 assert(core_slot); 3404 return core_slot->props; 3405 } 3406 3407 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3408 { 3409 return idx / smp_cores % nb_numa_nodes; 3410 } 3411 3412 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3413 { 3414 int i; 3415 int spapr_max_cores = max_cpus / smp_threads; 3416 MachineClass *mc = MACHINE_GET_CLASS(machine); 3417 3418 if (!mc->has_hotpluggable_cpus) { 3419 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3420 } 3421 if (machine->possible_cpus) { 3422 assert(machine->possible_cpus->len == spapr_max_cores); 3423 return machine->possible_cpus; 3424 } 3425 3426 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3427 sizeof(CPUArchId) * spapr_max_cores); 3428 machine->possible_cpus->len = spapr_max_cores; 3429 for (i = 0; i < machine->possible_cpus->len; i++) { 3430 int core_id = i * smp_threads; 3431 3432 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3433 machine->possible_cpus->cpus[i].arch_id = core_id; 3434 machine->possible_cpus->cpus[i].props.has_core_id = true; 3435 machine->possible_cpus->cpus[i].props.core_id = core_id; 3436 } 3437 return machine->possible_cpus; 3438 } 3439 3440 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3441 uint64_t *buid, hwaddr *pio, 3442 hwaddr *mmio32, hwaddr *mmio64, 3443 unsigned n_dma, uint32_t *liobns, Error **errp) 3444 { 3445 /* 3446 * New-style PHB window placement. 3447 * 3448 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3449 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3450 * windows. 3451 * 3452 * Some guest kernels can't work with MMIO windows above 1<<46 3453 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3454 * 3455 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3456 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3457 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3458 * 1TiB 64-bit MMIO windows for each PHB. 3459 */ 3460 const uint64_t base_buid = 0x800000020000000ULL; 3461 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3462 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3463 int i; 3464 3465 /* Sanity check natural alignments */ 3466 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3467 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3468 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3469 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3470 /* Sanity check bounds */ 3471 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3472 SPAPR_PCI_MEM32_WIN_SIZE); 3473 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3474 SPAPR_PCI_MEM64_WIN_SIZE); 3475 3476 if (index >= SPAPR_MAX_PHBS) { 3477 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3478 SPAPR_MAX_PHBS - 1); 3479 return; 3480 } 3481 3482 *buid = base_buid + index; 3483 for (i = 0; i < n_dma; ++i) { 3484 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3485 } 3486 3487 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3488 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3489 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3490 } 3491 3492 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3493 { 3494 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3495 3496 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3497 } 3498 3499 static void spapr_ics_resend(XICSFabric *dev) 3500 { 3501 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3502 3503 ics_resend(spapr->ics); 3504 } 3505 3506 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3507 { 3508 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3509 3510 return cpu ? ICP(cpu->intc) : NULL; 3511 } 3512 3513 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3514 Monitor *mon) 3515 { 3516 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3517 CPUState *cs; 3518 3519 CPU_FOREACH(cs) { 3520 PowerPCCPU *cpu = POWERPC_CPU(cs); 3521 3522 icp_pic_print_info(ICP(cpu->intc), mon); 3523 } 3524 3525 ics_pic_print_info(spapr->ics, mon); 3526 } 3527 3528 int spapr_vcpu_id(PowerPCCPU *cpu) 3529 { 3530 CPUState *cs = CPU(cpu); 3531 3532 if (kvm_enabled()) { 3533 return kvm_arch_vcpu_id(cs); 3534 } else { 3535 return cs->cpu_index; 3536 } 3537 } 3538 3539 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3540 { 3541 CPUState *cs; 3542 3543 CPU_FOREACH(cs) { 3544 PowerPCCPU *cpu = POWERPC_CPU(cs); 3545 3546 if (spapr_vcpu_id(cpu) == vcpu_id) { 3547 return cpu; 3548 } 3549 } 3550 3551 return NULL; 3552 } 3553 3554 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3555 { 3556 MachineClass *mc = MACHINE_CLASS(oc); 3557 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3558 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3559 NMIClass *nc = NMI_CLASS(oc); 3560 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3561 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3562 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3563 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3564 3565 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3566 3567 /* 3568 * We set up the default / latest behaviour here. The class_init 3569 * functions for the specific versioned machine types can override 3570 * these details for backwards compatibility 3571 */ 3572 mc->init = ppc_spapr_init; 3573 mc->reset = ppc_spapr_reset; 3574 mc->block_default_type = IF_SCSI; 3575 mc->max_cpus = 1024; 3576 mc->no_parallel = 1; 3577 mc->default_boot_order = ""; 3578 mc->default_ram_size = 512 * M_BYTE; 3579 mc->kvm_type = spapr_kvm_type; 3580 mc->has_dynamic_sysbus = true; 3581 mc->pci_allow_0_address = true; 3582 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3583 hc->pre_plug = spapr_machine_device_pre_plug; 3584 hc->plug = spapr_machine_device_plug; 3585 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3586 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3587 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3588 hc->unplug_request = spapr_machine_device_unplug_request; 3589 3590 smc->dr_lmb_enabled = true; 3591 smc->tcg_default_cpu = "POWER8"; 3592 mc->has_hotpluggable_cpus = true; 3593 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3594 fwc->get_dev_path = spapr_get_fw_dev_path; 3595 nc->nmi_monitor_handler = spapr_nmi; 3596 smc->phb_placement = spapr_phb_placement; 3597 vhc->hypercall = emulate_spapr_hypercall; 3598 vhc->hpt_mask = spapr_hpt_mask; 3599 vhc->map_hptes = spapr_map_hptes; 3600 vhc->unmap_hptes = spapr_unmap_hptes; 3601 vhc->store_hpte = spapr_store_hpte; 3602 vhc->get_patbe = spapr_get_patbe; 3603 xic->ics_get = spapr_ics_get; 3604 xic->ics_resend = spapr_ics_resend; 3605 xic->icp_get = spapr_icp_get; 3606 ispc->print_info = spapr_pic_print_info; 3607 /* Force NUMA node memory size to be a multiple of 3608 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3609 * in which LMBs are represented and hot-added 3610 */ 3611 mc->numa_mem_align_shift = 28; 3612 } 3613 3614 static const TypeInfo spapr_machine_info = { 3615 .name = TYPE_SPAPR_MACHINE, 3616 .parent = TYPE_MACHINE, 3617 .abstract = true, 3618 .instance_size = sizeof(sPAPRMachineState), 3619 .instance_init = spapr_machine_initfn, 3620 .instance_finalize = spapr_machine_finalizefn, 3621 .class_size = sizeof(sPAPRMachineClass), 3622 .class_init = spapr_machine_class_init, 3623 .interfaces = (InterfaceInfo[]) { 3624 { TYPE_FW_PATH_PROVIDER }, 3625 { TYPE_NMI }, 3626 { TYPE_HOTPLUG_HANDLER }, 3627 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3628 { TYPE_XICS_FABRIC }, 3629 { TYPE_INTERRUPT_STATS_PROVIDER }, 3630 { } 3631 }, 3632 }; 3633 3634 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3635 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3636 void *data) \ 3637 { \ 3638 MachineClass *mc = MACHINE_CLASS(oc); \ 3639 spapr_machine_##suffix##_class_options(mc); \ 3640 if (latest) { \ 3641 mc->alias = "pseries"; \ 3642 mc->is_default = 1; \ 3643 } \ 3644 } \ 3645 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3646 { \ 3647 MachineState *machine = MACHINE(obj); \ 3648 spapr_machine_##suffix##_instance_options(machine); \ 3649 } \ 3650 static const TypeInfo spapr_machine_##suffix##_info = { \ 3651 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3652 .parent = TYPE_SPAPR_MACHINE, \ 3653 .class_init = spapr_machine_##suffix##_class_init, \ 3654 .instance_init = spapr_machine_##suffix##_instance_init, \ 3655 }; \ 3656 static void spapr_machine_register_##suffix(void) \ 3657 { \ 3658 type_register(&spapr_machine_##suffix##_info); \ 3659 } \ 3660 type_init(spapr_machine_register_##suffix) 3661 3662 /* 3663 * pseries-2.11 3664 */ 3665 static void spapr_machine_2_11_instance_options(MachineState *machine) 3666 { 3667 } 3668 3669 static void spapr_machine_2_11_class_options(MachineClass *mc) 3670 { 3671 /* Defaults for the latest behaviour inherited from the base class */ 3672 } 3673 3674 DEFINE_SPAPR_MACHINE(2_11, "2.11", true); 3675 3676 /* 3677 * pseries-2.10 3678 */ 3679 #define SPAPR_COMPAT_2_10 \ 3680 HW_COMPAT_2_10 \ 3681 3682 static void spapr_machine_2_10_instance_options(MachineState *machine) 3683 { 3684 } 3685 3686 static void spapr_machine_2_10_class_options(MachineClass *mc) 3687 { 3688 spapr_machine_2_11_class_options(mc); 3689 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 3690 } 3691 3692 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 3693 3694 /* 3695 * pseries-2.9 3696 */ 3697 #define SPAPR_COMPAT_2_9 \ 3698 HW_COMPAT_2_9 \ 3699 { \ 3700 .driver = TYPE_POWERPC_CPU, \ 3701 .property = "pre-2.10-migration", \ 3702 .value = "on", \ 3703 }, \ 3704 3705 static void spapr_machine_2_9_instance_options(MachineState *machine) 3706 { 3707 spapr_machine_2_10_instance_options(machine); 3708 } 3709 3710 static void spapr_machine_2_9_class_options(MachineClass *mc) 3711 { 3712 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3713 3714 spapr_machine_2_10_class_options(mc); 3715 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3716 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3717 smc->pre_2_10_has_unused_icps = true; 3718 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 3719 } 3720 3721 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3722 3723 /* 3724 * pseries-2.8 3725 */ 3726 #define SPAPR_COMPAT_2_8 \ 3727 HW_COMPAT_2_8 \ 3728 { \ 3729 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3730 .property = "pcie-extended-configuration-space", \ 3731 .value = "off", \ 3732 }, 3733 3734 static void spapr_machine_2_8_instance_options(MachineState *machine) 3735 { 3736 spapr_machine_2_9_instance_options(machine); 3737 } 3738 3739 static void spapr_machine_2_8_class_options(MachineClass *mc) 3740 { 3741 spapr_machine_2_9_class_options(mc); 3742 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3743 mc->numa_mem_align_shift = 23; 3744 } 3745 3746 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3747 3748 /* 3749 * pseries-2.7 3750 */ 3751 #define SPAPR_COMPAT_2_7 \ 3752 HW_COMPAT_2_7 \ 3753 { \ 3754 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3755 .property = "mem_win_size", \ 3756 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3757 }, \ 3758 { \ 3759 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3760 .property = "mem64_win_size", \ 3761 .value = "0", \ 3762 }, \ 3763 { \ 3764 .driver = TYPE_POWERPC_CPU, \ 3765 .property = "pre-2.8-migration", \ 3766 .value = "on", \ 3767 }, \ 3768 { \ 3769 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3770 .property = "pre-2.8-migration", \ 3771 .value = "on", \ 3772 }, 3773 3774 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3775 uint64_t *buid, hwaddr *pio, 3776 hwaddr *mmio32, hwaddr *mmio64, 3777 unsigned n_dma, uint32_t *liobns, Error **errp) 3778 { 3779 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3780 const uint64_t base_buid = 0x800000020000000ULL; 3781 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3782 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3783 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3784 const uint32_t max_index = 255; 3785 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3786 3787 uint64_t ram_top = MACHINE(spapr)->ram_size; 3788 hwaddr phb0_base, phb_base; 3789 int i; 3790 3791 /* Do we have hotpluggable memory? */ 3792 if (MACHINE(spapr)->maxram_size > ram_top) { 3793 /* Can't just use maxram_size, because there may be an 3794 * alignment gap between normal and hotpluggable memory 3795 * regions */ 3796 ram_top = spapr->hotplug_memory.base + 3797 memory_region_size(&spapr->hotplug_memory.mr); 3798 } 3799 3800 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3801 3802 if (index > max_index) { 3803 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3804 max_index); 3805 return; 3806 } 3807 3808 *buid = base_buid + index; 3809 for (i = 0; i < n_dma; ++i) { 3810 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3811 } 3812 3813 phb_base = phb0_base + index * phb_spacing; 3814 *pio = phb_base + pio_offset; 3815 *mmio32 = phb_base + mmio_offset; 3816 /* 3817 * We don't set the 64-bit MMIO window, relying on the PHB's 3818 * fallback behaviour of automatically splitting a large "32-bit" 3819 * window into contiguous 32-bit and 64-bit windows 3820 */ 3821 } 3822 3823 static void spapr_machine_2_7_instance_options(MachineState *machine) 3824 { 3825 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3826 3827 spapr_machine_2_8_instance_options(machine); 3828 spapr->use_hotplug_event_source = false; 3829 } 3830 3831 static void spapr_machine_2_7_class_options(MachineClass *mc) 3832 { 3833 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3834 3835 spapr_machine_2_8_class_options(mc); 3836 smc->tcg_default_cpu = "POWER7"; 3837 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3838 smc->phb_placement = phb_placement_2_7; 3839 } 3840 3841 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3842 3843 /* 3844 * pseries-2.6 3845 */ 3846 #define SPAPR_COMPAT_2_6 \ 3847 HW_COMPAT_2_6 \ 3848 { \ 3849 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3850 .property = "ddw",\ 3851 .value = stringify(off),\ 3852 }, 3853 3854 static void spapr_machine_2_6_instance_options(MachineState *machine) 3855 { 3856 spapr_machine_2_7_instance_options(machine); 3857 } 3858 3859 static void spapr_machine_2_6_class_options(MachineClass *mc) 3860 { 3861 spapr_machine_2_7_class_options(mc); 3862 mc->has_hotpluggable_cpus = false; 3863 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3864 } 3865 3866 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3867 3868 /* 3869 * pseries-2.5 3870 */ 3871 #define SPAPR_COMPAT_2_5 \ 3872 HW_COMPAT_2_5 \ 3873 { \ 3874 .driver = "spapr-vlan", \ 3875 .property = "use-rx-buffer-pools", \ 3876 .value = "off", \ 3877 }, 3878 3879 static void spapr_machine_2_5_instance_options(MachineState *machine) 3880 { 3881 spapr_machine_2_6_instance_options(machine); 3882 } 3883 3884 static void spapr_machine_2_5_class_options(MachineClass *mc) 3885 { 3886 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3887 3888 spapr_machine_2_6_class_options(mc); 3889 smc->use_ohci_by_default = true; 3890 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3891 } 3892 3893 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3894 3895 /* 3896 * pseries-2.4 3897 */ 3898 #define SPAPR_COMPAT_2_4 \ 3899 HW_COMPAT_2_4 3900 3901 static void spapr_machine_2_4_instance_options(MachineState *machine) 3902 { 3903 spapr_machine_2_5_instance_options(machine); 3904 } 3905 3906 static void spapr_machine_2_4_class_options(MachineClass *mc) 3907 { 3908 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3909 3910 spapr_machine_2_5_class_options(mc); 3911 smc->dr_lmb_enabled = false; 3912 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3913 } 3914 3915 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3916 3917 /* 3918 * pseries-2.3 3919 */ 3920 #define SPAPR_COMPAT_2_3 \ 3921 HW_COMPAT_2_3 \ 3922 {\ 3923 .driver = "spapr-pci-host-bridge",\ 3924 .property = "dynamic-reconfiguration",\ 3925 .value = "off",\ 3926 }, 3927 3928 static void spapr_machine_2_3_instance_options(MachineState *machine) 3929 { 3930 spapr_machine_2_4_instance_options(machine); 3931 } 3932 3933 static void spapr_machine_2_3_class_options(MachineClass *mc) 3934 { 3935 spapr_machine_2_4_class_options(mc); 3936 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3937 } 3938 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3939 3940 /* 3941 * pseries-2.2 3942 */ 3943 3944 #define SPAPR_COMPAT_2_2 \ 3945 HW_COMPAT_2_2 \ 3946 {\ 3947 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3948 .property = "mem_win_size",\ 3949 .value = "0x20000000",\ 3950 }, 3951 3952 static void spapr_machine_2_2_instance_options(MachineState *machine) 3953 { 3954 spapr_machine_2_3_instance_options(machine); 3955 machine->suppress_vmdesc = true; 3956 } 3957 3958 static void spapr_machine_2_2_class_options(MachineClass *mc) 3959 { 3960 spapr_machine_2_3_class_options(mc); 3961 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3962 } 3963 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3964 3965 /* 3966 * pseries-2.1 3967 */ 3968 #define SPAPR_COMPAT_2_1 \ 3969 HW_COMPAT_2_1 3970 3971 static void spapr_machine_2_1_instance_options(MachineState *machine) 3972 { 3973 spapr_machine_2_2_instance_options(machine); 3974 } 3975 3976 static void spapr_machine_2_1_class_options(MachineClass *mc) 3977 { 3978 spapr_machine_2_2_class_options(mc); 3979 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3980 } 3981 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3982 3983 static void spapr_machine_register_types(void) 3984 { 3985 type_register_static(&spapr_machine_info); 3986 } 3987 3988 type_init(spapr_machine_register_types) 3989