1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/numa.h" 32 #include "hw/hw.h" 33 #include "qemu/log.h" 34 #include "hw/fw-path-provider.h" 35 #include "elf.h" 36 #include "net/net.h" 37 #include "sysemu/device_tree.h" 38 #include "sysemu/block-backend.h" 39 #include "sysemu/cpus.h" 40 #include "sysemu/hw_accel.h" 41 #include "kvm_ppc.h" 42 #include "migration/misc.h" 43 #include "migration/global_state.h" 44 #include "migration/register.h" 45 #include "mmu-hash64.h" 46 #include "mmu-book3s-v3.h" 47 #include "qom/cpu.h" 48 49 #include "hw/boards.h" 50 #include "hw/ppc/ppc.h" 51 #include "hw/loader.h" 52 53 #include "hw/ppc/fdt.h" 54 #include "hw/ppc/spapr.h" 55 #include "hw/ppc/spapr_vio.h" 56 #include "hw/pci-host/spapr.h" 57 #include "hw/ppc/xics.h" 58 #include "hw/pci/msi.h" 59 60 #include "hw/pci/pci.h" 61 #include "hw/scsi/scsi.h" 62 #include "hw/virtio/virtio-scsi.h" 63 #include "hw/virtio/vhost-scsi-common.h" 64 65 #include "exec/address-spaces.h" 66 #include "hw/usb.h" 67 #include "qemu/config-file.h" 68 #include "qemu/error-report.h" 69 #include "trace.h" 70 #include "hw/nmi.h" 71 #include "hw/intc/intc.h" 72 73 #include "hw/compat.h" 74 #include "qemu/cutils.h" 75 #include "hw/ppc/spapr_cpu_core.h" 76 #include "qmp-commands.h" 77 78 #include <libfdt.h> 79 80 /* SLOF memory layout: 81 * 82 * SLOF raw image loaded at 0, copies its romfs right below the flat 83 * device-tree, then position SLOF itself 31M below that 84 * 85 * So we set FW_OVERHEAD to 40MB which should account for all of that 86 * and more 87 * 88 * We load our kernel at 4M, leaving space for SLOF initial image 89 */ 90 #define FDT_MAX_SIZE 0x100000 91 #define RTAS_MAX_SIZE 0x10000 92 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 93 #define FW_MAX_SIZE 0x400000 94 #define FW_FILE_NAME "slof.bin" 95 #define FW_OVERHEAD 0x2800000 96 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 97 98 #define MIN_RMA_SLOF 128UL 99 100 #define PHANDLE_XICP 0x00001111 101 102 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 103 const char *type_ics, 104 int nr_irqs, Error **errp) 105 { 106 Error *local_err = NULL; 107 Object *obj; 108 109 obj = object_new(type_ics); 110 object_property_add_child(OBJECT(spapr), "ics", obj, &error_abort); 111 object_property_add_const_link(obj, ICS_PROP_XICS, OBJECT(spapr), 112 &error_abort); 113 object_property_set_int(obj, nr_irqs, "nr-irqs", &local_err); 114 if (local_err) { 115 goto error; 116 } 117 object_property_set_bool(obj, true, "realized", &local_err); 118 if (local_err) { 119 goto error; 120 } 121 122 return ICS_SIMPLE(obj); 123 124 error: 125 error_propagate(errp, local_err); 126 return NULL; 127 } 128 129 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 130 { 131 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 132 * and newer QEMUs don't even have them. In both cases, we don't want 133 * to send anything on the wire. 134 */ 135 return false; 136 } 137 138 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 139 .name = "icp/server", 140 .version_id = 1, 141 .minimum_version_id = 1, 142 .needed = pre_2_10_vmstate_dummy_icp_needed, 143 .fields = (VMStateField[]) { 144 VMSTATE_UNUSED(4), /* uint32_t xirr */ 145 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 146 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 147 VMSTATE_END_OF_LIST() 148 }, 149 }; 150 151 static void pre_2_10_vmstate_register_dummy_icp(int i) 152 { 153 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 154 (void *)(uintptr_t) i); 155 } 156 157 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 158 { 159 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 160 (void *)(uintptr_t) i); 161 } 162 163 static inline int xics_max_server_number(void) 164 { 165 return DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(), smp_threads); 166 } 167 168 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 169 { 170 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 171 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 172 173 if (kvm_enabled()) { 174 if (machine_kernel_irqchip_allowed(machine) && 175 !xics_kvm_init(spapr, errp)) { 176 spapr->icp_type = TYPE_KVM_ICP; 177 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, errp); 178 } 179 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 180 error_prepend(errp, "kernel_irqchip requested but unavailable: "); 181 return; 182 } 183 } 184 185 if (!spapr->ics) { 186 xics_spapr_init(spapr); 187 spapr->icp_type = TYPE_ICP; 188 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 189 if (!spapr->ics) { 190 return; 191 } 192 } 193 194 if (smc->pre_2_10_has_unused_icps) { 195 int i; 196 197 for (i = 0; i < xics_max_server_number(); i++) { 198 /* Dummy entries get deregistered when real ICPState objects 199 * are registered during CPU core hotplug. 200 */ 201 pre_2_10_vmstate_register_dummy_icp(i); 202 } 203 } 204 } 205 206 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 207 int smt_threads) 208 { 209 int i, ret = 0; 210 uint32_t servers_prop[smt_threads]; 211 uint32_t gservers_prop[smt_threads * 2]; 212 int index = spapr_vcpu_id(cpu); 213 214 if (cpu->compat_pvr) { 215 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 216 if (ret < 0) { 217 return ret; 218 } 219 } 220 221 /* Build interrupt servers and gservers properties */ 222 for (i = 0; i < smt_threads; i++) { 223 servers_prop[i] = cpu_to_be32(index + i); 224 /* Hack, direct the group queues back to cpu 0 */ 225 gservers_prop[i*2] = cpu_to_be32(index + i); 226 gservers_prop[i*2 + 1] = 0; 227 } 228 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 229 servers_prop, sizeof(servers_prop)); 230 if (ret < 0) { 231 return ret; 232 } 233 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 234 gservers_prop, sizeof(gservers_prop)); 235 236 return ret; 237 } 238 239 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, PowerPCCPU *cpu) 240 { 241 int index = spapr_vcpu_id(cpu); 242 uint32_t associativity[] = {cpu_to_be32(0x5), 243 cpu_to_be32(0x0), 244 cpu_to_be32(0x0), 245 cpu_to_be32(0x0), 246 cpu_to_be32(cpu->node_id), 247 cpu_to_be32(index)}; 248 249 /* Advertise NUMA via ibm,associativity */ 250 return fdt_setprop(fdt, offset, "ibm,associativity", associativity, 251 sizeof(associativity)); 252 } 253 254 /* Populate the "ibm,pa-features" property */ 255 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 256 bool legacy_guest) 257 { 258 uint8_t pa_features_206[] = { 6, 0, 259 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 260 uint8_t pa_features_207[] = { 24, 0, 261 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 262 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 263 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 264 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 265 uint8_t pa_features_300[] = { 66, 0, 266 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 267 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 268 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 269 /* 6: DS207 */ 270 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 271 /* 16: Vector */ 272 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 273 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 274 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 275 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 276 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 277 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 278 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 279 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 280 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 281 /* 42: PM, 44: PC RA, 46: SC vec'd */ 282 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 283 /* 48: SIMD, 50: QP BFP, 52: String */ 284 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 285 /* 54: DecFP, 56: DecI, 58: SHA */ 286 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 287 /* 60: NM atomic, 62: RNG */ 288 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 289 }; 290 uint8_t *pa_features; 291 size_t pa_size; 292 293 switch (POWERPC_MMU_VER(env->mmu_model)) { 294 case POWERPC_MMU_VER_2_06: 295 pa_features = pa_features_206; 296 pa_size = sizeof(pa_features_206); 297 break; 298 case POWERPC_MMU_VER_2_07: 299 pa_features = pa_features_207; 300 pa_size = sizeof(pa_features_207); 301 break; 302 case POWERPC_MMU_VER_3_00: 303 pa_features = pa_features_300; 304 pa_size = sizeof(pa_features_300); 305 break; 306 default: 307 return; 308 } 309 310 if (env->ci_large_pages) { 311 /* 312 * Note: we keep CI large pages off by default because a 64K capable 313 * guest provisioned with large pages might otherwise try to map a qemu 314 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 315 * even if that qemu runs on a 4k host. 316 * We dd this bit back here if we are confident this is not an issue 317 */ 318 pa_features[3] |= 0x20; 319 } 320 if (kvmppc_has_cap_htm() && pa_size > 24) { 321 pa_features[24] |= 0x80; /* Transactional memory support */ 322 } 323 if (legacy_guest && pa_size > 40) { 324 /* Workaround for broken kernels that attempt (guest) radix 325 * mode when they can't handle it, if they see the radix bit set 326 * in pa-features. So hide it from them. */ 327 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 328 } 329 330 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 331 } 332 333 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 334 { 335 int ret = 0, offset, cpus_offset; 336 CPUState *cs; 337 char cpu_model[32]; 338 int smt = kvmppc_smt_threads(); 339 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 340 341 CPU_FOREACH(cs) { 342 PowerPCCPU *cpu = POWERPC_CPU(cs); 343 CPUPPCState *env = &cpu->env; 344 DeviceClass *dc = DEVICE_GET_CLASS(cs); 345 int index = spapr_vcpu_id(cpu); 346 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 347 348 if ((index % smt) != 0) { 349 continue; 350 } 351 352 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 353 354 cpus_offset = fdt_path_offset(fdt, "/cpus"); 355 if (cpus_offset < 0) { 356 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 357 "cpus"); 358 if (cpus_offset < 0) { 359 return cpus_offset; 360 } 361 } 362 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 363 if (offset < 0) { 364 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 365 if (offset < 0) { 366 return offset; 367 } 368 } 369 370 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 371 pft_size_prop, sizeof(pft_size_prop)); 372 if (ret < 0) { 373 return ret; 374 } 375 376 if (nb_numa_nodes > 1) { 377 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cpu); 378 if (ret < 0) { 379 return ret; 380 } 381 } 382 383 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 384 if (ret < 0) { 385 return ret; 386 } 387 388 spapr_populate_pa_features(env, fdt, offset, 389 spapr->cas_legacy_guest_workaround); 390 } 391 return ret; 392 } 393 394 static hwaddr spapr_node0_size(MachineState *machine) 395 { 396 if (nb_numa_nodes) { 397 int i; 398 for (i = 0; i < nb_numa_nodes; ++i) { 399 if (numa_info[i].node_mem) { 400 return MIN(pow2floor(numa_info[i].node_mem), 401 machine->ram_size); 402 } 403 } 404 } 405 return machine->ram_size; 406 } 407 408 static void add_str(GString *s, const gchar *s1) 409 { 410 g_string_append_len(s, s1, strlen(s1) + 1); 411 } 412 413 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 414 hwaddr size) 415 { 416 uint32_t associativity[] = { 417 cpu_to_be32(0x4), /* length */ 418 cpu_to_be32(0x0), cpu_to_be32(0x0), 419 cpu_to_be32(0x0), cpu_to_be32(nodeid) 420 }; 421 char mem_name[32]; 422 uint64_t mem_reg_property[2]; 423 int off; 424 425 mem_reg_property[0] = cpu_to_be64(start); 426 mem_reg_property[1] = cpu_to_be64(size); 427 428 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 429 off = fdt_add_subnode(fdt, 0, mem_name); 430 _FDT(off); 431 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 432 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 433 sizeof(mem_reg_property)))); 434 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 435 sizeof(associativity)))); 436 return off; 437 } 438 439 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 440 { 441 MachineState *machine = MACHINE(spapr); 442 hwaddr mem_start, node_size; 443 int i, nb_nodes = nb_numa_nodes; 444 NodeInfo *nodes = numa_info; 445 NodeInfo ramnode; 446 447 /* No NUMA nodes, assume there is just one node with whole RAM */ 448 if (!nb_numa_nodes) { 449 nb_nodes = 1; 450 ramnode.node_mem = machine->ram_size; 451 nodes = &ramnode; 452 } 453 454 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 455 if (!nodes[i].node_mem) { 456 continue; 457 } 458 if (mem_start >= machine->ram_size) { 459 node_size = 0; 460 } else { 461 node_size = nodes[i].node_mem; 462 if (node_size > machine->ram_size - mem_start) { 463 node_size = machine->ram_size - mem_start; 464 } 465 } 466 if (!mem_start) { 467 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 468 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 469 mem_start += spapr->rma_size; 470 node_size -= spapr->rma_size; 471 } 472 for ( ; node_size; ) { 473 hwaddr sizetmp = pow2floor(node_size); 474 475 /* mem_start != 0 here */ 476 if (ctzl(mem_start) < ctzl(sizetmp)) { 477 sizetmp = 1ULL << ctzl(mem_start); 478 } 479 480 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 481 node_size -= sizetmp; 482 mem_start += sizetmp; 483 } 484 } 485 486 return 0; 487 } 488 489 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 490 sPAPRMachineState *spapr) 491 { 492 PowerPCCPU *cpu = POWERPC_CPU(cs); 493 CPUPPCState *env = &cpu->env; 494 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 495 int index = spapr_vcpu_id(cpu); 496 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 497 0xffffffff, 0xffffffff}; 498 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 499 : SPAPR_TIMEBASE_FREQ; 500 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 501 uint32_t page_sizes_prop[64]; 502 size_t page_sizes_prop_size; 503 uint32_t vcpus_per_socket = smp_threads * smp_cores; 504 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 505 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 506 sPAPRDRConnector *drc; 507 int drc_index; 508 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 509 int i; 510 511 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 512 if (drc) { 513 drc_index = spapr_drc_index(drc); 514 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 515 } 516 517 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 518 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 519 520 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 521 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 522 env->dcache_line_size))); 523 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 524 env->dcache_line_size))); 525 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 526 env->icache_line_size))); 527 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 528 env->icache_line_size))); 529 530 if (pcc->l1_dcache_size) { 531 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 532 pcc->l1_dcache_size))); 533 } else { 534 warn_report("Unknown L1 dcache size for cpu"); 535 } 536 if (pcc->l1_icache_size) { 537 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 538 pcc->l1_icache_size))); 539 } else { 540 warn_report("Unknown L1 icache size for cpu"); 541 } 542 543 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 544 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 545 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 546 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 547 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 548 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 549 550 if (env->spr_cb[SPR_PURR].oea_read) { 551 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 552 } 553 554 if (env->mmu_model & POWERPC_MMU_1TSEG) { 555 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 556 segs, sizeof(segs)))); 557 } 558 559 /* Advertise VMX/VSX (vector extensions) if available 560 * 0 / no property == no vector extensions 561 * 1 == VMX / Altivec available 562 * 2 == VSX available */ 563 if (env->insns_flags & PPC_ALTIVEC) { 564 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 565 566 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 567 } 568 569 /* Advertise DFP (Decimal Floating Point) if available 570 * 0 / no property == no DFP 571 * 1 == DFP available */ 572 if (env->insns_flags2 & PPC2_DFP) { 573 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 574 } 575 576 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 577 sizeof(page_sizes_prop)); 578 if (page_sizes_prop_size) { 579 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 580 page_sizes_prop, page_sizes_prop_size))); 581 } 582 583 spapr_populate_pa_features(env, fdt, offset, false); 584 585 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 586 cs->cpu_index / vcpus_per_socket))); 587 588 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 589 pft_size_prop, sizeof(pft_size_prop)))); 590 591 if (nb_numa_nodes > 1) { 592 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); 593 } 594 595 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 596 597 if (pcc->radix_page_info) { 598 for (i = 0; i < pcc->radix_page_info->count; i++) { 599 radix_AP_encodings[i] = 600 cpu_to_be32(pcc->radix_page_info->entries[i]); 601 } 602 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 603 radix_AP_encodings, 604 pcc->radix_page_info->count * 605 sizeof(radix_AP_encodings[0])))); 606 } 607 } 608 609 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 610 { 611 CPUState *cs; 612 int cpus_offset; 613 char *nodename; 614 int smt = kvmppc_smt_threads(); 615 616 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 617 _FDT(cpus_offset); 618 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 619 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 620 621 /* 622 * We walk the CPUs in reverse order to ensure that CPU DT nodes 623 * created by fdt_add_subnode() end up in the right order in FDT 624 * for the guest kernel the enumerate the CPUs correctly. 625 */ 626 CPU_FOREACH_REVERSE(cs) { 627 PowerPCCPU *cpu = POWERPC_CPU(cs); 628 int index = spapr_vcpu_id(cpu); 629 DeviceClass *dc = DEVICE_GET_CLASS(cs); 630 int offset; 631 632 if ((index % smt) != 0) { 633 continue; 634 } 635 636 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 637 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 638 g_free(nodename); 639 _FDT(offset); 640 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 641 } 642 643 } 644 645 /* 646 * Adds ibm,dynamic-reconfiguration-memory node. 647 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 648 * of this device tree node. 649 */ 650 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 651 { 652 MachineState *machine = MACHINE(spapr); 653 int ret, i, offset; 654 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 655 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 656 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 657 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 658 memory_region_size(&spapr->hotplug_memory.mr)) / 659 lmb_size; 660 uint32_t *int_buf, *cur_index, buf_len; 661 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 662 663 /* 664 * Don't create the node if there is no hotpluggable memory 665 */ 666 if (machine->ram_size == machine->maxram_size) { 667 return 0; 668 } 669 670 /* 671 * Allocate enough buffer size to fit in ibm,dynamic-memory 672 * or ibm,associativity-lookup-arrays 673 */ 674 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 675 * sizeof(uint32_t); 676 cur_index = int_buf = g_malloc0(buf_len); 677 678 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 679 680 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 681 sizeof(prop_lmb_size)); 682 if (ret < 0) { 683 goto out; 684 } 685 686 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 687 if (ret < 0) { 688 goto out; 689 } 690 691 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 692 if (ret < 0) { 693 goto out; 694 } 695 696 /* ibm,dynamic-memory */ 697 int_buf[0] = cpu_to_be32(nr_lmbs); 698 cur_index++; 699 for (i = 0; i < nr_lmbs; i++) { 700 uint64_t addr = i * lmb_size; 701 uint32_t *dynamic_memory = cur_index; 702 703 if (i >= hotplug_lmb_start) { 704 sPAPRDRConnector *drc; 705 706 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 707 g_assert(drc); 708 709 dynamic_memory[0] = cpu_to_be32(addr >> 32); 710 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 711 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 712 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 713 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 714 if (memory_region_present(get_system_memory(), addr)) { 715 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 716 } else { 717 dynamic_memory[5] = cpu_to_be32(0); 718 } 719 } else { 720 /* 721 * LMB information for RMA, boot time RAM and gap b/n RAM and 722 * hotplug memory region -- all these are marked as reserved 723 * and as having no valid DRC. 724 */ 725 dynamic_memory[0] = cpu_to_be32(addr >> 32); 726 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 727 dynamic_memory[2] = cpu_to_be32(0); 728 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 729 dynamic_memory[4] = cpu_to_be32(-1); 730 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 731 SPAPR_LMB_FLAGS_DRC_INVALID); 732 } 733 734 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 735 } 736 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 737 if (ret < 0) { 738 goto out; 739 } 740 741 /* ibm,associativity-lookup-arrays */ 742 cur_index = int_buf; 743 int_buf[0] = cpu_to_be32(nr_nodes); 744 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 745 cur_index += 2; 746 for (i = 0; i < nr_nodes; i++) { 747 uint32_t associativity[] = { 748 cpu_to_be32(0x0), 749 cpu_to_be32(0x0), 750 cpu_to_be32(0x0), 751 cpu_to_be32(i) 752 }; 753 memcpy(cur_index, associativity, sizeof(associativity)); 754 cur_index += 4; 755 } 756 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 757 (cur_index - int_buf) * sizeof(uint32_t)); 758 out: 759 g_free(int_buf); 760 return ret; 761 } 762 763 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 764 sPAPROptionVector *ov5_updates) 765 { 766 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 767 int ret = 0, offset; 768 769 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 770 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 771 g_assert(smc->dr_lmb_enabled); 772 ret = spapr_populate_drconf_memory(spapr, fdt); 773 if (ret) { 774 goto out; 775 } 776 } 777 778 offset = fdt_path_offset(fdt, "/chosen"); 779 if (offset < 0) { 780 offset = fdt_add_subnode(fdt, 0, "chosen"); 781 if (offset < 0) { 782 return offset; 783 } 784 } 785 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 786 "ibm,architecture-vec-5"); 787 788 out: 789 return ret; 790 } 791 792 static bool spapr_hotplugged_dev_before_cas(void) 793 { 794 Object *drc_container, *obj; 795 ObjectProperty *prop; 796 ObjectPropertyIterator iter; 797 798 drc_container = container_get(object_get_root(), "/dr-connector"); 799 object_property_iter_init(&iter, drc_container); 800 while ((prop = object_property_iter_next(&iter))) { 801 if (!strstart(prop->type, "link<", NULL)) { 802 continue; 803 } 804 obj = object_property_get_link(drc_container, prop->name, NULL); 805 if (spapr_drc_needed(obj)) { 806 return true; 807 } 808 } 809 return false; 810 } 811 812 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 813 target_ulong addr, target_ulong size, 814 sPAPROptionVector *ov5_updates) 815 { 816 void *fdt, *fdt_skel; 817 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 818 819 if (spapr_hotplugged_dev_before_cas()) { 820 return 1; 821 } 822 823 size -= sizeof(hdr); 824 825 /* Create skeleton */ 826 fdt_skel = g_malloc0(size); 827 _FDT((fdt_create(fdt_skel, size))); 828 _FDT((fdt_begin_node(fdt_skel, ""))); 829 _FDT((fdt_end_node(fdt_skel))); 830 _FDT((fdt_finish(fdt_skel))); 831 fdt = g_malloc0(size); 832 _FDT((fdt_open_into(fdt_skel, fdt, size))); 833 g_free(fdt_skel); 834 835 /* Fixup cpu nodes */ 836 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 837 838 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 839 return -1; 840 } 841 842 /* Pack resulting tree */ 843 _FDT((fdt_pack(fdt))); 844 845 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 846 trace_spapr_cas_failed(size); 847 return -1; 848 } 849 850 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 851 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 852 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 853 g_free(fdt); 854 855 return 0; 856 } 857 858 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 859 { 860 int rtas; 861 GString *hypertas = g_string_sized_new(256); 862 GString *qemu_hypertas = g_string_sized_new(256); 863 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 864 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 865 memory_region_size(&spapr->hotplug_memory.mr); 866 uint32_t lrdr_capacity[] = { 867 cpu_to_be32(max_hotplug_addr >> 32), 868 cpu_to_be32(max_hotplug_addr & 0xffffffff), 869 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 870 cpu_to_be32(max_cpus / smp_threads), 871 }; 872 873 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 874 875 /* hypertas */ 876 add_str(hypertas, "hcall-pft"); 877 add_str(hypertas, "hcall-term"); 878 add_str(hypertas, "hcall-dabr"); 879 add_str(hypertas, "hcall-interrupt"); 880 add_str(hypertas, "hcall-tce"); 881 add_str(hypertas, "hcall-vio"); 882 add_str(hypertas, "hcall-splpar"); 883 add_str(hypertas, "hcall-bulk"); 884 add_str(hypertas, "hcall-set-mode"); 885 add_str(hypertas, "hcall-sprg0"); 886 add_str(hypertas, "hcall-copy"); 887 add_str(hypertas, "hcall-debug"); 888 add_str(qemu_hypertas, "hcall-memop1"); 889 890 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 891 add_str(hypertas, "hcall-multi-tce"); 892 } 893 894 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 895 add_str(hypertas, "hcall-hpt-resize"); 896 } 897 898 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 899 hypertas->str, hypertas->len)); 900 g_string_free(hypertas, TRUE); 901 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 902 qemu_hypertas->str, qemu_hypertas->len)); 903 g_string_free(qemu_hypertas, TRUE); 904 905 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 906 refpoints, sizeof(refpoints))); 907 908 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 909 RTAS_ERROR_LOG_MAX)); 910 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 911 RTAS_EVENT_SCAN_RATE)); 912 913 if (msi_nonbroken) { 914 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 915 } 916 917 /* 918 * According to PAPR, rtas ibm,os-term does not guarantee a return 919 * back to the guest cpu. 920 * 921 * While an additional ibm,extended-os-term property indicates 922 * that rtas call return will always occur. Set this property. 923 */ 924 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 925 926 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 927 lrdr_capacity, sizeof(lrdr_capacity))); 928 929 spapr_dt_rtas_tokens(fdt, rtas); 930 } 931 932 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 933 * that the guest may request and thus the valid values for bytes 24..26 of 934 * option vector 5: */ 935 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 936 { 937 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 938 939 char val[2 * 4] = { 940 23, 0x00, /* Xive mode, filled in below. */ 941 24, 0x00, /* Hash/Radix, filled in below. */ 942 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 943 26, 0x40, /* Radix options: GTSE == yes. */ 944 }; 945 946 if (kvm_enabled()) { 947 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 948 val[3] = 0x80; /* OV5_MMU_BOTH */ 949 } else if (kvmppc_has_cap_mmu_radix()) { 950 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 951 } else { 952 val[3] = 0x00; /* Hash */ 953 } 954 } else { 955 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 956 /* V3 MMU supports both hash and radix (with dynamic switching) */ 957 val[3] = 0xC0; 958 } else { 959 /* Otherwise we can only do hash */ 960 val[3] = 0x00; 961 } 962 } 963 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 964 val, sizeof(val))); 965 } 966 967 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 968 { 969 MachineState *machine = MACHINE(spapr); 970 int chosen; 971 const char *boot_device = machine->boot_order; 972 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 973 size_t cb = 0; 974 char *bootlist = get_boot_devices_list(&cb, true); 975 976 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 977 978 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 979 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 980 spapr->initrd_base)); 981 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 982 spapr->initrd_base + spapr->initrd_size)); 983 984 if (spapr->kernel_size) { 985 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 986 cpu_to_be64(spapr->kernel_size) }; 987 988 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 989 &kprop, sizeof(kprop))); 990 if (spapr->kernel_le) { 991 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 992 } 993 } 994 if (boot_menu) { 995 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 996 } 997 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 998 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 999 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1000 1001 if (cb && bootlist) { 1002 int i; 1003 1004 for (i = 0; i < cb; i++) { 1005 if (bootlist[i] == '\n') { 1006 bootlist[i] = ' '; 1007 } 1008 } 1009 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1010 } 1011 1012 if (boot_device && strlen(boot_device)) { 1013 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1014 } 1015 1016 if (!spapr->has_graphics && stdout_path) { 1017 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1018 } 1019 1020 spapr_dt_ov5_platform_support(fdt, chosen); 1021 1022 g_free(stdout_path); 1023 g_free(bootlist); 1024 } 1025 1026 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 1027 { 1028 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1029 * KVM to work under pHyp with some guest co-operation */ 1030 int hypervisor; 1031 uint8_t hypercall[16]; 1032 1033 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1034 /* indicate KVM hypercall interface */ 1035 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1036 if (kvmppc_has_cap_fixup_hcalls()) { 1037 /* 1038 * Older KVM versions with older guest kernels were broken 1039 * with the magic page, don't allow the guest to map it. 1040 */ 1041 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1042 sizeof(hypercall))) { 1043 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1044 hypercall, sizeof(hypercall))); 1045 } 1046 } 1047 } 1048 1049 static void *spapr_build_fdt(sPAPRMachineState *spapr, 1050 hwaddr rtas_addr, 1051 hwaddr rtas_size) 1052 { 1053 MachineState *machine = MACHINE(spapr); 1054 MachineClass *mc = MACHINE_GET_CLASS(machine); 1055 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1056 int ret; 1057 void *fdt; 1058 sPAPRPHBState *phb; 1059 char *buf; 1060 1061 fdt = g_malloc0(FDT_MAX_SIZE); 1062 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 1063 1064 /* Root node */ 1065 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1066 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1067 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1068 1069 /* 1070 * Add info to guest to indentify which host is it being run on 1071 * and what is the uuid of the guest 1072 */ 1073 if (kvmppc_get_host_model(&buf)) { 1074 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1075 g_free(buf); 1076 } 1077 if (kvmppc_get_host_serial(&buf)) { 1078 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1079 g_free(buf); 1080 } 1081 1082 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1083 1084 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1085 if (qemu_uuid_set) { 1086 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1087 } 1088 g_free(buf); 1089 1090 if (qemu_get_vm_name()) { 1091 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1092 qemu_get_vm_name())); 1093 } 1094 1095 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1096 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1097 1098 /* /interrupt controller */ 1099 spapr_dt_xics(xics_max_server_number(), fdt, PHANDLE_XICP); 1100 1101 ret = spapr_populate_memory(spapr, fdt); 1102 if (ret < 0) { 1103 error_report("couldn't setup memory nodes in fdt"); 1104 exit(1); 1105 } 1106 1107 /* /vdevice */ 1108 spapr_dt_vdevice(spapr->vio_bus, fdt); 1109 1110 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1111 ret = spapr_rng_populate_dt(fdt); 1112 if (ret < 0) { 1113 error_report("could not set up rng device in the fdt"); 1114 exit(1); 1115 } 1116 } 1117 1118 QLIST_FOREACH(phb, &spapr->phbs, list) { 1119 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1120 if (ret < 0) { 1121 error_report("couldn't setup PCI devices in fdt"); 1122 exit(1); 1123 } 1124 } 1125 1126 /* cpus */ 1127 spapr_populate_cpus_dt_node(fdt, spapr); 1128 1129 if (smc->dr_lmb_enabled) { 1130 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1131 } 1132 1133 if (mc->has_hotpluggable_cpus) { 1134 int offset = fdt_path_offset(fdt, "/cpus"); 1135 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1136 SPAPR_DR_CONNECTOR_TYPE_CPU); 1137 if (ret < 0) { 1138 error_report("Couldn't set up CPU DR device tree properties"); 1139 exit(1); 1140 } 1141 } 1142 1143 /* /event-sources */ 1144 spapr_dt_events(spapr, fdt); 1145 1146 /* /rtas */ 1147 spapr_dt_rtas(spapr, fdt); 1148 1149 /* /chosen */ 1150 spapr_dt_chosen(spapr, fdt); 1151 1152 /* /hypervisor */ 1153 if (kvm_enabled()) { 1154 spapr_dt_hypervisor(spapr, fdt); 1155 } 1156 1157 /* Build memory reserve map */ 1158 if (spapr->kernel_size) { 1159 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1160 } 1161 if (spapr->initrd_size) { 1162 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1163 } 1164 1165 /* ibm,client-architecture-support updates */ 1166 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1167 if (ret < 0) { 1168 error_report("couldn't setup CAS properties fdt"); 1169 exit(1); 1170 } 1171 1172 return fdt; 1173 } 1174 1175 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1176 { 1177 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1178 } 1179 1180 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1181 PowerPCCPU *cpu) 1182 { 1183 CPUPPCState *env = &cpu->env; 1184 1185 /* The TCG path should also be holding the BQL at this point */ 1186 g_assert(qemu_mutex_iothread_locked()); 1187 1188 if (msr_pr) { 1189 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1190 env->gpr[3] = H_PRIVILEGE; 1191 } else { 1192 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1193 } 1194 } 1195 1196 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1197 { 1198 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1199 1200 return spapr->patb_entry; 1201 } 1202 1203 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1204 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1205 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1206 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1207 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1208 1209 /* 1210 * Get the fd to access the kernel htab, re-opening it if necessary 1211 */ 1212 static int get_htab_fd(sPAPRMachineState *spapr) 1213 { 1214 Error *local_err = NULL; 1215 1216 if (spapr->htab_fd >= 0) { 1217 return spapr->htab_fd; 1218 } 1219 1220 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1221 if (spapr->htab_fd < 0) { 1222 error_report_err(local_err); 1223 } 1224 1225 return spapr->htab_fd; 1226 } 1227 1228 void close_htab_fd(sPAPRMachineState *spapr) 1229 { 1230 if (spapr->htab_fd >= 0) { 1231 close(spapr->htab_fd); 1232 } 1233 spapr->htab_fd = -1; 1234 } 1235 1236 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1237 { 1238 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1239 1240 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1241 } 1242 1243 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1244 { 1245 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1246 1247 assert(kvm_enabled()); 1248 1249 if (!spapr->htab) { 1250 return 0; 1251 } 1252 1253 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1254 } 1255 1256 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1257 hwaddr ptex, int n) 1258 { 1259 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1260 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1261 1262 if (!spapr->htab) { 1263 /* 1264 * HTAB is controlled by KVM. Fetch into temporary buffer 1265 */ 1266 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1267 kvmppc_read_hptes(hptes, ptex, n); 1268 return hptes; 1269 } 1270 1271 /* 1272 * HTAB is controlled by QEMU. Just point to the internally 1273 * accessible PTEG. 1274 */ 1275 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1276 } 1277 1278 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1279 const ppc_hash_pte64_t *hptes, 1280 hwaddr ptex, int n) 1281 { 1282 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1283 1284 if (!spapr->htab) { 1285 g_free((void *)hptes); 1286 } 1287 1288 /* Nothing to do for qemu managed HPT */ 1289 } 1290 1291 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1292 uint64_t pte0, uint64_t pte1) 1293 { 1294 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1295 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1296 1297 if (!spapr->htab) { 1298 kvmppc_write_hpte(ptex, pte0, pte1); 1299 } else { 1300 stq_p(spapr->htab + offset, pte0); 1301 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1302 } 1303 } 1304 1305 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1306 { 1307 int shift; 1308 1309 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1310 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1311 * that's much more than is needed for Linux guests */ 1312 shift = ctz64(pow2ceil(ramsize)) - 7; 1313 shift = MAX(shift, 18); /* Minimum architected size */ 1314 shift = MIN(shift, 46); /* Maximum architected size */ 1315 return shift; 1316 } 1317 1318 void spapr_free_hpt(sPAPRMachineState *spapr) 1319 { 1320 g_free(spapr->htab); 1321 spapr->htab = NULL; 1322 spapr->htab_shift = 0; 1323 close_htab_fd(spapr); 1324 } 1325 1326 void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1327 Error **errp) 1328 { 1329 long rc; 1330 1331 /* Clean up any HPT info from a previous boot */ 1332 spapr_free_hpt(spapr); 1333 1334 rc = kvmppc_reset_htab(shift); 1335 if (rc < 0) { 1336 /* kernel-side HPT needed, but couldn't allocate one */ 1337 error_setg_errno(errp, errno, 1338 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1339 shift); 1340 /* This is almost certainly fatal, but if the caller really 1341 * wants to carry on with shift == 0, it's welcome to try */ 1342 } else if (rc > 0) { 1343 /* kernel-side HPT allocated */ 1344 if (rc != shift) { 1345 error_setg(errp, 1346 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1347 shift, rc); 1348 } 1349 1350 spapr->htab_shift = shift; 1351 spapr->htab = NULL; 1352 } else { 1353 /* kernel-side HPT not needed, allocate in userspace instead */ 1354 size_t size = 1ULL << shift; 1355 int i; 1356 1357 spapr->htab = qemu_memalign(size, size); 1358 if (!spapr->htab) { 1359 error_setg_errno(errp, errno, 1360 "Could not allocate HPT of order %d", shift); 1361 return; 1362 } 1363 1364 memset(spapr->htab, 0, size); 1365 spapr->htab_shift = shift; 1366 1367 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1368 DIRTY_HPTE(HPTE(spapr->htab, i)); 1369 } 1370 } 1371 } 1372 1373 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1374 { 1375 int hpt_shift; 1376 1377 if ((spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) 1378 || (spapr->cas_reboot 1379 && !spapr_ovec_test(spapr->ov5_cas, OV5_HPT_RESIZE))) { 1380 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1381 } else { 1382 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->ram_size); 1383 } 1384 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1385 1386 if (spapr->vrma_adjust) { 1387 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(MACHINE(spapr)), 1388 spapr->htab_shift); 1389 } 1390 /* We're setting up a hash table, so that means we're not radix */ 1391 spapr->patb_entry = 0; 1392 } 1393 1394 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1395 { 1396 bool matched = false; 1397 1398 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1399 matched = true; 1400 } 1401 1402 if (!matched) { 1403 error_report("Device %s is not supported by this machine yet.", 1404 qdev_fw_name(DEVICE(sbdev))); 1405 exit(1); 1406 } 1407 } 1408 1409 static void ppc_spapr_reset(void) 1410 { 1411 MachineState *machine = MACHINE(qdev_get_machine()); 1412 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1413 PowerPCCPU *first_ppc_cpu; 1414 uint32_t rtas_limit; 1415 hwaddr rtas_addr, fdt_addr; 1416 void *fdt; 1417 int rc; 1418 1419 /* Check for unknown sysbus devices */ 1420 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1421 1422 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1423 /* If using KVM with radix mode available, VCPUs can be started 1424 * without a HPT because KVM will start them in radix mode. 1425 * Set the GR bit in PATB so that we know there is no HPT. */ 1426 spapr->patb_entry = PATBE1_GR; 1427 } else { 1428 spapr_setup_hpt_and_vrma(spapr); 1429 } 1430 1431 qemu_devices_reset(); 1432 spapr_clear_pending_events(spapr); 1433 1434 /* 1435 * We place the device tree and RTAS just below either the top of the RMA, 1436 * or just below 2GB, whichever is lowere, so that it can be 1437 * processed with 32-bit real mode code if necessary 1438 */ 1439 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1440 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1441 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1442 1443 /* if this reset wasn't generated by CAS, we should reset our 1444 * negotiated options and start from scratch */ 1445 if (!spapr->cas_reboot) { 1446 spapr_ovec_cleanup(spapr->ov5_cas); 1447 spapr->ov5_cas = spapr_ovec_new(); 1448 1449 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1450 } 1451 1452 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1453 1454 spapr_load_rtas(spapr, fdt, rtas_addr); 1455 1456 rc = fdt_pack(fdt); 1457 1458 /* Should only fail if we've built a corrupted tree */ 1459 assert(rc == 0); 1460 1461 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1462 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1463 fdt_totalsize(fdt), FDT_MAX_SIZE); 1464 exit(1); 1465 } 1466 1467 /* Load the fdt */ 1468 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1469 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1470 g_free(fdt); 1471 1472 /* Set up the entry state */ 1473 first_ppc_cpu = POWERPC_CPU(first_cpu); 1474 first_ppc_cpu->env.gpr[3] = fdt_addr; 1475 first_ppc_cpu->env.gpr[5] = 0; 1476 first_cpu->halted = 0; 1477 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1478 1479 spapr->cas_reboot = false; 1480 } 1481 1482 static void spapr_create_nvram(sPAPRMachineState *spapr) 1483 { 1484 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1485 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1486 1487 if (dinfo) { 1488 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1489 &error_fatal); 1490 } 1491 1492 qdev_init_nofail(dev); 1493 1494 spapr->nvram = (struct sPAPRNVRAM *)dev; 1495 } 1496 1497 static void spapr_rtc_create(sPAPRMachineState *spapr) 1498 { 1499 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1500 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1501 &error_fatal); 1502 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1503 &error_fatal); 1504 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1505 "date", &error_fatal); 1506 } 1507 1508 /* Returns whether we want to use VGA or not */ 1509 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1510 { 1511 switch (vga_interface_type) { 1512 case VGA_NONE: 1513 return false; 1514 case VGA_DEVICE: 1515 return true; 1516 case VGA_STD: 1517 case VGA_VIRTIO: 1518 return pci_vga_init(pci_bus) != NULL; 1519 default: 1520 error_setg(errp, 1521 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1522 return false; 1523 } 1524 } 1525 1526 static int spapr_post_load(void *opaque, int version_id) 1527 { 1528 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1529 int err = 0; 1530 1531 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1532 CPUState *cs; 1533 CPU_FOREACH(cs) { 1534 PowerPCCPU *cpu = POWERPC_CPU(cs); 1535 icp_resend(ICP(cpu->intc)); 1536 } 1537 } 1538 1539 /* In earlier versions, there was no separate qdev for the PAPR 1540 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1541 * So when migrating from those versions, poke the incoming offset 1542 * value into the RTC device */ 1543 if (version_id < 3) { 1544 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1545 } 1546 1547 if (spapr->patb_entry) { 1548 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1549 bool radix = !!(spapr->patb_entry & PATBE1_GR); 1550 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1551 1552 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1553 if (err) { 1554 error_report("Process table config unsupported by the host"); 1555 return -EINVAL; 1556 } 1557 } 1558 1559 return err; 1560 } 1561 1562 static bool version_before_3(void *opaque, int version_id) 1563 { 1564 return version_id < 3; 1565 } 1566 1567 static bool spapr_pending_events_needed(void *opaque) 1568 { 1569 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1570 return !QTAILQ_EMPTY(&spapr->pending_events); 1571 } 1572 1573 static const VMStateDescription vmstate_spapr_event_entry = { 1574 .name = "spapr_event_log_entry", 1575 .version_id = 1, 1576 .minimum_version_id = 1, 1577 .fields = (VMStateField[]) { 1578 VMSTATE_UINT32(summary, sPAPREventLogEntry), 1579 VMSTATE_UINT32(extended_length, sPAPREventLogEntry), 1580 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, sPAPREventLogEntry, 0, 1581 NULL, extended_length), 1582 VMSTATE_END_OF_LIST() 1583 }, 1584 }; 1585 1586 static const VMStateDescription vmstate_spapr_pending_events = { 1587 .name = "spapr_pending_events", 1588 .version_id = 1, 1589 .minimum_version_id = 1, 1590 .needed = spapr_pending_events_needed, 1591 .fields = (VMStateField[]) { 1592 VMSTATE_QTAILQ_V(pending_events, sPAPRMachineState, 1, 1593 vmstate_spapr_event_entry, sPAPREventLogEntry, next), 1594 VMSTATE_END_OF_LIST() 1595 }, 1596 }; 1597 1598 static bool spapr_ov5_cas_needed(void *opaque) 1599 { 1600 sPAPRMachineState *spapr = opaque; 1601 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1602 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1603 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1604 bool cas_needed; 1605 1606 /* Prior to the introduction of sPAPROptionVector, we had two option 1607 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1608 * Both of these options encode machine topology into the device-tree 1609 * in such a way that the now-booted OS should still be able to interact 1610 * appropriately with QEMU regardless of what options were actually 1611 * negotiatied on the source side. 1612 * 1613 * As such, we can avoid migrating the CAS-negotiated options if these 1614 * are the only options available on the current machine/platform. 1615 * Since these are the only options available for pseries-2.7 and 1616 * earlier, this allows us to maintain old->new/new->old migration 1617 * compatibility. 1618 * 1619 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1620 * via default pseries-2.8 machines and explicit command-line parameters. 1621 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1622 * of the actual CAS-negotiated values to continue working properly. For 1623 * example, availability of memory unplug depends on knowing whether 1624 * OV5_HP_EVT was negotiated via CAS. 1625 * 1626 * Thus, for any cases where the set of available CAS-negotiatable 1627 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1628 * include the CAS-negotiated options in the migration stream. 1629 */ 1630 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1631 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1632 1633 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1634 * the mask itself since in the future it's possible "legacy" bits may be 1635 * removed via machine options, which could generate a false positive 1636 * that breaks migration. 1637 */ 1638 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1639 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1640 1641 spapr_ovec_cleanup(ov5_mask); 1642 spapr_ovec_cleanup(ov5_legacy); 1643 spapr_ovec_cleanup(ov5_removed); 1644 1645 return cas_needed; 1646 } 1647 1648 static const VMStateDescription vmstate_spapr_ov5_cas = { 1649 .name = "spapr_option_vector_ov5_cas", 1650 .version_id = 1, 1651 .minimum_version_id = 1, 1652 .needed = spapr_ov5_cas_needed, 1653 .fields = (VMStateField[]) { 1654 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1655 vmstate_spapr_ovec, sPAPROptionVector), 1656 VMSTATE_END_OF_LIST() 1657 }, 1658 }; 1659 1660 static bool spapr_patb_entry_needed(void *opaque) 1661 { 1662 sPAPRMachineState *spapr = opaque; 1663 1664 return !!spapr->patb_entry; 1665 } 1666 1667 static const VMStateDescription vmstate_spapr_patb_entry = { 1668 .name = "spapr_patb_entry", 1669 .version_id = 1, 1670 .minimum_version_id = 1, 1671 .needed = spapr_patb_entry_needed, 1672 .fields = (VMStateField[]) { 1673 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1674 VMSTATE_END_OF_LIST() 1675 }, 1676 }; 1677 1678 static const VMStateDescription vmstate_spapr = { 1679 .name = "spapr", 1680 .version_id = 3, 1681 .minimum_version_id = 1, 1682 .post_load = spapr_post_load, 1683 .fields = (VMStateField[]) { 1684 /* used to be @next_irq */ 1685 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1686 1687 /* RTC offset */ 1688 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1689 1690 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1691 VMSTATE_END_OF_LIST() 1692 }, 1693 .subsections = (const VMStateDescription*[]) { 1694 &vmstate_spapr_ov5_cas, 1695 &vmstate_spapr_patb_entry, 1696 &vmstate_spapr_pending_events, 1697 NULL 1698 } 1699 }; 1700 1701 static int htab_save_setup(QEMUFile *f, void *opaque) 1702 { 1703 sPAPRMachineState *spapr = opaque; 1704 1705 /* "Iteration" header */ 1706 if (!spapr->htab_shift) { 1707 qemu_put_be32(f, -1); 1708 } else { 1709 qemu_put_be32(f, spapr->htab_shift); 1710 } 1711 1712 if (spapr->htab) { 1713 spapr->htab_save_index = 0; 1714 spapr->htab_first_pass = true; 1715 } else { 1716 if (spapr->htab_shift) { 1717 assert(kvm_enabled()); 1718 } 1719 } 1720 1721 1722 return 0; 1723 } 1724 1725 static void htab_save_chunk(QEMUFile *f, sPAPRMachineState *spapr, 1726 int chunkstart, int n_valid, int n_invalid) 1727 { 1728 qemu_put_be32(f, chunkstart); 1729 qemu_put_be16(f, n_valid); 1730 qemu_put_be16(f, n_invalid); 1731 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1732 HASH_PTE_SIZE_64 * n_valid); 1733 } 1734 1735 static void htab_save_end_marker(QEMUFile *f) 1736 { 1737 qemu_put_be32(f, 0); 1738 qemu_put_be16(f, 0); 1739 qemu_put_be16(f, 0); 1740 } 1741 1742 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1743 int64_t max_ns) 1744 { 1745 bool has_timeout = max_ns != -1; 1746 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1747 int index = spapr->htab_save_index; 1748 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1749 1750 assert(spapr->htab_first_pass); 1751 1752 do { 1753 int chunkstart; 1754 1755 /* Consume invalid HPTEs */ 1756 while ((index < htabslots) 1757 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1758 CLEAN_HPTE(HPTE(spapr->htab, index)); 1759 index++; 1760 } 1761 1762 /* Consume valid HPTEs */ 1763 chunkstart = index; 1764 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1765 && HPTE_VALID(HPTE(spapr->htab, index))) { 1766 CLEAN_HPTE(HPTE(spapr->htab, index)); 1767 index++; 1768 } 1769 1770 if (index > chunkstart) { 1771 int n_valid = index - chunkstart; 1772 1773 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 1774 1775 if (has_timeout && 1776 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1777 break; 1778 } 1779 } 1780 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1781 1782 if (index >= htabslots) { 1783 assert(index == htabslots); 1784 index = 0; 1785 spapr->htab_first_pass = false; 1786 } 1787 spapr->htab_save_index = index; 1788 } 1789 1790 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1791 int64_t max_ns) 1792 { 1793 bool final = max_ns < 0; 1794 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1795 int examined = 0, sent = 0; 1796 int index = spapr->htab_save_index; 1797 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1798 1799 assert(!spapr->htab_first_pass); 1800 1801 do { 1802 int chunkstart, invalidstart; 1803 1804 /* Consume non-dirty HPTEs */ 1805 while ((index < htabslots) 1806 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1807 index++; 1808 examined++; 1809 } 1810 1811 chunkstart = index; 1812 /* Consume valid dirty HPTEs */ 1813 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1814 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1815 && HPTE_VALID(HPTE(spapr->htab, index))) { 1816 CLEAN_HPTE(HPTE(spapr->htab, index)); 1817 index++; 1818 examined++; 1819 } 1820 1821 invalidstart = index; 1822 /* Consume invalid dirty HPTEs */ 1823 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1824 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1825 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1826 CLEAN_HPTE(HPTE(spapr->htab, index)); 1827 index++; 1828 examined++; 1829 } 1830 1831 if (index > chunkstart) { 1832 int n_valid = invalidstart - chunkstart; 1833 int n_invalid = index - invalidstart; 1834 1835 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 1836 sent += index - chunkstart; 1837 1838 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1839 break; 1840 } 1841 } 1842 1843 if (examined >= htabslots) { 1844 break; 1845 } 1846 1847 if (index >= htabslots) { 1848 assert(index == htabslots); 1849 index = 0; 1850 } 1851 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1852 1853 if (index >= htabslots) { 1854 assert(index == htabslots); 1855 index = 0; 1856 } 1857 1858 spapr->htab_save_index = index; 1859 1860 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1861 } 1862 1863 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1864 #define MAX_KVM_BUF_SIZE 2048 1865 1866 static int htab_save_iterate(QEMUFile *f, void *opaque) 1867 { 1868 sPAPRMachineState *spapr = opaque; 1869 int fd; 1870 int rc = 0; 1871 1872 /* Iteration header */ 1873 if (!spapr->htab_shift) { 1874 qemu_put_be32(f, -1); 1875 return 1; 1876 } else { 1877 qemu_put_be32(f, 0); 1878 } 1879 1880 if (!spapr->htab) { 1881 assert(kvm_enabled()); 1882 1883 fd = get_htab_fd(spapr); 1884 if (fd < 0) { 1885 return fd; 1886 } 1887 1888 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1889 if (rc < 0) { 1890 return rc; 1891 } 1892 } else if (spapr->htab_first_pass) { 1893 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1894 } else { 1895 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1896 } 1897 1898 htab_save_end_marker(f); 1899 1900 return rc; 1901 } 1902 1903 static int htab_save_complete(QEMUFile *f, void *opaque) 1904 { 1905 sPAPRMachineState *spapr = opaque; 1906 int fd; 1907 1908 /* Iteration header */ 1909 if (!spapr->htab_shift) { 1910 qemu_put_be32(f, -1); 1911 return 0; 1912 } else { 1913 qemu_put_be32(f, 0); 1914 } 1915 1916 if (!spapr->htab) { 1917 int rc; 1918 1919 assert(kvm_enabled()); 1920 1921 fd = get_htab_fd(spapr); 1922 if (fd < 0) { 1923 return fd; 1924 } 1925 1926 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1927 if (rc < 0) { 1928 return rc; 1929 } 1930 } else { 1931 if (spapr->htab_first_pass) { 1932 htab_save_first_pass(f, spapr, -1); 1933 } 1934 htab_save_later_pass(f, spapr, -1); 1935 } 1936 1937 /* End marker */ 1938 htab_save_end_marker(f); 1939 1940 return 0; 1941 } 1942 1943 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1944 { 1945 sPAPRMachineState *spapr = opaque; 1946 uint32_t section_hdr; 1947 int fd = -1; 1948 Error *local_err = NULL; 1949 1950 if (version_id < 1 || version_id > 1) { 1951 error_report("htab_load() bad version"); 1952 return -EINVAL; 1953 } 1954 1955 section_hdr = qemu_get_be32(f); 1956 1957 if (section_hdr == -1) { 1958 spapr_free_hpt(spapr); 1959 return 0; 1960 } 1961 1962 if (section_hdr) { 1963 /* First section gives the htab size */ 1964 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1965 if (local_err) { 1966 error_report_err(local_err); 1967 return -EINVAL; 1968 } 1969 return 0; 1970 } 1971 1972 if (!spapr->htab) { 1973 assert(kvm_enabled()); 1974 1975 fd = kvmppc_get_htab_fd(true, 0, &local_err); 1976 if (fd < 0) { 1977 error_report_err(local_err); 1978 return fd; 1979 } 1980 } 1981 1982 while (true) { 1983 uint32_t index; 1984 uint16_t n_valid, n_invalid; 1985 1986 index = qemu_get_be32(f); 1987 n_valid = qemu_get_be16(f); 1988 n_invalid = qemu_get_be16(f); 1989 1990 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1991 /* End of Stream */ 1992 break; 1993 } 1994 1995 if ((index + n_valid + n_invalid) > 1996 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1997 /* Bad index in stream */ 1998 error_report( 1999 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2000 index, n_valid, n_invalid, spapr->htab_shift); 2001 return -EINVAL; 2002 } 2003 2004 if (spapr->htab) { 2005 if (n_valid) { 2006 qemu_get_buffer(f, HPTE(spapr->htab, index), 2007 HASH_PTE_SIZE_64 * n_valid); 2008 } 2009 if (n_invalid) { 2010 memset(HPTE(spapr->htab, index + n_valid), 0, 2011 HASH_PTE_SIZE_64 * n_invalid); 2012 } 2013 } else { 2014 int rc; 2015 2016 assert(fd >= 0); 2017 2018 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 2019 if (rc < 0) { 2020 return rc; 2021 } 2022 } 2023 } 2024 2025 if (!spapr->htab) { 2026 assert(fd >= 0); 2027 close(fd); 2028 } 2029 2030 return 0; 2031 } 2032 2033 static void htab_save_cleanup(void *opaque) 2034 { 2035 sPAPRMachineState *spapr = opaque; 2036 2037 close_htab_fd(spapr); 2038 } 2039 2040 static SaveVMHandlers savevm_htab_handlers = { 2041 .save_setup = htab_save_setup, 2042 .save_live_iterate = htab_save_iterate, 2043 .save_live_complete_precopy = htab_save_complete, 2044 .save_cleanup = htab_save_cleanup, 2045 .load_state = htab_load, 2046 }; 2047 2048 static void spapr_boot_set(void *opaque, const char *boot_device, 2049 Error **errp) 2050 { 2051 MachineState *machine = MACHINE(opaque); 2052 machine->boot_order = g_strdup(boot_device); 2053 } 2054 2055 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 2056 { 2057 MachineState *machine = MACHINE(spapr); 2058 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2059 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2060 int i; 2061 2062 for (i = 0; i < nr_lmbs; i++) { 2063 uint64_t addr; 2064 2065 addr = i * lmb_size + spapr->hotplug_memory.base; 2066 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2067 addr / lmb_size); 2068 } 2069 } 2070 2071 /* 2072 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2073 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2074 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2075 */ 2076 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2077 { 2078 int i; 2079 2080 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2081 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2082 " is not aligned to %llu MiB", 2083 machine->ram_size, 2084 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2085 return; 2086 } 2087 2088 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2089 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2090 " is not aligned to %llu MiB", 2091 machine->ram_size, 2092 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2093 return; 2094 } 2095 2096 for (i = 0; i < nb_numa_nodes; i++) { 2097 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2098 error_setg(errp, 2099 "Node %d memory size 0x%" PRIx64 2100 " is not aligned to %llu MiB", 2101 i, numa_info[i].node_mem, 2102 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2103 return; 2104 } 2105 } 2106 } 2107 2108 /* find cpu slot in machine->possible_cpus by core_id */ 2109 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2110 { 2111 int index = id / smp_threads; 2112 2113 if (index >= ms->possible_cpus->len) { 2114 return NULL; 2115 } 2116 if (idx) { 2117 *idx = index; 2118 } 2119 return &ms->possible_cpus->cpus[index]; 2120 } 2121 2122 static void spapr_init_cpus(sPAPRMachineState *spapr) 2123 { 2124 MachineState *machine = MACHINE(spapr); 2125 MachineClass *mc = MACHINE_GET_CLASS(machine); 2126 char *type = spapr_get_cpu_core_type(machine->cpu_model); 2127 int smt = kvmppc_smt_threads(); 2128 const CPUArchIdList *possible_cpus; 2129 int boot_cores_nr = smp_cpus / smp_threads; 2130 int i; 2131 2132 if (!type) { 2133 error_report("Unable to find sPAPR CPU Core definition"); 2134 exit(1); 2135 } 2136 2137 possible_cpus = mc->possible_cpu_arch_ids(machine); 2138 if (mc->has_hotpluggable_cpus) { 2139 if (smp_cpus % smp_threads) { 2140 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2141 smp_cpus, smp_threads); 2142 exit(1); 2143 } 2144 if (max_cpus % smp_threads) { 2145 error_report("max_cpus (%u) must be multiple of threads (%u)", 2146 max_cpus, smp_threads); 2147 exit(1); 2148 } 2149 } else { 2150 if (max_cpus != smp_cpus) { 2151 error_report("This machine version does not support CPU hotplug"); 2152 exit(1); 2153 } 2154 boot_cores_nr = possible_cpus->len; 2155 } 2156 2157 for (i = 0; i < possible_cpus->len; i++) { 2158 int core_id = i * smp_threads; 2159 2160 if (mc->has_hotpluggable_cpus) { 2161 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2162 (core_id / smp_threads) * smt); 2163 } 2164 2165 if (i < boot_cores_nr) { 2166 Object *core = object_new(type); 2167 int nr_threads = smp_threads; 2168 2169 /* Handle the partially filled core for older machine types */ 2170 if ((i + 1) * smp_threads >= smp_cpus) { 2171 nr_threads = smp_cpus - i * smp_threads; 2172 } 2173 2174 object_property_set_int(core, nr_threads, "nr-threads", 2175 &error_fatal); 2176 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2177 &error_fatal); 2178 object_property_set_bool(core, true, "realized", &error_fatal); 2179 } 2180 } 2181 g_free(type); 2182 } 2183 2184 static void spapr_set_vsmt_mode(sPAPRMachineState *spapr, Error **errp) 2185 { 2186 Error *local_err = NULL; 2187 bool vsmt_user = !!spapr->vsmt; 2188 int kvm_smt = kvmppc_smt_threads(); 2189 int ret; 2190 2191 if (!kvm_enabled() && (smp_threads > 1)) { 2192 error_setg(&local_err, "TCG cannot support more than 1 thread/core " 2193 "on a pseries machine"); 2194 goto out; 2195 } 2196 if (!is_power_of_2(smp_threads)) { 2197 error_setg(&local_err, "Cannot support %d threads/core on a pseries " 2198 "machine because it must be a power of 2", smp_threads); 2199 goto out; 2200 } 2201 2202 /* Detemine the VSMT mode to use: */ 2203 if (vsmt_user) { 2204 if (spapr->vsmt < smp_threads) { 2205 error_setg(&local_err, "Cannot support VSMT mode %d" 2206 " because it must be >= threads/core (%d)", 2207 spapr->vsmt, smp_threads); 2208 goto out; 2209 } 2210 /* In this case, spapr->vsmt has been set by the command line */ 2211 } else { 2212 /* Choose a VSMT mode that may be higher than necessary but is 2213 * likely to be compatible with hosts that don't have VSMT. */ 2214 spapr->vsmt = MAX(kvm_smt, smp_threads); 2215 } 2216 2217 /* KVM: If necessary, set the SMT mode: */ 2218 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2219 ret = kvmppc_set_smt_threads(spapr->vsmt); 2220 if (ret) { 2221 error_setg(&local_err, 2222 "Failed to set KVM's VSMT mode to %d (errno %d)", 2223 spapr->vsmt, ret); 2224 if (!vsmt_user) { 2225 error_append_hint(&local_err, "On PPC, a VM with %d threads/" 2226 "core on a host with %d threads/core requires " 2227 " the use of VSMT mode %d.\n", 2228 smp_threads, kvm_smt, spapr->vsmt); 2229 } 2230 kvmppc_hint_smt_possible(&local_err); 2231 goto out; 2232 } 2233 } 2234 /* else TCG: nothing to do currently */ 2235 out: 2236 error_propagate(errp, local_err); 2237 } 2238 2239 /* pSeries LPAR / sPAPR hardware init */ 2240 static void ppc_spapr_init(MachineState *machine) 2241 { 2242 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2243 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2244 const char *kernel_filename = machine->kernel_filename; 2245 const char *initrd_filename = machine->initrd_filename; 2246 PCIHostState *phb; 2247 int i; 2248 MemoryRegion *sysmem = get_system_memory(); 2249 MemoryRegion *ram = g_new(MemoryRegion, 1); 2250 MemoryRegion *rma_region; 2251 void *rma = NULL; 2252 hwaddr rma_alloc_size; 2253 hwaddr node0_size = spapr_node0_size(machine); 2254 long load_limit, fw_size; 2255 char *filename; 2256 Error *resize_hpt_err = NULL; 2257 2258 msi_nonbroken = true; 2259 2260 QLIST_INIT(&spapr->phbs); 2261 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2262 2263 /* Check HPT resizing availability */ 2264 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2265 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2266 /* 2267 * If the user explicitly requested a mode we should either 2268 * supply it, or fail completely (which we do below). But if 2269 * it's not set explicitly, we reset our mode to something 2270 * that works 2271 */ 2272 if (resize_hpt_err) { 2273 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2274 error_free(resize_hpt_err); 2275 resize_hpt_err = NULL; 2276 } else { 2277 spapr->resize_hpt = smc->resize_hpt_default; 2278 } 2279 } 2280 2281 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2282 2283 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2284 /* 2285 * User requested HPT resize, but this host can't supply it. Bail out 2286 */ 2287 error_report_err(resize_hpt_err); 2288 exit(1); 2289 } 2290 2291 /* Allocate RMA if necessary */ 2292 rma_alloc_size = kvmppc_alloc_rma(&rma); 2293 2294 if (rma_alloc_size == -1) { 2295 error_report("Unable to create RMA"); 2296 exit(1); 2297 } 2298 2299 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2300 spapr->rma_size = rma_alloc_size; 2301 } else { 2302 spapr->rma_size = node0_size; 2303 2304 /* With KVM, we don't actually know whether KVM supports an 2305 * unbounded RMA (PR KVM) or is limited by the hash table size 2306 * (HV KVM using VRMA), so we always assume the latter 2307 * 2308 * In that case, we also limit the initial allocations for RTAS 2309 * etc... to 256M since we have no way to know what the VRMA size 2310 * is going to be as it depends on the size of the hash table 2311 * isn't determined yet. 2312 */ 2313 if (kvm_enabled()) { 2314 spapr->vrma_adjust = 1; 2315 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2316 } 2317 2318 /* Actually we don't support unbounded RMA anymore since we 2319 * added proper emulation of HV mode. The max we can get is 2320 * 16G which also happens to be what we configure for PAPR 2321 * mode so make sure we don't do anything bigger than that 2322 */ 2323 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2324 } 2325 2326 if (spapr->rma_size > node0_size) { 2327 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2328 spapr->rma_size); 2329 exit(1); 2330 } 2331 2332 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2333 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2334 2335 /* Set up Interrupt Controller before we create the VCPUs */ 2336 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2337 2338 /* Set up containers for ibm,client-set-architecture negotiated options */ 2339 spapr->ov5 = spapr_ovec_new(); 2340 spapr->ov5_cas = spapr_ovec_new(); 2341 2342 if (smc->dr_lmb_enabled) { 2343 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2344 spapr_validate_node_memory(machine, &error_fatal); 2345 } 2346 2347 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2348 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2349 /* KVM and TCG always allow GTSE with radix... */ 2350 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2351 } 2352 /* ... but not with hash (currently). */ 2353 2354 /* advertise support for dedicated HP event source to guests */ 2355 if (spapr->use_hotplug_event_source) { 2356 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2357 } 2358 2359 /* advertise support for HPT resizing */ 2360 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2361 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2362 } 2363 2364 /* init CPUs */ 2365 if (machine->cpu_model == NULL) { 2366 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2367 } 2368 2369 spapr_cpu_parse_features(spapr); 2370 2371 spapr_set_vsmt_mode(spapr, &error_fatal); 2372 2373 spapr_init_cpus(spapr); 2374 2375 if (kvm_enabled()) { 2376 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2377 kvmppc_enable_logical_ci_hcalls(); 2378 kvmppc_enable_set_mode_hcall(); 2379 2380 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2381 kvmppc_enable_clear_ref_mod_hcalls(); 2382 } 2383 2384 /* allocate RAM */ 2385 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2386 machine->ram_size); 2387 memory_region_add_subregion(sysmem, 0, ram); 2388 2389 if (rma_alloc_size && rma) { 2390 rma_region = g_new(MemoryRegion, 1); 2391 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2392 rma_alloc_size, rma); 2393 vmstate_register_ram_global(rma_region); 2394 memory_region_add_subregion(sysmem, 0, rma_region); 2395 } 2396 2397 /* initialize hotplug memory address space */ 2398 if (machine->ram_size < machine->maxram_size) { 2399 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2400 /* 2401 * Limit the number of hotpluggable memory slots to half the number 2402 * slots that KVM supports, leaving the other half for PCI and other 2403 * devices. However ensure that number of slots doesn't drop below 32. 2404 */ 2405 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2406 SPAPR_MAX_RAM_SLOTS; 2407 2408 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2409 max_memslots = SPAPR_MAX_RAM_SLOTS; 2410 } 2411 if (machine->ram_slots > max_memslots) { 2412 error_report("Specified number of memory slots %" 2413 PRIu64" exceeds max supported %d", 2414 machine->ram_slots, max_memslots); 2415 exit(1); 2416 } 2417 2418 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2419 SPAPR_HOTPLUG_MEM_ALIGN); 2420 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2421 "hotplug-memory", hotplug_mem_size); 2422 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2423 &spapr->hotplug_memory.mr); 2424 } 2425 2426 if (smc->dr_lmb_enabled) { 2427 spapr_create_lmb_dr_connectors(spapr); 2428 } 2429 2430 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2431 if (!filename) { 2432 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2433 exit(1); 2434 } 2435 spapr->rtas_size = get_image_size(filename); 2436 if (spapr->rtas_size < 0) { 2437 error_report("Could not get size of LPAR rtas '%s'", filename); 2438 exit(1); 2439 } 2440 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2441 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2442 error_report("Could not load LPAR rtas '%s'", filename); 2443 exit(1); 2444 } 2445 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2446 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2447 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2448 exit(1); 2449 } 2450 g_free(filename); 2451 2452 /* Set up RTAS event infrastructure */ 2453 spapr_events_init(spapr); 2454 2455 /* Set up the RTC RTAS interfaces */ 2456 spapr_rtc_create(spapr); 2457 2458 /* Set up VIO bus */ 2459 spapr->vio_bus = spapr_vio_bus_init(); 2460 2461 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2462 if (serial_hds[i]) { 2463 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2464 } 2465 } 2466 2467 /* We always have at least the nvram device on VIO */ 2468 spapr_create_nvram(spapr); 2469 2470 /* Set up PCI */ 2471 spapr_pci_rtas_init(); 2472 2473 phb = spapr_create_phb(spapr, 0); 2474 2475 for (i = 0; i < nb_nics; i++) { 2476 NICInfo *nd = &nd_table[i]; 2477 2478 if (!nd->model) { 2479 nd->model = g_strdup("ibmveth"); 2480 } 2481 2482 if (strcmp(nd->model, "ibmveth") == 0) { 2483 spapr_vlan_create(spapr->vio_bus, nd); 2484 } else { 2485 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2486 } 2487 } 2488 2489 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2490 spapr_vscsi_create(spapr->vio_bus); 2491 } 2492 2493 /* Graphics */ 2494 if (spapr_vga_init(phb->bus, &error_fatal)) { 2495 spapr->has_graphics = true; 2496 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2497 } 2498 2499 if (machine->usb) { 2500 if (smc->use_ohci_by_default) { 2501 pci_create_simple(phb->bus, -1, "pci-ohci"); 2502 } else { 2503 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2504 } 2505 2506 if (spapr->has_graphics) { 2507 USBBus *usb_bus = usb_bus_find(-1); 2508 2509 usb_create_simple(usb_bus, "usb-kbd"); 2510 usb_create_simple(usb_bus, "usb-mouse"); 2511 } 2512 } 2513 2514 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2515 error_report( 2516 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2517 MIN_RMA_SLOF); 2518 exit(1); 2519 } 2520 2521 if (kernel_filename) { 2522 uint64_t lowaddr = 0; 2523 2524 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2525 NULL, NULL, &lowaddr, NULL, 1, 2526 PPC_ELF_MACHINE, 0, 0); 2527 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2528 spapr->kernel_size = load_elf(kernel_filename, 2529 translate_kernel_address, NULL, NULL, 2530 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2531 0, 0); 2532 spapr->kernel_le = spapr->kernel_size > 0; 2533 } 2534 if (spapr->kernel_size < 0) { 2535 error_report("error loading %s: %s", kernel_filename, 2536 load_elf_strerror(spapr->kernel_size)); 2537 exit(1); 2538 } 2539 2540 /* load initrd */ 2541 if (initrd_filename) { 2542 /* Try to locate the initrd in the gap between the kernel 2543 * and the firmware. Add a bit of space just in case 2544 */ 2545 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2546 + 0x1ffff) & ~0xffff; 2547 spapr->initrd_size = load_image_targphys(initrd_filename, 2548 spapr->initrd_base, 2549 load_limit 2550 - spapr->initrd_base); 2551 if (spapr->initrd_size < 0) { 2552 error_report("could not load initial ram disk '%s'", 2553 initrd_filename); 2554 exit(1); 2555 } 2556 } 2557 } 2558 2559 if (bios_name == NULL) { 2560 bios_name = FW_FILE_NAME; 2561 } 2562 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2563 if (!filename) { 2564 error_report("Could not find LPAR firmware '%s'", bios_name); 2565 exit(1); 2566 } 2567 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2568 if (fw_size <= 0) { 2569 error_report("Could not load LPAR firmware '%s'", filename); 2570 exit(1); 2571 } 2572 g_free(filename); 2573 2574 /* FIXME: Should register things through the MachineState's qdev 2575 * interface, this is a legacy from the sPAPREnvironment structure 2576 * which predated MachineState but had a similar function */ 2577 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2578 register_savevm_live(NULL, "spapr/htab", -1, 1, 2579 &savevm_htab_handlers, spapr); 2580 2581 qemu_register_boot_set(spapr_boot_set, spapr); 2582 2583 if (kvm_enabled()) { 2584 /* to stop and start vmclock */ 2585 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2586 &spapr->tb); 2587 2588 kvmppc_spapr_enable_inkernel_multitce(); 2589 } 2590 } 2591 2592 static int spapr_kvm_type(const char *vm_type) 2593 { 2594 if (!vm_type) { 2595 return 0; 2596 } 2597 2598 if (!strcmp(vm_type, "HV")) { 2599 return 1; 2600 } 2601 2602 if (!strcmp(vm_type, "PR")) { 2603 return 2; 2604 } 2605 2606 error_report("Unknown kvm-type specified '%s'", vm_type); 2607 exit(1); 2608 } 2609 2610 /* 2611 * Implementation of an interface to adjust firmware path 2612 * for the bootindex property handling. 2613 */ 2614 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2615 DeviceState *dev) 2616 { 2617 #define CAST(type, obj, name) \ 2618 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2619 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2620 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2621 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 2622 2623 if (d) { 2624 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2625 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2626 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2627 2628 if (spapr) { 2629 /* 2630 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2631 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2632 * in the top 16 bits of the 64-bit LUN 2633 */ 2634 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2635 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2636 (uint64_t)id << 48); 2637 } else if (virtio) { 2638 /* 2639 * We use SRP luns of the form 01000000 | (target << 8) | lun 2640 * in the top 32 bits of the 64-bit LUN 2641 * Note: the quote above is from SLOF and it is wrong, 2642 * the actual binding is: 2643 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2644 */ 2645 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2646 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2647 (uint64_t)id << 32); 2648 } else if (usb) { 2649 /* 2650 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2651 * in the top 32 bits of the 64-bit LUN 2652 */ 2653 unsigned usb_port = atoi(usb->port->path); 2654 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2655 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2656 (uint64_t)id << 32); 2657 } 2658 } 2659 2660 /* 2661 * SLOF probes the USB devices, and if it recognizes that the device is a 2662 * storage device, it changes its name to "storage" instead of "usb-host", 2663 * and additionally adds a child node for the SCSI LUN, so the correct 2664 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2665 */ 2666 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2667 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2668 if (usb_host_dev_is_scsi_storage(usbdev)) { 2669 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2670 } 2671 } 2672 2673 if (phb) { 2674 /* Replace "pci" with "pci@800000020000000" */ 2675 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2676 } 2677 2678 if (vsc) { 2679 /* Same logic as virtio above */ 2680 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 2681 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 2682 } 2683 2684 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 2685 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 2686 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 2687 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 2688 } 2689 2690 return NULL; 2691 } 2692 2693 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2694 { 2695 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2696 2697 return g_strdup(spapr->kvm_type); 2698 } 2699 2700 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2701 { 2702 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2703 2704 g_free(spapr->kvm_type); 2705 spapr->kvm_type = g_strdup(value); 2706 } 2707 2708 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2709 { 2710 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2711 2712 return spapr->use_hotplug_event_source; 2713 } 2714 2715 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2716 Error **errp) 2717 { 2718 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2719 2720 spapr->use_hotplug_event_source = value; 2721 } 2722 2723 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 2724 { 2725 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2726 2727 switch (spapr->resize_hpt) { 2728 case SPAPR_RESIZE_HPT_DEFAULT: 2729 return g_strdup("default"); 2730 case SPAPR_RESIZE_HPT_DISABLED: 2731 return g_strdup("disabled"); 2732 case SPAPR_RESIZE_HPT_ENABLED: 2733 return g_strdup("enabled"); 2734 case SPAPR_RESIZE_HPT_REQUIRED: 2735 return g_strdup("required"); 2736 } 2737 g_assert_not_reached(); 2738 } 2739 2740 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 2741 { 2742 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2743 2744 if (strcmp(value, "default") == 0) { 2745 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 2746 } else if (strcmp(value, "disabled") == 0) { 2747 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2748 } else if (strcmp(value, "enabled") == 0) { 2749 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 2750 } else if (strcmp(value, "required") == 0) { 2751 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 2752 } else { 2753 error_setg(errp, "Bad value for \"resize-hpt\" property"); 2754 } 2755 } 2756 2757 static void spapr_get_vsmt(Object *obj, Visitor *v, const char *name, 2758 void *opaque, Error **errp) 2759 { 2760 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2761 } 2762 2763 static void spapr_set_vsmt(Object *obj, Visitor *v, const char *name, 2764 void *opaque, Error **errp) 2765 { 2766 visit_type_uint32(v, name, (uint32_t *)opaque, errp); 2767 } 2768 2769 static void spapr_machine_initfn(Object *obj) 2770 { 2771 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2772 2773 spapr->htab_fd = -1; 2774 spapr->use_hotplug_event_source = true; 2775 object_property_add_str(obj, "kvm-type", 2776 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2777 object_property_set_description(obj, "kvm-type", 2778 "Specifies the KVM virtualization mode (HV, PR)", 2779 NULL); 2780 object_property_add_bool(obj, "modern-hotplug-events", 2781 spapr_get_modern_hotplug_events, 2782 spapr_set_modern_hotplug_events, 2783 NULL); 2784 object_property_set_description(obj, "modern-hotplug-events", 2785 "Use dedicated hotplug event mechanism in" 2786 " place of standard EPOW events when possible" 2787 " (required for memory hot-unplug support)", 2788 NULL); 2789 2790 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 2791 "Maximum permitted CPU compatibility mode", 2792 &error_fatal); 2793 2794 object_property_add_str(obj, "resize-hpt", 2795 spapr_get_resize_hpt, spapr_set_resize_hpt, NULL); 2796 object_property_set_description(obj, "resize-hpt", 2797 "Resizing of the Hash Page Table (enabled, disabled, required)", 2798 NULL); 2799 object_property_add(obj, "vsmt", "uint32", spapr_get_vsmt, 2800 spapr_set_vsmt, NULL, &spapr->vsmt, &error_abort); 2801 object_property_set_description(obj, "vsmt", 2802 "Virtual SMT: KVM behaves as if this were" 2803 " the host's SMT mode", &error_abort); 2804 } 2805 2806 static void spapr_machine_finalizefn(Object *obj) 2807 { 2808 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2809 2810 g_free(spapr->kvm_type); 2811 } 2812 2813 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2814 { 2815 cpu_synchronize_state(cs); 2816 ppc_cpu_do_system_reset(cs); 2817 } 2818 2819 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2820 { 2821 CPUState *cs; 2822 2823 CPU_FOREACH(cs) { 2824 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2825 } 2826 } 2827 2828 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2829 uint32_t node, bool dedicated_hp_event_source, 2830 Error **errp) 2831 { 2832 sPAPRDRConnector *drc; 2833 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2834 int i, fdt_offset, fdt_size; 2835 void *fdt; 2836 uint64_t addr = addr_start; 2837 bool hotplugged = spapr_drc_hotplugged(dev); 2838 Error *local_err = NULL; 2839 2840 for (i = 0; i < nr_lmbs; i++) { 2841 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2842 addr / SPAPR_MEMORY_BLOCK_SIZE); 2843 g_assert(drc); 2844 2845 fdt = create_device_tree(&fdt_size); 2846 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2847 SPAPR_MEMORY_BLOCK_SIZE); 2848 2849 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 2850 if (local_err) { 2851 while (addr > addr_start) { 2852 addr -= SPAPR_MEMORY_BLOCK_SIZE; 2853 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2854 addr / SPAPR_MEMORY_BLOCK_SIZE); 2855 spapr_drc_detach(drc); 2856 } 2857 g_free(fdt); 2858 error_propagate(errp, local_err); 2859 return; 2860 } 2861 if (!hotplugged) { 2862 spapr_drc_reset(drc); 2863 } 2864 addr += SPAPR_MEMORY_BLOCK_SIZE; 2865 } 2866 /* send hotplug notification to the 2867 * guest only in case of hotplugged memory 2868 */ 2869 if (hotplugged) { 2870 if (dedicated_hp_event_source) { 2871 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 2872 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2873 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2874 nr_lmbs, 2875 spapr_drc_index(drc)); 2876 } else { 2877 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2878 nr_lmbs); 2879 } 2880 } 2881 } 2882 2883 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2884 uint32_t node, Error **errp) 2885 { 2886 Error *local_err = NULL; 2887 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2888 PCDIMMDevice *dimm = PC_DIMM(dev); 2889 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2890 MemoryRegion *mr; 2891 uint64_t align, size, addr; 2892 2893 mr = ddc->get_memory_region(dimm, &local_err); 2894 if (local_err) { 2895 goto out; 2896 } 2897 align = memory_region_get_alignment(mr); 2898 size = memory_region_size(mr); 2899 2900 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2901 if (local_err) { 2902 goto out; 2903 } 2904 2905 addr = object_property_get_uint(OBJECT(dimm), 2906 PC_DIMM_ADDR_PROP, &local_err); 2907 if (local_err) { 2908 goto out_unplug; 2909 } 2910 2911 spapr_add_lmbs(dev, addr, size, node, 2912 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2913 &local_err); 2914 if (local_err) { 2915 goto out_unplug; 2916 } 2917 2918 return; 2919 2920 out_unplug: 2921 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2922 out: 2923 error_propagate(errp, local_err); 2924 } 2925 2926 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2927 Error **errp) 2928 { 2929 PCDIMMDevice *dimm = PC_DIMM(dev); 2930 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2931 MemoryRegion *mr; 2932 uint64_t size; 2933 char *mem_dev; 2934 2935 mr = ddc->get_memory_region(dimm, errp); 2936 if (!mr) { 2937 return; 2938 } 2939 size = memory_region_size(mr); 2940 2941 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2942 error_setg(errp, "Hotplugged memory size must be a multiple of " 2943 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 2944 return; 2945 } 2946 2947 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2948 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2949 error_setg(errp, "Memory backend has bad page size. " 2950 "Use 'memory-backend-file' with correct mem-path."); 2951 goto out; 2952 } 2953 2954 out: 2955 g_free(mem_dev); 2956 } 2957 2958 struct sPAPRDIMMState { 2959 PCDIMMDevice *dimm; 2960 uint32_t nr_lmbs; 2961 QTAILQ_ENTRY(sPAPRDIMMState) next; 2962 }; 2963 2964 static sPAPRDIMMState *spapr_pending_dimm_unplugs_find(sPAPRMachineState *s, 2965 PCDIMMDevice *dimm) 2966 { 2967 sPAPRDIMMState *dimm_state = NULL; 2968 2969 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 2970 if (dimm_state->dimm == dimm) { 2971 break; 2972 } 2973 } 2974 return dimm_state; 2975 } 2976 2977 static sPAPRDIMMState *spapr_pending_dimm_unplugs_add(sPAPRMachineState *spapr, 2978 uint32_t nr_lmbs, 2979 PCDIMMDevice *dimm) 2980 { 2981 sPAPRDIMMState *ds = NULL; 2982 2983 /* 2984 * If this request is for a DIMM whose removal had failed earlier 2985 * (due to guest's refusal to remove the LMBs), we would have this 2986 * dimm already in the pending_dimm_unplugs list. In that 2987 * case don't add again. 2988 */ 2989 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 2990 if (!ds) { 2991 ds = g_malloc0(sizeof(sPAPRDIMMState)); 2992 ds->nr_lmbs = nr_lmbs; 2993 ds->dimm = dimm; 2994 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 2995 } 2996 return ds; 2997 } 2998 2999 static void spapr_pending_dimm_unplugs_remove(sPAPRMachineState *spapr, 3000 sPAPRDIMMState *dimm_state) 3001 { 3002 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3003 g_free(dimm_state); 3004 } 3005 3006 static sPAPRDIMMState *spapr_recover_pending_dimm_state(sPAPRMachineState *ms, 3007 PCDIMMDevice *dimm) 3008 { 3009 sPAPRDRConnector *drc; 3010 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3011 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3012 uint64_t size = memory_region_size(mr); 3013 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3014 uint32_t avail_lmbs = 0; 3015 uint64_t addr_start, addr; 3016 int i; 3017 3018 addr_start = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3019 &error_abort); 3020 3021 addr = addr_start; 3022 for (i = 0; i < nr_lmbs; i++) { 3023 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3024 addr / SPAPR_MEMORY_BLOCK_SIZE); 3025 g_assert(drc); 3026 if (drc->dev) { 3027 avail_lmbs++; 3028 } 3029 addr += SPAPR_MEMORY_BLOCK_SIZE; 3030 } 3031 3032 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3033 } 3034 3035 /* Callback to be called during DRC release. */ 3036 void spapr_lmb_release(DeviceState *dev) 3037 { 3038 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_hotplug_handler(dev)); 3039 PCDIMMDevice *dimm = PC_DIMM(dev); 3040 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3041 MemoryRegion *mr = ddc->get_memory_region(dimm, &error_abort); 3042 sPAPRDIMMState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3043 3044 /* This information will get lost if a migration occurs 3045 * during the unplug process. In this case recover it. */ 3046 if (ds == NULL) { 3047 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3048 g_assert(ds); 3049 /* The DRC being examined by the caller at least must be counted */ 3050 g_assert(ds->nr_lmbs); 3051 } 3052 3053 if (--ds->nr_lmbs) { 3054 return; 3055 } 3056 3057 spapr_pending_dimm_unplugs_remove(spapr, ds); 3058 3059 /* 3060 * Now that all the LMBs have been removed by the guest, call the 3061 * pc-dimm unplug handler to cleanup up the pc-dimm device. 3062 */ 3063 pc_dimm_memory_unplug(dev, &spapr->hotplug_memory, mr); 3064 object_unparent(OBJECT(dev)); 3065 } 3066 3067 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3068 DeviceState *dev, Error **errp) 3069 { 3070 sPAPRMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3071 Error *local_err = NULL; 3072 PCDIMMDevice *dimm = PC_DIMM(dev); 3073 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 3074 MemoryRegion *mr; 3075 uint32_t nr_lmbs; 3076 uint64_t size, addr_start, addr; 3077 int i; 3078 sPAPRDRConnector *drc; 3079 3080 mr = ddc->get_memory_region(dimm, &local_err); 3081 if (local_err) { 3082 goto out; 3083 } 3084 size = memory_region_size(mr); 3085 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3086 3087 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3088 &local_err); 3089 if (local_err) { 3090 goto out; 3091 } 3092 3093 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3094 3095 addr = addr_start; 3096 for (i = 0; i < nr_lmbs; i++) { 3097 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3098 addr / SPAPR_MEMORY_BLOCK_SIZE); 3099 g_assert(drc); 3100 3101 spapr_drc_detach(drc); 3102 addr += SPAPR_MEMORY_BLOCK_SIZE; 3103 } 3104 3105 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3106 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3107 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3108 nr_lmbs, spapr_drc_index(drc)); 3109 out: 3110 error_propagate(errp, local_err); 3111 } 3112 3113 static void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 3114 sPAPRMachineState *spapr) 3115 { 3116 PowerPCCPU *cpu = POWERPC_CPU(cs); 3117 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3118 int id = spapr_vcpu_id(cpu); 3119 void *fdt; 3120 int offset, fdt_size; 3121 char *nodename; 3122 3123 fdt = create_device_tree(&fdt_size); 3124 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3125 offset = fdt_add_subnode(fdt, 0, nodename); 3126 3127 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 3128 g_free(nodename); 3129 3130 *fdt_offset = offset; 3131 return fdt; 3132 } 3133 3134 /* Callback to be called during DRC release. */ 3135 void spapr_core_release(DeviceState *dev) 3136 { 3137 MachineState *ms = MACHINE(qdev_get_hotplug_handler(dev)); 3138 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3139 CPUCore *cc = CPU_CORE(dev); 3140 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3141 3142 if (smc->pre_2_10_has_unused_icps) { 3143 sPAPRCPUCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3144 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3145 const char *typename = object_class_get_name(scc->cpu_class); 3146 size_t size = object_type_get_instance_size(typename); 3147 int i; 3148 3149 for (i = 0; i < cc->nr_threads; i++) { 3150 CPUState *cs = CPU(sc->threads + i * size); 3151 3152 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3153 } 3154 } 3155 3156 assert(core_slot); 3157 core_slot->cpu = NULL; 3158 object_unparent(OBJECT(dev)); 3159 } 3160 3161 static 3162 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3163 Error **errp) 3164 { 3165 int index; 3166 sPAPRDRConnector *drc; 3167 CPUCore *cc = CPU_CORE(dev); 3168 int smt = kvmppc_smt_threads(); 3169 3170 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3171 error_setg(errp, "Unable to find CPU core with core-id: %d", 3172 cc->core_id); 3173 return; 3174 } 3175 if (index == 0) { 3176 error_setg(errp, "Boot CPU core may not be unplugged"); 3177 return; 3178 } 3179 3180 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3181 g_assert(drc); 3182 3183 spapr_drc_detach(drc); 3184 3185 spapr_hotplug_req_remove_by_index(drc); 3186 } 3187 3188 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3189 Error **errp) 3190 { 3191 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3192 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3193 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3194 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3195 CPUCore *cc = CPU_CORE(dev); 3196 CPUState *cs = CPU(core->threads); 3197 sPAPRDRConnector *drc; 3198 Error *local_err = NULL; 3199 int smt = kvmppc_smt_threads(); 3200 CPUArchId *core_slot; 3201 int index; 3202 bool hotplugged = spapr_drc_hotplugged(dev); 3203 3204 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3205 if (!core_slot) { 3206 error_setg(errp, "Unable to find CPU core with core-id: %d", 3207 cc->core_id); 3208 return; 3209 } 3210 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index * smt); 3211 3212 g_assert(drc || !mc->has_hotpluggable_cpus); 3213 3214 if (drc) { 3215 void *fdt; 3216 int fdt_offset; 3217 3218 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 3219 3220 spapr_drc_attach(drc, dev, fdt, fdt_offset, &local_err); 3221 if (local_err) { 3222 g_free(fdt); 3223 error_propagate(errp, local_err); 3224 return; 3225 } 3226 3227 if (hotplugged) { 3228 /* 3229 * Send hotplug notification interrupt to the guest only 3230 * in case of hotplugged CPUs. 3231 */ 3232 spapr_hotplug_req_add_by_index(drc); 3233 } else { 3234 spapr_drc_reset(drc); 3235 } 3236 } 3237 3238 core_slot->cpu = OBJECT(dev); 3239 3240 if (smc->pre_2_10_has_unused_icps) { 3241 sPAPRCPUCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(OBJECT(cc)); 3242 const char *typename = object_class_get_name(scc->cpu_class); 3243 size_t size = object_type_get_instance_size(typename); 3244 int i; 3245 3246 for (i = 0; i < cc->nr_threads; i++) { 3247 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 3248 void *obj = sc->threads + i * size; 3249 3250 cs = CPU(obj); 3251 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3252 } 3253 } 3254 } 3255 3256 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3257 Error **errp) 3258 { 3259 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3260 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3261 Error *local_err = NULL; 3262 CPUCore *cc = CPU_CORE(dev); 3263 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 3264 const char *type = object_get_typename(OBJECT(dev)); 3265 CPUArchId *core_slot; 3266 int index; 3267 3268 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3269 error_setg(&local_err, "CPU hotplug not supported for this machine"); 3270 goto out; 3271 } 3272 3273 if (strcmp(base_core_type, type)) { 3274 error_setg(&local_err, "CPU core type should be %s", base_core_type); 3275 goto out; 3276 } 3277 3278 if (cc->core_id % smp_threads) { 3279 error_setg(&local_err, "invalid core id %d", cc->core_id); 3280 goto out; 3281 } 3282 3283 /* 3284 * In general we should have homogeneous threads-per-core, but old 3285 * (pre hotplug support) machine types allow the last core to have 3286 * reduced threads as a compatibility hack for when we allowed 3287 * total vcpus not a multiple of threads-per-core. 3288 */ 3289 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 3290 error_setg(&local_err, "invalid nr-threads %d, must be %d", 3291 cc->nr_threads, smp_threads); 3292 goto out; 3293 } 3294 3295 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3296 if (!core_slot) { 3297 error_setg(&local_err, "core id %d out of range", cc->core_id); 3298 goto out; 3299 } 3300 3301 if (core_slot->cpu) { 3302 error_setg(&local_err, "core %d already populated", cc->core_id); 3303 goto out; 3304 } 3305 3306 numa_cpu_pre_plug(core_slot, dev, &local_err); 3307 3308 out: 3309 g_free(base_core_type); 3310 error_propagate(errp, local_err); 3311 } 3312 3313 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 3314 DeviceState *dev, Error **errp) 3315 { 3316 MachineState *ms = MACHINE(hotplug_dev); 3317 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3318 3319 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3320 int node; 3321 3322 if (!smc->dr_lmb_enabled) { 3323 error_setg(errp, "Memory hotplug not supported for this machine"); 3324 return; 3325 } 3326 node = object_property_get_uint(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 3327 if (*errp) { 3328 return; 3329 } 3330 if (node < 0 || node >= MAX_NODES) { 3331 error_setg(errp, "Invaild node %d", node); 3332 return; 3333 } 3334 3335 /* 3336 * Currently PowerPC kernel doesn't allow hot-adding memory to 3337 * memory-less node, but instead will silently add the memory 3338 * to the first node that has some memory. This causes two 3339 * unexpected behaviours for the user. 3340 * 3341 * - Memory gets hotplugged to a different node than what the user 3342 * specified. 3343 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 3344 * to memory-less node, a reboot will set things accordingly 3345 * and the previously hotplugged memory now ends in the right node. 3346 * This appears as if some memory moved from one node to another. 3347 * 3348 * So until kernel starts supporting memory hotplug to memory-less 3349 * nodes, just prevent such attempts upfront in QEMU. 3350 */ 3351 if (nb_numa_nodes && !numa_info[node].node_mem) { 3352 error_setg(errp, "Can't hotplug memory to memory-less node %d", 3353 node); 3354 return; 3355 } 3356 3357 spapr_memory_plug(hotplug_dev, dev, node, errp); 3358 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3359 spapr_core_plug(hotplug_dev, dev, errp); 3360 } 3361 } 3362 3363 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 3364 DeviceState *dev, Error **errp) 3365 { 3366 sPAPRMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3367 MachineClass *mc = MACHINE_GET_CLASS(sms); 3368 3369 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3370 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 3371 spapr_memory_unplug_request(hotplug_dev, dev, errp); 3372 } else { 3373 /* NOTE: this means there is a window after guest reset, prior to 3374 * CAS negotiation, where unplug requests will fail due to the 3375 * capability not being detected yet. This is a bit different than 3376 * the case with PCI unplug, where the events will be queued and 3377 * eventually handled by the guest after boot 3378 */ 3379 error_setg(errp, "Memory hot unplug not supported for this guest"); 3380 } 3381 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3382 if (!mc->has_hotpluggable_cpus) { 3383 error_setg(errp, "CPU hot unplug not supported on this machine"); 3384 return; 3385 } 3386 spapr_core_unplug_request(hotplug_dev, dev, errp); 3387 } 3388 } 3389 3390 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 3391 DeviceState *dev, Error **errp) 3392 { 3393 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 3394 spapr_memory_pre_plug(hotplug_dev, dev, errp); 3395 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3396 spapr_core_pre_plug(hotplug_dev, dev, errp); 3397 } 3398 } 3399 3400 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 3401 DeviceState *dev) 3402 { 3403 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3404 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3405 return HOTPLUG_HANDLER(machine); 3406 } 3407 return NULL; 3408 } 3409 3410 static CpuInstanceProperties 3411 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3412 { 3413 CPUArchId *core_slot; 3414 MachineClass *mc = MACHINE_GET_CLASS(machine); 3415 3416 /* make sure possible_cpu are intialized */ 3417 mc->possible_cpu_arch_ids(machine); 3418 /* get CPU core slot containing thread that matches cpu_index */ 3419 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3420 assert(core_slot); 3421 return core_slot->props; 3422 } 3423 3424 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 3425 { 3426 return idx / smp_cores % nb_numa_nodes; 3427 } 3428 3429 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3430 { 3431 int i; 3432 int spapr_max_cores = max_cpus / smp_threads; 3433 MachineClass *mc = MACHINE_GET_CLASS(machine); 3434 3435 if (!mc->has_hotpluggable_cpus) { 3436 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3437 } 3438 if (machine->possible_cpus) { 3439 assert(machine->possible_cpus->len == spapr_max_cores); 3440 return machine->possible_cpus; 3441 } 3442 3443 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3444 sizeof(CPUArchId) * spapr_max_cores); 3445 machine->possible_cpus->len = spapr_max_cores; 3446 for (i = 0; i < machine->possible_cpus->len; i++) { 3447 int core_id = i * smp_threads; 3448 3449 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3450 machine->possible_cpus->cpus[i].arch_id = core_id; 3451 machine->possible_cpus->cpus[i].props.has_core_id = true; 3452 machine->possible_cpus->cpus[i].props.core_id = core_id; 3453 } 3454 return machine->possible_cpus; 3455 } 3456 3457 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3458 uint64_t *buid, hwaddr *pio, 3459 hwaddr *mmio32, hwaddr *mmio64, 3460 unsigned n_dma, uint32_t *liobns, Error **errp) 3461 { 3462 /* 3463 * New-style PHB window placement. 3464 * 3465 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3466 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3467 * windows. 3468 * 3469 * Some guest kernels can't work with MMIO windows above 1<<46 3470 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3471 * 3472 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3473 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3474 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3475 * 1TiB 64-bit MMIO windows for each PHB. 3476 */ 3477 const uint64_t base_buid = 0x800000020000000ULL; 3478 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3479 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3480 int i; 3481 3482 /* Sanity check natural alignments */ 3483 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3484 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3485 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3486 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3487 /* Sanity check bounds */ 3488 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3489 SPAPR_PCI_MEM32_WIN_SIZE); 3490 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3491 SPAPR_PCI_MEM64_WIN_SIZE); 3492 3493 if (index >= SPAPR_MAX_PHBS) { 3494 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3495 SPAPR_MAX_PHBS - 1); 3496 return; 3497 } 3498 3499 *buid = base_buid + index; 3500 for (i = 0; i < n_dma; ++i) { 3501 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3502 } 3503 3504 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3505 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3506 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3507 } 3508 3509 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3510 { 3511 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3512 3513 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3514 } 3515 3516 static void spapr_ics_resend(XICSFabric *dev) 3517 { 3518 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3519 3520 ics_resend(spapr->ics); 3521 } 3522 3523 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 3524 { 3525 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 3526 3527 return cpu ? ICP(cpu->intc) : NULL; 3528 } 3529 3530 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3531 Monitor *mon) 3532 { 3533 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3534 CPUState *cs; 3535 3536 CPU_FOREACH(cs) { 3537 PowerPCCPU *cpu = POWERPC_CPU(cs); 3538 3539 icp_pic_print_info(ICP(cpu->intc), mon); 3540 } 3541 3542 ics_pic_print_info(spapr->ics, mon); 3543 } 3544 3545 int spapr_vcpu_id(PowerPCCPU *cpu) 3546 { 3547 CPUState *cs = CPU(cpu); 3548 3549 if (kvm_enabled()) { 3550 return kvm_arch_vcpu_id(cs); 3551 } else { 3552 return cs->cpu_index; 3553 } 3554 } 3555 3556 PowerPCCPU *spapr_find_cpu(int vcpu_id) 3557 { 3558 CPUState *cs; 3559 3560 CPU_FOREACH(cs) { 3561 PowerPCCPU *cpu = POWERPC_CPU(cs); 3562 3563 if (spapr_vcpu_id(cpu) == vcpu_id) { 3564 return cpu; 3565 } 3566 } 3567 3568 return NULL; 3569 } 3570 3571 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3572 { 3573 MachineClass *mc = MACHINE_CLASS(oc); 3574 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3575 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3576 NMIClass *nc = NMI_CLASS(oc); 3577 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3578 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3579 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3580 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3581 3582 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3583 3584 /* 3585 * We set up the default / latest behaviour here. The class_init 3586 * functions for the specific versioned machine types can override 3587 * these details for backwards compatibility 3588 */ 3589 mc->init = ppc_spapr_init; 3590 mc->reset = ppc_spapr_reset; 3591 mc->block_default_type = IF_SCSI; 3592 mc->max_cpus = 1024; 3593 mc->no_parallel = 1; 3594 mc->default_boot_order = ""; 3595 mc->default_ram_size = 512 * M_BYTE; 3596 mc->kvm_type = spapr_kvm_type; 3597 mc->has_dynamic_sysbus = true; 3598 mc->pci_allow_0_address = true; 3599 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3600 hc->pre_plug = spapr_machine_device_pre_plug; 3601 hc->plug = spapr_machine_device_plug; 3602 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3603 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 3604 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3605 hc->unplug_request = spapr_machine_device_unplug_request; 3606 3607 smc->dr_lmb_enabled = true; 3608 smc->tcg_default_cpu = "POWER8"; 3609 mc->has_hotpluggable_cpus = true; 3610 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 3611 fwc->get_dev_path = spapr_get_fw_dev_path; 3612 nc->nmi_monitor_handler = spapr_nmi; 3613 smc->phb_placement = spapr_phb_placement; 3614 vhc->hypercall = emulate_spapr_hypercall; 3615 vhc->hpt_mask = spapr_hpt_mask; 3616 vhc->map_hptes = spapr_map_hptes; 3617 vhc->unmap_hptes = spapr_unmap_hptes; 3618 vhc->store_hpte = spapr_store_hpte; 3619 vhc->get_patbe = spapr_get_patbe; 3620 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 3621 xic->ics_get = spapr_ics_get; 3622 xic->ics_resend = spapr_ics_resend; 3623 xic->icp_get = spapr_icp_get; 3624 ispc->print_info = spapr_pic_print_info; 3625 /* Force NUMA node memory size to be a multiple of 3626 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3627 * in which LMBs are represented and hot-added 3628 */ 3629 mc->numa_mem_align_shift = 28; 3630 } 3631 3632 static const TypeInfo spapr_machine_info = { 3633 .name = TYPE_SPAPR_MACHINE, 3634 .parent = TYPE_MACHINE, 3635 .abstract = true, 3636 .instance_size = sizeof(sPAPRMachineState), 3637 .instance_init = spapr_machine_initfn, 3638 .instance_finalize = spapr_machine_finalizefn, 3639 .class_size = sizeof(sPAPRMachineClass), 3640 .class_init = spapr_machine_class_init, 3641 .interfaces = (InterfaceInfo[]) { 3642 { TYPE_FW_PATH_PROVIDER }, 3643 { TYPE_NMI }, 3644 { TYPE_HOTPLUG_HANDLER }, 3645 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3646 { TYPE_XICS_FABRIC }, 3647 { TYPE_INTERRUPT_STATS_PROVIDER }, 3648 { } 3649 }, 3650 }; 3651 3652 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3653 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3654 void *data) \ 3655 { \ 3656 MachineClass *mc = MACHINE_CLASS(oc); \ 3657 spapr_machine_##suffix##_class_options(mc); \ 3658 if (latest) { \ 3659 mc->alias = "pseries"; \ 3660 mc->is_default = 1; \ 3661 } \ 3662 } \ 3663 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3664 { \ 3665 MachineState *machine = MACHINE(obj); \ 3666 spapr_machine_##suffix##_instance_options(machine); \ 3667 } \ 3668 static const TypeInfo spapr_machine_##suffix##_info = { \ 3669 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3670 .parent = TYPE_SPAPR_MACHINE, \ 3671 .class_init = spapr_machine_##suffix##_class_init, \ 3672 .instance_init = spapr_machine_##suffix##_instance_init, \ 3673 }; \ 3674 static void spapr_machine_register_##suffix(void) \ 3675 { \ 3676 type_register(&spapr_machine_##suffix##_info); \ 3677 } \ 3678 type_init(spapr_machine_register_##suffix) 3679 3680 /* 3681 * pseries-2.11 3682 */ 3683 static void spapr_machine_2_11_instance_options(MachineState *machine) 3684 { 3685 } 3686 3687 static void spapr_machine_2_11_class_options(MachineClass *mc) 3688 { 3689 /* Defaults for the latest behaviour inherited from the base class */ 3690 } 3691 3692 DEFINE_SPAPR_MACHINE(2_11, "2.11", true); 3693 3694 /* 3695 * pseries-2.10 3696 */ 3697 #define SPAPR_COMPAT_2_10 \ 3698 HW_COMPAT_2_10 \ 3699 3700 static void spapr_machine_2_10_instance_options(MachineState *machine) 3701 { 3702 } 3703 3704 static void spapr_machine_2_10_class_options(MachineClass *mc) 3705 { 3706 spapr_machine_2_11_class_options(mc); 3707 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_10); 3708 } 3709 3710 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 3711 3712 /* 3713 * pseries-2.9 3714 */ 3715 #define SPAPR_COMPAT_2_9 \ 3716 HW_COMPAT_2_9 \ 3717 { \ 3718 .driver = TYPE_POWERPC_CPU, \ 3719 .property = "pre-2.10-migration", \ 3720 .value = "on", \ 3721 }, \ 3722 3723 static void spapr_machine_2_9_instance_options(MachineState *machine) 3724 { 3725 spapr_machine_2_10_instance_options(machine); 3726 } 3727 3728 static void spapr_machine_2_9_class_options(MachineClass *mc) 3729 { 3730 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3731 3732 spapr_machine_2_10_class_options(mc); 3733 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3734 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3735 smc->pre_2_10_has_unused_icps = true; 3736 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 3737 } 3738 3739 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3740 3741 /* 3742 * pseries-2.8 3743 */ 3744 #define SPAPR_COMPAT_2_8 \ 3745 HW_COMPAT_2_8 \ 3746 { \ 3747 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3748 .property = "pcie-extended-configuration-space", \ 3749 .value = "off", \ 3750 }, 3751 3752 static void spapr_machine_2_8_instance_options(MachineState *machine) 3753 { 3754 spapr_machine_2_9_instance_options(machine); 3755 } 3756 3757 static void spapr_machine_2_8_class_options(MachineClass *mc) 3758 { 3759 spapr_machine_2_9_class_options(mc); 3760 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3761 mc->numa_mem_align_shift = 23; 3762 } 3763 3764 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3765 3766 /* 3767 * pseries-2.7 3768 */ 3769 #define SPAPR_COMPAT_2_7 \ 3770 HW_COMPAT_2_7 \ 3771 { \ 3772 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3773 .property = "mem_win_size", \ 3774 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3775 }, \ 3776 { \ 3777 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3778 .property = "mem64_win_size", \ 3779 .value = "0", \ 3780 }, \ 3781 { \ 3782 .driver = TYPE_POWERPC_CPU, \ 3783 .property = "pre-2.8-migration", \ 3784 .value = "on", \ 3785 }, \ 3786 { \ 3787 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3788 .property = "pre-2.8-migration", \ 3789 .value = "on", \ 3790 }, 3791 3792 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3793 uint64_t *buid, hwaddr *pio, 3794 hwaddr *mmio32, hwaddr *mmio64, 3795 unsigned n_dma, uint32_t *liobns, Error **errp) 3796 { 3797 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3798 const uint64_t base_buid = 0x800000020000000ULL; 3799 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3800 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3801 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3802 const uint32_t max_index = 255; 3803 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3804 3805 uint64_t ram_top = MACHINE(spapr)->ram_size; 3806 hwaddr phb0_base, phb_base; 3807 int i; 3808 3809 /* Do we have hotpluggable memory? */ 3810 if (MACHINE(spapr)->maxram_size > ram_top) { 3811 /* Can't just use maxram_size, because there may be an 3812 * alignment gap between normal and hotpluggable memory 3813 * regions */ 3814 ram_top = spapr->hotplug_memory.base + 3815 memory_region_size(&spapr->hotplug_memory.mr); 3816 } 3817 3818 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3819 3820 if (index > max_index) { 3821 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3822 max_index); 3823 return; 3824 } 3825 3826 *buid = base_buid + index; 3827 for (i = 0; i < n_dma; ++i) { 3828 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3829 } 3830 3831 phb_base = phb0_base + index * phb_spacing; 3832 *pio = phb_base + pio_offset; 3833 *mmio32 = phb_base + mmio_offset; 3834 /* 3835 * We don't set the 64-bit MMIO window, relying on the PHB's 3836 * fallback behaviour of automatically splitting a large "32-bit" 3837 * window into contiguous 32-bit and 64-bit windows 3838 */ 3839 } 3840 3841 static void spapr_machine_2_7_instance_options(MachineState *machine) 3842 { 3843 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3844 3845 spapr_machine_2_8_instance_options(machine); 3846 spapr->use_hotplug_event_source = false; 3847 } 3848 3849 static void spapr_machine_2_7_class_options(MachineClass *mc) 3850 { 3851 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3852 3853 spapr_machine_2_8_class_options(mc); 3854 smc->tcg_default_cpu = "POWER7"; 3855 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3856 smc->phb_placement = phb_placement_2_7; 3857 } 3858 3859 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3860 3861 /* 3862 * pseries-2.6 3863 */ 3864 #define SPAPR_COMPAT_2_6 \ 3865 HW_COMPAT_2_6 \ 3866 { \ 3867 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3868 .property = "ddw",\ 3869 .value = stringify(off),\ 3870 }, 3871 3872 static void spapr_machine_2_6_instance_options(MachineState *machine) 3873 { 3874 spapr_machine_2_7_instance_options(machine); 3875 } 3876 3877 static void spapr_machine_2_6_class_options(MachineClass *mc) 3878 { 3879 spapr_machine_2_7_class_options(mc); 3880 mc->has_hotpluggable_cpus = false; 3881 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3882 } 3883 3884 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3885 3886 /* 3887 * pseries-2.5 3888 */ 3889 #define SPAPR_COMPAT_2_5 \ 3890 HW_COMPAT_2_5 \ 3891 { \ 3892 .driver = "spapr-vlan", \ 3893 .property = "use-rx-buffer-pools", \ 3894 .value = "off", \ 3895 }, 3896 3897 static void spapr_machine_2_5_instance_options(MachineState *machine) 3898 { 3899 spapr_machine_2_6_instance_options(machine); 3900 } 3901 3902 static void spapr_machine_2_5_class_options(MachineClass *mc) 3903 { 3904 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3905 3906 spapr_machine_2_6_class_options(mc); 3907 smc->use_ohci_by_default = true; 3908 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3909 } 3910 3911 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3912 3913 /* 3914 * pseries-2.4 3915 */ 3916 #define SPAPR_COMPAT_2_4 \ 3917 HW_COMPAT_2_4 3918 3919 static void spapr_machine_2_4_instance_options(MachineState *machine) 3920 { 3921 spapr_machine_2_5_instance_options(machine); 3922 } 3923 3924 static void spapr_machine_2_4_class_options(MachineClass *mc) 3925 { 3926 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3927 3928 spapr_machine_2_5_class_options(mc); 3929 smc->dr_lmb_enabled = false; 3930 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3931 } 3932 3933 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3934 3935 /* 3936 * pseries-2.3 3937 */ 3938 #define SPAPR_COMPAT_2_3 \ 3939 HW_COMPAT_2_3 \ 3940 {\ 3941 .driver = "spapr-pci-host-bridge",\ 3942 .property = "dynamic-reconfiguration",\ 3943 .value = "off",\ 3944 }, 3945 3946 static void spapr_machine_2_3_instance_options(MachineState *machine) 3947 { 3948 spapr_machine_2_4_instance_options(machine); 3949 } 3950 3951 static void spapr_machine_2_3_class_options(MachineClass *mc) 3952 { 3953 spapr_machine_2_4_class_options(mc); 3954 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3955 } 3956 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3957 3958 /* 3959 * pseries-2.2 3960 */ 3961 3962 #define SPAPR_COMPAT_2_2 \ 3963 HW_COMPAT_2_2 \ 3964 {\ 3965 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3966 .property = "mem_win_size",\ 3967 .value = "0x20000000",\ 3968 }, 3969 3970 static void spapr_machine_2_2_instance_options(MachineState *machine) 3971 { 3972 spapr_machine_2_3_instance_options(machine); 3973 machine->suppress_vmdesc = true; 3974 } 3975 3976 static void spapr_machine_2_2_class_options(MachineClass *mc) 3977 { 3978 spapr_machine_2_3_class_options(mc); 3979 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3980 } 3981 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3982 3983 /* 3984 * pseries-2.1 3985 */ 3986 #define SPAPR_COMPAT_2_1 \ 3987 HW_COMPAT_2_1 3988 3989 static void spapr_machine_2_1_instance_options(MachineState *machine) 3990 { 3991 spapr_machine_2_2_instance_options(machine); 3992 } 3993 3994 static void spapr_machine_2_1_class_options(MachineClass *mc) 3995 { 3996 spapr_machine_2_2_class_options(mc); 3997 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3998 } 3999 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 4000 4001 static void spapr_machine_register_types(void) 4002 { 4003 type_register_static(&spapr_machine_info); 4004 } 4005 4006 type_init(spapr_machine_register_types) 4007