1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "mmu-book3s-v3.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/fdt.h" 51 #include "hw/ppc/spapr.h" 52 #include "hw/ppc/spapr_vio.h" 53 #include "hw/pci-host/spapr.h" 54 #include "hw/ppc/xics.h" 55 #include "hw/pci/msi.h" 56 57 #include "hw/pci/pci.h" 58 #include "hw/scsi/scsi.h" 59 #include "hw/virtio/virtio-scsi.h" 60 61 #include "exec/address-spaces.h" 62 #include "hw/usb.h" 63 #include "qemu/config-file.h" 64 #include "qemu/error-report.h" 65 #include "trace.h" 66 #include "hw/nmi.h" 67 #include "hw/intc/intc.h" 68 69 #include "hw/compat.h" 70 #include "qemu/cutils.h" 71 #include "hw/ppc/spapr_cpu_core.h" 72 #include "qmp-commands.h" 73 74 #include <libfdt.h> 75 76 /* SLOF memory layout: 77 * 78 * SLOF raw image loaded at 0, copies its romfs right below the flat 79 * device-tree, then position SLOF itself 31M below that 80 * 81 * So we set FW_OVERHEAD to 40MB which should account for all of that 82 * and more 83 * 84 * We load our kernel at 4M, leaving space for SLOF initial image 85 */ 86 #define FDT_MAX_SIZE 0x100000 87 #define RTAS_MAX_SIZE 0x10000 88 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 89 #define FW_MAX_SIZE 0x400000 90 #define FW_FILE_NAME "slof.bin" 91 #define FW_OVERHEAD 0x2800000 92 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 93 94 #define MIN_RMA_SLOF 128UL 95 96 #define PHANDLE_XICP 0x00001111 97 98 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 99 100 static ICSState *spapr_ics_create(sPAPRMachineState *spapr, 101 const char *type_ics, 102 int nr_irqs, Error **errp) 103 { 104 Error *err = NULL, *local_err = NULL; 105 Object *obj; 106 107 obj = object_new(type_ics); 108 object_property_add_child(OBJECT(spapr), "ics", obj, NULL); 109 object_property_add_const_link(obj, "xics", OBJECT(spapr), &error_abort); 110 object_property_set_int(obj, nr_irqs, "nr-irqs", &err); 111 object_property_set_bool(obj, true, "realized", &local_err); 112 error_propagate(&err, local_err); 113 if (err) { 114 error_propagate(errp, err); 115 return NULL; 116 } 117 118 return ICS_SIMPLE(obj); 119 } 120 121 static void xics_system_init(MachineState *machine, int nr_irqs, Error **errp) 122 { 123 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 124 125 if (kvm_enabled()) { 126 Error *err = NULL; 127 128 if (machine_kernel_irqchip_allowed(machine) && 129 !xics_kvm_init(spapr, errp)) { 130 spapr->icp_type = TYPE_KVM_ICP; 131 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_KVM, nr_irqs, &err); 132 } 133 if (machine_kernel_irqchip_required(machine) && !spapr->ics) { 134 error_reportf_err(err, 135 "kernel_irqchip requested but unavailable: "); 136 } else { 137 error_free(err); 138 } 139 } 140 141 if (!spapr->ics) { 142 xics_spapr_init(spapr, errp); 143 spapr->icp_type = TYPE_ICP; 144 spapr->ics = spapr_ics_create(spapr, TYPE_ICS_SIMPLE, nr_irqs, errp); 145 } 146 } 147 148 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 149 int smt_threads) 150 { 151 int i, ret = 0; 152 uint32_t servers_prop[smt_threads]; 153 uint32_t gservers_prop[smt_threads * 2]; 154 int index = ppc_get_vcpu_dt_id(cpu); 155 156 if (cpu->compat_pvr) { 157 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 158 if (ret < 0) { 159 return ret; 160 } 161 } 162 163 /* Build interrupt servers and gservers properties */ 164 for (i = 0; i < smt_threads; i++) { 165 servers_prop[i] = cpu_to_be32(index + i); 166 /* Hack, direct the group queues back to cpu 0 */ 167 gservers_prop[i*2] = cpu_to_be32(index + i); 168 gservers_prop[i*2 + 1] = 0; 169 } 170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 171 servers_prop, sizeof(servers_prop)); 172 if (ret < 0) { 173 return ret; 174 } 175 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 176 gservers_prop, sizeof(gservers_prop)); 177 178 return ret; 179 } 180 181 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 182 { 183 int ret = 0; 184 PowerPCCPU *cpu = POWERPC_CPU(cs); 185 int index = ppc_get_vcpu_dt_id(cpu); 186 uint32_t associativity[] = {cpu_to_be32(0x5), 187 cpu_to_be32(0x0), 188 cpu_to_be32(0x0), 189 cpu_to_be32(0x0), 190 cpu_to_be32(cs->numa_node), 191 cpu_to_be32(index)}; 192 193 /* Advertise NUMA via ibm,associativity */ 194 if (nb_numa_nodes > 1) { 195 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 196 sizeof(associativity)); 197 } 198 199 return ret; 200 } 201 202 /* Populate the "ibm,pa-features" property */ 203 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset, 204 bool legacy_guest) 205 { 206 uint8_t pa_features_206[] = { 6, 0, 207 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 208 uint8_t pa_features_207[] = { 24, 0, 209 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 210 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 211 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 212 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 213 uint8_t pa_features_300[] = { 66, 0, 214 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 215 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 216 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 217 /* 6: DS207 */ 218 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 219 /* 16: Vector */ 220 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 221 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 222 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 223 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 224 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 225 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 226 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 227 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 228 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 229 /* 42: PM, 44: PC RA, 46: SC vec'd */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 231 /* 48: SIMD, 50: QP BFP, 52: String */ 232 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 233 /* 54: DecFP, 56: DecI, 58: SHA */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 235 /* 60: NM atomic, 62: RNG */ 236 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 237 }; 238 uint8_t *pa_features; 239 size_t pa_size; 240 241 switch (POWERPC_MMU_VER(env->mmu_model)) { 242 case POWERPC_MMU_VER_2_06: 243 pa_features = pa_features_206; 244 pa_size = sizeof(pa_features_206); 245 break; 246 case POWERPC_MMU_VER_2_07: 247 pa_features = pa_features_207; 248 pa_size = sizeof(pa_features_207); 249 break; 250 case POWERPC_MMU_VER_3_00: 251 pa_features = pa_features_300; 252 pa_size = sizeof(pa_features_300); 253 break; 254 default: 255 return; 256 } 257 258 if (env->ci_large_pages) { 259 /* 260 * Note: we keep CI large pages off by default because a 64K capable 261 * guest provisioned with large pages might otherwise try to map a qemu 262 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 263 * even if that qemu runs on a 4k host. 264 * We dd this bit back here if we are confident this is not an issue 265 */ 266 pa_features[3] |= 0x20; 267 } 268 if (kvmppc_has_cap_htm() && pa_size > 24) { 269 pa_features[24] |= 0x80; /* Transactional memory support */ 270 } 271 if (legacy_guest && pa_size > 40) { 272 /* Workaround for broken kernels that attempt (guest) radix 273 * mode when they can't handle it, if they see the radix bit set 274 * in pa-features. So hide it from them. */ 275 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 276 } 277 278 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 279 } 280 281 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 282 { 283 int ret = 0, offset, cpus_offset; 284 CPUState *cs; 285 char cpu_model[32]; 286 int smt = kvmppc_smt_threads(); 287 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 288 289 CPU_FOREACH(cs) { 290 PowerPCCPU *cpu = POWERPC_CPU(cs); 291 CPUPPCState *env = &cpu->env; 292 DeviceClass *dc = DEVICE_GET_CLASS(cs); 293 int index = ppc_get_vcpu_dt_id(cpu); 294 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 295 296 if ((index % smt) != 0) { 297 continue; 298 } 299 300 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 301 302 cpus_offset = fdt_path_offset(fdt, "/cpus"); 303 if (cpus_offset < 0) { 304 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 305 "cpus"); 306 if (cpus_offset < 0) { 307 return cpus_offset; 308 } 309 } 310 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 311 if (offset < 0) { 312 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 313 if (offset < 0) { 314 return offset; 315 } 316 } 317 318 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 319 pft_size_prop, sizeof(pft_size_prop)); 320 if (ret < 0) { 321 return ret; 322 } 323 324 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 325 if (ret < 0) { 326 return ret; 327 } 328 329 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 330 if (ret < 0) { 331 return ret; 332 } 333 334 spapr_populate_pa_features(env, fdt, offset, 335 spapr->cas_legacy_guest_workaround); 336 } 337 return ret; 338 } 339 340 static hwaddr spapr_node0_size(void) 341 { 342 MachineState *machine = MACHINE(qdev_get_machine()); 343 344 if (nb_numa_nodes) { 345 int i; 346 for (i = 0; i < nb_numa_nodes; ++i) { 347 if (numa_info[i].node_mem) { 348 return MIN(pow2floor(numa_info[i].node_mem), 349 machine->ram_size); 350 } 351 } 352 } 353 return machine->ram_size; 354 } 355 356 static void add_str(GString *s, const gchar *s1) 357 { 358 g_string_append_len(s, s1, strlen(s1) + 1); 359 } 360 361 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 362 hwaddr size) 363 { 364 uint32_t associativity[] = { 365 cpu_to_be32(0x4), /* length */ 366 cpu_to_be32(0x0), cpu_to_be32(0x0), 367 cpu_to_be32(0x0), cpu_to_be32(nodeid) 368 }; 369 char mem_name[32]; 370 uint64_t mem_reg_property[2]; 371 int off; 372 373 mem_reg_property[0] = cpu_to_be64(start); 374 mem_reg_property[1] = cpu_to_be64(size); 375 376 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 377 off = fdt_add_subnode(fdt, 0, mem_name); 378 _FDT(off); 379 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 380 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 381 sizeof(mem_reg_property)))); 382 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 383 sizeof(associativity)))); 384 return off; 385 } 386 387 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 388 { 389 MachineState *machine = MACHINE(spapr); 390 hwaddr mem_start, node_size; 391 int i, nb_nodes = nb_numa_nodes; 392 NodeInfo *nodes = numa_info; 393 NodeInfo ramnode; 394 395 /* No NUMA nodes, assume there is just one node with whole RAM */ 396 if (!nb_numa_nodes) { 397 nb_nodes = 1; 398 ramnode.node_mem = machine->ram_size; 399 nodes = &ramnode; 400 } 401 402 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 403 if (!nodes[i].node_mem) { 404 continue; 405 } 406 if (mem_start >= machine->ram_size) { 407 node_size = 0; 408 } else { 409 node_size = nodes[i].node_mem; 410 if (node_size > machine->ram_size - mem_start) { 411 node_size = machine->ram_size - mem_start; 412 } 413 } 414 if (!mem_start) { 415 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 416 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 417 mem_start += spapr->rma_size; 418 node_size -= spapr->rma_size; 419 } 420 for ( ; node_size; ) { 421 hwaddr sizetmp = pow2floor(node_size); 422 423 /* mem_start != 0 here */ 424 if (ctzl(mem_start) < ctzl(sizetmp)) { 425 sizetmp = 1ULL << ctzl(mem_start); 426 } 427 428 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 429 node_size -= sizetmp; 430 mem_start += sizetmp; 431 } 432 } 433 434 return 0; 435 } 436 437 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 438 sPAPRMachineState *spapr) 439 { 440 PowerPCCPU *cpu = POWERPC_CPU(cs); 441 CPUPPCState *env = &cpu->env; 442 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 443 int index = ppc_get_vcpu_dt_id(cpu); 444 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 445 0xffffffff, 0xffffffff}; 446 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 447 : SPAPR_TIMEBASE_FREQ; 448 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 449 uint32_t page_sizes_prop[64]; 450 size_t page_sizes_prop_size; 451 uint32_t vcpus_per_socket = smp_threads * smp_cores; 452 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 453 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 454 sPAPRDRConnector *drc; 455 sPAPRDRConnectorClass *drck; 456 int drc_index; 457 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 458 int i; 459 460 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 461 if (drc) { 462 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 463 drc_index = drck->get_index(drc); 464 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 465 } 466 467 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 468 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 469 470 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 471 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 472 env->dcache_line_size))); 473 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 474 env->dcache_line_size))); 475 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 476 env->icache_line_size))); 477 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 478 env->icache_line_size))); 479 480 if (pcc->l1_dcache_size) { 481 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 482 pcc->l1_dcache_size))); 483 } else { 484 error_report("Warning: Unknown L1 dcache size for cpu"); 485 } 486 if (pcc->l1_icache_size) { 487 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 488 pcc->l1_icache_size))); 489 } else { 490 error_report("Warning: Unknown L1 icache size for cpu"); 491 } 492 493 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 494 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 495 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 496 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 497 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 498 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 499 500 if (env->spr_cb[SPR_PURR].oea_read) { 501 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 502 } 503 504 if (env->mmu_model & POWERPC_MMU_1TSEG) { 505 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 506 segs, sizeof(segs)))); 507 } 508 509 /* Advertise VMX/VSX (vector extensions) if available 510 * 0 / no property == no vector extensions 511 * 1 == VMX / Altivec available 512 * 2 == VSX available */ 513 if (env->insns_flags & PPC_ALTIVEC) { 514 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 515 516 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 517 } 518 519 /* Advertise DFP (Decimal Floating Point) if available 520 * 0 / no property == no DFP 521 * 1 == DFP available */ 522 if (env->insns_flags2 & PPC2_DFP) { 523 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 524 } 525 526 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 527 sizeof(page_sizes_prop)); 528 if (page_sizes_prop_size) { 529 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 530 page_sizes_prop, page_sizes_prop_size))); 531 } 532 533 spapr_populate_pa_features(env, fdt, offset, false); 534 535 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 536 cs->cpu_index / vcpus_per_socket))); 537 538 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 539 pft_size_prop, sizeof(pft_size_prop)))); 540 541 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 542 543 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 544 545 if (pcc->radix_page_info) { 546 for (i = 0; i < pcc->radix_page_info->count; i++) { 547 radix_AP_encodings[i] = 548 cpu_to_be32(pcc->radix_page_info->entries[i]); 549 } 550 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 551 radix_AP_encodings, 552 pcc->radix_page_info->count * 553 sizeof(radix_AP_encodings[0])))); 554 } 555 } 556 557 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 558 { 559 CPUState *cs; 560 int cpus_offset; 561 char *nodename; 562 int smt = kvmppc_smt_threads(); 563 564 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 565 _FDT(cpus_offset); 566 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 567 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 568 569 /* 570 * We walk the CPUs in reverse order to ensure that CPU DT nodes 571 * created by fdt_add_subnode() end up in the right order in FDT 572 * for the guest kernel the enumerate the CPUs correctly. 573 */ 574 CPU_FOREACH_REVERSE(cs) { 575 PowerPCCPU *cpu = POWERPC_CPU(cs); 576 int index = ppc_get_vcpu_dt_id(cpu); 577 DeviceClass *dc = DEVICE_GET_CLASS(cs); 578 int offset; 579 580 if ((index % smt) != 0) { 581 continue; 582 } 583 584 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 585 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 586 g_free(nodename); 587 _FDT(offset); 588 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 589 } 590 591 } 592 593 /* 594 * Adds ibm,dynamic-reconfiguration-memory node. 595 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 596 * of this device tree node. 597 */ 598 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 599 { 600 MachineState *machine = MACHINE(spapr); 601 int ret, i, offset; 602 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 603 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 604 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 605 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 606 memory_region_size(&spapr->hotplug_memory.mr)) / 607 lmb_size; 608 uint32_t *int_buf, *cur_index, buf_len; 609 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 610 611 /* 612 * Don't create the node if there is no hotpluggable memory 613 */ 614 if (machine->ram_size == machine->maxram_size) { 615 return 0; 616 } 617 618 /* 619 * Allocate enough buffer size to fit in ibm,dynamic-memory 620 * or ibm,associativity-lookup-arrays 621 */ 622 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 623 * sizeof(uint32_t); 624 cur_index = int_buf = g_malloc0(buf_len); 625 626 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 627 628 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 629 sizeof(prop_lmb_size)); 630 if (ret < 0) { 631 goto out; 632 } 633 634 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 635 if (ret < 0) { 636 goto out; 637 } 638 639 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 640 if (ret < 0) { 641 goto out; 642 } 643 644 /* ibm,dynamic-memory */ 645 int_buf[0] = cpu_to_be32(nr_lmbs); 646 cur_index++; 647 for (i = 0; i < nr_lmbs; i++) { 648 uint64_t addr = i * lmb_size; 649 uint32_t *dynamic_memory = cur_index; 650 651 if (i >= hotplug_lmb_start) { 652 sPAPRDRConnector *drc; 653 sPAPRDRConnectorClass *drck; 654 655 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 656 g_assert(drc); 657 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 658 659 dynamic_memory[0] = cpu_to_be32(addr >> 32); 660 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 661 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 662 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 663 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 664 if (memory_region_present(get_system_memory(), addr)) { 665 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 666 } else { 667 dynamic_memory[5] = cpu_to_be32(0); 668 } 669 } else { 670 /* 671 * LMB information for RMA, boot time RAM and gap b/n RAM and 672 * hotplug memory region -- all these are marked as reserved 673 * and as having no valid DRC. 674 */ 675 dynamic_memory[0] = cpu_to_be32(addr >> 32); 676 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 677 dynamic_memory[2] = cpu_to_be32(0); 678 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 679 dynamic_memory[4] = cpu_to_be32(-1); 680 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 681 SPAPR_LMB_FLAGS_DRC_INVALID); 682 } 683 684 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 685 } 686 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 687 if (ret < 0) { 688 goto out; 689 } 690 691 /* ibm,associativity-lookup-arrays */ 692 cur_index = int_buf; 693 int_buf[0] = cpu_to_be32(nr_nodes); 694 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 695 cur_index += 2; 696 for (i = 0; i < nr_nodes; i++) { 697 uint32_t associativity[] = { 698 cpu_to_be32(0x0), 699 cpu_to_be32(0x0), 700 cpu_to_be32(0x0), 701 cpu_to_be32(i) 702 }; 703 memcpy(cur_index, associativity, sizeof(associativity)); 704 cur_index += 4; 705 } 706 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 707 (cur_index - int_buf) * sizeof(uint32_t)); 708 out: 709 g_free(int_buf); 710 return ret; 711 } 712 713 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 714 sPAPROptionVector *ov5_updates) 715 { 716 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 717 int ret = 0, offset; 718 719 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 720 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 721 g_assert(smc->dr_lmb_enabled); 722 ret = spapr_populate_drconf_memory(spapr, fdt); 723 if (ret) { 724 goto out; 725 } 726 } 727 728 offset = fdt_path_offset(fdt, "/chosen"); 729 if (offset < 0) { 730 offset = fdt_add_subnode(fdt, 0, "chosen"); 731 if (offset < 0) { 732 return offset; 733 } 734 } 735 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 736 "ibm,architecture-vec-5"); 737 738 out: 739 return ret; 740 } 741 742 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 743 target_ulong addr, target_ulong size, 744 sPAPROptionVector *ov5_updates) 745 { 746 void *fdt, *fdt_skel; 747 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 748 749 size -= sizeof(hdr); 750 751 /* Create sceleton */ 752 fdt_skel = g_malloc0(size); 753 _FDT((fdt_create(fdt_skel, size))); 754 _FDT((fdt_begin_node(fdt_skel, ""))); 755 _FDT((fdt_end_node(fdt_skel))); 756 _FDT((fdt_finish(fdt_skel))); 757 fdt = g_malloc0(size); 758 _FDT((fdt_open_into(fdt_skel, fdt, size))); 759 g_free(fdt_skel); 760 761 /* Fixup cpu nodes */ 762 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 763 764 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 765 return -1; 766 } 767 768 /* Pack resulting tree */ 769 _FDT((fdt_pack(fdt))); 770 771 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 772 trace_spapr_cas_failed(size); 773 return -1; 774 } 775 776 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 777 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 778 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 779 g_free(fdt); 780 781 return 0; 782 } 783 784 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 785 { 786 int rtas; 787 GString *hypertas = g_string_sized_new(256); 788 GString *qemu_hypertas = g_string_sized_new(256); 789 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 790 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 791 memory_region_size(&spapr->hotplug_memory.mr); 792 uint32_t lrdr_capacity[] = { 793 cpu_to_be32(max_hotplug_addr >> 32), 794 cpu_to_be32(max_hotplug_addr & 0xffffffff), 795 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 796 cpu_to_be32(max_cpus / smp_threads), 797 }; 798 799 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 800 801 /* hypertas */ 802 add_str(hypertas, "hcall-pft"); 803 add_str(hypertas, "hcall-term"); 804 add_str(hypertas, "hcall-dabr"); 805 add_str(hypertas, "hcall-interrupt"); 806 add_str(hypertas, "hcall-tce"); 807 add_str(hypertas, "hcall-vio"); 808 add_str(hypertas, "hcall-splpar"); 809 add_str(hypertas, "hcall-bulk"); 810 add_str(hypertas, "hcall-set-mode"); 811 add_str(hypertas, "hcall-sprg0"); 812 add_str(hypertas, "hcall-copy"); 813 add_str(hypertas, "hcall-debug"); 814 add_str(qemu_hypertas, "hcall-memop1"); 815 816 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 817 add_str(hypertas, "hcall-multi-tce"); 818 } 819 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 820 hypertas->str, hypertas->len)); 821 g_string_free(hypertas, TRUE); 822 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 823 qemu_hypertas->str, qemu_hypertas->len)); 824 g_string_free(qemu_hypertas, TRUE); 825 826 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 827 refpoints, sizeof(refpoints))); 828 829 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 830 RTAS_ERROR_LOG_MAX)); 831 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 832 RTAS_EVENT_SCAN_RATE)); 833 834 if (msi_nonbroken) { 835 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 836 } 837 838 /* 839 * According to PAPR, rtas ibm,os-term does not guarantee a return 840 * back to the guest cpu. 841 * 842 * While an additional ibm,extended-os-term property indicates 843 * that rtas call return will always occur. Set this property. 844 */ 845 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 846 847 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 848 lrdr_capacity, sizeof(lrdr_capacity))); 849 850 spapr_dt_rtas_tokens(fdt, rtas); 851 } 852 853 /* Prepare ibm,arch-vec-5-platform-support, which indicates the MMU features 854 * that the guest may request and thus the valid values for bytes 24..26 of 855 * option vector 5: */ 856 static void spapr_dt_ov5_platform_support(void *fdt, int chosen) 857 { 858 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 859 860 char val[2 * 3] = { 861 24, 0x00, /* Hash/Radix, filled in below. */ 862 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 863 26, 0x40, /* Radix options: GTSE == yes. */ 864 }; 865 866 if (kvm_enabled()) { 867 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 868 val[1] = 0x80; /* OV5_MMU_BOTH */ 869 } else if (kvmppc_has_cap_mmu_radix()) { 870 val[1] = 0x40; /* OV5_MMU_RADIX_300 */ 871 } else { 872 val[1] = 0x00; /* Hash */ 873 } 874 } else { 875 if (first_ppc_cpu->env.mmu_model & POWERPC_MMU_V3) { 876 /* V3 MMU supports both hash and radix (with dynamic switching) */ 877 val[1] = 0xC0; 878 } else { 879 /* Otherwise we can only do hash */ 880 val[1] = 0x00; 881 } 882 } 883 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 884 val, sizeof(val))); 885 } 886 887 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 888 { 889 MachineState *machine = MACHINE(spapr); 890 int chosen; 891 const char *boot_device = machine->boot_order; 892 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 893 size_t cb = 0; 894 char *bootlist = get_boot_devices_list(&cb, true); 895 896 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 897 898 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 899 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 900 spapr->initrd_base)); 901 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 902 spapr->initrd_base + spapr->initrd_size)); 903 904 if (spapr->kernel_size) { 905 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 906 cpu_to_be64(spapr->kernel_size) }; 907 908 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 909 &kprop, sizeof(kprop))); 910 if (spapr->kernel_le) { 911 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 912 } 913 } 914 if (boot_menu) { 915 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 916 } 917 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 918 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 919 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 920 921 if (cb && bootlist) { 922 int i; 923 924 for (i = 0; i < cb; i++) { 925 if (bootlist[i] == '\n') { 926 bootlist[i] = ' '; 927 } 928 } 929 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 930 } 931 932 if (boot_device && strlen(boot_device)) { 933 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 934 } 935 936 if (!spapr->has_graphics && stdout_path) { 937 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 938 } 939 940 spapr_dt_ov5_platform_support(fdt, chosen); 941 942 g_free(stdout_path); 943 g_free(bootlist); 944 } 945 946 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 947 { 948 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 949 * KVM to work under pHyp with some guest co-operation */ 950 int hypervisor; 951 uint8_t hypercall[16]; 952 953 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 954 /* indicate KVM hypercall interface */ 955 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 956 if (kvmppc_has_cap_fixup_hcalls()) { 957 /* 958 * Older KVM versions with older guest kernels were broken 959 * with the magic page, don't allow the guest to map it. 960 */ 961 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 962 sizeof(hypercall))) { 963 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 964 hypercall, sizeof(hypercall))); 965 } 966 } 967 } 968 969 static void *spapr_build_fdt(sPAPRMachineState *spapr, 970 hwaddr rtas_addr, 971 hwaddr rtas_size) 972 { 973 MachineState *machine = MACHINE(qdev_get_machine()); 974 MachineClass *mc = MACHINE_GET_CLASS(machine); 975 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 976 int ret; 977 void *fdt; 978 sPAPRPHBState *phb; 979 char *buf; 980 int smt = kvmppc_smt_threads(); 981 982 fdt = g_malloc0(FDT_MAX_SIZE); 983 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 984 985 /* Root node */ 986 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 987 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 988 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 989 990 /* 991 * Add info to guest to indentify which host is it being run on 992 * and what is the uuid of the guest 993 */ 994 if (kvmppc_get_host_model(&buf)) { 995 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 996 g_free(buf); 997 } 998 if (kvmppc_get_host_serial(&buf)) { 999 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1000 g_free(buf); 1001 } 1002 1003 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1004 1005 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1006 if (qemu_uuid_set) { 1007 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1008 } 1009 g_free(buf); 1010 1011 if (qemu_get_vm_name()) { 1012 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1013 qemu_get_vm_name())); 1014 } 1015 1016 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1017 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1018 1019 /* /interrupt controller */ 1020 spapr_dt_xics(DIV_ROUND_UP(max_cpus * smt, smp_threads), fdt, PHANDLE_XICP); 1021 1022 ret = spapr_populate_memory(spapr, fdt); 1023 if (ret < 0) { 1024 error_report("couldn't setup memory nodes in fdt"); 1025 exit(1); 1026 } 1027 1028 /* /vdevice */ 1029 spapr_dt_vdevice(spapr->vio_bus, fdt); 1030 1031 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1032 ret = spapr_rng_populate_dt(fdt); 1033 if (ret < 0) { 1034 error_report("could not set up rng device in the fdt"); 1035 exit(1); 1036 } 1037 } 1038 1039 QLIST_FOREACH(phb, &spapr->phbs, list) { 1040 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 1041 if (ret < 0) { 1042 error_report("couldn't setup PCI devices in fdt"); 1043 exit(1); 1044 } 1045 } 1046 1047 /* cpus */ 1048 spapr_populate_cpus_dt_node(fdt, spapr); 1049 1050 if (smc->dr_lmb_enabled) { 1051 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1052 } 1053 1054 if (mc->has_hotpluggable_cpus) { 1055 int offset = fdt_path_offset(fdt, "/cpus"); 1056 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1057 SPAPR_DR_CONNECTOR_TYPE_CPU); 1058 if (ret < 0) { 1059 error_report("Couldn't set up CPU DR device tree properties"); 1060 exit(1); 1061 } 1062 } 1063 1064 /* /event-sources */ 1065 spapr_dt_events(spapr, fdt); 1066 1067 /* /rtas */ 1068 spapr_dt_rtas(spapr, fdt); 1069 1070 /* /chosen */ 1071 spapr_dt_chosen(spapr, fdt); 1072 1073 /* /hypervisor */ 1074 if (kvm_enabled()) { 1075 spapr_dt_hypervisor(spapr, fdt); 1076 } 1077 1078 /* Build memory reserve map */ 1079 if (spapr->kernel_size) { 1080 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 1081 } 1082 if (spapr->initrd_size) { 1083 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 1084 } 1085 1086 /* ibm,client-architecture-support updates */ 1087 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 1088 if (ret < 0) { 1089 error_report("couldn't setup CAS properties fdt"); 1090 exit(1); 1091 } 1092 1093 return fdt; 1094 } 1095 1096 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1097 { 1098 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1099 } 1100 1101 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1102 PowerPCCPU *cpu) 1103 { 1104 CPUPPCState *env = &cpu->env; 1105 1106 /* The TCG path should also be holding the BQL at this point */ 1107 g_assert(qemu_mutex_iothread_locked()); 1108 1109 if (msr_pr) { 1110 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1111 env->gpr[3] = H_PRIVILEGE; 1112 } else { 1113 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1114 } 1115 } 1116 1117 static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp) 1118 { 1119 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1120 1121 return spapr->patb_entry; 1122 } 1123 1124 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1125 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1126 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1127 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1128 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1129 1130 /* 1131 * Get the fd to access the kernel htab, re-opening it if necessary 1132 */ 1133 static int get_htab_fd(sPAPRMachineState *spapr) 1134 { 1135 if (spapr->htab_fd >= 0) { 1136 return spapr->htab_fd; 1137 } 1138 1139 spapr->htab_fd = kvmppc_get_htab_fd(false); 1140 if (spapr->htab_fd < 0) { 1141 error_report("Unable to open fd for reading hash table from KVM: %s", 1142 strerror(errno)); 1143 } 1144 1145 return spapr->htab_fd; 1146 } 1147 1148 void close_htab_fd(sPAPRMachineState *spapr) 1149 { 1150 if (spapr->htab_fd >= 0) { 1151 close(spapr->htab_fd); 1152 } 1153 spapr->htab_fd = -1; 1154 } 1155 1156 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1157 { 1158 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1159 1160 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1161 } 1162 1163 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1164 hwaddr ptex, int n) 1165 { 1166 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1167 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1168 1169 if (!spapr->htab) { 1170 /* 1171 * HTAB is controlled by KVM. Fetch into temporary buffer 1172 */ 1173 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1174 kvmppc_read_hptes(hptes, ptex, n); 1175 return hptes; 1176 } 1177 1178 /* 1179 * HTAB is controlled by QEMU. Just point to the internally 1180 * accessible PTEG. 1181 */ 1182 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1183 } 1184 1185 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1186 const ppc_hash_pte64_t *hptes, 1187 hwaddr ptex, int n) 1188 { 1189 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1190 1191 if (!spapr->htab) { 1192 g_free((void *)hptes); 1193 } 1194 1195 /* Nothing to do for qemu managed HPT */ 1196 } 1197 1198 static void spapr_store_hpte(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1199 uint64_t pte0, uint64_t pte1) 1200 { 1201 sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp); 1202 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1203 1204 if (!spapr->htab) { 1205 kvmppc_write_hpte(ptex, pte0, pte1); 1206 } else { 1207 stq_p(spapr->htab + offset, pte0); 1208 stq_p(spapr->htab + offset + HASH_PTE_SIZE_64 / 2, pte1); 1209 } 1210 } 1211 1212 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1213 { 1214 int shift; 1215 1216 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1217 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1218 * that's much more than is needed for Linux guests */ 1219 shift = ctz64(pow2ceil(ramsize)) - 7; 1220 shift = MAX(shift, 18); /* Minimum architected size */ 1221 shift = MIN(shift, 46); /* Maximum architected size */ 1222 return shift; 1223 } 1224 1225 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1226 Error **errp) 1227 { 1228 long rc; 1229 1230 /* Clean up any HPT info from a previous boot */ 1231 g_free(spapr->htab); 1232 spapr->htab = NULL; 1233 spapr->htab_shift = 0; 1234 close_htab_fd(spapr); 1235 1236 rc = kvmppc_reset_htab(shift); 1237 if (rc < 0) { 1238 /* kernel-side HPT needed, but couldn't allocate one */ 1239 error_setg_errno(errp, errno, 1240 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1241 shift); 1242 /* This is almost certainly fatal, but if the caller really 1243 * wants to carry on with shift == 0, it's welcome to try */ 1244 } else if (rc > 0) { 1245 /* kernel-side HPT allocated */ 1246 if (rc != shift) { 1247 error_setg(errp, 1248 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1249 shift, rc); 1250 } 1251 1252 spapr->htab_shift = shift; 1253 spapr->htab = NULL; 1254 } else { 1255 /* kernel-side HPT not needed, allocate in userspace instead */ 1256 size_t size = 1ULL << shift; 1257 int i; 1258 1259 spapr->htab = qemu_memalign(size, size); 1260 if (!spapr->htab) { 1261 error_setg_errno(errp, errno, 1262 "Could not allocate HPT of order %d", shift); 1263 return; 1264 } 1265 1266 memset(spapr->htab, 0, size); 1267 spapr->htab_shift = shift; 1268 1269 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1270 DIRTY_HPTE(HPTE(spapr->htab, i)); 1271 } 1272 } 1273 } 1274 1275 void spapr_setup_hpt_and_vrma(sPAPRMachineState *spapr) 1276 { 1277 spapr_reallocate_hpt(spapr, 1278 spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size), 1279 &error_fatal); 1280 if (spapr->vrma_adjust) { 1281 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1282 spapr->htab_shift); 1283 } 1284 /* We're setting up a hash table, so that means we're not radix */ 1285 spapr->patb_entry = 0; 1286 } 1287 1288 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1289 { 1290 bool matched = false; 1291 1292 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1293 matched = true; 1294 } 1295 1296 if (!matched) { 1297 error_report("Device %s is not supported by this machine yet.", 1298 qdev_fw_name(DEVICE(sbdev))); 1299 exit(1); 1300 } 1301 } 1302 1303 static void ppc_spapr_reset(void) 1304 { 1305 MachineState *machine = MACHINE(qdev_get_machine()); 1306 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1307 PowerPCCPU *first_ppc_cpu; 1308 uint32_t rtas_limit; 1309 hwaddr rtas_addr, fdt_addr; 1310 void *fdt; 1311 int rc; 1312 1313 /* Check for unknown sysbus devices */ 1314 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1315 1316 if (kvm_enabled() && kvmppc_has_cap_mmu_radix()) { 1317 /* If using KVM with radix mode available, VCPUs can be started 1318 * without a HPT because KVM will start them in radix mode. 1319 * Set the GR bit in PATB so that we know there is no HPT. */ 1320 spapr->patb_entry = PATBE1_GR; 1321 } else { 1322 spapr->patb_entry = 0; 1323 spapr_setup_hpt_and_vrma(spapr); 1324 } 1325 1326 qemu_devices_reset(); 1327 1328 /* 1329 * We place the device tree and RTAS just below either the top of the RMA, 1330 * or just below 2GB, whichever is lowere, so that it can be 1331 * processed with 32-bit real mode code if necessary 1332 */ 1333 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1334 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1335 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1336 1337 /* if this reset wasn't generated by CAS, we should reset our 1338 * negotiated options and start from scratch */ 1339 if (!spapr->cas_reboot) { 1340 spapr_ovec_cleanup(spapr->ov5_cas); 1341 spapr->ov5_cas = spapr_ovec_new(); 1342 } 1343 1344 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1345 1346 spapr_load_rtas(spapr, fdt, rtas_addr); 1347 1348 rc = fdt_pack(fdt); 1349 1350 /* Should only fail if we've built a corrupted tree */ 1351 assert(rc == 0); 1352 1353 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1354 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1355 fdt_totalsize(fdt), FDT_MAX_SIZE); 1356 exit(1); 1357 } 1358 1359 /* Load the fdt */ 1360 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1361 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1362 g_free(fdt); 1363 1364 /* Set up the entry state */ 1365 first_ppc_cpu = POWERPC_CPU(first_cpu); 1366 first_ppc_cpu->env.gpr[3] = fdt_addr; 1367 first_ppc_cpu->env.gpr[5] = 0; 1368 first_cpu->halted = 0; 1369 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1370 1371 spapr->cas_reboot = false; 1372 } 1373 1374 static void spapr_create_nvram(sPAPRMachineState *spapr) 1375 { 1376 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1377 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1378 1379 if (dinfo) { 1380 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1381 &error_fatal); 1382 } 1383 1384 qdev_init_nofail(dev); 1385 1386 spapr->nvram = (struct sPAPRNVRAM *)dev; 1387 } 1388 1389 static void spapr_rtc_create(sPAPRMachineState *spapr) 1390 { 1391 object_initialize(&spapr->rtc, sizeof(spapr->rtc), TYPE_SPAPR_RTC); 1392 object_property_add_child(OBJECT(spapr), "rtc", OBJECT(&spapr->rtc), 1393 &error_fatal); 1394 object_property_set_bool(OBJECT(&spapr->rtc), true, "realized", 1395 &error_fatal); 1396 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1397 "date", &error_fatal); 1398 } 1399 1400 /* Returns whether we want to use VGA or not */ 1401 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1402 { 1403 switch (vga_interface_type) { 1404 case VGA_NONE: 1405 return false; 1406 case VGA_DEVICE: 1407 return true; 1408 case VGA_STD: 1409 case VGA_VIRTIO: 1410 return pci_vga_init(pci_bus) != NULL; 1411 default: 1412 error_setg(errp, 1413 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1414 return false; 1415 } 1416 } 1417 1418 static int spapr_post_load(void *opaque, int version_id) 1419 { 1420 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1421 int err = 0; 1422 1423 if (!object_dynamic_cast(OBJECT(spapr->ics), TYPE_ICS_KVM)) { 1424 CPUState *cs; 1425 CPU_FOREACH(cs) { 1426 PowerPCCPU *cpu = POWERPC_CPU(cs); 1427 icp_resend(ICP(cpu->intc)); 1428 } 1429 } 1430 1431 /* In earlier versions, there was no separate qdev for the PAPR 1432 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1433 * So when migrating from those versions, poke the incoming offset 1434 * value into the RTC device */ 1435 if (version_id < 3) { 1436 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1437 } 1438 1439 return err; 1440 } 1441 1442 static bool version_before_3(void *opaque, int version_id) 1443 { 1444 return version_id < 3; 1445 } 1446 1447 static bool spapr_ov5_cas_needed(void *opaque) 1448 { 1449 sPAPRMachineState *spapr = opaque; 1450 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1451 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1452 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1453 bool cas_needed; 1454 1455 /* Prior to the introduction of sPAPROptionVector, we had two option 1456 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1457 * Both of these options encode machine topology into the device-tree 1458 * in such a way that the now-booted OS should still be able to interact 1459 * appropriately with QEMU regardless of what options were actually 1460 * negotiatied on the source side. 1461 * 1462 * As such, we can avoid migrating the CAS-negotiated options if these 1463 * are the only options available on the current machine/platform. 1464 * Since these are the only options available for pseries-2.7 and 1465 * earlier, this allows us to maintain old->new/new->old migration 1466 * compatibility. 1467 * 1468 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1469 * via default pseries-2.8 machines and explicit command-line parameters. 1470 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1471 * of the actual CAS-negotiated values to continue working properly. For 1472 * example, availability of memory unplug depends on knowing whether 1473 * OV5_HP_EVT was negotiated via CAS. 1474 * 1475 * Thus, for any cases where the set of available CAS-negotiatable 1476 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1477 * include the CAS-negotiated options in the migration stream. 1478 */ 1479 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1480 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1481 1482 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1483 * the mask itself since in the future it's possible "legacy" bits may be 1484 * removed via machine options, which could generate a false positive 1485 * that breaks migration. 1486 */ 1487 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1488 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1489 1490 spapr_ovec_cleanup(ov5_mask); 1491 spapr_ovec_cleanup(ov5_legacy); 1492 spapr_ovec_cleanup(ov5_removed); 1493 1494 return cas_needed; 1495 } 1496 1497 static const VMStateDescription vmstate_spapr_ov5_cas = { 1498 .name = "spapr_option_vector_ov5_cas", 1499 .version_id = 1, 1500 .minimum_version_id = 1, 1501 .needed = spapr_ov5_cas_needed, 1502 .fields = (VMStateField[]) { 1503 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1504 vmstate_spapr_ovec, sPAPROptionVector), 1505 VMSTATE_END_OF_LIST() 1506 }, 1507 }; 1508 1509 static bool spapr_patb_entry_needed(void *opaque) 1510 { 1511 sPAPRMachineState *spapr = opaque; 1512 1513 return !!spapr->patb_entry; 1514 } 1515 1516 static const VMStateDescription vmstate_spapr_patb_entry = { 1517 .name = "spapr_patb_entry", 1518 .version_id = 1, 1519 .minimum_version_id = 1, 1520 .needed = spapr_patb_entry_needed, 1521 .fields = (VMStateField[]) { 1522 VMSTATE_UINT64(patb_entry, sPAPRMachineState), 1523 VMSTATE_END_OF_LIST() 1524 }, 1525 }; 1526 1527 static const VMStateDescription vmstate_spapr = { 1528 .name = "spapr", 1529 .version_id = 3, 1530 .minimum_version_id = 1, 1531 .post_load = spapr_post_load, 1532 .fields = (VMStateField[]) { 1533 /* used to be @next_irq */ 1534 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1535 1536 /* RTC offset */ 1537 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1538 1539 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1540 VMSTATE_END_OF_LIST() 1541 }, 1542 .subsections = (const VMStateDescription*[]) { 1543 &vmstate_spapr_ov5_cas, 1544 &vmstate_spapr_patb_entry, 1545 NULL 1546 } 1547 }; 1548 1549 static int htab_save_setup(QEMUFile *f, void *opaque) 1550 { 1551 sPAPRMachineState *spapr = opaque; 1552 1553 /* "Iteration" header */ 1554 qemu_put_be32(f, spapr->htab_shift); 1555 1556 if (spapr->htab) { 1557 spapr->htab_save_index = 0; 1558 spapr->htab_first_pass = true; 1559 } else { 1560 assert(kvm_enabled()); 1561 } 1562 1563 1564 return 0; 1565 } 1566 1567 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1568 int64_t max_ns) 1569 { 1570 bool has_timeout = max_ns != -1; 1571 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1572 int index = spapr->htab_save_index; 1573 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1574 1575 assert(spapr->htab_first_pass); 1576 1577 do { 1578 int chunkstart; 1579 1580 /* Consume invalid HPTEs */ 1581 while ((index < htabslots) 1582 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1583 CLEAN_HPTE(HPTE(spapr->htab, index)); 1584 index++; 1585 } 1586 1587 /* Consume valid HPTEs */ 1588 chunkstart = index; 1589 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1590 && HPTE_VALID(HPTE(spapr->htab, index))) { 1591 CLEAN_HPTE(HPTE(spapr->htab, index)); 1592 index++; 1593 } 1594 1595 if (index > chunkstart) { 1596 int n_valid = index - chunkstart; 1597 1598 qemu_put_be32(f, chunkstart); 1599 qemu_put_be16(f, n_valid); 1600 qemu_put_be16(f, 0); 1601 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1602 HASH_PTE_SIZE_64 * n_valid); 1603 1604 if (has_timeout && 1605 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1606 break; 1607 } 1608 } 1609 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1610 1611 if (index >= htabslots) { 1612 assert(index == htabslots); 1613 index = 0; 1614 spapr->htab_first_pass = false; 1615 } 1616 spapr->htab_save_index = index; 1617 } 1618 1619 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1620 int64_t max_ns) 1621 { 1622 bool final = max_ns < 0; 1623 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1624 int examined = 0, sent = 0; 1625 int index = spapr->htab_save_index; 1626 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1627 1628 assert(!spapr->htab_first_pass); 1629 1630 do { 1631 int chunkstart, invalidstart; 1632 1633 /* Consume non-dirty HPTEs */ 1634 while ((index < htabslots) 1635 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1636 index++; 1637 examined++; 1638 } 1639 1640 chunkstart = index; 1641 /* Consume valid dirty HPTEs */ 1642 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1643 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1644 && HPTE_VALID(HPTE(spapr->htab, index))) { 1645 CLEAN_HPTE(HPTE(spapr->htab, index)); 1646 index++; 1647 examined++; 1648 } 1649 1650 invalidstart = index; 1651 /* Consume invalid dirty HPTEs */ 1652 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1653 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1654 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1655 CLEAN_HPTE(HPTE(spapr->htab, index)); 1656 index++; 1657 examined++; 1658 } 1659 1660 if (index > chunkstart) { 1661 int n_valid = invalidstart - chunkstart; 1662 int n_invalid = index - invalidstart; 1663 1664 qemu_put_be32(f, chunkstart); 1665 qemu_put_be16(f, n_valid); 1666 qemu_put_be16(f, n_invalid); 1667 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1668 HASH_PTE_SIZE_64 * n_valid); 1669 sent += index - chunkstart; 1670 1671 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1672 break; 1673 } 1674 } 1675 1676 if (examined >= htabslots) { 1677 break; 1678 } 1679 1680 if (index >= htabslots) { 1681 assert(index == htabslots); 1682 index = 0; 1683 } 1684 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1685 1686 if (index >= htabslots) { 1687 assert(index == htabslots); 1688 index = 0; 1689 } 1690 1691 spapr->htab_save_index = index; 1692 1693 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1694 } 1695 1696 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1697 #define MAX_KVM_BUF_SIZE 2048 1698 1699 static int htab_save_iterate(QEMUFile *f, void *opaque) 1700 { 1701 sPAPRMachineState *spapr = opaque; 1702 int fd; 1703 int rc = 0; 1704 1705 /* Iteration header */ 1706 qemu_put_be32(f, 0); 1707 1708 if (!spapr->htab) { 1709 assert(kvm_enabled()); 1710 1711 fd = get_htab_fd(spapr); 1712 if (fd < 0) { 1713 return fd; 1714 } 1715 1716 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1717 if (rc < 0) { 1718 return rc; 1719 } 1720 } else if (spapr->htab_first_pass) { 1721 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1722 } else { 1723 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1724 } 1725 1726 /* End marker */ 1727 qemu_put_be32(f, 0); 1728 qemu_put_be16(f, 0); 1729 qemu_put_be16(f, 0); 1730 1731 return rc; 1732 } 1733 1734 static int htab_save_complete(QEMUFile *f, void *opaque) 1735 { 1736 sPAPRMachineState *spapr = opaque; 1737 int fd; 1738 1739 /* Iteration header */ 1740 qemu_put_be32(f, 0); 1741 1742 if (!spapr->htab) { 1743 int rc; 1744 1745 assert(kvm_enabled()); 1746 1747 fd = get_htab_fd(spapr); 1748 if (fd < 0) { 1749 return fd; 1750 } 1751 1752 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1753 if (rc < 0) { 1754 return rc; 1755 } 1756 } else { 1757 if (spapr->htab_first_pass) { 1758 htab_save_first_pass(f, spapr, -1); 1759 } 1760 htab_save_later_pass(f, spapr, -1); 1761 } 1762 1763 /* End marker */ 1764 qemu_put_be32(f, 0); 1765 qemu_put_be16(f, 0); 1766 qemu_put_be16(f, 0); 1767 1768 return 0; 1769 } 1770 1771 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1772 { 1773 sPAPRMachineState *spapr = opaque; 1774 uint32_t section_hdr; 1775 int fd = -1; 1776 1777 if (version_id < 1 || version_id > 1) { 1778 error_report("htab_load() bad version"); 1779 return -EINVAL; 1780 } 1781 1782 section_hdr = qemu_get_be32(f); 1783 1784 if (section_hdr) { 1785 Error *local_err = NULL; 1786 1787 /* First section gives the htab size */ 1788 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1789 if (local_err) { 1790 error_report_err(local_err); 1791 return -EINVAL; 1792 } 1793 return 0; 1794 } 1795 1796 if (!spapr->htab) { 1797 assert(kvm_enabled()); 1798 1799 fd = kvmppc_get_htab_fd(true); 1800 if (fd < 0) { 1801 error_report("Unable to open fd to restore KVM hash table: %s", 1802 strerror(errno)); 1803 } 1804 } 1805 1806 while (true) { 1807 uint32_t index; 1808 uint16_t n_valid, n_invalid; 1809 1810 index = qemu_get_be32(f); 1811 n_valid = qemu_get_be16(f); 1812 n_invalid = qemu_get_be16(f); 1813 1814 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1815 /* End of Stream */ 1816 break; 1817 } 1818 1819 if ((index + n_valid + n_invalid) > 1820 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1821 /* Bad index in stream */ 1822 error_report( 1823 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1824 index, n_valid, n_invalid, spapr->htab_shift); 1825 return -EINVAL; 1826 } 1827 1828 if (spapr->htab) { 1829 if (n_valid) { 1830 qemu_get_buffer(f, HPTE(spapr->htab, index), 1831 HASH_PTE_SIZE_64 * n_valid); 1832 } 1833 if (n_invalid) { 1834 memset(HPTE(spapr->htab, index + n_valid), 0, 1835 HASH_PTE_SIZE_64 * n_invalid); 1836 } 1837 } else { 1838 int rc; 1839 1840 assert(fd >= 0); 1841 1842 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1843 if (rc < 0) { 1844 return rc; 1845 } 1846 } 1847 } 1848 1849 if (!spapr->htab) { 1850 assert(fd >= 0); 1851 close(fd); 1852 } 1853 1854 return 0; 1855 } 1856 1857 static void htab_cleanup(void *opaque) 1858 { 1859 sPAPRMachineState *spapr = opaque; 1860 1861 close_htab_fd(spapr); 1862 } 1863 1864 static SaveVMHandlers savevm_htab_handlers = { 1865 .save_live_setup = htab_save_setup, 1866 .save_live_iterate = htab_save_iterate, 1867 .save_live_complete_precopy = htab_save_complete, 1868 .cleanup = htab_cleanup, 1869 .load_state = htab_load, 1870 }; 1871 1872 static void spapr_boot_set(void *opaque, const char *boot_device, 1873 Error **errp) 1874 { 1875 MachineState *machine = MACHINE(qdev_get_machine()); 1876 machine->boot_order = g_strdup(boot_device); 1877 } 1878 1879 /* 1880 * Reset routine for LMB DR devices. 1881 * 1882 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1883 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1884 * when it walks all its children devices. LMB devices reset occurs 1885 * as part of spapr_ppc_reset(). 1886 */ 1887 static void spapr_drc_reset(void *opaque) 1888 { 1889 sPAPRDRConnector *drc = opaque; 1890 DeviceState *d = DEVICE(drc); 1891 1892 if (d) { 1893 device_reset(d); 1894 } 1895 } 1896 1897 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1898 { 1899 MachineState *machine = MACHINE(spapr); 1900 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1901 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1902 int i; 1903 1904 for (i = 0; i < nr_lmbs; i++) { 1905 sPAPRDRConnector *drc; 1906 uint64_t addr; 1907 1908 addr = i * lmb_size + spapr->hotplug_memory.base; 1909 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1910 addr/lmb_size); 1911 qemu_register_reset(spapr_drc_reset, drc); 1912 } 1913 } 1914 1915 /* 1916 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1917 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1918 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1919 */ 1920 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1921 { 1922 int i; 1923 1924 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1925 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1926 " is not aligned to %llu MiB", 1927 machine->ram_size, 1928 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1929 return; 1930 } 1931 1932 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1933 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1934 " is not aligned to %llu MiB", 1935 machine->ram_size, 1936 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1937 return; 1938 } 1939 1940 for (i = 0; i < nb_numa_nodes; i++) { 1941 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1942 error_setg(errp, 1943 "Node %d memory size 0x%" PRIx64 1944 " is not aligned to %llu MiB", 1945 i, numa_info[i].node_mem, 1946 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1947 return; 1948 } 1949 } 1950 } 1951 1952 /* find cpu slot in machine->possible_cpus by core_id */ 1953 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 1954 { 1955 int index = id / smp_threads; 1956 1957 if (index >= ms->possible_cpus->len) { 1958 return NULL; 1959 } 1960 if (idx) { 1961 *idx = index; 1962 } 1963 return &ms->possible_cpus->cpus[index]; 1964 } 1965 1966 static void spapr_init_cpus(sPAPRMachineState *spapr) 1967 { 1968 MachineState *machine = MACHINE(spapr); 1969 MachineClass *mc = MACHINE_GET_CLASS(machine); 1970 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1971 int smt = kvmppc_smt_threads(); 1972 const CPUArchIdList *possible_cpus; 1973 int boot_cores_nr = smp_cpus / smp_threads; 1974 int i; 1975 1976 if (!type) { 1977 error_report("Unable to find sPAPR CPU Core definition"); 1978 exit(1); 1979 } 1980 1981 possible_cpus = mc->possible_cpu_arch_ids(machine); 1982 if (mc->has_hotpluggable_cpus) { 1983 if (smp_cpus % smp_threads) { 1984 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1985 smp_cpus, smp_threads); 1986 exit(1); 1987 } 1988 if (max_cpus % smp_threads) { 1989 error_report("max_cpus (%u) must be multiple of threads (%u)", 1990 max_cpus, smp_threads); 1991 exit(1); 1992 } 1993 } else { 1994 if (max_cpus != smp_cpus) { 1995 error_report("This machine version does not support CPU hotplug"); 1996 exit(1); 1997 } 1998 boot_cores_nr = possible_cpus->len; 1999 } 2000 2001 for (i = 0; i < possible_cpus->len; i++) { 2002 int core_id = i * smp_threads; 2003 2004 if (mc->has_hotpluggable_cpus) { 2005 sPAPRDRConnector *drc = 2006 spapr_dr_connector_new(OBJECT(spapr), 2007 SPAPR_DR_CONNECTOR_TYPE_CPU, 2008 (core_id / smp_threads) * smt); 2009 2010 qemu_register_reset(spapr_drc_reset, drc); 2011 } 2012 2013 if (i < boot_cores_nr) { 2014 Object *core = object_new(type); 2015 int nr_threads = smp_threads; 2016 2017 /* Handle the partially filled core for older machine types */ 2018 if ((i + 1) * smp_threads >= smp_cpus) { 2019 nr_threads = smp_cpus - i * smp_threads; 2020 } 2021 2022 object_property_set_int(core, nr_threads, "nr-threads", 2023 &error_fatal); 2024 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 2025 &error_fatal); 2026 object_property_set_bool(core, true, "realized", &error_fatal); 2027 } 2028 } 2029 g_free(type); 2030 } 2031 2032 /* pSeries LPAR / sPAPR hardware init */ 2033 static void ppc_spapr_init(MachineState *machine) 2034 { 2035 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2036 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2037 const char *kernel_filename = machine->kernel_filename; 2038 const char *initrd_filename = machine->initrd_filename; 2039 PCIHostState *phb; 2040 int i; 2041 MemoryRegion *sysmem = get_system_memory(); 2042 MemoryRegion *ram = g_new(MemoryRegion, 1); 2043 MemoryRegion *rma_region; 2044 void *rma = NULL; 2045 hwaddr rma_alloc_size; 2046 hwaddr node0_size = spapr_node0_size(); 2047 long load_limit, fw_size; 2048 char *filename; 2049 2050 msi_nonbroken = true; 2051 2052 QLIST_INIT(&spapr->phbs); 2053 2054 /* Allocate RMA if necessary */ 2055 rma_alloc_size = kvmppc_alloc_rma(&rma); 2056 2057 if (rma_alloc_size == -1) { 2058 error_report("Unable to create RMA"); 2059 exit(1); 2060 } 2061 2062 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 2063 spapr->rma_size = rma_alloc_size; 2064 } else { 2065 spapr->rma_size = node0_size; 2066 2067 /* With KVM, we don't actually know whether KVM supports an 2068 * unbounded RMA (PR KVM) or is limited by the hash table size 2069 * (HV KVM using VRMA), so we always assume the latter 2070 * 2071 * In that case, we also limit the initial allocations for RTAS 2072 * etc... to 256M since we have no way to know what the VRMA size 2073 * is going to be as it depends on the size of the hash table 2074 * isn't determined yet. 2075 */ 2076 if (kvm_enabled()) { 2077 spapr->vrma_adjust = 1; 2078 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 2079 } 2080 2081 /* Actually we don't support unbounded RMA anymore since we 2082 * added proper emulation of HV mode. The max we can get is 2083 * 16G which also happens to be what we configure for PAPR 2084 * mode so make sure we don't do anything bigger than that 2085 */ 2086 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 2087 } 2088 2089 if (spapr->rma_size > node0_size) { 2090 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 2091 spapr->rma_size); 2092 exit(1); 2093 } 2094 2095 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2096 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 2097 2098 /* Set up Interrupt Controller before we create the VCPUs */ 2099 xics_system_init(machine, XICS_IRQS_SPAPR, &error_fatal); 2100 2101 /* Set up containers for ibm,client-set-architecture negotiated options */ 2102 spapr->ov5 = spapr_ovec_new(); 2103 spapr->ov5_cas = spapr_ovec_new(); 2104 2105 if (smc->dr_lmb_enabled) { 2106 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2107 spapr_validate_node_memory(machine, &error_fatal); 2108 } 2109 2110 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2111 if (!kvm_enabled() || kvmppc_has_cap_mmu_radix()) { 2112 /* KVM and TCG always allow GTSE with radix... */ 2113 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2114 } 2115 /* ... but not with hash (currently). */ 2116 2117 /* advertise support for dedicated HP event source to guests */ 2118 if (spapr->use_hotplug_event_source) { 2119 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2120 } 2121 2122 /* init CPUs */ 2123 if (machine->cpu_model == NULL) { 2124 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 2125 } 2126 2127 ppc_cpu_parse_features(machine->cpu_model); 2128 2129 spapr_init_cpus(spapr); 2130 2131 if (kvm_enabled()) { 2132 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2133 kvmppc_enable_logical_ci_hcalls(); 2134 kvmppc_enable_set_mode_hcall(); 2135 2136 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2137 kvmppc_enable_clear_ref_mod_hcalls(); 2138 } 2139 2140 /* allocate RAM */ 2141 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 2142 machine->ram_size); 2143 memory_region_add_subregion(sysmem, 0, ram); 2144 2145 if (rma_alloc_size && rma) { 2146 rma_region = g_new(MemoryRegion, 1); 2147 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 2148 rma_alloc_size, rma); 2149 vmstate_register_ram_global(rma_region); 2150 memory_region_add_subregion(sysmem, 0, rma_region); 2151 } 2152 2153 /* initialize hotplug memory address space */ 2154 if (machine->ram_size < machine->maxram_size) { 2155 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 2156 /* 2157 * Limit the number of hotpluggable memory slots to half the number 2158 * slots that KVM supports, leaving the other half for PCI and other 2159 * devices. However ensure that number of slots doesn't drop below 32. 2160 */ 2161 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2162 SPAPR_MAX_RAM_SLOTS; 2163 2164 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2165 max_memslots = SPAPR_MAX_RAM_SLOTS; 2166 } 2167 if (machine->ram_slots > max_memslots) { 2168 error_report("Specified number of memory slots %" 2169 PRIu64" exceeds max supported %d", 2170 machine->ram_slots, max_memslots); 2171 exit(1); 2172 } 2173 2174 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 2175 SPAPR_HOTPLUG_MEM_ALIGN); 2176 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 2177 "hotplug-memory", hotplug_mem_size); 2178 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 2179 &spapr->hotplug_memory.mr); 2180 } 2181 2182 if (smc->dr_lmb_enabled) { 2183 spapr_create_lmb_dr_connectors(spapr); 2184 } 2185 2186 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 2187 if (!filename) { 2188 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 2189 exit(1); 2190 } 2191 spapr->rtas_size = get_image_size(filename); 2192 if (spapr->rtas_size < 0) { 2193 error_report("Could not get size of LPAR rtas '%s'", filename); 2194 exit(1); 2195 } 2196 spapr->rtas_blob = g_malloc(spapr->rtas_size); 2197 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 2198 error_report("Could not load LPAR rtas '%s'", filename); 2199 exit(1); 2200 } 2201 if (spapr->rtas_size > RTAS_MAX_SIZE) { 2202 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 2203 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 2204 exit(1); 2205 } 2206 g_free(filename); 2207 2208 /* Set up RTAS event infrastructure */ 2209 spapr_events_init(spapr); 2210 2211 /* Set up the RTC RTAS interfaces */ 2212 spapr_rtc_create(spapr); 2213 2214 /* Set up VIO bus */ 2215 spapr->vio_bus = spapr_vio_bus_init(); 2216 2217 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2218 if (serial_hds[i]) { 2219 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2220 } 2221 } 2222 2223 /* We always have at least the nvram device on VIO */ 2224 spapr_create_nvram(spapr); 2225 2226 /* Set up PCI */ 2227 spapr_pci_rtas_init(); 2228 2229 phb = spapr_create_phb(spapr, 0); 2230 2231 for (i = 0; i < nb_nics; i++) { 2232 NICInfo *nd = &nd_table[i]; 2233 2234 if (!nd->model) { 2235 nd->model = g_strdup("ibmveth"); 2236 } 2237 2238 if (strcmp(nd->model, "ibmveth") == 0) { 2239 spapr_vlan_create(spapr->vio_bus, nd); 2240 } else { 2241 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2242 } 2243 } 2244 2245 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2246 spapr_vscsi_create(spapr->vio_bus); 2247 } 2248 2249 /* Graphics */ 2250 if (spapr_vga_init(phb->bus, &error_fatal)) { 2251 spapr->has_graphics = true; 2252 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2253 } 2254 2255 if (machine->usb) { 2256 if (smc->use_ohci_by_default) { 2257 pci_create_simple(phb->bus, -1, "pci-ohci"); 2258 } else { 2259 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2260 } 2261 2262 if (spapr->has_graphics) { 2263 USBBus *usb_bus = usb_bus_find(-1); 2264 2265 usb_create_simple(usb_bus, "usb-kbd"); 2266 usb_create_simple(usb_bus, "usb-mouse"); 2267 } 2268 } 2269 2270 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2271 error_report( 2272 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2273 MIN_RMA_SLOF); 2274 exit(1); 2275 } 2276 2277 if (kernel_filename) { 2278 uint64_t lowaddr = 0; 2279 2280 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2281 NULL, NULL, &lowaddr, NULL, 1, 2282 PPC_ELF_MACHINE, 0, 0); 2283 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2284 spapr->kernel_size = load_elf(kernel_filename, 2285 translate_kernel_address, NULL, NULL, 2286 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2287 0, 0); 2288 spapr->kernel_le = spapr->kernel_size > 0; 2289 } 2290 if (spapr->kernel_size < 0) { 2291 error_report("error loading %s: %s", kernel_filename, 2292 load_elf_strerror(spapr->kernel_size)); 2293 exit(1); 2294 } 2295 2296 /* load initrd */ 2297 if (initrd_filename) { 2298 /* Try to locate the initrd in the gap between the kernel 2299 * and the firmware. Add a bit of space just in case 2300 */ 2301 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2302 + 0x1ffff) & ~0xffff; 2303 spapr->initrd_size = load_image_targphys(initrd_filename, 2304 spapr->initrd_base, 2305 load_limit 2306 - spapr->initrd_base); 2307 if (spapr->initrd_size < 0) { 2308 error_report("could not load initial ram disk '%s'", 2309 initrd_filename); 2310 exit(1); 2311 } 2312 } 2313 } 2314 2315 if (bios_name == NULL) { 2316 bios_name = FW_FILE_NAME; 2317 } 2318 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2319 if (!filename) { 2320 error_report("Could not find LPAR firmware '%s'", bios_name); 2321 exit(1); 2322 } 2323 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2324 if (fw_size <= 0) { 2325 error_report("Could not load LPAR firmware '%s'", filename); 2326 exit(1); 2327 } 2328 g_free(filename); 2329 2330 /* FIXME: Should register things through the MachineState's qdev 2331 * interface, this is a legacy from the sPAPREnvironment structure 2332 * which predated MachineState but had a similar function */ 2333 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2334 register_savevm_live(NULL, "spapr/htab", -1, 1, 2335 &savevm_htab_handlers, spapr); 2336 2337 /* used by RTAS */ 2338 QTAILQ_INIT(&spapr->ccs_list); 2339 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2340 2341 qemu_register_boot_set(spapr_boot_set, spapr); 2342 2343 if (kvm_enabled()) { 2344 /* to stop and start vmclock */ 2345 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 2346 &spapr->tb); 2347 2348 kvmppc_spapr_enable_inkernel_multitce(); 2349 } 2350 } 2351 2352 static int spapr_kvm_type(const char *vm_type) 2353 { 2354 if (!vm_type) { 2355 return 0; 2356 } 2357 2358 if (!strcmp(vm_type, "HV")) { 2359 return 1; 2360 } 2361 2362 if (!strcmp(vm_type, "PR")) { 2363 return 2; 2364 } 2365 2366 error_report("Unknown kvm-type specified '%s'", vm_type); 2367 exit(1); 2368 } 2369 2370 /* 2371 * Implementation of an interface to adjust firmware path 2372 * for the bootindex property handling. 2373 */ 2374 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2375 DeviceState *dev) 2376 { 2377 #define CAST(type, obj, name) \ 2378 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2379 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2380 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2381 2382 if (d) { 2383 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2384 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2385 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2386 2387 if (spapr) { 2388 /* 2389 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2390 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2391 * in the top 16 bits of the 64-bit LUN 2392 */ 2393 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2394 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2395 (uint64_t)id << 48); 2396 } else if (virtio) { 2397 /* 2398 * We use SRP luns of the form 01000000 | (target << 8) | lun 2399 * in the top 32 bits of the 64-bit LUN 2400 * Note: the quote above is from SLOF and it is wrong, 2401 * the actual binding is: 2402 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2403 */ 2404 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2405 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2406 (uint64_t)id << 32); 2407 } else if (usb) { 2408 /* 2409 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2410 * in the top 32 bits of the 64-bit LUN 2411 */ 2412 unsigned usb_port = atoi(usb->port->path); 2413 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2414 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2415 (uint64_t)id << 32); 2416 } 2417 } 2418 2419 /* 2420 * SLOF probes the USB devices, and if it recognizes that the device is a 2421 * storage device, it changes its name to "storage" instead of "usb-host", 2422 * and additionally adds a child node for the SCSI LUN, so the correct 2423 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2424 */ 2425 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2426 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2427 if (usb_host_dev_is_scsi_storage(usbdev)) { 2428 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2429 } 2430 } 2431 2432 if (phb) { 2433 /* Replace "pci" with "pci@800000020000000" */ 2434 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2435 } 2436 2437 return NULL; 2438 } 2439 2440 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2441 { 2442 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2443 2444 return g_strdup(spapr->kvm_type); 2445 } 2446 2447 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2448 { 2449 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2450 2451 g_free(spapr->kvm_type); 2452 spapr->kvm_type = g_strdup(value); 2453 } 2454 2455 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2456 { 2457 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2458 2459 return spapr->use_hotplug_event_source; 2460 } 2461 2462 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2463 Error **errp) 2464 { 2465 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2466 2467 spapr->use_hotplug_event_source = value; 2468 } 2469 2470 static void spapr_machine_initfn(Object *obj) 2471 { 2472 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2473 2474 spapr->htab_fd = -1; 2475 spapr->use_hotplug_event_source = true; 2476 object_property_add_str(obj, "kvm-type", 2477 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2478 object_property_set_description(obj, "kvm-type", 2479 "Specifies the KVM virtualization mode (HV, PR)", 2480 NULL); 2481 object_property_add_bool(obj, "modern-hotplug-events", 2482 spapr_get_modern_hotplug_events, 2483 spapr_set_modern_hotplug_events, 2484 NULL); 2485 object_property_set_description(obj, "modern-hotplug-events", 2486 "Use dedicated hotplug event mechanism in" 2487 " place of standard EPOW events when possible" 2488 " (required for memory hot-unplug support)", 2489 NULL); 2490 } 2491 2492 static void spapr_machine_finalizefn(Object *obj) 2493 { 2494 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2495 2496 g_free(spapr->kvm_type); 2497 } 2498 2499 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2500 { 2501 cpu_synchronize_state(cs); 2502 ppc_cpu_do_system_reset(cs); 2503 } 2504 2505 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2506 { 2507 CPUState *cs; 2508 2509 CPU_FOREACH(cs) { 2510 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2511 } 2512 } 2513 2514 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2515 uint32_t node, bool dedicated_hp_event_source, 2516 Error **errp) 2517 { 2518 sPAPRDRConnector *drc; 2519 sPAPRDRConnectorClass *drck; 2520 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2521 int i, fdt_offset, fdt_size; 2522 void *fdt; 2523 uint64_t addr = addr_start; 2524 2525 for (i = 0; i < nr_lmbs; i++) { 2526 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2527 addr/SPAPR_MEMORY_BLOCK_SIZE); 2528 g_assert(drc); 2529 2530 fdt = create_device_tree(&fdt_size); 2531 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2532 SPAPR_MEMORY_BLOCK_SIZE); 2533 2534 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2535 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2536 addr += SPAPR_MEMORY_BLOCK_SIZE; 2537 if (!dev->hotplugged) { 2538 /* guests expect coldplugged LMBs to be pre-allocated */ 2539 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2540 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2541 } 2542 } 2543 /* send hotplug notification to the 2544 * guest only in case of hotplugged memory 2545 */ 2546 if (dev->hotplugged) { 2547 if (dedicated_hp_event_source) { 2548 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2549 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2550 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2551 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2552 nr_lmbs, 2553 drck->get_index(drc)); 2554 } else { 2555 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2556 nr_lmbs); 2557 } 2558 } 2559 } 2560 2561 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2562 uint32_t node, Error **errp) 2563 { 2564 Error *local_err = NULL; 2565 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2566 PCDIMMDevice *dimm = PC_DIMM(dev); 2567 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2568 MemoryRegion *mr = ddc->get_memory_region(dimm); 2569 uint64_t align = memory_region_get_alignment(mr); 2570 uint64_t size = memory_region_size(mr); 2571 uint64_t addr; 2572 char *mem_dev; 2573 2574 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2575 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2576 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2577 goto out; 2578 } 2579 2580 mem_dev = object_property_get_str(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, NULL); 2581 if (mem_dev && !kvmppc_is_mem_backend_page_size_ok(mem_dev)) { 2582 error_setg(&local_err, "Memory backend has bad page size. " 2583 "Use 'memory-backend-file' with correct mem-path."); 2584 goto out; 2585 } 2586 2587 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2588 if (local_err) { 2589 goto out; 2590 } 2591 2592 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2593 if (local_err) { 2594 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2595 goto out; 2596 } 2597 2598 spapr_add_lmbs(dev, addr, size, node, 2599 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2600 &error_abort); 2601 2602 out: 2603 error_propagate(errp, local_err); 2604 } 2605 2606 typedef struct sPAPRDIMMState { 2607 uint32_t nr_lmbs; 2608 } sPAPRDIMMState; 2609 2610 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2611 { 2612 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2613 HotplugHandler *hotplug_ctrl; 2614 2615 if (--ds->nr_lmbs) { 2616 return; 2617 } 2618 2619 g_free(ds); 2620 2621 /* 2622 * Now that all the LMBs have been removed by the guest, call the 2623 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2624 */ 2625 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2626 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2627 } 2628 2629 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2630 Error **errp) 2631 { 2632 sPAPRDRConnector *drc; 2633 sPAPRDRConnectorClass *drck; 2634 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2635 int i; 2636 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2637 uint64_t addr = addr_start; 2638 2639 ds->nr_lmbs = nr_lmbs; 2640 for (i = 0; i < nr_lmbs; i++) { 2641 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2642 addr / SPAPR_MEMORY_BLOCK_SIZE); 2643 g_assert(drc); 2644 2645 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2646 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2647 addr += SPAPR_MEMORY_BLOCK_SIZE; 2648 } 2649 2650 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2651 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2652 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2653 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2654 nr_lmbs, 2655 drck->get_index(drc)); 2656 } 2657 2658 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2659 Error **errp) 2660 { 2661 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2662 PCDIMMDevice *dimm = PC_DIMM(dev); 2663 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2664 MemoryRegion *mr = ddc->get_memory_region(dimm); 2665 2666 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2667 object_unparent(OBJECT(dev)); 2668 } 2669 2670 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2671 DeviceState *dev, Error **errp) 2672 { 2673 Error *local_err = NULL; 2674 PCDIMMDevice *dimm = PC_DIMM(dev); 2675 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2676 MemoryRegion *mr = ddc->get_memory_region(dimm); 2677 uint64_t size = memory_region_size(mr); 2678 uint64_t addr; 2679 2680 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2681 if (local_err) { 2682 goto out; 2683 } 2684 2685 spapr_del_lmbs(dev, addr, size, &error_abort); 2686 out: 2687 error_propagate(errp, local_err); 2688 } 2689 2690 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2691 sPAPRMachineState *spapr) 2692 { 2693 PowerPCCPU *cpu = POWERPC_CPU(cs); 2694 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2695 int id = ppc_get_vcpu_dt_id(cpu); 2696 void *fdt; 2697 int offset, fdt_size; 2698 char *nodename; 2699 2700 fdt = create_device_tree(&fdt_size); 2701 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2702 offset = fdt_add_subnode(fdt, 0, nodename); 2703 2704 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2705 g_free(nodename); 2706 2707 *fdt_offset = offset; 2708 return fdt; 2709 } 2710 2711 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2712 Error **errp) 2713 { 2714 MachineState *ms = MACHINE(qdev_get_machine()); 2715 CPUCore *cc = CPU_CORE(dev); 2716 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 2717 2718 core_slot->cpu = NULL; 2719 object_unparent(OBJECT(dev)); 2720 } 2721 2722 static void spapr_core_release(DeviceState *dev, void *opaque) 2723 { 2724 HotplugHandler *hotplug_ctrl; 2725 2726 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2727 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2728 } 2729 2730 static 2731 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 2732 Error **errp) 2733 { 2734 int index; 2735 sPAPRDRConnector *drc; 2736 sPAPRDRConnectorClass *drck; 2737 Error *local_err = NULL; 2738 CPUCore *cc = CPU_CORE(dev); 2739 int smt = kvmppc_smt_threads(); 2740 2741 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 2742 error_setg(errp, "Unable to find CPU core with core-id: %d", 2743 cc->core_id); 2744 return; 2745 } 2746 if (index == 0) { 2747 error_setg(errp, "Boot CPU core may not be unplugged"); 2748 return; 2749 } 2750 2751 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2752 g_assert(drc); 2753 2754 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2755 drck->detach(drc, dev, spapr_core_release, NULL, &local_err); 2756 if (local_err) { 2757 error_propagate(errp, local_err); 2758 return; 2759 } 2760 2761 spapr_hotplug_req_remove_by_index(drc); 2762 } 2763 2764 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2765 Error **errp) 2766 { 2767 sPAPRMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 2768 MachineClass *mc = MACHINE_GET_CLASS(spapr); 2769 sPAPRCPUCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 2770 CPUCore *cc = CPU_CORE(dev); 2771 CPUState *cs = CPU(core->threads); 2772 sPAPRDRConnector *drc; 2773 Error *local_err = NULL; 2774 void *fdt = NULL; 2775 int fdt_offset = 0; 2776 int smt = kvmppc_smt_threads(); 2777 CPUArchId *core_slot; 2778 int index; 2779 2780 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2781 if (!core_slot) { 2782 error_setg(errp, "Unable to find CPU core with core-id: %d", 2783 cc->core_id); 2784 return; 2785 } 2786 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index * smt); 2787 2788 g_assert(drc || !mc->has_hotpluggable_cpus); 2789 2790 /* 2791 * Setup CPU DT entries only for hotplugged CPUs. For boot time or 2792 * coldplugged CPUs DT entries are setup in spapr_build_fdt(). 2793 */ 2794 if (dev->hotplugged) { 2795 fdt = spapr_populate_hotplug_cpu_dt(cs, &fdt_offset, spapr); 2796 } 2797 2798 if (drc) { 2799 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2800 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, &local_err); 2801 if (local_err) { 2802 g_free(fdt); 2803 error_propagate(errp, local_err); 2804 return; 2805 } 2806 } 2807 2808 if (dev->hotplugged) { 2809 /* 2810 * Send hotplug notification interrupt to the guest only in case 2811 * of hotplugged CPUs. 2812 */ 2813 spapr_hotplug_req_add_by_index(drc); 2814 } else { 2815 /* 2816 * Set the right DRC states for cold plugged CPU. 2817 */ 2818 if (drc) { 2819 sPAPRDRConnectorClass *drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2820 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2821 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2822 } 2823 } 2824 core_slot->cpu = OBJECT(dev); 2825 } 2826 2827 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2828 Error **errp) 2829 { 2830 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 2831 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 2832 Error *local_err = NULL; 2833 CPUCore *cc = CPU_CORE(dev); 2834 sPAPRCPUCore *sc = SPAPR_CPU_CORE(dev); 2835 char *base_core_type = spapr_get_cpu_core_type(machine->cpu_model); 2836 const char *type = object_get_typename(OBJECT(dev)); 2837 CPUArchId *core_slot; 2838 int node_id; 2839 int index; 2840 2841 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 2842 error_setg(&local_err, "CPU hotplug not supported for this machine"); 2843 goto out; 2844 } 2845 2846 if (strcmp(base_core_type, type)) { 2847 error_setg(&local_err, "CPU core type should be %s", base_core_type); 2848 goto out; 2849 } 2850 2851 if (cc->core_id % smp_threads) { 2852 error_setg(&local_err, "invalid core id %d", cc->core_id); 2853 goto out; 2854 } 2855 2856 if (cc->nr_threads != smp_threads) { 2857 error_setg(errp, "invalid nr-threads %d, must be %d", 2858 cc->nr_threads, smp_threads); 2859 return; 2860 } 2861 2862 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 2863 if (!core_slot) { 2864 error_setg(&local_err, "core id %d out of range", cc->core_id); 2865 goto out; 2866 } 2867 2868 if (core_slot->cpu) { 2869 error_setg(&local_err, "core %d already populated", cc->core_id); 2870 goto out; 2871 } 2872 2873 node_id = core_slot->props.node_id; 2874 if (!core_slot->props.has_node_id) { 2875 /* by default CPUState::numa_node was 0 if it's not set via CLI 2876 * keep it this way for now but in future we probably should 2877 * refuse to start up with incomplete numa mapping */ 2878 node_id = 0; 2879 } 2880 if (sc->node_id == CPU_UNSET_NUMA_NODE_ID) { 2881 sc->node_id = node_id; 2882 } else if (sc->node_id != node_id) { 2883 error_setg(&local_err, "node-id %d must match numa node specified" 2884 "with -numa option for cpu-index %d", sc->node_id, cc->core_id); 2885 goto out; 2886 } 2887 2888 out: 2889 g_free(base_core_type); 2890 error_propagate(errp, local_err); 2891 } 2892 2893 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2894 DeviceState *dev, Error **errp) 2895 { 2896 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2897 2898 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2899 int node; 2900 2901 if (!smc->dr_lmb_enabled) { 2902 error_setg(errp, "Memory hotplug not supported for this machine"); 2903 return; 2904 } 2905 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2906 if (*errp) { 2907 return; 2908 } 2909 if (node < 0 || node >= MAX_NODES) { 2910 error_setg(errp, "Invaild node %d", node); 2911 return; 2912 } 2913 2914 /* 2915 * Currently PowerPC kernel doesn't allow hot-adding memory to 2916 * memory-less node, but instead will silently add the memory 2917 * to the first node that has some memory. This causes two 2918 * unexpected behaviours for the user. 2919 * 2920 * - Memory gets hotplugged to a different node than what the user 2921 * specified. 2922 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2923 * to memory-less node, a reboot will set things accordingly 2924 * and the previously hotplugged memory now ends in the right node. 2925 * This appears as if some memory moved from one node to another. 2926 * 2927 * So until kernel starts supporting memory hotplug to memory-less 2928 * nodes, just prevent such attempts upfront in QEMU. 2929 */ 2930 if (nb_numa_nodes && !numa_info[node].node_mem) { 2931 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2932 node); 2933 return; 2934 } 2935 2936 spapr_memory_plug(hotplug_dev, dev, node, errp); 2937 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2938 spapr_core_plug(hotplug_dev, dev, errp); 2939 } 2940 } 2941 2942 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2943 DeviceState *dev, Error **errp) 2944 { 2945 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2946 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2947 2948 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2949 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2950 spapr_memory_unplug(hotplug_dev, dev, errp); 2951 } else { 2952 error_setg(errp, "Memory hot unplug not supported for this guest"); 2953 } 2954 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2955 if (!mc->has_hotpluggable_cpus) { 2956 error_setg(errp, "CPU hot unplug not supported on this machine"); 2957 return; 2958 } 2959 spapr_core_unplug(hotplug_dev, dev, errp); 2960 } 2961 } 2962 2963 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2964 DeviceState *dev, Error **errp) 2965 { 2966 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2967 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2968 2969 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2970 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2971 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2972 } else { 2973 /* NOTE: this means there is a window after guest reset, prior to 2974 * CAS negotiation, where unplug requests will fail due to the 2975 * capability not being detected yet. This is a bit different than 2976 * the case with PCI unplug, where the events will be queued and 2977 * eventually handled by the guest after boot 2978 */ 2979 error_setg(errp, "Memory hot unplug not supported for this guest"); 2980 } 2981 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2982 if (!mc->has_hotpluggable_cpus) { 2983 error_setg(errp, "CPU hot unplug not supported on this machine"); 2984 return; 2985 } 2986 spapr_core_unplug_request(hotplug_dev, dev, errp); 2987 } 2988 } 2989 2990 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2991 DeviceState *dev, Error **errp) 2992 { 2993 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2994 spapr_core_pre_plug(hotplug_dev, dev, errp); 2995 } 2996 } 2997 2998 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2999 DeviceState *dev) 3000 { 3001 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 3002 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 3003 return HOTPLUG_HANDLER(machine); 3004 } 3005 return NULL; 3006 } 3007 3008 static CpuInstanceProperties 3009 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 3010 { 3011 CPUArchId *core_slot; 3012 MachineClass *mc = MACHINE_GET_CLASS(machine); 3013 3014 /* make sure possible_cpu are intialized */ 3015 mc->possible_cpu_arch_ids(machine); 3016 /* get CPU core slot containing thread that matches cpu_index */ 3017 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 3018 assert(core_slot); 3019 return core_slot->props; 3020 } 3021 3022 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 3023 { 3024 int i; 3025 int spapr_max_cores = max_cpus / smp_threads; 3026 MachineClass *mc = MACHINE_GET_CLASS(machine); 3027 3028 if (!mc->has_hotpluggable_cpus) { 3029 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 3030 } 3031 if (machine->possible_cpus) { 3032 assert(machine->possible_cpus->len == spapr_max_cores); 3033 return machine->possible_cpus; 3034 } 3035 3036 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 3037 sizeof(CPUArchId) * spapr_max_cores); 3038 machine->possible_cpus->len = spapr_max_cores; 3039 for (i = 0; i < machine->possible_cpus->len; i++) { 3040 int core_id = i * smp_threads; 3041 3042 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 3043 machine->possible_cpus->cpus[i].arch_id = core_id; 3044 machine->possible_cpus->cpus[i].props.has_core_id = true; 3045 machine->possible_cpus->cpus[i].props.core_id = core_id; 3046 3047 /* default distribution of CPUs over NUMA nodes */ 3048 if (nb_numa_nodes) { 3049 /* preset values but do not enable them i.e. 'has_node_id = false', 3050 * numa init code will enable them later if manual mapping wasn't 3051 * present on CLI */ 3052 machine->possible_cpus->cpus[i].props.node_id = 3053 core_id / smp_threads / smp_cores % nb_numa_nodes; 3054 } 3055 } 3056 return machine->possible_cpus; 3057 } 3058 3059 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 3060 uint64_t *buid, hwaddr *pio, 3061 hwaddr *mmio32, hwaddr *mmio64, 3062 unsigned n_dma, uint32_t *liobns, Error **errp) 3063 { 3064 /* 3065 * New-style PHB window placement. 3066 * 3067 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 3068 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 3069 * windows. 3070 * 3071 * Some guest kernels can't work with MMIO windows above 1<<46 3072 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 3073 * 3074 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 3075 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 3076 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 3077 * 1TiB 64-bit MMIO windows for each PHB. 3078 */ 3079 const uint64_t base_buid = 0x800000020000000ULL; 3080 #define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \ 3081 SPAPR_PCI_MEM64_WIN_SIZE - 1) 3082 int i; 3083 3084 /* Sanity check natural alignments */ 3085 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3086 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 3087 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 3088 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 3089 /* Sanity check bounds */ 3090 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 3091 SPAPR_PCI_MEM32_WIN_SIZE); 3092 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 3093 SPAPR_PCI_MEM64_WIN_SIZE); 3094 3095 if (index >= SPAPR_MAX_PHBS) { 3096 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 3097 SPAPR_MAX_PHBS - 1); 3098 return; 3099 } 3100 3101 *buid = base_buid + index; 3102 for (i = 0; i < n_dma; ++i) { 3103 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3104 } 3105 3106 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 3107 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 3108 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 3109 } 3110 3111 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 3112 { 3113 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3114 3115 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 3116 } 3117 3118 static void spapr_ics_resend(XICSFabric *dev) 3119 { 3120 sPAPRMachineState *spapr = SPAPR_MACHINE(dev); 3121 3122 ics_resend(spapr->ics); 3123 } 3124 3125 static ICPState *spapr_icp_get(XICSFabric *xi, int cpu_dt_id) 3126 { 3127 PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id); 3128 3129 return cpu ? ICP(cpu->intc) : NULL; 3130 } 3131 3132 static void spapr_pic_print_info(InterruptStatsProvider *obj, 3133 Monitor *mon) 3134 { 3135 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 3136 CPUState *cs; 3137 3138 CPU_FOREACH(cs) { 3139 PowerPCCPU *cpu = POWERPC_CPU(cs); 3140 3141 icp_pic_print_info(ICP(cpu->intc), mon); 3142 } 3143 3144 ics_pic_print_info(spapr->ics, mon); 3145 } 3146 3147 static void spapr_machine_class_init(ObjectClass *oc, void *data) 3148 { 3149 MachineClass *mc = MACHINE_CLASS(oc); 3150 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 3151 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 3152 NMIClass *nc = NMI_CLASS(oc); 3153 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 3154 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 3155 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 3156 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 3157 3158 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 3159 3160 /* 3161 * We set up the default / latest behaviour here. The class_init 3162 * functions for the specific versioned machine types can override 3163 * these details for backwards compatibility 3164 */ 3165 mc->init = ppc_spapr_init; 3166 mc->reset = ppc_spapr_reset; 3167 mc->block_default_type = IF_SCSI; 3168 mc->max_cpus = 1024; 3169 mc->no_parallel = 1; 3170 mc->default_boot_order = ""; 3171 mc->default_ram_size = 512 * M_BYTE; 3172 mc->kvm_type = spapr_kvm_type; 3173 mc->has_dynamic_sysbus = true; 3174 mc->pci_allow_0_address = true; 3175 mc->get_hotplug_handler = spapr_get_hotplug_handler; 3176 hc->pre_plug = spapr_machine_device_pre_plug; 3177 hc->plug = spapr_machine_device_plug; 3178 hc->unplug = spapr_machine_device_unplug; 3179 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 3180 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 3181 hc->unplug_request = spapr_machine_device_unplug_request; 3182 3183 smc->dr_lmb_enabled = true; 3184 smc->tcg_default_cpu = "POWER8"; 3185 mc->has_hotpluggable_cpus = true; 3186 fwc->get_dev_path = spapr_get_fw_dev_path; 3187 nc->nmi_monitor_handler = spapr_nmi; 3188 smc->phb_placement = spapr_phb_placement; 3189 vhc->hypercall = emulate_spapr_hypercall; 3190 vhc->hpt_mask = spapr_hpt_mask; 3191 vhc->map_hptes = spapr_map_hptes; 3192 vhc->unmap_hptes = spapr_unmap_hptes; 3193 vhc->store_hpte = spapr_store_hpte; 3194 vhc->get_patbe = spapr_get_patbe; 3195 xic->ics_get = spapr_ics_get; 3196 xic->ics_resend = spapr_ics_resend; 3197 xic->icp_get = spapr_icp_get; 3198 ispc->print_info = spapr_pic_print_info; 3199 /* Force NUMA node memory size to be a multiple of 3200 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 3201 * in which LMBs are represented and hot-added 3202 */ 3203 mc->numa_mem_align_shift = 28; 3204 } 3205 3206 static const TypeInfo spapr_machine_info = { 3207 .name = TYPE_SPAPR_MACHINE, 3208 .parent = TYPE_MACHINE, 3209 .abstract = true, 3210 .instance_size = sizeof(sPAPRMachineState), 3211 .instance_init = spapr_machine_initfn, 3212 .instance_finalize = spapr_machine_finalizefn, 3213 .class_size = sizeof(sPAPRMachineClass), 3214 .class_init = spapr_machine_class_init, 3215 .interfaces = (InterfaceInfo[]) { 3216 { TYPE_FW_PATH_PROVIDER }, 3217 { TYPE_NMI }, 3218 { TYPE_HOTPLUG_HANDLER }, 3219 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 3220 { TYPE_XICS_FABRIC }, 3221 { TYPE_INTERRUPT_STATS_PROVIDER }, 3222 { } 3223 }, 3224 }; 3225 3226 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 3227 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 3228 void *data) \ 3229 { \ 3230 MachineClass *mc = MACHINE_CLASS(oc); \ 3231 spapr_machine_##suffix##_class_options(mc); \ 3232 if (latest) { \ 3233 mc->alias = "pseries"; \ 3234 mc->is_default = 1; \ 3235 } \ 3236 } \ 3237 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 3238 { \ 3239 MachineState *machine = MACHINE(obj); \ 3240 spapr_machine_##suffix##_instance_options(machine); \ 3241 } \ 3242 static const TypeInfo spapr_machine_##suffix##_info = { \ 3243 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 3244 .parent = TYPE_SPAPR_MACHINE, \ 3245 .class_init = spapr_machine_##suffix##_class_init, \ 3246 .instance_init = spapr_machine_##suffix##_instance_init, \ 3247 }; \ 3248 static void spapr_machine_register_##suffix(void) \ 3249 { \ 3250 type_register(&spapr_machine_##suffix##_info); \ 3251 } \ 3252 type_init(spapr_machine_register_##suffix) 3253 3254 /* 3255 * pseries-2.10 3256 */ 3257 static void spapr_machine_2_10_instance_options(MachineState *machine) 3258 { 3259 } 3260 3261 static void spapr_machine_2_10_class_options(MachineClass *mc) 3262 { 3263 /* Defaults for the latest behaviour inherited from the base class */ 3264 } 3265 3266 DEFINE_SPAPR_MACHINE(2_10, "2.10", true); 3267 3268 /* 3269 * pseries-2.9 3270 */ 3271 #define SPAPR_COMPAT_2_9 \ 3272 HW_COMPAT_2_9 3273 3274 static void spapr_machine_2_9_instance_options(MachineState *machine) 3275 { 3276 spapr_machine_2_10_instance_options(machine); 3277 } 3278 3279 static void spapr_machine_2_9_class_options(MachineClass *mc) 3280 { 3281 spapr_machine_2_10_class_options(mc); 3282 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_9); 3283 mc->numa_auto_assign_ram = numa_legacy_auto_assign_ram; 3284 } 3285 3286 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 3287 3288 /* 3289 * pseries-2.8 3290 */ 3291 #define SPAPR_COMPAT_2_8 \ 3292 HW_COMPAT_2_8 \ 3293 { \ 3294 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3295 .property = "pcie-extended-configuration-space", \ 3296 .value = "off", \ 3297 }, 3298 3299 static void spapr_machine_2_8_instance_options(MachineState *machine) 3300 { 3301 spapr_machine_2_9_instance_options(machine); 3302 } 3303 3304 static void spapr_machine_2_8_class_options(MachineClass *mc) 3305 { 3306 spapr_machine_2_9_class_options(mc); 3307 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 3308 mc->numa_mem_align_shift = 23; 3309 } 3310 3311 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 3312 3313 /* 3314 * pseries-2.7 3315 */ 3316 #define SPAPR_COMPAT_2_7 \ 3317 HW_COMPAT_2_7 \ 3318 { \ 3319 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3320 .property = "mem_win_size", \ 3321 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 3322 }, \ 3323 { \ 3324 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3325 .property = "mem64_win_size", \ 3326 .value = "0", \ 3327 }, \ 3328 { \ 3329 .driver = TYPE_POWERPC_CPU, \ 3330 .property = "pre-2.8-migration", \ 3331 .value = "on", \ 3332 }, \ 3333 { \ 3334 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 3335 .property = "pre-2.8-migration", \ 3336 .value = "on", \ 3337 }, 3338 3339 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 3340 uint64_t *buid, hwaddr *pio, 3341 hwaddr *mmio32, hwaddr *mmio64, 3342 unsigned n_dma, uint32_t *liobns, Error **errp) 3343 { 3344 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 3345 const uint64_t base_buid = 0x800000020000000ULL; 3346 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 3347 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 3348 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 3349 const uint32_t max_index = 255; 3350 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 3351 3352 uint64_t ram_top = MACHINE(spapr)->ram_size; 3353 hwaddr phb0_base, phb_base; 3354 int i; 3355 3356 /* Do we have hotpluggable memory? */ 3357 if (MACHINE(spapr)->maxram_size > ram_top) { 3358 /* Can't just use maxram_size, because there may be an 3359 * alignment gap between normal and hotpluggable memory 3360 * regions */ 3361 ram_top = spapr->hotplug_memory.base + 3362 memory_region_size(&spapr->hotplug_memory.mr); 3363 } 3364 3365 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 3366 3367 if (index > max_index) { 3368 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 3369 max_index); 3370 return; 3371 } 3372 3373 *buid = base_buid + index; 3374 for (i = 0; i < n_dma; ++i) { 3375 liobns[i] = SPAPR_PCI_LIOBN(index, i); 3376 } 3377 3378 phb_base = phb0_base + index * phb_spacing; 3379 *pio = phb_base + pio_offset; 3380 *mmio32 = phb_base + mmio_offset; 3381 /* 3382 * We don't set the 64-bit MMIO window, relying on the PHB's 3383 * fallback behaviour of automatically splitting a large "32-bit" 3384 * window into contiguous 32-bit and 64-bit windows 3385 */ 3386 } 3387 3388 static void spapr_machine_2_7_instance_options(MachineState *machine) 3389 { 3390 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 3391 3392 spapr_machine_2_8_instance_options(machine); 3393 spapr->use_hotplug_event_source = false; 3394 } 3395 3396 static void spapr_machine_2_7_class_options(MachineClass *mc) 3397 { 3398 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3399 3400 spapr_machine_2_8_class_options(mc); 3401 smc->tcg_default_cpu = "POWER7"; 3402 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 3403 smc->phb_placement = phb_placement_2_7; 3404 } 3405 3406 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 3407 3408 /* 3409 * pseries-2.6 3410 */ 3411 #define SPAPR_COMPAT_2_6 \ 3412 HW_COMPAT_2_6 \ 3413 { \ 3414 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3415 .property = "ddw",\ 3416 .value = stringify(off),\ 3417 }, 3418 3419 static void spapr_machine_2_6_instance_options(MachineState *machine) 3420 { 3421 spapr_machine_2_7_instance_options(machine); 3422 } 3423 3424 static void spapr_machine_2_6_class_options(MachineClass *mc) 3425 { 3426 spapr_machine_2_7_class_options(mc); 3427 mc->has_hotpluggable_cpus = false; 3428 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 3429 } 3430 3431 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 3432 3433 /* 3434 * pseries-2.5 3435 */ 3436 #define SPAPR_COMPAT_2_5 \ 3437 HW_COMPAT_2_5 \ 3438 { \ 3439 .driver = "spapr-vlan", \ 3440 .property = "use-rx-buffer-pools", \ 3441 .value = "off", \ 3442 }, 3443 3444 static void spapr_machine_2_5_instance_options(MachineState *machine) 3445 { 3446 spapr_machine_2_6_instance_options(machine); 3447 } 3448 3449 static void spapr_machine_2_5_class_options(MachineClass *mc) 3450 { 3451 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3452 3453 spapr_machine_2_6_class_options(mc); 3454 smc->use_ohci_by_default = true; 3455 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 3456 } 3457 3458 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 3459 3460 /* 3461 * pseries-2.4 3462 */ 3463 #define SPAPR_COMPAT_2_4 \ 3464 HW_COMPAT_2_4 3465 3466 static void spapr_machine_2_4_instance_options(MachineState *machine) 3467 { 3468 spapr_machine_2_5_instance_options(machine); 3469 } 3470 3471 static void spapr_machine_2_4_class_options(MachineClass *mc) 3472 { 3473 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3474 3475 spapr_machine_2_5_class_options(mc); 3476 smc->dr_lmb_enabled = false; 3477 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 3478 } 3479 3480 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 3481 3482 /* 3483 * pseries-2.3 3484 */ 3485 #define SPAPR_COMPAT_2_3 \ 3486 HW_COMPAT_2_3 \ 3487 {\ 3488 .driver = "spapr-pci-host-bridge",\ 3489 .property = "dynamic-reconfiguration",\ 3490 .value = "off",\ 3491 }, 3492 3493 static void spapr_machine_2_3_instance_options(MachineState *machine) 3494 { 3495 spapr_machine_2_4_instance_options(machine); 3496 savevm_skip_section_footers(); 3497 global_state_set_optional(); 3498 savevm_skip_configuration(); 3499 } 3500 3501 static void spapr_machine_2_3_class_options(MachineClass *mc) 3502 { 3503 spapr_machine_2_4_class_options(mc); 3504 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3505 } 3506 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3507 3508 /* 3509 * pseries-2.2 3510 */ 3511 3512 #define SPAPR_COMPAT_2_2 \ 3513 HW_COMPAT_2_2 \ 3514 {\ 3515 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3516 .property = "mem_win_size",\ 3517 .value = "0x20000000",\ 3518 }, 3519 3520 static void spapr_machine_2_2_instance_options(MachineState *machine) 3521 { 3522 spapr_machine_2_3_instance_options(machine); 3523 machine->suppress_vmdesc = true; 3524 } 3525 3526 static void spapr_machine_2_2_class_options(MachineClass *mc) 3527 { 3528 spapr_machine_2_3_class_options(mc); 3529 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3530 } 3531 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3532 3533 /* 3534 * pseries-2.1 3535 */ 3536 #define SPAPR_COMPAT_2_1 \ 3537 HW_COMPAT_2_1 3538 3539 static void spapr_machine_2_1_instance_options(MachineState *machine) 3540 { 3541 spapr_machine_2_2_instance_options(machine); 3542 } 3543 3544 static void spapr_machine_2_1_class_options(MachineClass *mc) 3545 { 3546 spapr_machine_2_2_class_options(mc); 3547 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3548 } 3549 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3550 3551 static void spapr_machine_register_types(void) 3552 { 3553 type_register_static(&spapr_machine_info); 3554 } 3555 3556 type_init(spapr_machine_register_types) 3557