1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/kvm.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(const char *type, int nr_servers, 99 int nr_irqs, Error **errp) 100 { 101 Error *err = NULL; 102 DeviceState *dev; 103 104 dev = qdev_create(NULL, type); 105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 107 object_property_set_bool(OBJECT(dev), true, "realized", &err); 108 if (err) { 109 error_propagate(errp, err); 110 object_unparent(OBJECT(dev)); 111 return NULL; 112 } 113 return XICS_COMMON(dev); 114 } 115 116 static XICSState *xics_system_init(MachineState *machine, 117 int nr_servers, int nr_irqs, Error **errp) 118 { 119 XICSState *xics = NULL; 120 121 if (kvm_enabled()) { 122 Error *err = NULL; 123 124 if (machine_kernel_irqchip_allowed(machine)) { 125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, 126 &err); 127 } 128 if (machine_kernel_irqchip_required(machine) && !xics) { 129 error_reportf_err(err, 130 "kernel_irqchip requested but unavailable: "); 131 } else { 132 error_free(err); 133 } 134 } 135 136 if (!xics) { 137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); 138 } 139 140 return xics; 141 } 142 143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 144 int smt_threads) 145 { 146 int i, ret = 0; 147 uint32_t servers_prop[smt_threads]; 148 uint32_t gservers_prop[smt_threads * 2]; 149 int index = ppc_get_vcpu_dt_id(cpu); 150 151 if (cpu->cpu_version) { 152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 153 if (ret < 0) { 154 return ret; 155 } 156 } 157 158 /* Build interrupt servers and gservers properties */ 159 for (i = 0; i < smt_threads; i++) { 160 servers_prop[i] = cpu_to_be32(index + i); 161 /* Hack, direct the group queues back to cpu 0 */ 162 gservers_prop[i*2] = cpu_to_be32(index + i); 163 gservers_prop[i*2 + 1] = 0; 164 } 165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 166 servers_prop, sizeof(servers_prop)); 167 if (ret < 0) { 168 return ret; 169 } 170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 171 gservers_prop, sizeof(gservers_prop)); 172 173 return ret; 174 } 175 176 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 177 { 178 int ret = 0; 179 PowerPCCPU *cpu = POWERPC_CPU(cs); 180 int index = ppc_get_vcpu_dt_id(cpu); 181 uint32_t associativity[] = {cpu_to_be32(0x5), 182 cpu_to_be32(0x0), 183 cpu_to_be32(0x0), 184 cpu_to_be32(0x0), 185 cpu_to_be32(cs->numa_node), 186 cpu_to_be32(index)}; 187 188 /* Advertise NUMA via ibm,associativity */ 189 if (nb_numa_nodes > 1) { 190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 191 sizeof(associativity)); 192 } 193 194 return ret; 195 } 196 197 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 198 { 199 int ret = 0, offset, cpus_offset; 200 CPUState *cs; 201 char cpu_model[32]; 202 int smt = kvmppc_smt_threads(); 203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 204 205 CPU_FOREACH(cs) { 206 PowerPCCPU *cpu = POWERPC_CPU(cs); 207 DeviceClass *dc = DEVICE_GET_CLASS(cs); 208 int index = ppc_get_vcpu_dt_id(cpu); 209 210 if ((index % smt) != 0) { 211 continue; 212 } 213 214 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 215 216 cpus_offset = fdt_path_offset(fdt, "/cpus"); 217 if (cpus_offset < 0) { 218 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 219 "cpus"); 220 if (cpus_offset < 0) { 221 return cpus_offset; 222 } 223 } 224 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 225 if (offset < 0) { 226 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 227 if (offset < 0) { 228 return offset; 229 } 230 } 231 232 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 233 pft_size_prop, sizeof(pft_size_prop)); 234 if (ret < 0) { 235 return ret; 236 } 237 238 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 239 if (ret < 0) { 240 return ret; 241 } 242 243 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 244 ppc_get_compat_smt_threads(cpu)); 245 if (ret < 0) { 246 return ret; 247 } 248 } 249 return ret; 250 } 251 252 static hwaddr spapr_node0_size(void) 253 { 254 MachineState *machine = MACHINE(qdev_get_machine()); 255 256 if (nb_numa_nodes) { 257 int i; 258 for (i = 0; i < nb_numa_nodes; ++i) { 259 if (numa_info[i].node_mem) { 260 return MIN(pow2floor(numa_info[i].node_mem), 261 machine->ram_size); 262 } 263 } 264 } 265 return machine->ram_size; 266 } 267 268 static void add_str(GString *s, const gchar *s1) 269 { 270 g_string_append_len(s, s1, strlen(s1) + 1); 271 } 272 273 static void *spapr_create_fdt_skel(hwaddr initrd_base, 274 hwaddr initrd_size, 275 hwaddr kernel_size, 276 bool little_endian, 277 const char *kernel_cmdline, 278 uint32_t epow_irq) 279 { 280 void *fdt; 281 uint32_t start_prop = cpu_to_be32(initrd_base); 282 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 283 GString *hypertas = g_string_sized_new(256); 284 GString *qemu_hypertas = g_string_sized_new(256); 285 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 286 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 287 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 288 char *buf; 289 290 add_str(hypertas, "hcall-pft"); 291 add_str(hypertas, "hcall-term"); 292 add_str(hypertas, "hcall-dabr"); 293 add_str(hypertas, "hcall-interrupt"); 294 add_str(hypertas, "hcall-tce"); 295 add_str(hypertas, "hcall-vio"); 296 add_str(hypertas, "hcall-splpar"); 297 add_str(hypertas, "hcall-bulk"); 298 add_str(hypertas, "hcall-set-mode"); 299 add_str(hypertas, "hcall-sprg0"); 300 add_str(hypertas, "hcall-copy"); 301 add_str(hypertas, "hcall-debug"); 302 add_str(qemu_hypertas, "hcall-memop1"); 303 304 fdt = g_malloc0(FDT_MAX_SIZE); 305 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 306 307 if (kernel_size) { 308 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 309 } 310 if (initrd_size) { 311 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 312 } 313 _FDT((fdt_finish_reservemap(fdt))); 314 315 /* Root node */ 316 _FDT((fdt_begin_node(fdt, ""))); 317 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 318 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 319 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 320 321 /* 322 * Add info to guest to indentify which host is it being run on 323 * and what is the uuid of the guest 324 */ 325 if (kvmppc_get_host_model(&buf)) { 326 _FDT((fdt_property_string(fdt, "host-model", buf))); 327 g_free(buf); 328 } 329 if (kvmppc_get_host_serial(&buf)) { 330 _FDT((fdt_property_string(fdt, "host-serial", buf))); 331 g_free(buf); 332 } 333 334 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 335 336 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 337 if (qemu_uuid_set) { 338 _FDT((fdt_property_string(fdt, "system-id", buf))); 339 } 340 g_free(buf); 341 342 if (qemu_get_vm_name()) { 343 _FDT((fdt_property_string(fdt, "ibm,partition-name", 344 qemu_get_vm_name()))); 345 } 346 347 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 348 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 349 350 /* /chosen */ 351 _FDT((fdt_begin_node(fdt, "chosen"))); 352 353 /* Set Form1_affinity */ 354 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 355 356 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 357 _FDT((fdt_property(fdt, "linux,initrd-start", 358 &start_prop, sizeof(start_prop)))); 359 _FDT((fdt_property(fdt, "linux,initrd-end", 360 &end_prop, sizeof(end_prop)))); 361 if (kernel_size) { 362 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 363 cpu_to_be64(kernel_size) }; 364 365 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 366 if (little_endian) { 367 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 368 } 369 } 370 if (boot_menu) { 371 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 372 } 373 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 374 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 375 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 376 377 _FDT((fdt_end_node(fdt))); 378 379 /* RTAS */ 380 _FDT((fdt_begin_node(fdt, "rtas"))); 381 382 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 383 add_str(hypertas, "hcall-multi-tce"); 384 } 385 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 386 hypertas->len))); 387 g_string_free(hypertas, TRUE); 388 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 389 qemu_hypertas->len))); 390 g_string_free(qemu_hypertas, TRUE); 391 392 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 393 refpoints, sizeof(refpoints)))); 394 395 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 396 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 397 RTAS_EVENT_SCAN_RATE))); 398 399 if (msi_nonbroken) { 400 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 401 } 402 403 /* 404 * According to PAPR, rtas ibm,os-term does not guarantee a return 405 * back to the guest cpu. 406 * 407 * While an additional ibm,extended-os-term property indicates that 408 * rtas call return will always occur. Set this property. 409 */ 410 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 411 412 _FDT((fdt_end_node(fdt))); 413 414 /* interrupt controller */ 415 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 416 417 _FDT((fdt_property_string(fdt, "device_type", 418 "PowerPC-External-Interrupt-Presentation"))); 419 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 420 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 421 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 422 interrupt_server_ranges_prop, 423 sizeof(interrupt_server_ranges_prop)))); 424 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 425 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 426 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 427 428 _FDT((fdt_end_node(fdt))); 429 430 /* vdevice */ 431 _FDT((fdt_begin_node(fdt, "vdevice"))); 432 433 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 434 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 435 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 436 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 437 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 438 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 439 440 _FDT((fdt_end_node(fdt))); 441 442 /* event-sources */ 443 spapr_events_fdt_skel(fdt, epow_irq); 444 445 /* /hypervisor node */ 446 if (kvm_enabled()) { 447 uint8_t hypercall[16]; 448 449 /* indicate KVM hypercall interface */ 450 _FDT((fdt_begin_node(fdt, "hypervisor"))); 451 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 452 if (kvmppc_has_cap_fixup_hcalls()) { 453 /* 454 * Older KVM versions with older guest kernels were broken with the 455 * magic page, don't allow the guest to map it. 456 */ 457 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 458 sizeof(hypercall))) { 459 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 460 sizeof(hypercall)))); 461 } 462 } 463 _FDT((fdt_end_node(fdt))); 464 } 465 466 _FDT((fdt_end_node(fdt))); /* close root node */ 467 _FDT((fdt_finish(fdt))); 468 469 return fdt; 470 } 471 472 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 473 hwaddr size) 474 { 475 uint32_t associativity[] = { 476 cpu_to_be32(0x4), /* length */ 477 cpu_to_be32(0x0), cpu_to_be32(0x0), 478 cpu_to_be32(0x0), cpu_to_be32(nodeid) 479 }; 480 char mem_name[32]; 481 uint64_t mem_reg_property[2]; 482 int off; 483 484 mem_reg_property[0] = cpu_to_be64(start); 485 mem_reg_property[1] = cpu_to_be64(size); 486 487 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 488 off = fdt_add_subnode(fdt, 0, mem_name); 489 _FDT(off); 490 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 491 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 492 sizeof(mem_reg_property)))); 493 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 494 sizeof(associativity)))); 495 return off; 496 } 497 498 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 499 { 500 MachineState *machine = MACHINE(spapr); 501 hwaddr mem_start, node_size; 502 int i, nb_nodes = nb_numa_nodes; 503 NodeInfo *nodes = numa_info; 504 NodeInfo ramnode; 505 506 /* No NUMA nodes, assume there is just one node with whole RAM */ 507 if (!nb_numa_nodes) { 508 nb_nodes = 1; 509 ramnode.node_mem = machine->ram_size; 510 nodes = &ramnode; 511 } 512 513 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 514 if (!nodes[i].node_mem) { 515 continue; 516 } 517 if (mem_start >= machine->ram_size) { 518 node_size = 0; 519 } else { 520 node_size = nodes[i].node_mem; 521 if (node_size > machine->ram_size - mem_start) { 522 node_size = machine->ram_size - mem_start; 523 } 524 } 525 if (!mem_start) { 526 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 527 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 528 mem_start += spapr->rma_size; 529 node_size -= spapr->rma_size; 530 } 531 for ( ; node_size; ) { 532 hwaddr sizetmp = pow2floor(node_size); 533 534 /* mem_start != 0 here */ 535 if (ctzl(mem_start) < ctzl(sizetmp)) { 536 sizetmp = 1ULL << ctzl(mem_start); 537 } 538 539 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 540 node_size -= sizetmp; 541 mem_start += sizetmp; 542 } 543 } 544 545 return 0; 546 } 547 548 /* Populate the "ibm,pa-features" property */ 549 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 550 { 551 uint8_t pa_features_206[] = { 6, 0, 552 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 553 uint8_t pa_features_207[] = { 24, 0, 554 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 555 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 556 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 557 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 558 uint8_t *pa_features; 559 size_t pa_size; 560 561 switch (env->mmu_model) { 562 case POWERPC_MMU_2_06: 563 case POWERPC_MMU_2_06a: 564 pa_features = pa_features_206; 565 pa_size = sizeof(pa_features_206); 566 break; 567 case POWERPC_MMU_2_07: 568 case POWERPC_MMU_2_07a: 569 pa_features = pa_features_207; 570 pa_size = sizeof(pa_features_207); 571 break; 572 default: 573 return; 574 } 575 576 if (env->ci_large_pages) { 577 /* 578 * Note: we keep CI large pages off by default because a 64K capable 579 * guest provisioned with large pages might otherwise try to map a qemu 580 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 581 * even if that qemu runs on a 4k host. 582 * We dd this bit back here if we are confident this is not an issue 583 */ 584 pa_features[3] |= 0x20; 585 } 586 if (kvmppc_has_cap_htm() && pa_size > 24) { 587 pa_features[24] |= 0x80; /* Transactional memory support */ 588 } 589 590 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 591 } 592 593 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 594 sPAPRMachineState *spapr) 595 { 596 PowerPCCPU *cpu = POWERPC_CPU(cs); 597 CPUPPCState *env = &cpu->env; 598 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 599 int index = ppc_get_vcpu_dt_id(cpu); 600 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 601 0xffffffff, 0xffffffff}; 602 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 603 : SPAPR_TIMEBASE_FREQ; 604 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 605 uint32_t page_sizes_prop[64]; 606 size_t page_sizes_prop_size; 607 uint32_t vcpus_per_socket = smp_threads * smp_cores; 608 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 609 sPAPRDRConnector *drc; 610 sPAPRDRConnectorClass *drck; 611 int drc_index; 612 613 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 614 if (drc) { 615 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 616 drc_index = drck->get_index(drc); 617 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 618 } 619 620 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 621 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 622 623 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 624 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 625 env->dcache_line_size))); 626 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 627 env->dcache_line_size))); 628 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 629 env->icache_line_size))); 630 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 631 env->icache_line_size))); 632 633 if (pcc->l1_dcache_size) { 634 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 635 pcc->l1_dcache_size))); 636 } else { 637 error_report("Warning: Unknown L1 dcache size for cpu"); 638 } 639 if (pcc->l1_icache_size) { 640 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 641 pcc->l1_icache_size))); 642 } else { 643 error_report("Warning: Unknown L1 icache size for cpu"); 644 } 645 646 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 647 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 648 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 649 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 650 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 651 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 652 653 if (env->spr_cb[SPR_PURR].oea_read) { 654 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 655 } 656 657 if (env->mmu_model & POWERPC_MMU_1TSEG) { 658 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 659 segs, sizeof(segs)))); 660 } 661 662 /* Advertise VMX/VSX (vector extensions) if available 663 * 0 / no property == no vector extensions 664 * 1 == VMX / Altivec available 665 * 2 == VSX available */ 666 if (env->insns_flags & PPC_ALTIVEC) { 667 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 668 669 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 670 } 671 672 /* Advertise DFP (Decimal Floating Point) if available 673 * 0 / no property == no DFP 674 * 1 == DFP available */ 675 if (env->insns_flags2 & PPC2_DFP) { 676 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 677 } 678 679 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 680 sizeof(page_sizes_prop)); 681 if (page_sizes_prop_size) { 682 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 683 page_sizes_prop, page_sizes_prop_size))); 684 } 685 686 spapr_populate_pa_features(env, fdt, offset); 687 688 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 689 cs->cpu_index / vcpus_per_socket))); 690 691 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 692 pft_size_prop, sizeof(pft_size_prop)))); 693 694 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 695 696 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 697 ppc_get_compat_smt_threads(cpu))); 698 } 699 700 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 701 { 702 CPUState *cs; 703 int cpus_offset; 704 char *nodename; 705 int smt = kvmppc_smt_threads(); 706 707 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 708 _FDT(cpus_offset); 709 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 710 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 711 712 /* 713 * We walk the CPUs in reverse order to ensure that CPU DT nodes 714 * created by fdt_add_subnode() end up in the right order in FDT 715 * for the guest kernel the enumerate the CPUs correctly. 716 */ 717 CPU_FOREACH_REVERSE(cs) { 718 PowerPCCPU *cpu = POWERPC_CPU(cs); 719 int index = ppc_get_vcpu_dt_id(cpu); 720 DeviceClass *dc = DEVICE_GET_CLASS(cs); 721 int offset; 722 723 if ((index % smt) != 0) { 724 continue; 725 } 726 727 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 728 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 729 g_free(nodename); 730 _FDT(offset); 731 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 732 } 733 734 } 735 736 /* 737 * Adds ibm,dynamic-reconfiguration-memory node. 738 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 739 * of this device tree node. 740 */ 741 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 742 { 743 MachineState *machine = MACHINE(spapr); 744 int ret, i, offset; 745 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 746 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 747 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 748 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 749 memory_region_size(&spapr->hotplug_memory.mr)) / 750 lmb_size; 751 uint32_t *int_buf, *cur_index, buf_len; 752 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 753 754 /* 755 * Don't create the node if there is no hotpluggable memory 756 */ 757 if (machine->ram_size == machine->maxram_size) { 758 return 0; 759 } 760 761 /* 762 * Allocate enough buffer size to fit in ibm,dynamic-memory 763 * or ibm,associativity-lookup-arrays 764 */ 765 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 766 * sizeof(uint32_t); 767 cur_index = int_buf = g_malloc0(buf_len); 768 769 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 770 771 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 772 sizeof(prop_lmb_size)); 773 if (ret < 0) { 774 goto out; 775 } 776 777 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 778 if (ret < 0) { 779 goto out; 780 } 781 782 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 783 if (ret < 0) { 784 goto out; 785 } 786 787 /* ibm,dynamic-memory */ 788 int_buf[0] = cpu_to_be32(nr_lmbs); 789 cur_index++; 790 for (i = 0; i < nr_lmbs; i++) { 791 uint64_t addr = i * lmb_size; 792 uint32_t *dynamic_memory = cur_index; 793 794 if (i >= hotplug_lmb_start) { 795 sPAPRDRConnector *drc; 796 sPAPRDRConnectorClass *drck; 797 798 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 799 g_assert(drc); 800 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 801 802 dynamic_memory[0] = cpu_to_be32(addr >> 32); 803 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 804 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 805 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 806 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 807 if (memory_region_present(get_system_memory(), addr)) { 808 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 809 } else { 810 dynamic_memory[5] = cpu_to_be32(0); 811 } 812 } else { 813 /* 814 * LMB information for RMA, boot time RAM and gap b/n RAM and 815 * hotplug memory region -- all these are marked as reserved 816 * and as having no valid DRC. 817 */ 818 dynamic_memory[0] = cpu_to_be32(addr >> 32); 819 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 820 dynamic_memory[2] = cpu_to_be32(0); 821 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 822 dynamic_memory[4] = cpu_to_be32(-1); 823 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 824 SPAPR_LMB_FLAGS_DRC_INVALID); 825 } 826 827 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 828 } 829 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 830 if (ret < 0) { 831 goto out; 832 } 833 834 /* ibm,associativity-lookup-arrays */ 835 cur_index = int_buf; 836 int_buf[0] = cpu_to_be32(nr_nodes); 837 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 838 cur_index += 2; 839 for (i = 0; i < nr_nodes; i++) { 840 uint32_t associativity[] = { 841 cpu_to_be32(0x0), 842 cpu_to_be32(0x0), 843 cpu_to_be32(0x0), 844 cpu_to_be32(i) 845 }; 846 memcpy(cur_index, associativity, sizeof(associativity)); 847 cur_index += 4; 848 } 849 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 850 (cur_index - int_buf) * sizeof(uint32_t)); 851 out: 852 g_free(int_buf); 853 return ret; 854 } 855 856 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 857 target_ulong addr, target_ulong size, 858 bool cpu_update, bool memory_update) 859 { 860 void *fdt, *fdt_skel; 861 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 862 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 863 864 size -= sizeof(hdr); 865 866 /* Create sceleton */ 867 fdt_skel = g_malloc0(size); 868 _FDT((fdt_create(fdt_skel, size))); 869 _FDT((fdt_begin_node(fdt_skel, ""))); 870 _FDT((fdt_end_node(fdt_skel))); 871 _FDT((fdt_finish(fdt_skel))); 872 fdt = g_malloc0(size); 873 _FDT((fdt_open_into(fdt_skel, fdt, size))); 874 g_free(fdt_skel); 875 876 /* Fixup cpu nodes */ 877 if (cpu_update) { 878 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 879 } 880 881 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 882 if (memory_update && smc->dr_lmb_enabled) { 883 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 884 } 885 886 /* Pack resulting tree */ 887 _FDT((fdt_pack(fdt))); 888 889 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 890 trace_spapr_cas_failed(size); 891 return -1; 892 } 893 894 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 895 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 896 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 897 g_free(fdt); 898 899 return 0; 900 } 901 902 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 903 hwaddr fdt_addr, 904 hwaddr rtas_addr, 905 hwaddr rtas_size) 906 { 907 MachineState *machine = MACHINE(qdev_get_machine()); 908 MachineClass *mc = MACHINE_GET_CLASS(machine); 909 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 910 const char *boot_device = machine->boot_order; 911 int ret, i; 912 size_t cb = 0; 913 char *bootlist; 914 void *fdt; 915 sPAPRPHBState *phb; 916 917 fdt = g_malloc(FDT_MAX_SIZE); 918 919 /* open out the base tree into a temp buffer for the final tweaks */ 920 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 921 922 ret = spapr_populate_memory(spapr, fdt); 923 if (ret < 0) { 924 error_report("couldn't setup memory nodes in fdt"); 925 exit(1); 926 } 927 928 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 929 if (ret < 0) { 930 error_report("couldn't setup vio devices in fdt"); 931 exit(1); 932 } 933 934 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 935 ret = spapr_rng_populate_dt(fdt); 936 if (ret < 0) { 937 error_report("could not set up rng device in the fdt"); 938 exit(1); 939 } 940 } 941 942 QLIST_FOREACH(phb, &spapr->phbs, list) { 943 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 944 if (ret < 0) { 945 error_report("couldn't setup PCI devices in fdt"); 946 exit(1); 947 } 948 } 949 950 /* RTAS */ 951 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 952 if (ret < 0) { 953 error_report("Couldn't set up RTAS device tree properties"); 954 } 955 956 /* cpus */ 957 spapr_populate_cpus_dt_node(fdt, spapr); 958 959 bootlist = get_boot_devices_list(&cb, true); 960 if (cb && bootlist) { 961 int offset = fdt_path_offset(fdt, "/chosen"); 962 if (offset < 0) { 963 exit(1); 964 } 965 for (i = 0; i < cb; i++) { 966 if (bootlist[i] == '\n') { 967 bootlist[i] = ' '; 968 } 969 970 } 971 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 972 } 973 974 if (boot_device && strlen(boot_device)) { 975 int offset = fdt_path_offset(fdt, "/chosen"); 976 977 if (offset < 0) { 978 exit(1); 979 } 980 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 981 } 982 983 if (!spapr->has_graphics) { 984 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 985 } 986 987 if (smc->dr_lmb_enabled) { 988 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 989 } 990 991 if (mc->query_hotpluggable_cpus) { 992 int offset = fdt_path_offset(fdt, "/cpus"); 993 ret = spapr_drc_populate_dt(fdt, offset, NULL, 994 SPAPR_DR_CONNECTOR_TYPE_CPU); 995 if (ret < 0) { 996 error_report("Couldn't set up CPU DR device tree properties"); 997 exit(1); 998 } 999 } 1000 1001 _FDT((fdt_pack(fdt))); 1002 1003 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1004 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1005 fdt_totalsize(fdt), FDT_MAX_SIZE); 1006 exit(1); 1007 } 1008 1009 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1010 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1011 1012 g_free(bootlist); 1013 g_free(fdt); 1014 } 1015 1016 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1017 { 1018 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1019 } 1020 1021 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 1022 { 1023 CPUPPCState *env = &cpu->env; 1024 1025 if (msr_pr) { 1026 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1027 env->gpr[3] = H_PRIVILEGE; 1028 } else { 1029 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1030 } 1031 } 1032 1033 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1034 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1035 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1036 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1037 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1038 1039 /* 1040 * Get the fd to access the kernel htab, re-opening it if necessary 1041 */ 1042 static int get_htab_fd(sPAPRMachineState *spapr) 1043 { 1044 if (spapr->htab_fd >= 0) { 1045 return spapr->htab_fd; 1046 } 1047 1048 spapr->htab_fd = kvmppc_get_htab_fd(false); 1049 if (spapr->htab_fd < 0) { 1050 error_report("Unable to open fd for reading hash table from KVM: %s", 1051 strerror(errno)); 1052 } 1053 1054 return spapr->htab_fd; 1055 } 1056 1057 static void close_htab_fd(sPAPRMachineState *spapr) 1058 { 1059 if (spapr->htab_fd >= 0) { 1060 close(spapr->htab_fd); 1061 } 1062 spapr->htab_fd = -1; 1063 } 1064 1065 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1066 { 1067 int shift; 1068 1069 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1070 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1071 * that's much more than is needed for Linux guests */ 1072 shift = ctz64(pow2ceil(ramsize)) - 7; 1073 shift = MAX(shift, 18); /* Minimum architected size */ 1074 shift = MIN(shift, 46); /* Maximum architected size */ 1075 return shift; 1076 } 1077 1078 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1079 Error **errp) 1080 { 1081 long rc; 1082 1083 /* Clean up any HPT info from a previous boot */ 1084 g_free(spapr->htab); 1085 spapr->htab = NULL; 1086 spapr->htab_shift = 0; 1087 close_htab_fd(spapr); 1088 1089 rc = kvmppc_reset_htab(shift); 1090 if (rc < 0) { 1091 /* kernel-side HPT needed, but couldn't allocate one */ 1092 error_setg_errno(errp, errno, 1093 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1094 shift); 1095 /* This is almost certainly fatal, but if the caller really 1096 * wants to carry on with shift == 0, it's welcome to try */ 1097 } else if (rc > 0) { 1098 /* kernel-side HPT allocated */ 1099 if (rc != shift) { 1100 error_setg(errp, 1101 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1102 shift, rc); 1103 } 1104 1105 spapr->htab_shift = shift; 1106 spapr->htab = NULL; 1107 } else { 1108 /* kernel-side HPT not needed, allocate in userspace instead */ 1109 size_t size = 1ULL << shift; 1110 int i; 1111 1112 spapr->htab = qemu_memalign(size, size); 1113 if (!spapr->htab) { 1114 error_setg_errno(errp, errno, 1115 "Could not allocate HPT of order %d", shift); 1116 return; 1117 } 1118 1119 memset(spapr->htab, 0, size); 1120 spapr->htab_shift = shift; 1121 1122 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1123 DIRTY_HPTE(HPTE(spapr->htab, i)); 1124 } 1125 } 1126 } 1127 1128 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1129 { 1130 bool matched = false; 1131 1132 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1133 matched = true; 1134 } 1135 1136 if (!matched) { 1137 error_report("Device %s is not supported by this machine yet.", 1138 qdev_fw_name(DEVICE(sbdev))); 1139 exit(1); 1140 } 1141 } 1142 1143 static void ppc_spapr_reset(void) 1144 { 1145 MachineState *machine = MACHINE(qdev_get_machine()); 1146 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1147 PowerPCCPU *first_ppc_cpu; 1148 uint32_t rtas_limit; 1149 1150 /* Check for unknown sysbus devices */ 1151 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1152 1153 /* Allocate and/or reset the hash page table */ 1154 spapr_reallocate_hpt(spapr, 1155 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1156 &error_fatal); 1157 1158 /* Update the RMA size if necessary */ 1159 if (spapr->vrma_adjust) { 1160 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1161 spapr->htab_shift); 1162 } 1163 1164 qemu_devices_reset(); 1165 1166 /* 1167 * We place the device tree and RTAS just below either the top of the RMA, 1168 * or just below 2GB, whichever is lowere, so that it can be 1169 * processed with 32-bit real mode code if necessary 1170 */ 1171 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1172 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1173 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1174 1175 /* Load the fdt */ 1176 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1177 spapr->rtas_size); 1178 1179 /* Copy RTAS over */ 1180 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1181 spapr->rtas_size); 1182 1183 /* Set up the entry state */ 1184 first_ppc_cpu = POWERPC_CPU(first_cpu); 1185 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1186 first_ppc_cpu->env.gpr[5] = 0; 1187 first_cpu->halted = 0; 1188 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1189 1190 } 1191 1192 static void spapr_create_nvram(sPAPRMachineState *spapr) 1193 { 1194 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1195 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1196 1197 if (dinfo) { 1198 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1199 &error_fatal); 1200 } 1201 1202 qdev_init_nofail(dev); 1203 1204 spapr->nvram = (struct sPAPRNVRAM *)dev; 1205 } 1206 1207 static void spapr_rtc_create(sPAPRMachineState *spapr) 1208 { 1209 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1210 1211 qdev_init_nofail(dev); 1212 spapr->rtc = dev; 1213 1214 object_property_add_alias(qdev_get_machine(), "rtc-time", 1215 OBJECT(spapr->rtc), "date", NULL); 1216 } 1217 1218 /* Returns whether we want to use VGA or not */ 1219 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1220 { 1221 switch (vga_interface_type) { 1222 case VGA_NONE: 1223 return false; 1224 case VGA_DEVICE: 1225 return true; 1226 case VGA_STD: 1227 case VGA_VIRTIO: 1228 return pci_vga_init(pci_bus) != NULL; 1229 default: 1230 error_setg(errp, 1231 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1232 return false; 1233 } 1234 } 1235 1236 static int spapr_post_load(void *opaque, int version_id) 1237 { 1238 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1239 int err = 0; 1240 1241 /* In earlier versions, there was no separate qdev for the PAPR 1242 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1243 * So when migrating from those versions, poke the incoming offset 1244 * value into the RTC device */ 1245 if (version_id < 3) { 1246 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1247 } 1248 1249 return err; 1250 } 1251 1252 static bool version_before_3(void *opaque, int version_id) 1253 { 1254 return version_id < 3; 1255 } 1256 1257 static const VMStateDescription vmstate_spapr = { 1258 .name = "spapr", 1259 .version_id = 3, 1260 .minimum_version_id = 1, 1261 .post_load = spapr_post_load, 1262 .fields = (VMStateField[]) { 1263 /* used to be @next_irq */ 1264 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1265 1266 /* RTC offset */ 1267 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1268 1269 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1270 VMSTATE_END_OF_LIST() 1271 }, 1272 }; 1273 1274 static int htab_save_setup(QEMUFile *f, void *opaque) 1275 { 1276 sPAPRMachineState *spapr = opaque; 1277 1278 /* "Iteration" header */ 1279 qemu_put_be32(f, spapr->htab_shift); 1280 1281 if (spapr->htab) { 1282 spapr->htab_save_index = 0; 1283 spapr->htab_first_pass = true; 1284 } else { 1285 assert(kvm_enabled()); 1286 } 1287 1288 1289 return 0; 1290 } 1291 1292 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1293 int64_t max_ns) 1294 { 1295 bool has_timeout = max_ns != -1; 1296 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1297 int index = spapr->htab_save_index; 1298 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1299 1300 assert(spapr->htab_first_pass); 1301 1302 do { 1303 int chunkstart; 1304 1305 /* Consume invalid HPTEs */ 1306 while ((index < htabslots) 1307 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1308 index++; 1309 CLEAN_HPTE(HPTE(spapr->htab, index)); 1310 } 1311 1312 /* Consume valid HPTEs */ 1313 chunkstart = index; 1314 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1315 && HPTE_VALID(HPTE(spapr->htab, index))) { 1316 index++; 1317 CLEAN_HPTE(HPTE(spapr->htab, index)); 1318 } 1319 1320 if (index > chunkstart) { 1321 int n_valid = index - chunkstart; 1322 1323 qemu_put_be32(f, chunkstart); 1324 qemu_put_be16(f, n_valid); 1325 qemu_put_be16(f, 0); 1326 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1327 HASH_PTE_SIZE_64 * n_valid); 1328 1329 if (has_timeout && 1330 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1331 break; 1332 } 1333 } 1334 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1335 1336 if (index >= htabslots) { 1337 assert(index == htabslots); 1338 index = 0; 1339 spapr->htab_first_pass = false; 1340 } 1341 spapr->htab_save_index = index; 1342 } 1343 1344 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1345 int64_t max_ns) 1346 { 1347 bool final = max_ns < 0; 1348 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1349 int examined = 0, sent = 0; 1350 int index = spapr->htab_save_index; 1351 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1352 1353 assert(!spapr->htab_first_pass); 1354 1355 do { 1356 int chunkstart, invalidstart; 1357 1358 /* Consume non-dirty HPTEs */ 1359 while ((index < htabslots) 1360 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1361 index++; 1362 examined++; 1363 } 1364 1365 chunkstart = index; 1366 /* Consume valid dirty HPTEs */ 1367 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1368 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1369 && HPTE_VALID(HPTE(spapr->htab, index))) { 1370 CLEAN_HPTE(HPTE(spapr->htab, index)); 1371 index++; 1372 examined++; 1373 } 1374 1375 invalidstart = index; 1376 /* Consume invalid dirty HPTEs */ 1377 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1378 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1379 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1380 CLEAN_HPTE(HPTE(spapr->htab, index)); 1381 index++; 1382 examined++; 1383 } 1384 1385 if (index > chunkstart) { 1386 int n_valid = invalidstart - chunkstart; 1387 int n_invalid = index - invalidstart; 1388 1389 qemu_put_be32(f, chunkstart); 1390 qemu_put_be16(f, n_valid); 1391 qemu_put_be16(f, n_invalid); 1392 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1393 HASH_PTE_SIZE_64 * n_valid); 1394 sent += index - chunkstart; 1395 1396 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1397 break; 1398 } 1399 } 1400 1401 if (examined >= htabslots) { 1402 break; 1403 } 1404 1405 if (index >= htabslots) { 1406 assert(index == htabslots); 1407 index = 0; 1408 } 1409 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1410 1411 if (index >= htabslots) { 1412 assert(index == htabslots); 1413 index = 0; 1414 } 1415 1416 spapr->htab_save_index = index; 1417 1418 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1419 } 1420 1421 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1422 #define MAX_KVM_BUF_SIZE 2048 1423 1424 static int htab_save_iterate(QEMUFile *f, void *opaque) 1425 { 1426 sPAPRMachineState *spapr = opaque; 1427 int fd; 1428 int rc = 0; 1429 1430 /* Iteration header */ 1431 qemu_put_be32(f, 0); 1432 1433 if (!spapr->htab) { 1434 assert(kvm_enabled()); 1435 1436 fd = get_htab_fd(spapr); 1437 if (fd < 0) { 1438 return fd; 1439 } 1440 1441 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1442 if (rc < 0) { 1443 return rc; 1444 } 1445 } else if (spapr->htab_first_pass) { 1446 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1447 } else { 1448 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1449 } 1450 1451 /* End marker */ 1452 qemu_put_be32(f, 0); 1453 qemu_put_be16(f, 0); 1454 qemu_put_be16(f, 0); 1455 1456 return rc; 1457 } 1458 1459 static int htab_save_complete(QEMUFile *f, void *opaque) 1460 { 1461 sPAPRMachineState *spapr = opaque; 1462 int fd; 1463 1464 /* Iteration header */ 1465 qemu_put_be32(f, 0); 1466 1467 if (!spapr->htab) { 1468 int rc; 1469 1470 assert(kvm_enabled()); 1471 1472 fd = get_htab_fd(spapr); 1473 if (fd < 0) { 1474 return fd; 1475 } 1476 1477 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1478 if (rc < 0) { 1479 return rc; 1480 } 1481 } else { 1482 if (spapr->htab_first_pass) { 1483 htab_save_first_pass(f, spapr, -1); 1484 } 1485 htab_save_later_pass(f, spapr, -1); 1486 } 1487 1488 /* End marker */ 1489 qemu_put_be32(f, 0); 1490 qemu_put_be16(f, 0); 1491 qemu_put_be16(f, 0); 1492 1493 return 0; 1494 } 1495 1496 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1497 { 1498 sPAPRMachineState *spapr = opaque; 1499 uint32_t section_hdr; 1500 int fd = -1; 1501 1502 if (version_id < 1 || version_id > 1) { 1503 error_report("htab_load() bad version"); 1504 return -EINVAL; 1505 } 1506 1507 section_hdr = qemu_get_be32(f); 1508 1509 if (section_hdr) { 1510 Error *local_err = NULL; 1511 1512 /* First section gives the htab size */ 1513 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1514 if (local_err) { 1515 error_report_err(local_err); 1516 return -EINVAL; 1517 } 1518 return 0; 1519 } 1520 1521 if (!spapr->htab) { 1522 assert(kvm_enabled()); 1523 1524 fd = kvmppc_get_htab_fd(true); 1525 if (fd < 0) { 1526 error_report("Unable to open fd to restore KVM hash table: %s", 1527 strerror(errno)); 1528 } 1529 } 1530 1531 while (true) { 1532 uint32_t index; 1533 uint16_t n_valid, n_invalid; 1534 1535 index = qemu_get_be32(f); 1536 n_valid = qemu_get_be16(f); 1537 n_invalid = qemu_get_be16(f); 1538 1539 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1540 /* End of Stream */ 1541 break; 1542 } 1543 1544 if ((index + n_valid + n_invalid) > 1545 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1546 /* Bad index in stream */ 1547 error_report( 1548 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1549 index, n_valid, n_invalid, spapr->htab_shift); 1550 return -EINVAL; 1551 } 1552 1553 if (spapr->htab) { 1554 if (n_valid) { 1555 qemu_get_buffer(f, HPTE(spapr->htab, index), 1556 HASH_PTE_SIZE_64 * n_valid); 1557 } 1558 if (n_invalid) { 1559 memset(HPTE(spapr->htab, index + n_valid), 0, 1560 HASH_PTE_SIZE_64 * n_invalid); 1561 } 1562 } else { 1563 int rc; 1564 1565 assert(fd >= 0); 1566 1567 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1568 if (rc < 0) { 1569 return rc; 1570 } 1571 } 1572 } 1573 1574 if (!spapr->htab) { 1575 assert(fd >= 0); 1576 close(fd); 1577 } 1578 1579 return 0; 1580 } 1581 1582 static void htab_cleanup(void *opaque) 1583 { 1584 sPAPRMachineState *spapr = opaque; 1585 1586 close_htab_fd(spapr); 1587 } 1588 1589 static SaveVMHandlers savevm_htab_handlers = { 1590 .save_live_setup = htab_save_setup, 1591 .save_live_iterate = htab_save_iterate, 1592 .save_live_complete_precopy = htab_save_complete, 1593 .cleanup = htab_cleanup, 1594 .load_state = htab_load, 1595 }; 1596 1597 static void spapr_boot_set(void *opaque, const char *boot_device, 1598 Error **errp) 1599 { 1600 MachineState *machine = MACHINE(qdev_get_machine()); 1601 machine->boot_order = g_strdup(boot_device); 1602 } 1603 1604 /* 1605 * Reset routine for LMB DR devices. 1606 * 1607 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1608 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1609 * when it walks all its children devices. LMB devices reset occurs 1610 * as part of spapr_ppc_reset(). 1611 */ 1612 static void spapr_drc_reset(void *opaque) 1613 { 1614 sPAPRDRConnector *drc = opaque; 1615 DeviceState *d = DEVICE(drc); 1616 1617 if (d) { 1618 device_reset(d); 1619 } 1620 } 1621 1622 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1623 { 1624 MachineState *machine = MACHINE(spapr); 1625 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1626 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1627 int i; 1628 1629 for (i = 0; i < nr_lmbs; i++) { 1630 sPAPRDRConnector *drc; 1631 uint64_t addr; 1632 1633 addr = i * lmb_size + spapr->hotplug_memory.base; 1634 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1635 addr/lmb_size); 1636 qemu_register_reset(spapr_drc_reset, drc); 1637 } 1638 } 1639 1640 /* 1641 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1642 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1643 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1644 */ 1645 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1646 { 1647 int i; 1648 1649 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1650 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1651 " is not aligned to %llu MiB", 1652 machine->ram_size, 1653 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1654 return; 1655 } 1656 1657 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1658 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1659 " is not aligned to %llu MiB", 1660 machine->ram_size, 1661 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1662 return; 1663 } 1664 1665 for (i = 0; i < nb_numa_nodes; i++) { 1666 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1667 error_setg(errp, 1668 "Node %d memory size 0x%" PRIx64 1669 " is not aligned to %llu MiB", 1670 i, numa_info[i].node_mem, 1671 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1672 return; 1673 } 1674 } 1675 } 1676 1677 /* pSeries LPAR / sPAPR hardware init */ 1678 static void ppc_spapr_init(MachineState *machine) 1679 { 1680 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1681 MachineClass *mc = MACHINE_GET_CLASS(machine); 1682 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1683 const char *kernel_filename = machine->kernel_filename; 1684 const char *kernel_cmdline = machine->kernel_cmdline; 1685 const char *initrd_filename = machine->initrd_filename; 1686 PCIHostState *phb; 1687 int i; 1688 MemoryRegion *sysmem = get_system_memory(); 1689 MemoryRegion *ram = g_new(MemoryRegion, 1); 1690 MemoryRegion *rma_region; 1691 void *rma = NULL; 1692 hwaddr rma_alloc_size; 1693 hwaddr node0_size = spapr_node0_size(); 1694 uint32_t initrd_base = 0; 1695 long kernel_size = 0, initrd_size = 0; 1696 long load_limit, fw_size; 1697 bool kernel_le = false; 1698 char *filename; 1699 int smt = kvmppc_smt_threads(); 1700 int spapr_cores = smp_cpus / smp_threads; 1701 int spapr_max_cores = max_cpus / smp_threads; 1702 1703 if (mc->query_hotpluggable_cpus) { 1704 if (smp_cpus % smp_threads) { 1705 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1706 smp_cpus, smp_threads); 1707 exit(1); 1708 } 1709 if (max_cpus % smp_threads) { 1710 error_report("max_cpus (%u) must be multiple of threads (%u)", 1711 max_cpus, smp_threads); 1712 exit(1); 1713 } 1714 } 1715 1716 msi_nonbroken = true; 1717 1718 QLIST_INIT(&spapr->phbs); 1719 1720 cpu_ppc_hypercall = emulate_spapr_hypercall; 1721 1722 /* Allocate RMA if necessary */ 1723 rma_alloc_size = kvmppc_alloc_rma(&rma); 1724 1725 if (rma_alloc_size == -1) { 1726 error_report("Unable to create RMA"); 1727 exit(1); 1728 } 1729 1730 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1731 spapr->rma_size = rma_alloc_size; 1732 } else { 1733 spapr->rma_size = node0_size; 1734 1735 /* With KVM, we don't actually know whether KVM supports an 1736 * unbounded RMA (PR KVM) or is limited by the hash table size 1737 * (HV KVM using VRMA), so we always assume the latter 1738 * 1739 * In that case, we also limit the initial allocations for RTAS 1740 * etc... to 256M since we have no way to know what the VRMA size 1741 * is going to be as it depends on the size of the hash table 1742 * isn't determined yet. 1743 */ 1744 if (kvm_enabled()) { 1745 spapr->vrma_adjust = 1; 1746 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1747 } 1748 1749 /* Actually we don't support unbounded RMA anymore since we 1750 * added proper emulation of HV mode. The max we can get is 1751 * 16G which also happens to be what we configure for PAPR 1752 * mode so make sure we don't do anything bigger than that 1753 */ 1754 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1755 } 1756 1757 if (spapr->rma_size > node0_size) { 1758 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1759 spapr->rma_size); 1760 exit(1); 1761 } 1762 1763 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1764 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1765 1766 /* Set up Interrupt Controller before we create the VCPUs */ 1767 spapr->xics = xics_system_init(machine, 1768 DIV_ROUND_UP(max_cpus * smt, smp_threads), 1769 XICS_IRQS_SPAPR, &error_fatal); 1770 1771 if (smc->dr_lmb_enabled) { 1772 spapr_validate_node_memory(machine, &error_fatal); 1773 } 1774 1775 /* init CPUs */ 1776 if (machine->cpu_model == NULL) { 1777 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 1778 } 1779 1780 ppc_cpu_parse_features(machine->cpu_model); 1781 1782 if (mc->query_hotpluggable_cpus) { 1783 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1784 1785 if (type == NULL) { 1786 error_report("Unable to find sPAPR CPU Core definition"); 1787 exit(1); 1788 } 1789 1790 spapr->cores = g_new0(Object *, spapr_max_cores); 1791 for (i = 0; i < spapr_max_cores; i++) { 1792 int core_id = i * smp_threads; 1793 sPAPRDRConnector *drc = 1794 spapr_dr_connector_new(OBJECT(spapr), 1795 SPAPR_DR_CONNECTOR_TYPE_CPU, 1796 (core_id / smp_threads) * smt); 1797 1798 qemu_register_reset(spapr_drc_reset, drc); 1799 1800 if (i < spapr_cores) { 1801 Object *core = object_new(type); 1802 object_property_set_int(core, smp_threads, "nr-threads", 1803 &error_fatal); 1804 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1805 &error_fatal); 1806 object_property_set_bool(core, true, "realized", &error_fatal); 1807 } 1808 } 1809 g_free(type); 1810 } else { 1811 for (i = 0; i < smp_cpus; i++) { 1812 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model); 1813 if (cpu == NULL) { 1814 error_report("Unable to find PowerPC CPU definition"); 1815 exit(1); 1816 } 1817 spapr_cpu_init(spapr, cpu, &error_fatal); 1818 } 1819 } 1820 1821 if (kvm_enabled()) { 1822 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1823 kvmppc_enable_logical_ci_hcalls(); 1824 kvmppc_enable_set_mode_hcall(); 1825 1826 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 1827 kvmppc_enable_clear_ref_mod_hcalls(); 1828 } 1829 1830 /* allocate RAM */ 1831 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1832 machine->ram_size); 1833 memory_region_add_subregion(sysmem, 0, ram); 1834 1835 if (rma_alloc_size && rma) { 1836 rma_region = g_new(MemoryRegion, 1); 1837 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1838 rma_alloc_size, rma); 1839 vmstate_register_ram_global(rma_region); 1840 memory_region_add_subregion(sysmem, 0, rma_region); 1841 } 1842 1843 /* initialize hotplug memory address space */ 1844 if (machine->ram_size < machine->maxram_size) { 1845 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1846 /* 1847 * Limit the number of hotpluggable memory slots to half the number 1848 * slots that KVM supports, leaving the other half for PCI and other 1849 * devices. However ensure that number of slots doesn't drop below 32. 1850 */ 1851 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 1852 SPAPR_MAX_RAM_SLOTS; 1853 1854 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 1855 max_memslots = SPAPR_MAX_RAM_SLOTS; 1856 } 1857 if (machine->ram_slots > max_memslots) { 1858 error_report("Specified number of memory slots %" 1859 PRIu64" exceeds max supported %d", 1860 machine->ram_slots, max_memslots); 1861 exit(1); 1862 } 1863 1864 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1865 SPAPR_HOTPLUG_MEM_ALIGN); 1866 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1867 "hotplug-memory", hotplug_mem_size); 1868 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1869 &spapr->hotplug_memory.mr); 1870 } 1871 1872 if (smc->dr_lmb_enabled) { 1873 spapr_create_lmb_dr_connectors(spapr); 1874 } 1875 1876 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1877 if (!filename) { 1878 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1879 exit(1); 1880 } 1881 spapr->rtas_size = get_image_size(filename); 1882 if (spapr->rtas_size < 0) { 1883 error_report("Could not get size of LPAR rtas '%s'", filename); 1884 exit(1); 1885 } 1886 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1887 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1888 error_report("Could not load LPAR rtas '%s'", filename); 1889 exit(1); 1890 } 1891 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1892 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1893 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1894 exit(1); 1895 } 1896 g_free(filename); 1897 1898 /* Set up EPOW events infrastructure */ 1899 spapr_events_init(spapr); 1900 1901 /* Set up the RTC RTAS interfaces */ 1902 spapr_rtc_create(spapr); 1903 1904 /* Set up VIO bus */ 1905 spapr->vio_bus = spapr_vio_bus_init(); 1906 1907 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1908 if (serial_hds[i]) { 1909 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1910 } 1911 } 1912 1913 /* We always have at least the nvram device on VIO */ 1914 spapr_create_nvram(spapr); 1915 1916 /* Set up PCI */ 1917 spapr_pci_rtas_init(); 1918 1919 phb = spapr_create_phb(spapr, 0); 1920 1921 for (i = 0; i < nb_nics; i++) { 1922 NICInfo *nd = &nd_table[i]; 1923 1924 if (!nd->model) { 1925 nd->model = g_strdup("ibmveth"); 1926 } 1927 1928 if (strcmp(nd->model, "ibmveth") == 0) { 1929 spapr_vlan_create(spapr->vio_bus, nd); 1930 } else { 1931 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1932 } 1933 } 1934 1935 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1936 spapr_vscsi_create(spapr->vio_bus); 1937 } 1938 1939 /* Graphics */ 1940 if (spapr_vga_init(phb->bus, &error_fatal)) { 1941 spapr->has_graphics = true; 1942 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1943 } 1944 1945 if (machine->usb) { 1946 if (smc->use_ohci_by_default) { 1947 pci_create_simple(phb->bus, -1, "pci-ohci"); 1948 } else { 1949 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 1950 } 1951 1952 if (spapr->has_graphics) { 1953 USBBus *usb_bus = usb_bus_find(-1); 1954 1955 usb_create_simple(usb_bus, "usb-kbd"); 1956 usb_create_simple(usb_bus, "usb-mouse"); 1957 } 1958 } 1959 1960 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1961 error_report( 1962 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 1963 MIN_RMA_SLOF); 1964 exit(1); 1965 } 1966 1967 if (kernel_filename) { 1968 uint64_t lowaddr = 0; 1969 1970 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1971 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 1972 0, 0); 1973 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1974 kernel_size = load_elf(kernel_filename, 1975 translate_kernel_address, NULL, 1976 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 1977 0, 0); 1978 kernel_le = kernel_size > 0; 1979 } 1980 if (kernel_size < 0) { 1981 error_report("error loading %s: %s", 1982 kernel_filename, load_elf_strerror(kernel_size)); 1983 exit(1); 1984 } 1985 1986 /* load initrd */ 1987 if (initrd_filename) { 1988 /* Try to locate the initrd in the gap between the kernel 1989 * and the firmware. Add a bit of space just in case 1990 */ 1991 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 1992 initrd_size = load_image_targphys(initrd_filename, initrd_base, 1993 load_limit - initrd_base); 1994 if (initrd_size < 0) { 1995 error_report("could not load initial ram disk '%s'", 1996 initrd_filename); 1997 exit(1); 1998 } 1999 } else { 2000 initrd_base = 0; 2001 initrd_size = 0; 2002 } 2003 } 2004 2005 if (bios_name == NULL) { 2006 bios_name = FW_FILE_NAME; 2007 } 2008 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2009 if (!filename) { 2010 error_report("Could not find LPAR firmware '%s'", bios_name); 2011 exit(1); 2012 } 2013 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2014 if (fw_size <= 0) { 2015 error_report("Could not load LPAR firmware '%s'", filename); 2016 exit(1); 2017 } 2018 g_free(filename); 2019 2020 /* FIXME: Should register things through the MachineState's qdev 2021 * interface, this is a legacy from the sPAPREnvironment structure 2022 * which predated MachineState but had a similar function */ 2023 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2024 register_savevm_live(NULL, "spapr/htab", -1, 1, 2025 &savevm_htab_handlers, spapr); 2026 2027 /* Prepare the device tree */ 2028 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 2029 kernel_size, kernel_le, 2030 kernel_cmdline, 2031 spapr->check_exception_irq); 2032 assert(spapr->fdt_skel != NULL); 2033 2034 /* used by RTAS */ 2035 QTAILQ_INIT(&spapr->ccs_list); 2036 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2037 2038 qemu_register_boot_set(spapr_boot_set, spapr); 2039 } 2040 2041 static int spapr_kvm_type(const char *vm_type) 2042 { 2043 if (!vm_type) { 2044 return 0; 2045 } 2046 2047 if (!strcmp(vm_type, "HV")) { 2048 return 1; 2049 } 2050 2051 if (!strcmp(vm_type, "PR")) { 2052 return 2; 2053 } 2054 2055 error_report("Unknown kvm-type specified '%s'", vm_type); 2056 exit(1); 2057 } 2058 2059 /* 2060 * Implementation of an interface to adjust firmware path 2061 * for the bootindex property handling. 2062 */ 2063 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2064 DeviceState *dev) 2065 { 2066 #define CAST(type, obj, name) \ 2067 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2068 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2069 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2070 2071 if (d) { 2072 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2073 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2074 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2075 2076 if (spapr) { 2077 /* 2078 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2079 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2080 * in the top 16 bits of the 64-bit LUN 2081 */ 2082 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2083 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2084 (uint64_t)id << 48); 2085 } else if (virtio) { 2086 /* 2087 * We use SRP luns of the form 01000000 | (target << 8) | lun 2088 * in the top 32 bits of the 64-bit LUN 2089 * Note: the quote above is from SLOF and it is wrong, 2090 * the actual binding is: 2091 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2092 */ 2093 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2094 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2095 (uint64_t)id << 32); 2096 } else if (usb) { 2097 /* 2098 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2099 * in the top 32 bits of the 64-bit LUN 2100 */ 2101 unsigned usb_port = atoi(usb->port->path); 2102 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2103 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2104 (uint64_t)id << 32); 2105 } 2106 } 2107 2108 if (phb) { 2109 /* Replace "pci" with "pci@800000020000000" */ 2110 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2111 } 2112 2113 return NULL; 2114 } 2115 2116 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2117 { 2118 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2119 2120 return g_strdup(spapr->kvm_type); 2121 } 2122 2123 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2124 { 2125 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2126 2127 g_free(spapr->kvm_type); 2128 spapr->kvm_type = g_strdup(value); 2129 } 2130 2131 static void spapr_machine_initfn(Object *obj) 2132 { 2133 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2134 2135 spapr->htab_fd = -1; 2136 object_property_add_str(obj, "kvm-type", 2137 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2138 object_property_set_description(obj, "kvm-type", 2139 "Specifies the KVM virtualization mode (HV, PR)", 2140 NULL); 2141 } 2142 2143 static void spapr_machine_finalizefn(Object *obj) 2144 { 2145 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2146 2147 g_free(spapr->kvm_type); 2148 } 2149 2150 static void ppc_cpu_do_nmi_on_cpu(CPUState *cs, void *arg) 2151 { 2152 cpu_synchronize_state(cs); 2153 ppc_cpu_do_system_reset(cs); 2154 } 2155 2156 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2157 { 2158 CPUState *cs; 2159 2160 CPU_FOREACH(cs) { 2161 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, NULL); 2162 } 2163 } 2164 2165 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2166 uint32_t node, Error **errp) 2167 { 2168 sPAPRDRConnector *drc; 2169 sPAPRDRConnectorClass *drck; 2170 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2171 int i, fdt_offset, fdt_size; 2172 void *fdt; 2173 2174 for (i = 0; i < nr_lmbs; i++) { 2175 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2176 addr/SPAPR_MEMORY_BLOCK_SIZE); 2177 g_assert(drc); 2178 2179 fdt = create_device_tree(&fdt_size); 2180 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2181 SPAPR_MEMORY_BLOCK_SIZE); 2182 2183 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2184 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2185 addr += SPAPR_MEMORY_BLOCK_SIZE; 2186 } 2187 /* send hotplug notification to the 2188 * guest only in case of hotplugged memory 2189 */ 2190 if (dev->hotplugged) { 2191 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2192 } 2193 } 2194 2195 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2196 uint32_t node, Error **errp) 2197 { 2198 Error *local_err = NULL; 2199 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2200 PCDIMMDevice *dimm = PC_DIMM(dev); 2201 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2202 MemoryRegion *mr = ddc->get_memory_region(dimm); 2203 uint64_t align = memory_region_get_alignment(mr); 2204 uint64_t size = memory_region_size(mr); 2205 uint64_t addr; 2206 2207 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2208 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2209 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2210 goto out; 2211 } 2212 2213 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2214 if (local_err) { 2215 goto out; 2216 } 2217 2218 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2219 if (local_err) { 2220 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2221 goto out; 2222 } 2223 2224 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2225 2226 out: 2227 error_propagate(errp, local_err); 2228 } 2229 2230 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2231 sPAPRMachineState *spapr) 2232 { 2233 PowerPCCPU *cpu = POWERPC_CPU(cs); 2234 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2235 int id = ppc_get_vcpu_dt_id(cpu); 2236 void *fdt; 2237 int offset, fdt_size; 2238 char *nodename; 2239 2240 fdt = create_device_tree(&fdt_size); 2241 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2242 offset = fdt_add_subnode(fdt, 0, nodename); 2243 2244 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2245 g_free(nodename); 2246 2247 *fdt_offset = offset; 2248 return fdt; 2249 } 2250 2251 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2252 DeviceState *dev, Error **errp) 2253 { 2254 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2255 2256 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2257 int node; 2258 2259 if (!smc->dr_lmb_enabled) { 2260 error_setg(errp, "Memory hotplug not supported for this machine"); 2261 return; 2262 } 2263 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2264 if (*errp) { 2265 return; 2266 } 2267 if (node < 0 || node >= MAX_NODES) { 2268 error_setg(errp, "Invaild node %d", node); 2269 return; 2270 } 2271 2272 /* 2273 * Currently PowerPC kernel doesn't allow hot-adding memory to 2274 * memory-less node, but instead will silently add the memory 2275 * to the first node that has some memory. This causes two 2276 * unexpected behaviours for the user. 2277 * 2278 * - Memory gets hotplugged to a different node than what the user 2279 * specified. 2280 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2281 * to memory-less node, a reboot will set things accordingly 2282 * and the previously hotplugged memory now ends in the right node. 2283 * This appears as if some memory moved from one node to another. 2284 * 2285 * So until kernel starts supporting memory hotplug to memory-less 2286 * nodes, just prevent such attempts upfront in QEMU. 2287 */ 2288 if (nb_numa_nodes && !numa_info[node].node_mem) { 2289 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2290 node); 2291 return; 2292 } 2293 2294 spapr_memory_plug(hotplug_dev, dev, node, errp); 2295 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2296 spapr_core_plug(hotplug_dev, dev, errp); 2297 } 2298 } 2299 2300 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2301 DeviceState *dev, Error **errp) 2302 { 2303 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2304 2305 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2306 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2307 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2308 if (!mc->query_hotpluggable_cpus) { 2309 error_setg(errp, "CPU hot unplug not supported on this machine"); 2310 return; 2311 } 2312 spapr_core_unplug(hotplug_dev, dev, errp); 2313 } 2314 } 2315 2316 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2317 DeviceState *dev, Error **errp) 2318 { 2319 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2320 spapr_core_pre_plug(hotplug_dev, dev, errp); 2321 } 2322 } 2323 2324 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2325 DeviceState *dev) 2326 { 2327 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2328 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2329 return HOTPLUG_HANDLER(machine); 2330 } 2331 return NULL; 2332 } 2333 2334 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2335 { 2336 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2337 * socket means much for the paravirtualized PAPR platform) */ 2338 return cpu_index / smp_threads / smp_cores; 2339 } 2340 2341 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) 2342 { 2343 int i; 2344 HotpluggableCPUList *head = NULL; 2345 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2346 int spapr_max_cores = max_cpus / smp_threads; 2347 2348 for (i = 0; i < spapr_max_cores; i++) { 2349 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); 2350 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 2351 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); 2352 2353 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); 2354 cpu_item->vcpus_count = smp_threads; 2355 cpu_props->has_core_id = true; 2356 cpu_props->core_id = i * smp_threads; 2357 /* TODO: add 'has_node/node' here to describe 2358 to which node core belongs */ 2359 2360 cpu_item->props = cpu_props; 2361 if (spapr->cores[i]) { 2362 cpu_item->has_qom_path = true; 2363 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); 2364 } 2365 list_item->value = cpu_item; 2366 list_item->next = head; 2367 head = list_item; 2368 } 2369 return head; 2370 } 2371 2372 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2373 uint64_t *buid, hwaddr *pio, 2374 hwaddr *mmio32, hwaddr *mmio64, 2375 unsigned n_dma, uint32_t *liobns, Error **errp) 2376 { 2377 /* 2378 * New-style PHB window placement. 2379 * 2380 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2381 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2382 * windows. 2383 * 2384 * Some guest kernels can't work with MMIO windows above 1<<46 2385 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2386 * 2387 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2388 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2389 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2390 * 1TiB 64-bit MMIO windows for each PHB. 2391 */ 2392 const uint64_t base_buid = 0x800000020000000ULL; 2393 const int max_phbs = 2394 (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1; 2395 int i; 2396 2397 /* Sanity check natural alignments */ 2398 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2399 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2400 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2401 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2402 /* Sanity check bounds */ 2403 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE); 2404 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE); 2405 2406 if (index >= max_phbs) { 2407 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 2408 max_phbs - 1); 2409 return; 2410 } 2411 2412 *buid = base_buid + index; 2413 for (i = 0; i < n_dma; ++i) { 2414 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2415 } 2416 2417 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2418 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2419 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2420 } 2421 2422 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2423 { 2424 MachineClass *mc = MACHINE_CLASS(oc); 2425 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2426 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2427 NMIClass *nc = NMI_CLASS(oc); 2428 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2429 2430 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2431 2432 /* 2433 * We set up the default / latest behaviour here. The class_init 2434 * functions for the specific versioned machine types can override 2435 * these details for backwards compatibility 2436 */ 2437 mc->init = ppc_spapr_init; 2438 mc->reset = ppc_spapr_reset; 2439 mc->block_default_type = IF_SCSI; 2440 mc->max_cpus = 255; 2441 mc->no_parallel = 1; 2442 mc->default_boot_order = ""; 2443 mc->default_ram_size = 512 * M_BYTE; 2444 mc->kvm_type = spapr_kvm_type; 2445 mc->has_dynamic_sysbus = true; 2446 mc->pci_allow_0_address = true; 2447 mc->get_hotplug_handler = spapr_get_hotplug_handler; 2448 hc->pre_plug = spapr_machine_device_pre_plug; 2449 hc->plug = spapr_machine_device_plug; 2450 hc->unplug = spapr_machine_device_unplug; 2451 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2452 2453 smc->dr_lmb_enabled = true; 2454 smc->tcg_default_cpu = "POWER8"; 2455 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; 2456 fwc->get_dev_path = spapr_get_fw_dev_path; 2457 nc->nmi_monitor_handler = spapr_nmi; 2458 smc->phb_placement = spapr_phb_placement; 2459 } 2460 2461 static const TypeInfo spapr_machine_info = { 2462 .name = TYPE_SPAPR_MACHINE, 2463 .parent = TYPE_MACHINE, 2464 .abstract = true, 2465 .instance_size = sizeof(sPAPRMachineState), 2466 .instance_init = spapr_machine_initfn, 2467 .instance_finalize = spapr_machine_finalizefn, 2468 .class_size = sizeof(sPAPRMachineClass), 2469 .class_init = spapr_machine_class_init, 2470 .interfaces = (InterfaceInfo[]) { 2471 { TYPE_FW_PATH_PROVIDER }, 2472 { TYPE_NMI }, 2473 { TYPE_HOTPLUG_HANDLER }, 2474 { } 2475 }, 2476 }; 2477 2478 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2479 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2480 void *data) \ 2481 { \ 2482 MachineClass *mc = MACHINE_CLASS(oc); \ 2483 spapr_machine_##suffix##_class_options(mc); \ 2484 if (latest) { \ 2485 mc->alias = "pseries"; \ 2486 mc->is_default = 1; \ 2487 } \ 2488 } \ 2489 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2490 { \ 2491 MachineState *machine = MACHINE(obj); \ 2492 spapr_machine_##suffix##_instance_options(machine); \ 2493 } \ 2494 static const TypeInfo spapr_machine_##suffix##_info = { \ 2495 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2496 .parent = TYPE_SPAPR_MACHINE, \ 2497 .class_init = spapr_machine_##suffix##_class_init, \ 2498 .instance_init = spapr_machine_##suffix##_instance_init, \ 2499 }; \ 2500 static void spapr_machine_register_##suffix(void) \ 2501 { \ 2502 type_register(&spapr_machine_##suffix##_info); \ 2503 } \ 2504 type_init(spapr_machine_register_##suffix) 2505 2506 /* 2507 * pseries-2.8 2508 */ 2509 static void spapr_machine_2_8_instance_options(MachineState *machine) 2510 { 2511 } 2512 2513 static void spapr_machine_2_8_class_options(MachineClass *mc) 2514 { 2515 /* Defaults for the latest behaviour inherited from the base class */ 2516 } 2517 2518 DEFINE_SPAPR_MACHINE(2_8, "2.8", true); 2519 2520 /* 2521 * pseries-2.7 2522 */ 2523 #define SPAPR_COMPAT_2_7 \ 2524 HW_COMPAT_2_7 \ 2525 { \ 2526 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 2527 .property = "mem_win_size", \ 2528 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 2529 }, \ 2530 { \ 2531 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 2532 .property = "mem64_win_size", \ 2533 .value = "0", \ 2534 }, 2535 2536 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 2537 uint64_t *buid, hwaddr *pio, 2538 hwaddr *mmio32, hwaddr *mmio64, 2539 unsigned n_dma, uint32_t *liobns, Error **errp) 2540 { 2541 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 2542 const uint64_t base_buid = 0x800000020000000ULL; 2543 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 2544 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 2545 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 2546 const uint32_t max_index = 255; 2547 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 2548 2549 uint64_t ram_top = MACHINE(spapr)->ram_size; 2550 hwaddr phb0_base, phb_base; 2551 int i; 2552 2553 /* Do we have hotpluggable memory? */ 2554 if (MACHINE(spapr)->maxram_size > ram_top) { 2555 /* Can't just use maxram_size, because there may be an 2556 * alignment gap between normal and hotpluggable memory 2557 * regions */ 2558 ram_top = spapr->hotplug_memory.base + 2559 memory_region_size(&spapr->hotplug_memory.mr); 2560 } 2561 2562 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 2563 2564 if (index > max_index) { 2565 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 2566 max_index); 2567 return; 2568 } 2569 2570 *buid = base_buid + index; 2571 for (i = 0; i < n_dma; ++i) { 2572 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2573 } 2574 2575 phb_base = phb0_base + index * phb_spacing; 2576 *pio = phb_base + pio_offset; 2577 *mmio32 = phb_base + mmio_offset; 2578 /* 2579 * We don't set the 64-bit MMIO window, relying on the PHB's 2580 * fallback behaviour of automatically splitting a large "32-bit" 2581 * window into contiguous 32-bit and 64-bit windows 2582 */ 2583 } 2584 2585 static void spapr_machine_2_7_instance_options(MachineState *machine) 2586 { 2587 spapr_machine_2_8_instance_options(machine); 2588 } 2589 2590 static void spapr_machine_2_7_class_options(MachineClass *mc) 2591 { 2592 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2593 2594 spapr_machine_2_8_class_options(mc); 2595 smc->tcg_default_cpu = "POWER7"; 2596 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 2597 smc->phb_placement = phb_placement_2_7; 2598 } 2599 2600 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 2601 2602 /* 2603 * pseries-2.6 2604 */ 2605 #define SPAPR_COMPAT_2_6 \ 2606 HW_COMPAT_2_6 \ 2607 { \ 2608 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2609 .property = "ddw",\ 2610 .value = stringify(off),\ 2611 }, 2612 2613 static void spapr_machine_2_6_instance_options(MachineState *machine) 2614 { 2615 spapr_machine_2_7_instance_options(machine); 2616 } 2617 2618 static void spapr_machine_2_6_class_options(MachineClass *mc) 2619 { 2620 spapr_machine_2_7_class_options(mc); 2621 mc->query_hotpluggable_cpus = NULL; 2622 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 2623 } 2624 2625 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 2626 2627 /* 2628 * pseries-2.5 2629 */ 2630 #define SPAPR_COMPAT_2_5 \ 2631 HW_COMPAT_2_5 \ 2632 { \ 2633 .driver = "spapr-vlan", \ 2634 .property = "use-rx-buffer-pools", \ 2635 .value = "off", \ 2636 }, 2637 2638 static void spapr_machine_2_5_instance_options(MachineState *machine) 2639 { 2640 spapr_machine_2_6_instance_options(machine); 2641 } 2642 2643 static void spapr_machine_2_5_class_options(MachineClass *mc) 2644 { 2645 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2646 2647 spapr_machine_2_6_class_options(mc); 2648 smc->use_ohci_by_default = true; 2649 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2650 } 2651 2652 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2653 2654 /* 2655 * pseries-2.4 2656 */ 2657 #define SPAPR_COMPAT_2_4 \ 2658 HW_COMPAT_2_4 2659 2660 static void spapr_machine_2_4_instance_options(MachineState *machine) 2661 { 2662 spapr_machine_2_5_instance_options(machine); 2663 } 2664 2665 static void spapr_machine_2_4_class_options(MachineClass *mc) 2666 { 2667 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2668 2669 spapr_machine_2_5_class_options(mc); 2670 smc->dr_lmb_enabled = false; 2671 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2672 } 2673 2674 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2675 2676 /* 2677 * pseries-2.3 2678 */ 2679 #define SPAPR_COMPAT_2_3 \ 2680 HW_COMPAT_2_3 \ 2681 {\ 2682 .driver = "spapr-pci-host-bridge",\ 2683 .property = "dynamic-reconfiguration",\ 2684 .value = "off",\ 2685 }, 2686 2687 static void spapr_machine_2_3_instance_options(MachineState *machine) 2688 { 2689 spapr_machine_2_4_instance_options(machine); 2690 savevm_skip_section_footers(); 2691 global_state_set_optional(); 2692 savevm_skip_configuration(); 2693 } 2694 2695 static void spapr_machine_2_3_class_options(MachineClass *mc) 2696 { 2697 spapr_machine_2_4_class_options(mc); 2698 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 2699 } 2700 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 2701 2702 /* 2703 * pseries-2.2 2704 */ 2705 2706 #define SPAPR_COMPAT_2_2 \ 2707 HW_COMPAT_2_2 \ 2708 {\ 2709 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2710 .property = "mem_win_size",\ 2711 .value = "0x20000000",\ 2712 }, 2713 2714 static void spapr_machine_2_2_instance_options(MachineState *machine) 2715 { 2716 spapr_machine_2_3_instance_options(machine); 2717 machine->suppress_vmdesc = true; 2718 } 2719 2720 static void spapr_machine_2_2_class_options(MachineClass *mc) 2721 { 2722 spapr_machine_2_3_class_options(mc); 2723 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 2724 } 2725 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 2726 2727 /* 2728 * pseries-2.1 2729 */ 2730 #define SPAPR_COMPAT_2_1 \ 2731 HW_COMPAT_2_1 2732 2733 static void spapr_machine_2_1_instance_options(MachineState *machine) 2734 { 2735 spapr_machine_2_2_instance_options(machine); 2736 } 2737 2738 static void spapr_machine_2_1_class_options(MachineClass *mc) 2739 { 2740 spapr_machine_2_2_class_options(mc); 2741 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 2742 } 2743 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 2744 2745 static void spapr_machine_register_types(void) 2746 { 2747 type_register_static(&spapr_machine_info); 2748 } 2749 2750 type_init(spapr_machine_register_types) 2751