1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "qemu/datadir.h" 29 #include "qemu/memalign.h" 30 #include "qapi/error.h" 31 #include "qapi/qapi-events-machine.h" 32 #include "qapi/qapi-events-qdev.h" 33 #include "qapi/visitor.h" 34 #include "sysemu/sysemu.h" 35 #include "sysemu/hostmem.h" 36 #include "sysemu/numa.h" 37 #include "sysemu/qtest.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "qemu/log.h" 41 #include "hw/fw-path-provider.h" 42 #include "elf.h" 43 #include "net/net.h" 44 #include "sysemu/device_tree.h" 45 #include "sysemu/cpus.h" 46 #include "sysemu/hw_accel.h" 47 #include "kvm_ppc.h" 48 #include "migration/misc.h" 49 #include "migration/qemu-file-types.h" 50 #include "migration/global_state.h" 51 #include "migration/register.h" 52 #include "migration/blocker.h" 53 #include "mmu-hash64.h" 54 #include "mmu-book3s-v3.h" 55 #include "cpu-models.h" 56 #include "hw/core/cpu.h" 57 58 #include "hw/ppc/ppc.h" 59 #include "hw/loader.h" 60 61 #include "hw/ppc/fdt.h" 62 #include "hw/ppc/spapr.h" 63 #include "hw/ppc/spapr_vio.h" 64 #include "hw/qdev-properties.h" 65 #include "hw/pci-host/spapr.h" 66 #include "hw/pci/msi.h" 67 68 #include "hw/pci/pci.h" 69 #include "hw/scsi/scsi.h" 70 #include "hw/virtio/virtio-scsi.h" 71 #include "hw/virtio/vhost-scsi-common.h" 72 73 #include "exec/ram_addr.h" 74 #include "hw/usb.h" 75 #include "qemu/config-file.h" 76 #include "qemu/error-report.h" 77 #include "trace.h" 78 #include "hw/nmi.h" 79 #include "hw/intc/intc.h" 80 81 #include "hw/ppc/spapr_cpu_core.h" 82 #include "hw/mem/memory-device.h" 83 #include "hw/ppc/spapr_tpm_proxy.h" 84 #include "hw/ppc/spapr_nvdimm.h" 85 #include "hw/ppc/spapr_numa.h" 86 #include "hw/ppc/pef.h" 87 88 #include "monitor/monitor.h" 89 90 #include <libfdt.h> 91 92 /* SLOF memory layout: 93 * 94 * SLOF raw image loaded at 0, copies its romfs right below the flat 95 * device-tree, then position SLOF itself 31M below that 96 * 97 * So we set FW_OVERHEAD to 40MB which should account for all of that 98 * and more 99 * 100 * We load our kernel at 4M, leaving space for SLOF initial image 101 */ 102 #define FDT_MAX_ADDR 0x80000000 /* FDT must stay below that */ 103 #define FW_MAX_SIZE 0x400000 104 #define FW_FILE_NAME "slof.bin" 105 #define FW_FILE_NAME_VOF "vof.bin" 106 #define FW_OVERHEAD 0x2800000 107 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 108 109 #define MIN_RMA_SLOF (128 * MiB) 110 111 #define PHANDLE_INTC 0x00001111 112 113 /* These two functions implement the VCPU id numbering: one to compute them 114 * all and one to identify thread 0 of a VCORE. Any change to the first one 115 * is likely to have an impact on the second one, so let's keep them close. 116 */ 117 static int spapr_vcpu_id(SpaprMachineState *spapr, int cpu_index) 118 { 119 MachineState *ms = MACHINE(spapr); 120 unsigned int smp_threads = ms->smp.threads; 121 122 assert(spapr->vsmt); 123 return 124 (cpu_index / smp_threads) * spapr->vsmt + cpu_index % smp_threads; 125 } 126 static bool spapr_is_thread0_in_vcore(SpaprMachineState *spapr, 127 PowerPCCPU *cpu) 128 { 129 assert(spapr->vsmt); 130 return spapr_get_vcpu_id(cpu) % spapr->vsmt == 0; 131 } 132 133 static bool pre_2_10_vmstate_dummy_icp_needed(void *opaque) 134 { 135 /* Dummy entries correspond to unused ICPState objects in older QEMUs, 136 * and newer QEMUs don't even have them. In both cases, we don't want 137 * to send anything on the wire. 138 */ 139 return false; 140 } 141 142 static const VMStateDescription pre_2_10_vmstate_dummy_icp = { 143 .name = "icp/server", 144 .version_id = 1, 145 .minimum_version_id = 1, 146 .needed = pre_2_10_vmstate_dummy_icp_needed, 147 .fields = (VMStateField[]) { 148 VMSTATE_UNUSED(4), /* uint32_t xirr */ 149 VMSTATE_UNUSED(1), /* uint8_t pending_priority */ 150 VMSTATE_UNUSED(1), /* uint8_t mfrr */ 151 VMSTATE_END_OF_LIST() 152 }, 153 }; 154 155 static void pre_2_10_vmstate_register_dummy_icp(int i) 156 { 157 vmstate_register(NULL, i, &pre_2_10_vmstate_dummy_icp, 158 (void *)(uintptr_t) i); 159 } 160 161 static void pre_2_10_vmstate_unregister_dummy_icp(int i) 162 { 163 vmstate_unregister(NULL, &pre_2_10_vmstate_dummy_icp, 164 (void *)(uintptr_t) i); 165 } 166 167 int spapr_max_server_number(SpaprMachineState *spapr) 168 { 169 MachineState *ms = MACHINE(spapr); 170 171 assert(spapr->vsmt); 172 return DIV_ROUND_UP(ms->smp.max_cpus * spapr->vsmt, ms->smp.threads); 173 } 174 175 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 176 int smt_threads) 177 { 178 int i, ret = 0; 179 uint32_t servers_prop[smt_threads]; 180 uint32_t gservers_prop[smt_threads * 2]; 181 int index = spapr_get_vcpu_id(cpu); 182 183 if (cpu->compat_pvr) { 184 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 185 if (ret < 0) { 186 return ret; 187 } 188 } 189 190 /* Build interrupt servers and gservers properties */ 191 for (i = 0; i < smt_threads; i++) { 192 servers_prop[i] = cpu_to_be32(index + i); 193 /* Hack, direct the group queues back to cpu 0 */ 194 gservers_prop[i*2] = cpu_to_be32(index + i); 195 gservers_prop[i*2 + 1] = 0; 196 } 197 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 198 servers_prop, sizeof(servers_prop)); 199 if (ret < 0) { 200 return ret; 201 } 202 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 203 gservers_prop, sizeof(gservers_prop)); 204 205 return ret; 206 } 207 208 static void spapr_dt_pa_features(SpaprMachineState *spapr, 209 PowerPCCPU *cpu, 210 void *fdt, int offset) 211 { 212 uint8_t pa_features_206[] = { 6, 0, 213 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 214 uint8_t pa_features_207[] = { 24, 0, 215 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 216 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 217 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 218 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 219 uint8_t pa_features_300[] = { 66, 0, 220 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 221 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, SSO, 5: LE|CFAR|EB|LSQ */ 222 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /* 0 - 5 */ 223 /* 6: DS207 */ 224 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 225 /* 16: Vector */ 226 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 227 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 228 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 229 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 230 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 231 /* 30: MMR, 32: LE atomic, 34: EBB + ext EBB */ 232 0x80, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 233 /* 36: SPR SO, 38: Copy/Paste, 40: Radix MMU */ 234 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 36 - 41 */ 235 /* 42: PM, 44: PC RA, 46: SC vec'd */ 236 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 237 /* 48: SIMD, 50: QP BFP, 52: String */ 238 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 239 /* 54: DecFP, 56: DecI, 58: SHA */ 240 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 241 /* 60: NM atomic, 62: RNG */ 242 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 243 }; 244 uint8_t *pa_features = NULL; 245 size_t pa_size; 246 247 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_06, 0, cpu->compat_pvr)) { 248 pa_features = pa_features_206; 249 pa_size = sizeof(pa_features_206); 250 } 251 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_2_07, 0, cpu->compat_pvr)) { 252 pa_features = pa_features_207; 253 pa_size = sizeof(pa_features_207); 254 } 255 if (ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0, cpu->compat_pvr)) { 256 pa_features = pa_features_300; 257 pa_size = sizeof(pa_features_300); 258 } 259 if (!pa_features) { 260 return; 261 } 262 263 if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) { 264 /* 265 * Note: we keep CI large pages off by default because a 64K capable 266 * guest provisioned with large pages might otherwise try to map a qemu 267 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 268 * even if that qemu runs on a 4k host. 269 * We dd this bit back here if we are confident this is not an issue 270 */ 271 pa_features[3] |= 0x20; 272 } 273 if ((spapr_get_cap(spapr, SPAPR_CAP_HTM) != 0) && pa_size > 24) { 274 pa_features[24] |= 0x80; /* Transactional memory support */ 275 } 276 if (spapr->cas_pre_isa3_guest && pa_size > 40) { 277 /* Workaround for broken kernels that attempt (guest) radix 278 * mode when they can't handle it, if they see the radix bit set 279 * in pa-features. So hide it from them. */ 280 pa_features[40 + 2] &= ~0x80; /* Radix MMU */ 281 } 282 283 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 284 } 285 286 static hwaddr spapr_node0_size(MachineState *machine) 287 { 288 if (machine->numa_state->num_nodes) { 289 int i; 290 for (i = 0; i < machine->numa_state->num_nodes; ++i) { 291 if (machine->numa_state->nodes[i].node_mem) { 292 return MIN(pow2floor(machine->numa_state->nodes[i].node_mem), 293 machine->ram_size); 294 } 295 } 296 } 297 return machine->ram_size; 298 } 299 300 static void add_str(GString *s, const gchar *s1) 301 { 302 g_string_append_len(s, s1, strlen(s1) + 1); 303 } 304 305 static int spapr_dt_memory_node(SpaprMachineState *spapr, void *fdt, int nodeid, 306 hwaddr start, hwaddr size) 307 { 308 char mem_name[32]; 309 uint64_t mem_reg_property[2]; 310 int off; 311 312 mem_reg_property[0] = cpu_to_be64(start); 313 mem_reg_property[1] = cpu_to_be64(size); 314 315 sprintf(mem_name, "memory@%" HWADDR_PRIx, start); 316 off = fdt_add_subnode(fdt, 0, mem_name); 317 _FDT(off); 318 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 319 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 320 sizeof(mem_reg_property)))); 321 spapr_numa_write_associativity_dt(spapr, fdt, off, nodeid); 322 return off; 323 } 324 325 static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t addr) 326 { 327 MemoryDeviceInfoList *info; 328 329 for (info = list; info; info = info->next) { 330 MemoryDeviceInfo *value = info->value; 331 332 if (value && value->type == MEMORY_DEVICE_INFO_KIND_DIMM) { 333 PCDIMMDeviceInfo *pcdimm_info = value->u.dimm.data; 334 335 if (addr >= pcdimm_info->addr && 336 addr < (pcdimm_info->addr + pcdimm_info->size)) { 337 return pcdimm_info->node; 338 } 339 } 340 } 341 342 return -1; 343 } 344 345 struct sPAPRDrconfCellV2 { 346 uint32_t seq_lmbs; 347 uint64_t base_addr; 348 uint32_t drc_index; 349 uint32_t aa_index; 350 uint32_t flags; 351 } QEMU_PACKED; 352 353 typedef struct DrconfCellQueue { 354 struct sPAPRDrconfCellV2 cell; 355 QSIMPLEQ_ENTRY(DrconfCellQueue) entry; 356 } DrconfCellQueue; 357 358 static DrconfCellQueue * 359 spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_addr, 360 uint32_t drc_index, uint32_t aa_index, 361 uint32_t flags) 362 { 363 DrconfCellQueue *elem; 364 365 elem = g_malloc0(sizeof(*elem)); 366 elem->cell.seq_lmbs = cpu_to_be32(seq_lmbs); 367 elem->cell.base_addr = cpu_to_be64(base_addr); 368 elem->cell.drc_index = cpu_to_be32(drc_index); 369 elem->cell.aa_index = cpu_to_be32(aa_index); 370 elem->cell.flags = cpu_to_be32(flags); 371 372 return elem; 373 } 374 375 static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, 376 int offset, MemoryDeviceInfoList *dimms) 377 { 378 MachineState *machine = MACHINE(spapr); 379 uint8_t *int_buf, *cur_index; 380 int ret; 381 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 382 uint64_t addr, cur_addr, size; 383 uint32_t nr_boot_lmbs = (machine->device_memory->base / lmb_size); 384 uint64_t mem_end = machine->device_memory->base + 385 memory_region_size(&machine->device_memory->mr); 386 uint32_t node, buf_len, nr_entries = 0; 387 SpaprDrc *drc; 388 DrconfCellQueue *elem, *next; 389 MemoryDeviceInfoList *info; 390 QSIMPLEQ_HEAD(, DrconfCellQueue) drconf_queue 391 = QSIMPLEQ_HEAD_INITIALIZER(drconf_queue); 392 393 /* Entry to cover RAM and the gap area */ 394 elem = spapr_get_drconf_cell(nr_boot_lmbs, 0, 0, -1, 395 SPAPR_LMB_FLAGS_RESERVED | 396 SPAPR_LMB_FLAGS_DRC_INVALID); 397 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 398 nr_entries++; 399 400 cur_addr = machine->device_memory->base; 401 for (info = dimms; info; info = info->next) { 402 PCDIMMDeviceInfo *di = info->value->u.dimm.data; 403 404 addr = di->addr; 405 size = di->size; 406 node = di->node; 407 408 /* 409 * The NVDIMM area is hotpluggable after the NVDIMM is unplugged. The 410 * area is marked hotpluggable in the next iteration for the bigger 411 * chunk including the NVDIMM occupied area. 412 */ 413 if (info->value->type == MEMORY_DEVICE_INFO_KIND_NVDIMM) 414 continue; 415 416 /* Entry for hot-pluggable area */ 417 if (cur_addr < addr) { 418 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 419 g_assert(drc); 420 elem = spapr_get_drconf_cell((addr - cur_addr) / lmb_size, 421 cur_addr, spapr_drc_index(drc), -1, 0); 422 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 423 nr_entries++; 424 } 425 426 /* Entry for DIMM */ 427 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, addr / lmb_size); 428 g_assert(drc); 429 elem = spapr_get_drconf_cell(size / lmb_size, addr, 430 spapr_drc_index(drc), node, 431 (SPAPR_LMB_FLAGS_ASSIGNED | 432 SPAPR_LMB_FLAGS_HOTREMOVABLE)); 433 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 434 nr_entries++; 435 cur_addr = addr + size; 436 } 437 438 /* Entry for remaining hotpluggable area */ 439 if (cur_addr < mem_end) { 440 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, cur_addr / lmb_size); 441 g_assert(drc); 442 elem = spapr_get_drconf_cell((mem_end - cur_addr) / lmb_size, 443 cur_addr, spapr_drc_index(drc), -1, 0); 444 QSIMPLEQ_INSERT_TAIL(&drconf_queue, elem, entry); 445 nr_entries++; 446 } 447 448 buf_len = nr_entries * sizeof(struct sPAPRDrconfCellV2) + sizeof(uint32_t); 449 int_buf = cur_index = g_malloc0(buf_len); 450 *(uint32_t *)int_buf = cpu_to_be32(nr_entries); 451 cur_index += sizeof(nr_entries); 452 453 QSIMPLEQ_FOREACH_SAFE(elem, &drconf_queue, entry, next) { 454 memcpy(cur_index, &elem->cell, sizeof(elem->cell)); 455 cur_index += sizeof(elem->cell); 456 QSIMPLEQ_REMOVE(&drconf_queue, elem, DrconfCellQueue, entry); 457 g_free(elem); 458 } 459 460 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory-v2", int_buf, buf_len); 461 g_free(int_buf); 462 if (ret < 0) { 463 return -1; 464 } 465 return 0; 466 } 467 468 static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, 469 int offset, MemoryDeviceInfoList *dimms) 470 { 471 MachineState *machine = MACHINE(spapr); 472 int i, ret; 473 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 474 uint32_t device_lmb_start = machine->device_memory->base / lmb_size; 475 uint32_t nr_lmbs = (machine->device_memory->base + 476 memory_region_size(&machine->device_memory->mr)) / 477 lmb_size; 478 uint32_t *int_buf, *cur_index, buf_len; 479 480 /* 481 * Allocate enough buffer size to fit in ibm,dynamic-memory 482 */ 483 buf_len = (nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1) * sizeof(uint32_t); 484 cur_index = int_buf = g_malloc0(buf_len); 485 int_buf[0] = cpu_to_be32(nr_lmbs); 486 cur_index++; 487 for (i = 0; i < nr_lmbs; i++) { 488 uint64_t addr = i * lmb_size; 489 uint32_t *dynamic_memory = cur_index; 490 491 if (i >= device_lmb_start) { 492 SpaprDrc *drc; 493 494 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, i); 495 g_assert(drc); 496 497 dynamic_memory[0] = cpu_to_be32(addr >> 32); 498 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 499 dynamic_memory[2] = cpu_to_be32(spapr_drc_index(drc)); 500 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 501 dynamic_memory[4] = cpu_to_be32(spapr_pc_dimm_node(dimms, addr)); 502 if (memory_region_present(get_system_memory(), addr)) { 503 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 504 } else { 505 dynamic_memory[5] = cpu_to_be32(0); 506 } 507 } else { 508 /* 509 * LMB information for RMA, boot time RAM and gap b/n RAM and 510 * device memory region -- all these are marked as reserved 511 * and as having no valid DRC. 512 */ 513 dynamic_memory[0] = cpu_to_be32(addr >> 32); 514 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 515 dynamic_memory[2] = cpu_to_be32(0); 516 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 517 dynamic_memory[4] = cpu_to_be32(-1); 518 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 519 SPAPR_LMB_FLAGS_DRC_INVALID); 520 } 521 522 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 523 } 524 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 525 g_free(int_buf); 526 if (ret < 0) { 527 return -1; 528 } 529 return 0; 530 } 531 532 /* 533 * Adds ibm,dynamic-reconfiguration-memory node. 534 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 535 * of this device tree node. 536 */ 537 static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spapr, 538 void *fdt) 539 { 540 MachineState *machine = MACHINE(spapr); 541 int ret, offset; 542 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 543 uint32_t prop_lmb_size[] = {cpu_to_be32(lmb_size >> 32), 544 cpu_to_be32(lmb_size & 0xffffffff)}; 545 MemoryDeviceInfoList *dimms = NULL; 546 547 /* 548 * Don't create the node if there is no device memory 549 */ 550 if (machine->ram_size == machine->maxram_size) { 551 return 0; 552 } 553 554 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 555 556 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 557 sizeof(prop_lmb_size)); 558 if (ret < 0) { 559 return ret; 560 } 561 562 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 563 if (ret < 0) { 564 return ret; 565 } 566 567 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 568 if (ret < 0) { 569 return ret; 570 } 571 572 /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ 573 dimms = qmp_memory_device_list(); 574 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { 575 ret = spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); 576 } else { 577 ret = spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); 578 } 579 qapi_free_MemoryDeviceInfoList(dimms); 580 581 if (ret < 0) { 582 return ret; 583 } 584 585 ret = spapr_numa_write_assoc_lookup_arrays(spapr, fdt, offset); 586 587 return ret; 588 } 589 590 static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) 591 { 592 MachineState *machine = MACHINE(spapr); 593 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 594 hwaddr mem_start, node_size; 595 int i, nb_nodes = machine->numa_state->num_nodes; 596 NodeInfo *nodes = machine->numa_state->nodes; 597 598 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 599 if (!nodes[i].node_mem) { 600 continue; 601 } 602 if (mem_start >= machine->ram_size) { 603 node_size = 0; 604 } else { 605 node_size = nodes[i].node_mem; 606 if (node_size > machine->ram_size - mem_start) { 607 node_size = machine->ram_size - mem_start; 608 } 609 } 610 if (!mem_start) { 611 /* spapr_machine_init() checks for rma_size <= node0_size 612 * already */ 613 spapr_dt_memory_node(spapr, fdt, i, 0, spapr->rma_size); 614 mem_start += spapr->rma_size; 615 node_size -= spapr->rma_size; 616 } 617 for ( ; node_size; ) { 618 hwaddr sizetmp = pow2floor(node_size); 619 620 /* mem_start != 0 here */ 621 if (ctzl(mem_start) < ctzl(sizetmp)) { 622 sizetmp = 1ULL << ctzl(mem_start); 623 } 624 625 spapr_dt_memory_node(spapr, fdt, i, mem_start, sizetmp); 626 node_size -= sizetmp; 627 mem_start += sizetmp; 628 } 629 } 630 631 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 632 if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { 633 int ret; 634 635 g_assert(smc->dr_lmb_enabled); 636 ret = spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); 637 if (ret) { 638 return ret; 639 } 640 } 641 642 return 0; 643 } 644 645 static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, 646 SpaprMachineState *spapr) 647 { 648 MachineState *ms = MACHINE(spapr); 649 PowerPCCPU *cpu = POWERPC_CPU(cs); 650 CPUPPCState *env = &cpu->env; 651 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 652 int index = spapr_get_vcpu_id(cpu); 653 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 654 0xffffffff, 0xffffffff}; 655 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 656 : SPAPR_TIMEBASE_FREQ; 657 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 658 uint32_t page_sizes_prop[64]; 659 size_t page_sizes_prop_size; 660 unsigned int smp_threads = ms->smp.threads; 661 uint32_t vcpus_per_socket = smp_threads * ms->smp.cores; 662 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 663 int compat_smt = MIN(smp_threads, ppc_compat_max_vthreads(cpu)); 664 SpaprDrc *drc; 665 int drc_index; 666 uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; 667 int i; 668 669 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); 670 if (drc) { 671 drc_index = spapr_drc_index(drc); 672 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 673 } 674 675 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 676 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 677 678 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 679 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 680 env->dcache_line_size))); 681 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 682 env->dcache_line_size))); 683 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 684 env->icache_line_size))); 685 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 686 env->icache_line_size))); 687 688 if (pcc->l1_dcache_size) { 689 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 690 pcc->l1_dcache_size))); 691 } else { 692 warn_report("Unknown L1 dcache size for cpu"); 693 } 694 if (pcc->l1_icache_size) { 695 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 696 pcc->l1_icache_size))); 697 } else { 698 warn_report("Unknown L1 icache size for cpu"); 699 } 700 701 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 702 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 703 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_size))); 704 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->slb_size))); 705 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 706 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 707 708 if (ppc_has_spr(cpu, SPR_PURR)) { 709 _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); 710 } 711 if (ppc_has_spr(cpu, SPR_PURR)) { 712 _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); 713 } 714 715 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 716 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 717 segs, sizeof(segs)))); 718 } 719 720 /* Advertise VSX (vector extensions) if available 721 * 1 == VMX / Altivec available 722 * 2 == VSX available 723 * 724 * Only CPUs for which we create core types in spapr_cpu_core.c 725 * are possible, and all of those have VMX */ 726 if (env->insns_flags & PPC_ALTIVEC) { 727 if (spapr_get_cap(spapr, SPAPR_CAP_VSX) != 0) { 728 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); 729 } else { 730 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); 731 } 732 } 733 734 /* Advertise DFP (Decimal Floating Point) if available 735 * 0 / no property == no DFP 736 * 1 == DFP available */ 737 if (spapr_get_cap(spapr, SPAPR_CAP_DFP) != 0) { 738 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 739 } 740 741 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 742 sizeof(page_sizes_prop)); 743 if (page_sizes_prop_size) { 744 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 745 page_sizes_prop, page_sizes_prop_size))); 746 } 747 748 spapr_dt_pa_features(spapr, cpu, fdt, offset); 749 750 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 751 cs->cpu_index / vcpus_per_socket))); 752 753 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 754 pft_size_prop, sizeof(pft_size_prop)))); 755 756 if (ms->numa_state->num_nodes > 1) { 757 _FDT(spapr_numa_fixup_cpu_dt(spapr, fdt, offset, cpu)); 758 } 759 760 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 761 762 if (pcc->radix_page_info) { 763 for (i = 0; i < pcc->radix_page_info->count; i++) { 764 radix_AP_encodings[i] = 765 cpu_to_be32(pcc->radix_page_info->entries[i]); 766 } 767 _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", 768 radix_AP_encodings, 769 pcc->radix_page_info->count * 770 sizeof(radix_AP_encodings[0])))); 771 } 772 773 /* 774 * We set this property to let the guest know that it can use the large 775 * decrementer and its width in bits. 776 */ 777 if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) != SPAPR_CAP_OFF) 778 _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", 779 pcc->lrg_decr_bits))); 780 } 781 782 static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) 783 { 784 CPUState **rev; 785 CPUState *cs; 786 int n_cpus; 787 int cpus_offset; 788 int i; 789 790 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 791 _FDT(cpus_offset); 792 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 793 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 794 795 /* 796 * We walk the CPUs in reverse order to ensure that CPU DT nodes 797 * created by fdt_add_subnode() end up in the right order in FDT 798 * for the guest kernel the enumerate the CPUs correctly. 799 * 800 * The CPU list cannot be traversed in reverse order, so we need 801 * to do extra work. 802 */ 803 n_cpus = 0; 804 rev = NULL; 805 CPU_FOREACH(cs) { 806 rev = g_renew(CPUState *, rev, n_cpus + 1); 807 rev[n_cpus++] = cs; 808 } 809 810 for (i = n_cpus - 1; i >= 0; i--) { 811 CPUState *cs = rev[i]; 812 PowerPCCPU *cpu = POWERPC_CPU(cs); 813 int index = spapr_get_vcpu_id(cpu); 814 DeviceClass *dc = DEVICE_GET_CLASS(cs); 815 g_autofree char *nodename = NULL; 816 int offset; 817 818 if (!spapr_is_thread0_in_vcore(spapr, cpu)) { 819 continue; 820 } 821 822 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 823 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 824 _FDT(offset); 825 spapr_dt_cpu(cs, fdt, offset, spapr); 826 } 827 828 g_free(rev); 829 } 830 831 static int spapr_dt_rng(void *fdt) 832 { 833 int node; 834 int ret; 835 836 node = qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); 837 if (node <= 0) { 838 return -1; 839 } 840 ret = fdt_setprop_string(fdt, node, "device_type", 841 "ibm,platform-facilities"); 842 ret |= fdt_setprop_cell(fdt, node, "#address-cells", 0x1); 843 ret |= fdt_setprop_cell(fdt, node, "#size-cells", 0x0); 844 845 node = fdt_add_subnode(fdt, node, "ibm,random-v1"); 846 if (node <= 0) { 847 return -1; 848 } 849 ret |= fdt_setprop_string(fdt, node, "compatible", "ibm,random"); 850 851 return ret ? -1 : 0; 852 } 853 854 static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) 855 { 856 MachineState *ms = MACHINE(spapr); 857 int rtas; 858 GString *hypertas = g_string_sized_new(256); 859 GString *qemu_hypertas = g_string_sized_new(256); 860 uint64_t max_device_addr = MACHINE(spapr)->device_memory->base + 861 memory_region_size(&MACHINE(spapr)->device_memory->mr); 862 uint32_t lrdr_capacity[] = { 863 cpu_to_be32(max_device_addr >> 32), 864 cpu_to_be32(max_device_addr & 0xffffffff), 865 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE >> 32), 866 cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE & 0xffffffff), 867 cpu_to_be32(ms->smp.max_cpus / ms->smp.threads), 868 }; 869 870 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 871 872 /* hypertas */ 873 add_str(hypertas, "hcall-pft"); 874 add_str(hypertas, "hcall-term"); 875 add_str(hypertas, "hcall-dabr"); 876 add_str(hypertas, "hcall-interrupt"); 877 add_str(hypertas, "hcall-tce"); 878 add_str(hypertas, "hcall-vio"); 879 add_str(hypertas, "hcall-splpar"); 880 add_str(hypertas, "hcall-join"); 881 add_str(hypertas, "hcall-bulk"); 882 add_str(hypertas, "hcall-set-mode"); 883 add_str(hypertas, "hcall-sprg0"); 884 add_str(hypertas, "hcall-copy"); 885 add_str(hypertas, "hcall-debug"); 886 add_str(hypertas, "hcall-vphn"); 887 if (spapr_get_cap(spapr, SPAPR_CAP_RPT_INVALIDATE) == SPAPR_CAP_ON) { 888 add_str(hypertas, "hcall-rpt-invalidate"); 889 } 890 891 add_str(qemu_hypertas, "hcall-memop1"); 892 893 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 894 add_str(hypertas, "hcall-multi-tce"); 895 } 896 897 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 898 add_str(hypertas, "hcall-hpt-resize"); 899 } 900 901 add_str(hypertas, "hcall-watchdog"); 902 903 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 904 hypertas->str, hypertas->len)); 905 g_string_free(hypertas, TRUE); 906 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 907 qemu_hypertas->str, qemu_hypertas->len)); 908 g_string_free(qemu_hypertas, TRUE); 909 910 spapr_numa_write_rtas_dt(spapr, fdt, rtas); 911 912 /* 913 * FWNMI reserves RTAS_ERROR_LOG_MAX for the machine check error log, 914 * and 16 bytes per CPU for system reset error log plus an extra 8 bytes. 915 * 916 * The system reset requirements are driven by existing Linux and PowerVM 917 * implementation which (contrary to PAPR) saves r3 in the error log 918 * structure like machine check, so Linux expects to find the saved r3 919 * value at the address in r3 upon FWNMI-enabled sreset interrupt (and 920 * does not look at the error value). 921 * 922 * System reset interrupts are not subject to interlock like machine 923 * check, so this memory area could be corrupted if the sreset is 924 * interrupted by a machine check (or vice versa) if it was shared. To 925 * prevent this, system reset uses per-CPU areas for the sreset save 926 * area. A system reset that interrupts a system reset handler could 927 * still overwrite this area, but Linux doesn't try to recover in that 928 * case anyway. 929 * 930 * The extra 8 bytes is required because Linux's FWNMI error log check 931 * is off-by-one. 932 * 933 * RTAS_MIN_SIZE is required for the RTAS blob itself. 934 */ 935 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-size", RTAS_MIN_SIZE + 936 RTAS_ERROR_LOG_MAX + 937 ms->smp.max_cpus * sizeof(uint64_t) * 2 + 938 sizeof(uint64_t))); 939 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 940 RTAS_ERROR_LOG_MAX)); 941 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 942 RTAS_EVENT_SCAN_RATE)); 943 944 g_assert(msi_nonbroken); 945 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 946 947 /* 948 * According to PAPR, rtas ibm,os-term does not guarantee a return 949 * back to the guest cpu. 950 * 951 * While an additional ibm,extended-os-term property indicates 952 * that rtas call return will always occur. Set this property. 953 */ 954 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 955 956 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 957 lrdr_capacity, sizeof(lrdr_capacity))); 958 959 spapr_dt_rtas_tokens(fdt, rtas); 960 } 961 962 /* 963 * Prepare ibm,arch-vec-5-platform-support, which indicates the MMU 964 * and the XIVE features that the guest may request and thus the valid 965 * values for bytes 23..26 of option vector 5: 966 */ 967 static void spapr_dt_ov5_platform_support(SpaprMachineState *spapr, void *fdt, 968 int chosen) 969 { 970 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 971 972 char val[2 * 4] = { 973 23, 0x00, /* XICS / XIVE mode */ 974 24, 0x00, /* Hash/Radix, filled in below. */ 975 25, 0x00, /* Hash options: Segment Tables == no, GTSE == no. */ 976 26, 0x40, /* Radix options: GTSE == yes. */ 977 }; 978 979 if (spapr->irq->xics && spapr->irq->xive) { 980 val[1] = SPAPR_OV5_XIVE_BOTH; 981 } else if (spapr->irq->xive) { 982 val[1] = SPAPR_OV5_XIVE_EXPLOIT; 983 } else { 984 assert(spapr->irq->xics); 985 val[1] = SPAPR_OV5_XIVE_LEGACY; 986 } 987 988 if (!ppc_check_compat(first_ppc_cpu, CPU_POWERPC_LOGICAL_3_00, 0, 989 first_ppc_cpu->compat_pvr)) { 990 /* 991 * If we're in a pre POWER9 compat mode then the guest should 992 * do hash and use the legacy interrupt mode 993 */ 994 val[1] = SPAPR_OV5_XIVE_LEGACY; /* XICS */ 995 val[3] = 0x00; /* Hash */ 996 spapr_check_mmu_mode(false); 997 } else if (kvm_enabled()) { 998 if (kvmppc_has_cap_mmu_radix() && kvmppc_has_cap_mmu_hash_v3()) { 999 val[3] = 0x80; /* OV5_MMU_BOTH */ 1000 } else if (kvmppc_has_cap_mmu_radix()) { 1001 val[3] = 0x40; /* OV5_MMU_RADIX_300 */ 1002 } else { 1003 val[3] = 0x00; /* Hash */ 1004 } 1005 } else { 1006 /* V3 MMU supports both hash and radix in tcg (with dynamic switching) */ 1007 val[3] = 0xC0; 1008 } 1009 _FDT(fdt_setprop(fdt, chosen, "ibm,arch-vec-5-platform-support", 1010 val, sizeof(val))); 1011 } 1012 1013 static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) 1014 { 1015 MachineState *machine = MACHINE(spapr); 1016 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1017 int chosen; 1018 1019 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 1020 1021 if (reset) { 1022 const char *boot_device = spapr->boot_device; 1023 g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 1024 size_t cb = 0; 1025 g_autofree char *bootlist = get_boot_devices_list(&cb); 1026 1027 if (machine->kernel_cmdline && machine->kernel_cmdline[0]) { 1028 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", 1029 machine->kernel_cmdline)); 1030 } 1031 1032 if (spapr->initrd_size) { 1033 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 1034 spapr->initrd_base)); 1035 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 1036 spapr->initrd_base + spapr->initrd_size)); 1037 } 1038 1039 if (spapr->kernel_size) { 1040 uint64_t kprop[2] = { cpu_to_be64(spapr->kernel_addr), 1041 cpu_to_be64(spapr->kernel_size) }; 1042 1043 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 1044 &kprop, sizeof(kprop))); 1045 if (spapr->kernel_le) { 1046 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 1047 } 1048 } 1049 if (machine->boot_config.has_menu && machine->boot_config.menu) { 1050 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", true))); 1051 } 1052 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 1053 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 1054 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 1055 1056 if (cb && bootlist) { 1057 int i; 1058 1059 for (i = 0; i < cb; i++) { 1060 if (bootlist[i] == '\n') { 1061 bootlist[i] = ' '; 1062 } 1063 } 1064 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 1065 } 1066 1067 if (boot_device && strlen(boot_device)) { 1068 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 1069 } 1070 1071 if (spapr->want_stdout_path && stdout_path) { 1072 /* 1073 * "linux,stdout-path" and "stdout" properties are 1074 * deprecated by linux kernel. New platforms should only 1075 * use the "stdout-path" property. Set the new property 1076 * and continue using older property to remain compatible 1077 * with the existing firmware. 1078 */ 1079 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 1080 _FDT(fdt_setprop_string(fdt, chosen, "stdout-path", stdout_path)); 1081 } 1082 1083 /* 1084 * We can deal with BAR reallocation just fine, advertise it 1085 * to the guest 1086 */ 1087 if (smc->linux_pci_probe) { 1088 _FDT(fdt_setprop_cell(fdt, chosen, "linux,pci-probe-only", 0)); 1089 } 1090 1091 spapr_dt_ov5_platform_support(spapr, fdt, chosen); 1092 } 1093 1094 _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); 1095 } 1096 1097 static void spapr_dt_hypervisor(SpaprMachineState *spapr, void *fdt) 1098 { 1099 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 1100 * KVM to work under pHyp with some guest co-operation */ 1101 int hypervisor; 1102 uint8_t hypercall[16]; 1103 1104 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 1105 /* indicate KVM hypercall interface */ 1106 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 1107 if (kvmppc_has_cap_fixup_hcalls()) { 1108 /* 1109 * Older KVM versions with older guest kernels were broken 1110 * with the magic page, don't allow the guest to map it. 1111 */ 1112 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 1113 sizeof(hypercall))) { 1114 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 1115 hypercall, sizeof(hypercall))); 1116 } 1117 } 1118 } 1119 1120 void *spapr_build_fdt(SpaprMachineState *spapr, bool reset, size_t space) 1121 { 1122 MachineState *machine = MACHINE(spapr); 1123 MachineClass *mc = MACHINE_GET_CLASS(machine); 1124 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1125 uint32_t root_drc_type_mask = 0; 1126 int ret; 1127 void *fdt; 1128 SpaprPhbState *phb; 1129 char *buf; 1130 1131 fdt = g_malloc0(space); 1132 _FDT((fdt_create_empty_tree(fdt, space))); 1133 1134 /* Root node */ 1135 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 1136 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 1137 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 1138 1139 /* Guest UUID & Name*/ 1140 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 1141 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 1142 if (qemu_uuid_set) { 1143 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 1144 } 1145 g_free(buf); 1146 1147 if (qemu_get_vm_name()) { 1148 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 1149 qemu_get_vm_name())); 1150 } 1151 1152 /* Host Model & Serial Number */ 1153 if (spapr->host_model) { 1154 _FDT(fdt_setprop_string(fdt, 0, "host-model", spapr->host_model)); 1155 } else if (smc->broken_host_serial_model && kvmppc_get_host_model(&buf)) { 1156 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 1157 g_free(buf); 1158 } 1159 1160 if (spapr->host_serial) { 1161 _FDT(fdt_setprop_string(fdt, 0, "host-serial", spapr->host_serial)); 1162 } else if (smc->broken_host_serial_model && kvmppc_get_host_serial(&buf)) { 1163 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 1164 g_free(buf); 1165 } 1166 1167 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 1168 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 1169 1170 /* /interrupt controller */ 1171 spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); 1172 1173 ret = spapr_dt_memory(spapr, fdt); 1174 if (ret < 0) { 1175 error_report("couldn't setup memory nodes in fdt"); 1176 exit(1); 1177 } 1178 1179 /* /vdevice */ 1180 spapr_dt_vdevice(spapr->vio_bus, fdt); 1181 1182 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 1183 ret = spapr_dt_rng(fdt); 1184 if (ret < 0) { 1185 error_report("could not set up rng device in the fdt"); 1186 exit(1); 1187 } 1188 } 1189 1190 QLIST_FOREACH(phb, &spapr->phbs, list) { 1191 ret = spapr_dt_phb(spapr, phb, PHANDLE_INTC, fdt, NULL); 1192 if (ret < 0) { 1193 error_report("couldn't setup PCI devices in fdt"); 1194 exit(1); 1195 } 1196 } 1197 1198 spapr_dt_cpus(fdt, spapr); 1199 1200 /* ibm,drc-indexes and friends */ 1201 if (smc->dr_lmb_enabled) { 1202 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_LMB; 1203 } 1204 if (smc->dr_phb_enabled) { 1205 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PHB; 1206 } 1207 if (mc->nvdimm_supported) { 1208 root_drc_type_mask |= SPAPR_DR_CONNECTOR_TYPE_PMEM; 1209 } 1210 if (root_drc_type_mask) { 1211 _FDT(spapr_dt_drc(fdt, 0, NULL, root_drc_type_mask)); 1212 } 1213 1214 if (mc->has_hotpluggable_cpus) { 1215 int offset = fdt_path_offset(fdt, "/cpus"); 1216 ret = spapr_dt_drc(fdt, offset, NULL, SPAPR_DR_CONNECTOR_TYPE_CPU); 1217 if (ret < 0) { 1218 error_report("Couldn't set up CPU DR device tree properties"); 1219 exit(1); 1220 } 1221 } 1222 1223 /* /event-sources */ 1224 spapr_dt_events(spapr, fdt); 1225 1226 /* /rtas */ 1227 spapr_dt_rtas(spapr, fdt); 1228 1229 /* /chosen */ 1230 spapr_dt_chosen(spapr, fdt, reset); 1231 1232 /* /hypervisor */ 1233 if (kvm_enabled()) { 1234 spapr_dt_hypervisor(spapr, fdt); 1235 } 1236 1237 /* Build memory reserve map */ 1238 if (reset) { 1239 if (spapr->kernel_size) { 1240 _FDT((fdt_add_mem_rsv(fdt, spapr->kernel_addr, 1241 spapr->kernel_size))); 1242 } 1243 if (spapr->initrd_size) { 1244 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, 1245 spapr->initrd_size))); 1246 } 1247 } 1248 1249 /* NVDIMM devices */ 1250 if (mc->nvdimm_supported) { 1251 spapr_dt_persistent_memory(spapr, fdt); 1252 } 1253 1254 return fdt; 1255 } 1256 1257 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1258 { 1259 SpaprMachineState *spapr = opaque; 1260 1261 return (addr & 0x0fffffff) + spapr->kernel_addr; 1262 } 1263 1264 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1265 PowerPCCPU *cpu) 1266 { 1267 CPUPPCState *env = &cpu->env; 1268 1269 /* The TCG path should also be holding the BQL at this point */ 1270 g_assert(qemu_mutex_iothread_locked()); 1271 1272 g_assert(!vhyp_cpu_in_nested(cpu)); 1273 1274 if (FIELD_EX64(env->msr, MSR, PR)) { 1275 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1276 env->gpr[3] = H_PRIVILEGE; 1277 } else { 1278 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1279 } 1280 } 1281 1282 struct LPCRSyncState { 1283 target_ulong value; 1284 target_ulong mask; 1285 }; 1286 1287 static void do_lpcr_sync(CPUState *cs, run_on_cpu_data arg) 1288 { 1289 struct LPCRSyncState *s = arg.host_ptr; 1290 PowerPCCPU *cpu = POWERPC_CPU(cs); 1291 CPUPPCState *env = &cpu->env; 1292 target_ulong lpcr; 1293 1294 cpu_synchronize_state(cs); 1295 lpcr = env->spr[SPR_LPCR]; 1296 lpcr &= ~s->mask; 1297 lpcr |= s->value; 1298 ppc_store_lpcr(cpu, lpcr); 1299 } 1300 1301 void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) 1302 { 1303 CPUState *cs; 1304 struct LPCRSyncState s = { 1305 .value = value, 1306 .mask = mask 1307 }; 1308 CPU_FOREACH(cs) { 1309 run_on_cpu(cs, do_lpcr_sync, RUN_ON_CPU_HOST_PTR(&s)); 1310 } 1311 } 1312 1313 static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, 1314 target_ulong lpid, ppc_v3_pate_t *entry) 1315 { 1316 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1317 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 1318 1319 if (!spapr_cpu->in_nested) { 1320 assert(lpid == 0); 1321 1322 /* Copy PATE1:GR into PATE0:HR */ 1323 entry->dw0 = spapr->patb_entry & PATE0_HR; 1324 entry->dw1 = spapr->patb_entry; 1325 1326 } else { 1327 uint64_t patb, pats; 1328 1329 assert(lpid != 0); 1330 1331 patb = spapr->nested_ptcr & PTCR_PATB; 1332 pats = spapr->nested_ptcr & PTCR_PATS; 1333 1334 /* Calculate number of entries */ 1335 pats = 1ull << (pats + 12 - 4); 1336 if (pats <= lpid) { 1337 return false; 1338 } 1339 1340 /* Grab entry */ 1341 patb += 16 * lpid; 1342 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 1343 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 1344 } 1345 1346 return true; 1347 } 1348 1349 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1350 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1351 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1352 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1353 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1354 1355 /* 1356 * Get the fd to access the kernel htab, re-opening it if necessary 1357 */ 1358 static int get_htab_fd(SpaprMachineState *spapr) 1359 { 1360 Error *local_err = NULL; 1361 1362 if (spapr->htab_fd >= 0) { 1363 return spapr->htab_fd; 1364 } 1365 1366 spapr->htab_fd = kvmppc_get_htab_fd(false, 0, &local_err); 1367 if (spapr->htab_fd < 0) { 1368 error_report_err(local_err); 1369 } 1370 1371 return spapr->htab_fd; 1372 } 1373 1374 void close_htab_fd(SpaprMachineState *spapr) 1375 { 1376 if (spapr->htab_fd >= 0) { 1377 close(spapr->htab_fd); 1378 } 1379 spapr->htab_fd = -1; 1380 } 1381 1382 static hwaddr spapr_hpt_mask(PPCVirtualHypervisor *vhyp) 1383 { 1384 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1385 1386 return HTAB_SIZE(spapr) / HASH_PTEG_SIZE_64 - 1; 1387 } 1388 1389 static target_ulong spapr_encode_hpt_for_kvm_pr(PPCVirtualHypervisor *vhyp) 1390 { 1391 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1392 1393 assert(kvm_enabled()); 1394 1395 if (!spapr->htab) { 1396 return 0; 1397 } 1398 1399 return (target_ulong)(uintptr_t)spapr->htab | (spapr->htab_shift - 18); 1400 } 1401 1402 static const ppc_hash_pte64_t *spapr_map_hptes(PPCVirtualHypervisor *vhyp, 1403 hwaddr ptex, int n) 1404 { 1405 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1406 hwaddr pte_offset = ptex * HASH_PTE_SIZE_64; 1407 1408 if (!spapr->htab) { 1409 /* 1410 * HTAB is controlled by KVM. Fetch into temporary buffer 1411 */ 1412 ppc_hash_pte64_t *hptes = g_malloc(n * HASH_PTE_SIZE_64); 1413 kvmppc_read_hptes(hptes, ptex, n); 1414 return hptes; 1415 } 1416 1417 /* 1418 * HTAB is controlled by QEMU. Just point to the internally 1419 * accessible PTEG. 1420 */ 1421 return (const ppc_hash_pte64_t *)(spapr->htab + pte_offset); 1422 } 1423 1424 static void spapr_unmap_hptes(PPCVirtualHypervisor *vhyp, 1425 const ppc_hash_pte64_t *hptes, 1426 hwaddr ptex, int n) 1427 { 1428 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1429 1430 if (!spapr->htab) { 1431 g_free((void *)hptes); 1432 } 1433 1434 /* Nothing to do for qemu managed HPT */ 1435 } 1436 1437 void spapr_store_hpte(PowerPCCPU *cpu, hwaddr ptex, 1438 uint64_t pte0, uint64_t pte1) 1439 { 1440 SpaprMachineState *spapr = SPAPR_MACHINE(cpu->vhyp); 1441 hwaddr offset = ptex * HASH_PTE_SIZE_64; 1442 1443 if (!spapr->htab) { 1444 kvmppc_write_hpte(ptex, pte0, pte1); 1445 } else { 1446 if (pte0 & HPTE64_V_VALID) { 1447 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1448 /* 1449 * When setting valid, we write PTE1 first. This ensures 1450 * proper synchronization with the reading code in 1451 * ppc_hash64_pteg_search() 1452 */ 1453 smp_wmb(); 1454 stq_p(spapr->htab + offset, pte0); 1455 } else { 1456 stq_p(spapr->htab + offset, pte0); 1457 /* 1458 * When clearing it we set PTE0 first. This ensures proper 1459 * synchronization with the reading code in 1460 * ppc_hash64_pteg_search() 1461 */ 1462 smp_wmb(); 1463 stq_p(spapr->htab + offset + HPTE64_DW1, pte1); 1464 } 1465 } 1466 } 1467 1468 static void spapr_hpte_set_c(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1469 uint64_t pte1) 1470 { 1471 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_C; 1472 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1473 1474 if (!spapr->htab) { 1475 /* There should always be a hash table when this is called */ 1476 error_report("spapr_hpte_set_c called with no hash table !"); 1477 return; 1478 } 1479 1480 /* The HW performs a non-atomic byte update */ 1481 stb_p(spapr->htab + offset, (pte1 & 0xff) | 0x80); 1482 } 1483 1484 static void spapr_hpte_set_r(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1485 uint64_t pte1) 1486 { 1487 hwaddr offset = ptex * HASH_PTE_SIZE_64 + HPTE64_DW1_R; 1488 SpaprMachineState *spapr = SPAPR_MACHINE(vhyp); 1489 1490 if (!spapr->htab) { 1491 /* There should always be a hash table when this is called */ 1492 error_report("spapr_hpte_set_r called with no hash table !"); 1493 return; 1494 } 1495 1496 /* The HW performs a non-atomic byte update */ 1497 stb_p(spapr->htab + offset, ((pte1 >> 8) & 0xff) | 0x01); 1498 } 1499 1500 int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1501 { 1502 int shift; 1503 1504 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1505 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1506 * that's much more than is needed for Linux guests */ 1507 shift = ctz64(pow2ceil(ramsize)) - 7; 1508 shift = MAX(shift, 18); /* Minimum architected size */ 1509 shift = MIN(shift, 46); /* Maximum architected size */ 1510 return shift; 1511 } 1512 1513 void spapr_free_hpt(SpaprMachineState *spapr) 1514 { 1515 g_free(spapr->htab); 1516 spapr->htab = NULL; 1517 spapr->htab_shift = 0; 1518 close_htab_fd(spapr); 1519 } 1520 1521 int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) 1522 { 1523 ERRP_GUARD(); 1524 long rc; 1525 1526 /* Clean up any HPT info from a previous boot */ 1527 spapr_free_hpt(spapr); 1528 1529 rc = kvmppc_reset_htab(shift); 1530 1531 if (rc == -EOPNOTSUPP) { 1532 error_setg(errp, "HPT not supported in nested guests"); 1533 return -EOPNOTSUPP; 1534 } 1535 1536 if (rc < 0) { 1537 /* kernel-side HPT needed, but couldn't allocate one */ 1538 error_setg_errno(errp, errno, "Failed to allocate KVM HPT of order %d", 1539 shift); 1540 error_append_hint(errp, "Try smaller maxmem?\n"); 1541 return -errno; 1542 } else if (rc > 0) { 1543 /* kernel-side HPT allocated */ 1544 if (rc != shift) { 1545 error_setg(errp, 1546 "Requested order %d HPT, but kernel allocated order %ld", 1547 shift, rc); 1548 error_append_hint(errp, "Try smaller maxmem?\n"); 1549 return -ENOSPC; 1550 } 1551 1552 spapr->htab_shift = shift; 1553 spapr->htab = NULL; 1554 } else { 1555 /* kernel-side HPT not needed, allocate in userspace instead */ 1556 size_t size = 1ULL << shift; 1557 int i; 1558 1559 spapr->htab = qemu_memalign(size, size); 1560 memset(spapr->htab, 0, size); 1561 spapr->htab_shift = shift; 1562 1563 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1564 DIRTY_HPTE(HPTE(spapr->htab, i)); 1565 } 1566 } 1567 /* We're setting up a hash table, so that means we're not radix */ 1568 spapr->patb_entry = 0; 1569 spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); 1570 return 0; 1571 } 1572 1573 void spapr_setup_hpt(SpaprMachineState *spapr) 1574 { 1575 int hpt_shift; 1576 1577 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 1578 hpt_shift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1579 } else { 1580 uint64_t current_ram_size; 1581 1582 current_ram_size = MACHINE(spapr)->ram_size + get_plugged_memory_size(); 1583 hpt_shift = spapr_hpt_shift_for_ramsize(current_ram_size); 1584 } 1585 spapr_reallocate_hpt(spapr, hpt_shift, &error_fatal); 1586 1587 if (kvm_enabled()) { 1588 hwaddr vrma_limit = kvmppc_vrma_limit(spapr->htab_shift); 1589 1590 /* Check our RMA fits in the possible VRMA */ 1591 if (vrma_limit < spapr->rma_size) { 1592 error_report("Unable to create %" HWADDR_PRIu 1593 "MiB RMA (VRMA only allows %" HWADDR_PRIu "MiB", 1594 spapr->rma_size / MiB, vrma_limit / MiB); 1595 exit(EXIT_FAILURE); 1596 } 1597 } 1598 } 1599 1600 void spapr_check_mmu_mode(bool guest_radix) 1601 { 1602 if (guest_radix) { 1603 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1604 error_report("Guest requested unavailable MMU mode (radix)."); 1605 exit(EXIT_FAILURE); 1606 } 1607 } else { 1608 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1609 && !kvmppc_has_cap_mmu_hash_v3()) { 1610 error_report("Guest requested unavailable MMU mode (hash)."); 1611 exit(EXIT_FAILURE); 1612 } 1613 } 1614 } 1615 1616 static void spapr_machine_reset(MachineState *machine) 1617 { 1618 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 1619 PowerPCCPU *first_ppc_cpu; 1620 hwaddr fdt_addr; 1621 void *fdt; 1622 int rc; 1623 1624 pef_kvm_reset(machine->cgs, &error_fatal); 1625 spapr_caps_apply(spapr); 1626 1627 first_ppc_cpu = POWERPC_CPU(first_cpu); 1628 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() && 1629 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 1630 spapr->max_compat_pvr)) { 1631 /* 1632 * If using KVM with radix mode available, VCPUs can be started 1633 * without a HPT because KVM will start them in radix mode. 1634 * Set the GR bit in PATE so that we know there is no HPT. 1635 */ 1636 spapr->patb_entry = PATE1_GR; 1637 spapr_set_all_lpcrs(LPCR_HR | LPCR_UPRT, LPCR_HR | LPCR_UPRT); 1638 } else { 1639 spapr_setup_hpt(spapr); 1640 } 1641 1642 qemu_devices_reset(); 1643 1644 spapr_ovec_cleanup(spapr->ov5_cas); 1645 spapr->ov5_cas = spapr_ovec_new(); 1646 1647 ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); 1648 1649 /* 1650 * This is fixing some of the default configuration of the XIVE 1651 * devices. To be called after the reset of the machine devices. 1652 */ 1653 spapr_irq_reset(spapr, &error_fatal); 1654 1655 /* 1656 * There is no CAS under qtest. Simulate one to please the code that 1657 * depends on spapr->ov5_cas. This is especially needed to test device 1658 * unplug, so we do that before resetting the DRCs. 1659 */ 1660 if (qtest_enabled()) { 1661 spapr_ovec_cleanup(spapr->ov5_cas); 1662 spapr->ov5_cas = spapr_ovec_clone(spapr->ov5); 1663 } 1664 1665 spapr_nvdimm_finish_flushes(); 1666 1667 /* DRC reset may cause a device to be unplugged. This will cause troubles 1668 * if this device is used by another device (eg, a running vhost backend 1669 * will crash QEMU if the DIMM holding the vring goes away). To avoid such 1670 * situations, we reset DRCs after all devices have been reset. 1671 */ 1672 spapr_drc_reset_all(spapr); 1673 1674 spapr_clear_pending_events(spapr); 1675 1676 /* 1677 * We place the device tree just below either the top of the RMA, 1678 * or just below 2GB, whichever is lower, so that it can be 1679 * processed with 32-bit real mode code if necessary 1680 */ 1681 fdt_addr = MIN(spapr->rma_size, FDT_MAX_ADDR) - FDT_MAX_SIZE; 1682 1683 fdt = spapr_build_fdt(spapr, true, FDT_MAX_SIZE); 1684 if (spapr->vof) { 1685 spapr_vof_reset(spapr, fdt, &error_fatal); 1686 /* 1687 * Do not pack the FDT as the client may change properties. 1688 * VOF client does not expect the FDT so we do not load it to the VM. 1689 */ 1690 } else { 1691 rc = fdt_pack(fdt); 1692 /* Should only fail if we've built a corrupted tree */ 1693 assert(rc == 0); 1694 1695 spapr_cpu_set_entry_state(first_ppc_cpu, SPAPR_ENTRY_POINT, 1696 0, fdt_addr, 0); 1697 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1698 } 1699 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1700 1701 g_free(spapr->fdt_blob); 1702 spapr->fdt_size = fdt_totalsize(fdt); 1703 spapr->fdt_initial_size = spapr->fdt_size; 1704 spapr->fdt_blob = fdt; 1705 1706 /* Set up the entry state */ 1707 first_ppc_cpu->env.gpr[5] = 0; 1708 1709 spapr->fwnmi_system_reset_addr = -1; 1710 spapr->fwnmi_machine_check_addr = -1; 1711 spapr->fwnmi_machine_check_interlock = -1; 1712 1713 /* Signal all vCPUs waiting on this condition */ 1714 qemu_cond_broadcast(&spapr->fwnmi_machine_check_interlock_cond); 1715 1716 migrate_del_blocker(spapr->fwnmi_migration_blocker); 1717 } 1718 1719 static void spapr_create_nvram(SpaprMachineState *spapr) 1720 { 1721 DeviceState *dev = qdev_new("spapr-nvram"); 1722 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1723 1724 if (dinfo) { 1725 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), 1726 &error_fatal); 1727 } 1728 1729 qdev_realize_and_unref(dev, &spapr->vio_bus->bus, &error_fatal); 1730 1731 spapr->nvram = (struct SpaprNvram *)dev; 1732 } 1733 1734 static void spapr_rtc_create(SpaprMachineState *spapr) 1735 { 1736 object_initialize_child_with_props(OBJECT(spapr), "rtc", &spapr->rtc, 1737 sizeof(spapr->rtc), TYPE_SPAPR_RTC, 1738 &error_fatal, NULL); 1739 qdev_realize(DEVICE(&spapr->rtc), NULL, &error_fatal); 1740 object_property_add_alias(OBJECT(spapr), "rtc-time", OBJECT(&spapr->rtc), 1741 "date"); 1742 } 1743 1744 /* Returns whether we want to use VGA or not */ 1745 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1746 { 1747 vga_interface_created = true; 1748 switch (vga_interface_type) { 1749 case VGA_NONE: 1750 return false; 1751 case VGA_DEVICE: 1752 return true; 1753 case VGA_STD: 1754 case VGA_VIRTIO: 1755 case VGA_CIRRUS: 1756 return pci_vga_init(pci_bus) != NULL; 1757 default: 1758 error_setg(errp, 1759 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1760 return false; 1761 } 1762 } 1763 1764 static int spapr_pre_load(void *opaque) 1765 { 1766 int rc; 1767 1768 rc = spapr_caps_pre_load(opaque); 1769 if (rc) { 1770 return rc; 1771 } 1772 1773 return 0; 1774 } 1775 1776 static int spapr_post_load(void *opaque, int version_id) 1777 { 1778 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1779 int err = 0; 1780 1781 err = spapr_caps_post_migration(spapr); 1782 if (err) { 1783 return err; 1784 } 1785 1786 /* 1787 * In earlier versions, there was no separate qdev for the PAPR 1788 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1789 * So when migrating from those versions, poke the incoming offset 1790 * value into the RTC device 1791 */ 1792 if (version_id < 3) { 1793 err = spapr_rtc_import_offset(&spapr->rtc, spapr->rtc_offset); 1794 if (err) { 1795 return err; 1796 } 1797 } 1798 1799 if (kvm_enabled() && spapr->patb_entry) { 1800 PowerPCCPU *cpu = POWERPC_CPU(first_cpu); 1801 bool radix = !!(spapr->patb_entry & PATE1_GR); 1802 bool gtse = !!(cpu->env.spr[SPR_LPCR] & LPCR_GTSE); 1803 1804 /* 1805 * Update LPCR:HR and UPRT as they may not be set properly in 1806 * the stream 1807 */ 1808 spapr_set_all_lpcrs(radix ? (LPCR_HR | LPCR_UPRT) : 0, 1809 LPCR_HR | LPCR_UPRT); 1810 1811 err = kvmppc_configure_v3_mmu(cpu, radix, gtse, spapr->patb_entry); 1812 if (err) { 1813 error_report("Process table config unsupported by the host"); 1814 return -EINVAL; 1815 } 1816 } 1817 1818 err = spapr_irq_post_load(spapr, version_id); 1819 if (err) { 1820 return err; 1821 } 1822 1823 return err; 1824 } 1825 1826 static int spapr_pre_save(void *opaque) 1827 { 1828 int rc; 1829 1830 rc = spapr_caps_pre_save(opaque); 1831 if (rc) { 1832 return rc; 1833 } 1834 1835 return 0; 1836 } 1837 1838 static bool version_before_3(void *opaque, int version_id) 1839 { 1840 return version_id < 3; 1841 } 1842 1843 static bool spapr_pending_events_needed(void *opaque) 1844 { 1845 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1846 return !QTAILQ_EMPTY(&spapr->pending_events); 1847 } 1848 1849 static const VMStateDescription vmstate_spapr_event_entry = { 1850 .name = "spapr_event_log_entry", 1851 .version_id = 1, 1852 .minimum_version_id = 1, 1853 .fields = (VMStateField[]) { 1854 VMSTATE_UINT32(summary, SpaprEventLogEntry), 1855 VMSTATE_UINT32(extended_length, SpaprEventLogEntry), 1856 VMSTATE_VBUFFER_ALLOC_UINT32(extended_log, SpaprEventLogEntry, 0, 1857 NULL, extended_length), 1858 VMSTATE_END_OF_LIST() 1859 }, 1860 }; 1861 1862 static const VMStateDescription vmstate_spapr_pending_events = { 1863 .name = "spapr_pending_events", 1864 .version_id = 1, 1865 .minimum_version_id = 1, 1866 .needed = spapr_pending_events_needed, 1867 .fields = (VMStateField[]) { 1868 VMSTATE_QTAILQ_V(pending_events, SpaprMachineState, 1, 1869 vmstate_spapr_event_entry, SpaprEventLogEntry, next), 1870 VMSTATE_END_OF_LIST() 1871 }, 1872 }; 1873 1874 static bool spapr_ov5_cas_needed(void *opaque) 1875 { 1876 SpaprMachineState *spapr = opaque; 1877 SpaprOptionVector *ov5_mask = spapr_ovec_new(); 1878 bool cas_needed; 1879 1880 /* Prior to the introduction of SpaprOptionVector, we had two option 1881 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1882 * Both of these options encode machine topology into the device-tree 1883 * in such a way that the now-booted OS should still be able to interact 1884 * appropriately with QEMU regardless of what options were actually 1885 * negotiatied on the source side. 1886 * 1887 * As such, we can avoid migrating the CAS-negotiated options if these 1888 * are the only options available on the current machine/platform. 1889 * Since these are the only options available for pseries-2.7 and 1890 * earlier, this allows us to maintain old->new/new->old migration 1891 * compatibility. 1892 * 1893 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1894 * via default pseries-2.8 machines and explicit command-line parameters. 1895 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1896 * of the actual CAS-negotiated values to continue working properly. For 1897 * example, availability of memory unplug depends on knowing whether 1898 * OV5_HP_EVT was negotiated via CAS. 1899 * 1900 * Thus, for any cases where the set of available CAS-negotiatable 1901 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1902 * include the CAS-negotiated options in the migration stream, unless 1903 * if they affect boot time behaviour only. 1904 */ 1905 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1906 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1907 spapr_ovec_set(ov5_mask, OV5_DRMEM_V2); 1908 1909 /* We need extra information if we have any bits outside the mask 1910 * defined above */ 1911 cas_needed = !spapr_ovec_subset(spapr->ov5, ov5_mask); 1912 1913 spapr_ovec_cleanup(ov5_mask); 1914 1915 return cas_needed; 1916 } 1917 1918 static const VMStateDescription vmstate_spapr_ov5_cas = { 1919 .name = "spapr_option_vector_ov5_cas", 1920 .version_id = 1, 1921 .minimum_version_id = 1, 1922 .needed = spapr_ov5_cas_needed, 1923 .fields = (VMStateField[]) { 1924 VMSTATE_STRUCT_POINTER_V(ov5_cas, SpaprMachineState, 1, 1925 vmstate_spapr_ovec, SpaprOptionVector), 1926 VMSTATE_END_OF_LIST() 1927 }, 1928 }; 1929 1930 static bool spapr_patb_entry_needed(void *opaque) 1931 { 1932 SpaprMachineState *spapr = opaque; 1933 1934 return !!spapr->patb_entry; 1935 } 1936 1937 static const VMStateDescription vmstate_spapr_patb_entry = { 1938 .name = "spapr_patb_entry", 1939 .version_id = 1, 1940 .minimum_version_id = 1, 1941 .needed = spapr_patb_entry_needed, 1942 .fields = (VMStateField[]) { 1943 VMSTATE_UINT64(patb_entry, SpaprMachineState), 1944 VMSTATE_END_OF_LIST() 1945 }, 1946 }; 1947 1948 static bool spapr_irq_map_needed(void *opaque) 1949 { 1950 SpaprMachineState *spapr = opaque; 1951 1952 return spapr->irq_map && !bitmap_empty(spapr->irq_map, spapr->irq_map_nr); 1953 } 1954 1955 static const VMStateDescription vmstate_spapr_irq_map = { 1956 .name = "spapr_irq_map", 1957 .version_id = 1, 1958 .minimum_version_id = 1, 1959 .needed = spapr_irq_map_needed, 1960 .fields = (VMStateField[]) { 1961 VMSTATE_BITMAP(irq_map, SpaprMachineState, 0, irq_map_nr), 1962 VMSTATE_END_OF_LIST() 1963 }, 1964 }; 1965 1966 static bool spapr_dtb_needed(void *opaque) 1967 { 1968 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(opaque); 1969 1970 return smc->update_dt_enabled; 1971 } 1972 1973 static int spapr_dtb_pre_load(void *opaque) 1974 { 1975 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 1976 1977 g_free(spapr->fdt_blob); 1978 spapr->fdt_blob = NULL; 1979 spapr->fdt_size = 0; 1980 1981 return 0; 1982 } 1983 1984 static const VMStateDescription vmstate_spapr_dtb = { 1985 .name = "spapr_dtb", 1986 .version_id = 1, 1987 .minimum_version_id = 1, 1988 .needed = spapr_dtb_needed, 1989 .pre_load = spapr_dtb_pre_load, 1990 .fields = (VMStateField[]) { 1991 VMSTATE_UINT32(fdt_initial_size, SpaprMachineState), 1992 VMSTATE_UINT32(fdt_size, SpaprMachineState), 1993 VMSTATE_VBUFFER_ALLOC_UINT32(fdt_blob, SpaprMachineState, 0, NULL, 1994 fdt_size), 1995 VMSTATE_END_OF_LIST() 1996 }, 1997 }; 1998 1999 static bool spapr_fwnmi_needed(void *opaque) 2000 { 2001 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2002 2003 return spapr->fwnmi_machine_check_addr != -1; 2004 } 2005 2006 static int spapr_fwnmi_pre_save(void *opaque) 2007 { 2008 SpaprMachineState *spapr = (SpaprMachineState *)opaque; 2009 2010 /* 2011 * Check if machine check handling is in progress and print a 2012 * warning message. 2013 */ 2014 if (spapr->fwnmi_machine_check_interlock != -1) { 2015 warn_report("A machine check is being handled during migration. The" 2016 "handler may run and log hardware error on the destination"); 2017 } 2018 2019 return 0; 2020 } 2021 2022 static const VMStateDescription vmstate_spapr_fwnmi = { 2023 .name = "spapr_fwnmi", 2024 .version_id = 1, 2025 .minimum_version_id = 1, 2026 .needed = spapr_fwnmi_needed, 2027 .pre_save = spapr_fwnmi_pre_save, 2028 .fields = (VMStateField[]) { 2029 VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), 2030 VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), 2031 VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), 2032 VMSTATE_END_OF_LIST() 2033 }, 2034 }; 2035 2036 static const VMStateDescription vmstate_spapr = { 2037 .name = "spapr", 2038 .version_id = 3, 2039 .minimum_version_id = 1, 2040 .pre_load = spapr_pre_load, 2041 .post_load = spapr_post_load, 2042 .pre_save = spapr_pre_save, 2043 .fields = (VMStateField[]) { 2044 /* used to be @next_irq */ 2045 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 2046 2047 /* RTC offset */ 2048 VMSTATE_UINT64_TEST(rtc_offset, SpaprMachineState, version_before_3), 2049 2050 VMSTATE_PPC_TIMEBASE_V(tb, SpaprMachineState, 2), 2051 VMSTATE_END_OF_LIST() 2052 }, 2053 .subsections = (const VMStateDescription*[]) { 2054 &vmstate_spapr_ov5_cas, 2055 &vmstate_spapr_patb_entry, 2056 &vmstate_spapr_pending_events, 2057 &vmstate_spapr_cap_htm, 2058 &vmstate_spapr_cap_vsx, 2059 &vmstate_spapr_cap_dfp, 2060 &vmstate_spapr_cap_cfpc, 2061 &vmstate_spapr_cap_sbbc, 2062 &vmstate_spapr_cap_ibs, 2063 &vmstate_spapr_cap_hpt_maxpagesize, 2064 &vmstate_spapr_irq_map, 2065 &vmstate_spapr_cap_nested_kvm_hv, 2066 &vmstate_spapr_dtb, 2067 &vmstate_spapr_cap_large_decr, 2068 &vmstate_spapr_cap_ccf_assist, 2069 &vmstate_spapr_cap_fwnmi, 2070 &vmstate_spapr_fwnmi, 2071 &vmstate_spapr_cap_rpt_invalidate, 2072 NULL 2073 } 2074 }; 2075 2076 static int htab_save_setup(QEMUFile *f, void *opaque) 2077 { 2078 SpaprMachineState *spapr = opaque; 2079 2080 /* "Iteration" header */ 2081 if (!spapr->htab_shift) { 2082 qemu_put_be32(f, -1); 2083 } else { 2084 qemu_put_be32(f, spapr->htab_shift); 2085 } 2086 2087 if (spapr->htab) { 2088 spapr->htab_save_index = 0; 2089 spapr->htab_first_pass = true; 2090 } else { 2091 if (spapr->htab_shift) { 2092 assert(kvm_enabled()); 2093 } 2094 } 2095 2096 2097 return 0; 2098 } 2099 2100 static void htab_save_chunk(QEMUFile *f, SpaprMachineState *spapr, 2101 int chunkstart, int n_valid, int n_invalid) 2102 { 2103 qemu_put_be32(f, chunkstart); 2104 qemu_put_be16(f, n_valid); 2105 qemu_put_be16(f, n_invalid); 2106 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 2107 HASH_PTE_SIZE_64 * n_valid); 2108 } 2109 2110 static void htab_save_end_marker(QEMUFile *f) 2111 { 2112 qemu_put_be32(f, 0); 2113 qemu_put_be16(f, 0); 2114 qemu_put_be16(f, 0); 2115 } 2116 2117 static void htab_save_first_pass(QEMUFile *f, SpaprMachineState *spapr, 2118 int64_t max_ns) 2119 { 2120 bool has_timeout = max_ns != -1; 2121 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2122 int index = spapr->htab_save_index; 2123 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2124 2125 assert(spapr->htab_first_pass); 2126 2127 do { 2128 int chunkstart; 2129 2130 /* Consume invalid HPTEs */ 2131 while ((index < htabslots) 2132 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2133 CLEAN_HPTE(HPTE(spapr->htab, index)); 2134 index++; 2135 } 2136 2137 /* Consume valid HPTEs */ 2138 chunkstart = index; 2139 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2140 && HPTE_VALID(HPTE(spapr->htab, index))) { 2141 CLEAN_HPTE(HPTE(spapr->htab, index)); 2142 index++; 2143 } 2144 2145 if (index > chunkstart) { 2146 int n_valid = index - chunkstart; 2147 2148 htab_save_chunk(f, spapr, chunkstart, n_valid, 0); 2149 2150 if (has_timeout && 2151 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2152 break; 2153 } 2154 } 2155 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 2156 2157 if (index >= htabslots) { 2158 assert(index == htabslots); 2159 index = 0; 2160 spapr->htab_first_pass = false; 2161 } 2162 spapr->htab_save_index = index; 2163 } 2164 2165 static int htab_save_later_pass(QEMUFile *f, SpaprMachineState *spapr, 2166 int64_t max_ns) 2167 { 2168 bool final = max_ns < 0; 2169 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 2170 int examined = 0, sent = 0; 2171 int index = spapr->htab_save_index; 2172 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 2173 2174 assert(!spapr->htab_first_pass); 2175 2176 do { 2177 int chunkstart, invalidstart; 2178 2179 /* Consume non-dirty HPTEs */ 2180 while ((index < htabslots) 2181 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 2182 index++; 2183 examined++; 2184 } 2185 2186 chunkstart = index; 2187 /* Consume valid dirty HPTEs */ 2188 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 2189 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2190 && HPTE_VALID(HPTE(spapr->htab, index))) { 2191 CLEAN_HPTE(HPTE(spapr->htab, index)); 2192 index++; 2193 examined++; 2194 } 2195 2196 invalidstart = index; 2197 /* Consume invalid dirty HPTEs */ 2198 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 2199 && HPTE_DIRTY(HPTE(spapr->htab, index)) 2200 && !HPTE_VALID(HPTE(spapr->htab, index))) { 2201 CLEAN_HPTE(HPTE(spapr->htab, index)); 2202 index++; 2203 examined++; 2204 } 2205 2206 if (index > chunkstart) { 2207 int n_valid = invalidstart - chunkstart; 2208 int n_invalid = index - invalidstart; 2209 2210 htab_save_chunk(f, spapr, chunkstart, n_valid, n_invalid); 2211 sent += index - chunkstart; 2212 2213 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 2214 break; 2215 } 2216 } 2217 2218 if (examined >= htabslots) { 2219 break; 2220 } 2221 2222 if (index >= htabslots) { 2223 assert(index == htabslots); 2224 index = 0; 2225 } 2226 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 2227 2228 if (index >= htabslots) { 2229 assert(index == htabslots); 2230 index = 0; 2231 } 2232 2233 spapr->htab_save_index = index; 2234 2235 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 2236 } 2237 2238 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 2239 #define MAX_KVM_BUF_SIZE 2048 2240 2241 static int htab_save_iterate(QEMUFile *f, void *opaque) 2242 { 2243 SpaprMachineState *spapr = opaque; 2244 int fd; 2245 int rc = 0; 2246 2247 /* Iteration header */ 2248 if (!spapr->htab_shift) { 2249 qemu_put_be32(f, -1); 2250 return 1; 2251 } else { 2252 qemu_put_be32(f, 0); 2253 } 2254 2255 if (!spapr->htab) { 2256 assert(kvm_enabled()); 2257 2258 fd = get_htab_fd(spapr); 2259 if (fd < 0) { 2260 return fd; 2261 } 2262 2263 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 2264 if (rc < 0) { 2265 return rc; 2266 } 2267 } else if (spapr->htab_first_pass) { 2268 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 2269 } else { 2270 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 2271 } 2272 2273 htab_save_end_marker(f); 2274 2275 return rc; 2276 } 2277 2278 static int htab_save_complete(QEMUFile *f, void *opaque) 2279 { 2280 SpaprMachineState *spapr = opaque; 2281 int fd; 2282 2283 /* Iteration header */ 2284 if (!spapr->htab_shift) { 2285 qemu_put_be32(f, -1); 2286 return 0; 2287 } else { 2288 qemu_put_be32(f, 0); 2289 } 2290 2291 if (!spapr->htab) { 2292 int rc; 2293 2294 assert(kvm_enabled()); 2295 2296 fd = get_htab_fd(spapr); 2297 if (fd < 0) { 2298 return fd; 2299 } 2300 2301 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 2302 if (rc < 0) { 2303 return rc; 2304 } 2305 } else { 2306 if (spapr->htab_first_pass) { 2307 htab_save_first_pass(f, spapr, -1); 2308 } 2309 htab_save_later_pass(f, spapr, -1); 2310 } 2311 2312 /* End marker */ 2313 htab_save_end_marker(f); 2314 2315 return 0; 2316 } 2317 2318 static int htab_load(QEMUFile *f, void *opaque, int version_id) 2319 { 2320 SpaprMachineState *spapr = opaque; 2321 uint32_t section_hdr; 2322 int fd = -1; 2323 Error *local_err = NULL; 2324 2325 if (version_id < 1 || version_id > 1) { 2326 error_report("htab_load() bad version"); 2327 return -EINVAL; 2328 } 2329 2330 section_hdr = qemu_get_be32(f); 2331 2332 if (section_hdr == -1) { 2333 spapr_free_hpt(spapr); 2334 return 0; 2335 } 2336 2337 if (section_hdr) { 2338 int ret; 2339 2340 /* First section gives the htab size */ 2341 ret = spapr_reallocate_hpt(spapr, section_hdr, &local_err); 2342 if (ret < 0) { 2343 error_report_err(local_err); 2344 return ret; 2345 } 2346 return 0; 2347 } 2348 2349 if (!spapr->htab) { 2350 assert(kvm_enabled()); 2351 2352 fd = kvmppc_get_htab_fd(true, 0, &local_err); 2353 if (fd < 0) { 2354 error_report_err(local_err); 2355 return fd; 2356 } 2357 } 2358 2359 while (true) { 2360 uint32_t index; 2361 uint16_t n_valid, n_invalid; 2362 2363 index = qemu_get_be32(f); 2364 n_valid = qemu_get_be16(f); 2365 n_invalid = qemu_get_be16(f); 2366 2367 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 2368 /* End of Stream */ 2369 break; 2370 } 2371 2372 if ((index + n_valid + n_invalid) > 2373 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 2374 /* Bad index in stream */ 2375 error_report( 2376 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 2377 index, n_valid, n_invalid, spapr->htab_shift); 2378 return -EINVAL; 2379 } 2380 2381 if (spapr->htab) { 2382 if (n_valid) { 2383 qemu_get_buffer(f, HPTE(spapr->htab, index), 2384 HASH_PTE_SIZE_64 * n_valid); 2385 } 2386 if (n_invalid) { 2387 memset(HPTE(spapr->htab, index + n_valid), 0, 2388 HASH_PTE_SIZE_64 * n_invalid); 2389 } 2390 } else { 2391 int rc; 2392 2393 assert(fd >= 0); 2394 2395 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid, 2396 &local_err); 2397 if (rc < 0) { 2398 error_report_err(local_err); 2399 return rc; 2400 } 2401 } 2402 } 2403 2404 if (!spapr->htab) { 2405 assert(fd >= 0); 2406 close(fd); 2407 } 2408 2409 return 0; 2410 } 2411 2412 static void htab_save_cleanup(void *opaque) 2413 { 2414 SpaprMachineState *spapr = opaque; 2415 2416 close_htab_fd(spapr); 2417 } 2418 2419 static SaveVMHandlers savevm_htab_handlers = { 2420 .save_setup = htab_save_setup, 2421 .save_live_iterate = htab_save_iterate, 2422 .save_live_complete_precopy = htab_save_complete, 2423 .save_cleanup = htab_save_cleanup, 2424 .load_state = htab_load, 2425 }; 2426 2427 static void spapr_boot_set(void *opaque, const char *boot_device, 2428 Error **errp) 2429 { 2430 SpaprMachineState *spapr = SPAPR_MACHINE(opaque); 2431 2432 g_free(spapr->boot_device); 2433 spapr->boot_device = g_strdup(boot_device); 2434 } 2435 2436 static void spapr_create_lmb_dr_connectors(SpaprMachineState *spapr) 2437 { 2438 MachineState *machine = MACHINE(spapr); 2439 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 2440 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 2441 int i; 2442 2443 for (i = 0; i < nr_lmbs; i++) { 2444 uint64_t addr; 2445 2446 addr = i * lmb_size + machine->device_memory->base; 2447 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_LMB, 2448 addr / lmb_size); 2449 } 2450 } 2451 2452 /* 2453 * If RAM size, maxmem size and individual node mem sizes aren't aligned 2454 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 2455 * since we can't support such unaligned sizes with DRCONF_MEMORY. 2456 */ 2457 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 2458 { 2459 int i; 2460 2461 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2462 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 2463 " is not aligned to %" PRIu64 " MiB", 2464 machine->ram_size, 2465 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2466 return; 2467 } 2468 2469 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 2470 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 2471 " is not aligned to %" PRIu64 " MiB", 2472 machine->ram_size, 2473 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2474 return; 2475 } 2476 2477 for (i = 0; i < machine->numa_state->num_nodes; i++) { 2478 if (machine->numa_state->nodes[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 2479 error_setg(errp, 2480 "Node %d memory size 0x%" PRIx64 2481 " is not aligned to %" PRIu64 " MiB", 2482 i, machine->numa_state->nodes[i].node_mem, 2483 SPAPR_MEMORY_BLOCK_SIZE / MiB); 2484 return; 2485 } 2486 } 2487 } 2488 2489 /* find cpu slot in machine->possible_cpus by core_id */ 2490 static CPUArchId *spapr_find_cpu_slot(MachineState *ms, uint32_t id, int *idx) 2491 { 2492 int index = id / ms->smp.threads; 2493 2494 if (index >= ms->possible_cpus->len) { 2495 return NULL; 2496 } 2497 if (idx) { 2498 *idx = index; 2499 } 2500 return &ms->possible_cpus->cpus[index]; 2501 } 2502 2503 static void spapr_set_vsmt_mode(SpaprMachineState *spapr, Error **errp) 2504 { 2505 MachineState *ms = MACHINE(spapr); 2506 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2507 Error *local_err = NULL; 2508 bool vsmt_user = !!spapr->vsmt; 2509 int kvm_smt = kvmppc_smt_threads(); 2510 int ret; 2511 unsigned int smp_threads = ms->smp.threads; 2512 2513 if (!kvm_enabled() && (smp_threads > 1)) { 2514 error_setg(errp, "TCG cannot support more than 1 thread/core " 2515 "on a pseries machine"); 2516 return; 2517 } 2518 if (!is_power_of_2(smp_threads)) { 2519 error_setg(errp, "Cannot support %d threads/core on a pseries " 2520 "machine because it must be a power of 2", smp_threads); 2521 return; 2522 } 2523 2524 /* Detemine the VSMT mode to use: */ 2525 if (vsmt_user) { 2526 if (spapr->vsmt < smp_threads) { 2527 error_setg(errp, "Cannot support VSMT mode %d" 2528 " because it must be >= threads/core (%d)", 2529 spapr->vsmt, smp_threads); 2530 return; 2531 } 2532 /* In this case, spapr->vsmt has been set by the command line */ 2533 } else if (!smc->smp_threads_vsmt) { 2534 /* 2535 * Default VSMT value is tricky, because we need it to be as 2536 * consistent as possible (for migration), but this requires 2537 * changing it for at least some existing cases. We pick 8 as 2538 * the value that we'd get with KVM on POWER8, the 2539 * overwhelmingly common case in production systems. 2540 */ 2541 spapr->vsmt = MAX(8, smp_threads); 2542 } else { 2543 spapr->vsmt = smp_threads; 2544 } 2545 2546 /* KVM: If necessary, set the SMT mode: */ 2547 if (kvm_enabled() && (spapr->vsmt != kvm_smt)) { 2548 ret = kvmppc_set_smt_threads(spapr->vsmt); 2549 if (ret) { 2550 /* Looks like KVM isn't able to change VSMT mode */ 2551 error_setg(&local_err, 2552 "Failed to set KVM's VSMT mode to %d (errno %d)", 2553 spapr->vsmt, ret); 2554 /* We can live with that if the default one is big enough 2555 * for the number of threads, and a submultiple of the one 2556 * we want. In this case we'll waste some vcpu ids, but 2557 * behaviour will be correct */ 2558 if ((kvm_smt >= smp_threads) && ((spapr->vsmt % kvm_smt) == 0)) { 2559 warn_report_err(local_err); 2560 } else { 2561 if (!vsmt_user) { 2562 error_append_hint(&local_err, 2563 "On PPC, a VM with %d threads/core" 2564 " on a host with %d threads/core" 2565 " requires the use of VSMT mode %d.\n", 2566 smp_threads, kvm_smt, spapr->vsmt); 2567 } 2568 kvmppc_error_append_smt_possible_hint(&local_err); 2569 error_propagate(errp, local_err); 2570 } 2571 } 2572 } 2573 /* else TCG: nothing to do currently */ 2574 } 2575 2576 static void spapr_init_cpus(SpaprMachineState *spapr) 2577 { 2578 MachineState *machine = MACHINE(spapr); 2579 MachineClass *mc = MACHINE_GET_CLASS(machine); 2580 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2581 const char *type = spapr_get_cpu_core_type(machine->cpu_type); 2582 const CPUArchIdList *possible_cpus; 2583 unsigned int smp_cpus = machine->smp.cpus; 2584 unsigned int smp_threads = machine->smp.threads; 2585 unsigned int max_cpus = machine->smp.max_cpus; 2586 int boot_cores_nr = smp_cpus / smp_threads; 2587 int i; 2588 2589 possible_cpus = mc->possible_cpu_arch_ids(machine); 2590 if (mc->has_hotpluggable_cpus) { 2591 if (smp_cpus % smp_threads) { 2592 error_report("smp_cpus (%u) must be multiple of threads (%u)", 2593 smp_cpus, smp_threads); 2594 exit(1); 2595 } 2596 if (max_cpus % smp_threads) { 2597 error_report("max_cpus (%u) must be multiple of threads (%u)", 2598 max_cpus, smp_threads); 2599 exit(1); 2600 } 2601 } else { 2602 if (max_cpus != smp_cpus) { 2603 error_report("This machine version does not support CPU hotplug"); 2604 exit(1); 2605 } 2606 boot_cores_nr = possible_cpus->len; 2607 } 2608 2609 if (smc->pre_2_10_has_unused_icps) { 2610 int i; 2611 2612 for (i = 0; i < spapr_max_server_number(spapr); i++) { 2613 /* Dummy entries get deregistered when real ICPState objects 2614 * are registered during CPU core hotplug. 2615 */ 2616 pre_2_10_vmstate_register_dummy_icp(i); 2617 } 2618 } 2619 2620 for (i = 0; i < possible_cpus->len; i++) { 2621 int core_id = i * smp_threads; 2622 2623 if (mc->has_hotpluggable_cpus) { 2624 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_CPU, 2625 spapr_vcpu_id(spapr, core_id)); 2626 } 2627 2628 if (i < boot_cores_nr) { 2629 Object *core = object_new(type); 2630 int nr_threads = smp_threads; 2631 2632 /* Handle the partially filled core for older machine types */ 2633 if ((i + 1) * smp_threads >= smp_cpus) { 2634 nr_threads = smp_cpus - i * smp_threads; 2635 } 2636 2637 object_property_set_int(core, "nr-threads", nr_threads, 2638 &error_fatal); 2639 object_property_set_int(core, CPU_CORE_PROP_CORE_ID, core_id, 2640 &error_fatal); 2641 qdev_realize(DEVICE(core), NULL, &error_fatal); 2642 2643 object_unref(core); 2644 } 2645 } 2646 } 2647 2648 static PCIHostState *spapr_create_default_phb(void) 2649 { 2650 DeviceState *dev; 2651 2652 dev = qdev_new(TYPE_SPAPR_PCI_HOST_BRIDGE); 2653 qdev_prop_set_uint32(dev, "index", 0); 2654 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 2655 2656 return PCI_HOST_BRIDGE(dev); 2657 } 2658 2659 static hwaddr spapr_rma_size(SpaprMachineState *spapr, Error **errp) 2660 { 2661 MachineState *machine = MACHINE(spapr); 2662 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 2663 hwaddr rma_size = machine->ram_size; 2664 hwaddr node0_size = spapr_node0_size(machine); 2665 2666 /* RMA has to fit in the first NUMA node */ 2667 rma_size = MIN(rma_size, node0_size); 2668 2669 /* 2670 * VRMA access is via a special 1TiB SLB mapping, so the RMA can 2671 * never exceed that 2672 */ 2673 rma_size = MIN(rma_size, 1 * TiB); 2674 2675 /* 2676 * Clamp the RMA size based on machine type. This is for 2677 * migration compatibility with older qemu versions, which limited 2678 * the RMA size for complicated and mostly bad reasons. 2679 */ 2680 if (smc->rma_limit) { 2681 rma_size = MIN(rma_size, smc->rma_limit); 2682 } 2683 2684 if (rma_size < MIN_RMA_SLOF) { 2685 error_setg(errp, 2686 "pSeries SLOF firmware requires >= %" HWADDR_PRIx 2687 "ldMiB guest RMA (Real Mode Area memory)", 2688 MIN_RMA_SLOF / MiB); 2689 return 0; 2690 } 2691 2692 return rma_size; 2693 } 2694 2695 static void spapr_create_nvdimm_dr_connectors(SpaprMachineState *spapr) 2696 { 2697 MachineState *machine = MACHINE(spapr); 2698 int i; 2699 2700 for (i = 0; i < machine->ram_slots; i++) { 2701 spapr_dr_connector_new(OBJECT(spapr), TYPE_SPAPR_DRC_PMEM, i); 2702 } 2703 } 2704 2705 /* pSeries LPAR / sPAPR hardware init */ 2706 static void spapr_machine_init(MachineState *machine) 2707 { 2708 SpaprMachineState *spapr = SPAPR_MACHINE(machine); 2709 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 2710 MachineClass *mc = MACHINE_GET_CLASS(machine); 2711 const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME; 2712 const char *bios_name = machine->firmware ?: bios_default; 2713 g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2714 const char *kernel_filename = machine->kernel_filename; 2715 const char *initrd_filename = machine->initrd_filename; 2716 PCIHostState *phb; 2717 bool has_vga; 2718 int i; 2719 MemoryRegion *sysmem = get_system_memory(); 2720 long load_limit, fw_size; 2721 Error *resize_hpt_err = NULL; 2722 2723 if (!filename) { 2724 error_report("Could not find LPAR firmware '%s'", bios_name); 2725 exit(1); 2726 } 2727 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2728 if (fw_size <= 0) { 2729 error_report("Could not load LPAR firmware '%s'", filename); 2730 exit(1); 2731 } 2732 2733 /* 2734 * if Secure VM (PEF) support is configured, then initialize it 2735 */ 2736 pef_kvm_init(machine->cgs, &error_fatal); 2737 2738 msi_nonbroken = true; 2739 2740 QLIST_INIT(&spapr->phbs); 2741 QTAILQ_INIT(&spapr->pending_dimm_unplugs); 2742 2743 /* Determine capabilities to run with */ 2744 spapr_caps_init(spapr); 2745 2746 kvmppc_check_papr_resize_hpt(&resize_hpt_err); 2747 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DEFAULT) { 2748 /* 2749 * If the user explicitly requested a mode we should either 2750 * supply it, or fail completely (which we do below). But if 2751 * it's not set explicitly, we reset our mode to something 2752 * that works 2753 */ 2754 if (resize_hpt_err) { 2755 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 2756 error_free(resize_hpt_err); 2757 resize_hpt_err = NULL; 2758 } else { 2759 spapr->resize_hpt = smc->resize_hpt_default; 2760 } 2761 } 2762 2763 assert(spapr->resize_hpt != SPAPR_RESIZE_HPT_DEFAULT); 2764 2765 if ((spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) && resize_hpt_err) { 2766 /* 2767 * User requested HPT resize, but this host can't supply it. Bail out 2768 */ 2769 error_report_err(resize_hpt_err); 2770 exit(1); 2771 } 2772 error_free(resize_hpt_err); 2773 2774 spapr->rma_size = spapr_rma_size(spapr, &error_fatal); 2775 2776 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 2777 load_limit = MIN(spapr->rma_size, FDT_MAX_ADDR) - FW_OVERHEAD; 2778 2779 /* 2780 * VSMT must be set in order to be able to compute VCPU ids, ie to 2781 * call spapr_max_server_number() or spapr_vcpu_id(). 2782 */ 2783 spapr_set_vsmt_mode(spapr, &error_fatal); 2784 2785 /* Set up Interrupt Controller before we create the VCPUs */ 2786 spapr_irq_init(spapr, &error_fatal); 2787 2788 /* Set up containers for ibm,client-architecture-support negotiated options 2789 */ 2790 spapr->ov5 = spapr_ovec_new(); 2791 spapr->ov5_cas = spapr_ovec_new(); 2792 2793 if (smc->dr_lmb_enabled) { 2794 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 2795 spapr_validate_node_memory(machine, &error_fatal); 2796 } 2797 2798 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 2799 2800 /* Do not advertise FORM2 NUMA support for pseries-6.1 and older */ 2801 if (!smc->pre_6_2_numa_affinity) { 2802 spapr_ovec_set(spapr->ov5, OV5_FORM2_AFFINITY); 2803 } 2804 2805 /* advertise support for dedicated HP event source to guests */ 2806 if (spapr->use_hotplug_event_source) { 2807 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 2808 } 2809 2810 /* advertise support for HPT resizing */ 2811 if (spapr->resize_hpt != SPAPR_RESIZE_HPT_DISABLED) { 2812 spapr_ovec_set(spapr->ov5, OV5_HPT_RESIZE); 2813 } 2814 2815 /* advertise support for ibm,dyamic-memory-v2 */ 2816 spapr_ovec_set(spapr->ov5, OV5_DRMEM_V2); 2817 2818 /* advertise XIVE on POWER9 machines */ 2819 if (spapr->irq->xive) { 2820 spapr_ovec_set(spapr->ov5, OV5_XIVE_EXPLOIT); 2821 } 2822 2823 /* init CPUs */ 2824 spapr_init_cpus(spapr); 2825 2826 spapr->gpu_numa_id = spapr_numa_initial_nvgpu_numa_id(machine); 2827 2828 /* Init numa_assoc_array */ 2829 spapr_numa_associativity_init(spapr, machine); 2830 2831 if ((!kvm_enabled() || kvmppc_has_cap_mmu_radix()) && 2832 ppc_type_check_compat(machine->cpu_type, CPU_POWERPC_LOGICAL_3_00, 0, 2833 spapr->max_compat_pvr)) { 2834 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_300); 2835 /* KVM and TCG always allow GTSE with radix... */ 2836 spapr_ovec_set(spapr->ov5, OV5_MMU_RADIX_GTSE); 2837 } 2838 /* ... but not with hash (currently). */ 2839 2840 if (kvm_enabled()) { 2841 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 2842 kvmppc_enable_logical_ci_hcalls(); 2843 kvmppc_enable_set_mode_hcall(); 2844 2845 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 2846 kvmppc_enable_clear_ref_mod_hcalls(); 2847 2848 /* Enable H_PAGE_INIT */ 2849 kvmppc_enable_h_page_init(); 2850 } 2851 2852 /* map RAM */ 2853 memory_region_add_subregion(sysmem, 0, machine->ram); 2854 2855 /* always allocate the device memory information */ 2856 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 2857 2858 /* initialize hotplug memory address space */ 2859 if (machine->ram_size < machine->maxram_size) { 2860 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 2861 /* 2862 * Limit the number of hotpluggable memory slots to half the number 2863 * slots that KVM supports, leaving the other half for PCI and other 2864 * devices. However ensure that number of slots doesn't drop below 32. 2865 */ 2866 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 2867 SPAPR_MAX_RAM_SLOTS; 2868 2869 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 2870 max_memslots = SPAPR_MAX_RAM_SLOTS; 2871 } 2872 if (machine->ram_slots > max_memslots) { 2873 error_report("Specified number of memory slots %" 2874 PRIu64" exceeds max supported %d", 2875 machine->ram_slots, max_memslots); 2876 exit(1); 2877 } 2878 2879 machine->device_memory->base = ROUND_UP(machine->ram_size, 2880 SPAPR_DEVICE_MEM_ALIGN); 2881 memory_region_init(&machine->device_memory->mr, OBJECT(spapr), 2882 "device-memory", device_mem_size); 2883 memory_region_add_subregion(sysmem, machine->device_memory->base, 2884 &machine->device_memory->mr); 2885 } 2886 2887 if (smc->dr_lmb_enabled) { 2888 spapr_create_lmb_dr_connectors(spapr); 2889 } 2890 2891 if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_ON) { 2892 /* Create the error string for live migration blocker */ 2893 error_setg(&spapr->fwnmi_migration_blocker, 2894 "A machine check is being handled during migration. The handler" 2895 "may run and log hardware error on the destination"); 2896 } 2897 2898 if (mc->nvdimm_supported) { 2899 spapr_create_nvdimm_dr_connectors(spapr); 2900 } 2901 2902 /* Set up RTAS event infrastructure */ 2903 spapr_events_init(spapr); 2904 2905 /* Set up the RTC RTAS interfaces */ 2906 spapr_rtc_create(spapr); 2907 2908 /* Set up VIO bus */ 2909 spapr->vio_bus = spapr_vio_bus_init(); 2910 2911 for (i = 0; serial_hd(i); i++) { 2912 spapr_vty_create(spapr->vio_bus, serial_hd(i)); 2913 } 2914 2915 /* We always have at least the nvram device on VIO */ 2916 spapr_create_nvram(spapr); 2917 2918 /* 2919 * Setup hotplug / dynamic-reconfiguration connectors. top-level 2920 * connectors (described in root DT node's "ibm,drc-types" property) 2921 * are pre-initialized here. additional child connectors (such as 2922 * connectors for a PHBs PCI slots) are added as needed during their 2923 * parent's realization. 2924 */ 2925 if (smc->dr_phb_enabled) { 2926 for (i = 0; i < SPAPR_MAX_PHBS; i++) { 2927 spapr_dr_connector_new(OBJECT(machine), TYPE_SPAPR_DRC_PHB, i); 2928 } 2929 } 2930 2931 /* Set up PCI */ 2932 spapr_pci_rtas_init(); 2933 2934 phb = spapr_create_default_phb(); 2935 2936 for (i = 0; i < nb_nics; i++) { 2937 NICInfo *nd = &nd_table[i]; 2938 2939 if (!nd->model) { 2940 nd->model = g_strdup("spapr-vlan"); 2941 } 2942 2943 if (g_str_equal(nd->model, "spapr-vlan") || 2944 g_str_equal(nd->model, "ibmveth")) { 2945 spapr_vlan_create(spapr->vio_bus, nd); 2946 } else { 2947 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2948 } 2949 } 2950 2951 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2952 spapr_vscsi_create(spapr->vio_bus); 2953 } 2954 2955 /* Graphics */ 2956 has_vga = spapr_vga_init(phb->bus, &error_fatal); 2957 if (has_vga) { 2958 spapr->want_stdout_path = !machine->enable_graphics; 2959 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2960 } else { 2961 spapr->want_stdout_path = true; 2962 } 2963 2964 if (machine->usb) { 2965 if (smc->use_ohci_by_default) { 2966 pci_create_simple(phb->bus, -1, "pci-ohci"); 2967 } else { 2968 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2969 } 2970 2971 if (has_vga) { 2972 USBBus *usb_bus = usb_bus_find(-1); 2973 2974 usb_create_simple(usb_bus, "usb-kbd"); 2975 usb_create_simple(usb_bus, "usb-mouse"); 2976 } 2977 } 2978 2979 if (kernel_filename) { 2980 uint64_t loaded_addr = 0; 2981 2982 spapr->kernel_size = load_elf(kernel_filename, NULL, 2983 translate_kernel_address, spapr, 2984 NULL, &loaded_addr, NULL, NULL, 1, 2985 PPC_ELF_MACHINE, 0, 0); 2986 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2987 spapr->kernel_size = load_elf(kernel_filename, NULL, 2988 translate_kernel_address, spapr, 2989 NULL, &loaded_addr, NULL, NULL, 0, 2990 PPC_ELF_MACHINE, 0, 0); 2991 spapr->kernel_le = spapr->kernel_size > 0; 2992 } 2993 if (spapr->kernel_size < 0) { 2994 error_report("error loading %s: %s", kernel_filename, 2995 load_elf_strerror(spapr->kernel_size)); 2996 exit(1); 2997 } 2998 2999 if (spapr->kernel_addr != loaded_addr) { 3000 warn_report("spapr: kernel_addr changed from 0x%"PRIx64 3001 " to 0x%"PRIx64, 3002 spapr->kernel_addr, loaded_addr); 3003 spapr->kernel_addr = loaded_addr; 3004 } 3005 3006 /* load initrd */ 3007 if (initrd_filename) { 3008 /* Try to locate the initrd in the gap between the kernel 3009 * and the firmware. Add a bit of space just in case 3010 */ 3011 spapr->initrd_base = (spapr->kernel_addr + spapr->kernel_size 3012 + 0x1ffff) & ~0xffff; 3013 spapr->initrd_size = load_image_targphys(initrd_filename, 3014 spapr->initrd_base, 3015 load_limit 3016 - spapr->initrd_base); 3017 if (spapr->initrd_size < 0) { 3018 error_report("could not load initial ram disk '%s'", 3019 initrd_filename); 3020 exit(1); 3021 } 3022 } 3023 } 3024 3025 /* FIXME: Should register things through the MachineState's qdev 3026 * interface, this is a legacy from the sPAPREnvironment structure 3027 * which predated MachineState but had a similar function */ 3028 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 3029 register_savevm_live("spapr/htab", VMSTATE_INSTANCE_ID_ANY, 1, 3030 &savevm_htab_handlers, spapr); 3031 3032 qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine)); 3033 3034 qemu_register_boot_set(spapr_boot_set, spapr); 3035 3036 /* 3037 * Nothing needs to be done to resume a suspended guest because 3038 * suspending does not change the machine state, so no need for 3039 * a ->wakeup method. 3040 */ 3041 qemu_register_wakeup_support(); 3042 3043 if (kvm_enabled()) { 3044 /* to stop and start vmclock */ 3045 qemu_add_vm_change_state_handler(cpu_ppc_clock_vm_state_change, 3046 &spapr->tb); 3047 3048 kvmppc_spapr_enable_inkernel_multitce(); 3049 } 3050 3051 qemu_cond_init(&spapr->fwnmi_machine_check_interlock_cond); 3052 if (spapr->vof) { 3053 spapr->vof->fw_size = fw_size; /* for claim() on itself */ 3054 spapr_register_hypercall(KVMPPC_H_VOF_CLIENT, spapr_h_vof_client); 3055 } 3056 3057 spapr_watchdog_init(spapr); 3058 } 3059 3060 #define DEFAULT_KVM_TYPE "auto" 3061 static int spapr_kvm_type(MachineState *machine, const char *vm_type) 3062 { 3063 /* 3064 * The use of g_ascii_strcasecmp() for 'hv' and 'pr' is to 3065 * accomodate the 'HV' and 'PV' formats that exists in the 3066 * wild. The 'auto' mode is being introduced already as 3067 * lower-case, thus we don't need to bother checking for 3068 * "AUTO". 3069 */ 3070 if (!vm_type || !strcmp(vm_type, DEFAULT_KVM_TYPE)) { 3071 return 0; 3072 } 3073 3074 if (!g_ascii_strcasecmp(vm_type, "hv")) { 3075 return 1; 3076 } 3077 3078 if (!g_ascii_strcasecmp(vm_type, "pr")) { 3079 return 2; 3080 } 3081 3082 error_report("Unknown kvm-type specified '%s'", vm_type); 3083 exit(1); 3084 } 3085 3086 /* 3087 * Implementation of an interface to adjust firmware path 3088 * for the bootindex property handling. 3089 */ 3090 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 3091 DeviceState *dev) 3092 { 3093 #define CAST(type, obj, name) \ 3094 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 3095 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 3096 SpaprPhbState *phb = CAST(SpaprPhbState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 3097 VHostSCSICommon *vsc = CAST(VHostSCSICommon, dev, TYPE_VHOST_SCSI_COMMON); 3098 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3099 3100 if (d && bus) { 3101 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 3102 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 3103 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 3104 3105 if (spapr) { 3106 /* 3107 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 3108 * In the top 16 bits of the 64-bit LUN, we use SRP luns of the form 3109 * 0x8000 | (target << 8) | (bus << 5) | lun 3110 * (see the "Logical unit addressing format" table in SAM5) 3111 */ 3112 unsigned id = 0x8000 | (d->id << 8) | (d->channel << 5) | d->lun; 3113 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3114 (uint64_t)id << 48); 3115 } else if (virtio) { 3116 /* 3117 * We use SRP luns of the form 01000000 | (target << 8) | lun 3118 * in the top 32 bits of the 64-bit LUN 3119 * Note: the quote above is from SLOF and it is wrong, 3120 * the actual binding is: 3121 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 3122 */ 3123 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 3124 if (d->lun >= 256) { 3125 /* Use the LUN "flat space addressing method" */ 3126 id |= 0x4000; 3127 } 3128 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3129 (uint64_t)id << 32); 3130 } else if (usb) { 3131 /* 3132 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 3133 * in the top 32 bits of the 64-bit LUN 3134 */ 3135 unsigned usb_port = atoi(usb->port->path); 3136 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 3137 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 3138 (uint64_t)id << 32); 3139 } 3140 } 3141 3142 /* 3143 * SLOF probes the USB devices, and if it recognizes that the device is a 3144 * storage device, it changes its name to "storage" instead of "usb-host", 3145 * and additionally adds a child node for the SCSI LUN, so the correct 3146 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 3147 */ 3148 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 3149 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 3150 if (usb_device_is_scsi_storage(usbdev)) { 3151 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 3152 } 3153 } 3154 3155 if (phb) { 3156 /* Replace "pci" with "pci@800000020000000" */ 3157 return g_strdup_printf("pci@%"PRIX64, phb->buid); 3158 } 3159 3160 if (vsc) { 3161 /* Same logic as virtio above */ 3162 unsigned id = 0x1000000 | (vsc->target << 16) | vsc->lun; 3163 return g_strdup_printf("disk@%"PRIX64, (uint64_t)id << 32); 3164 } 3165 3166 if (g_str_equal("pci-bridge", qdev_fw_name(dev))) { 3167 /* SLOF uses "pci" instead of "pci-bridge" for PCI bridges */ 3168 PCIDevice *pcidev = CAST(PCIDevice, dev, TYPE_PCI_DEVICE); 3169 return g_strdup_printf("pci@%x", PCI_SLOT(pcidev->devfn)); 3170 } 3171 3172 if (pcidev) { 3173 return spapr_pci_fw_dev_name(pcidev); 3174 } 3175 3176 return NULL; 3177 } 3178 3179 static char *spapr_get_kvm_type(Object *obj, Error **errp) 3180 { 3181 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3182 3183 return g_strdup(spapr->kvm_type); 3184 } 3185 3186 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 3187 { 3188 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3189 3190 g_free(spapr->kvm_type); 3191 spapr->kvm_type = g_strdup(value); 3192 } 3193 3194 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 3195 { 3196 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3197 3198 return spapr->use_hotplug_event_source; 3199 } 3200 3201 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 3202 Error **errp) 3203 { 3204 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3205 3206 spapr->use_hotplug_event_source = value; 3207 } 3208 3209 static bool spapr_get_msix_emulation(Object *obj, Error **errp) 3210 { 3211 return true; 3212 } 3213 3214 static char *spapr_get_resize_hpt(Object *obj, Error **errp) 3215 { 3216 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3217 3218 switch (spapr->resize_hpt) { 3219 case SPAPR_RESIZE_HPT_DEFAULT: 3220 return g_strdup("default"); 3221 case SPAPR_RESIZE_HPT_DISABLED: 3222 return g_strdup("disabled"); 3223 case SPAPR_RESIZE_HPT_ENABLED: 3224 return g_strdup("enabled"); 3225 case SPAPR_RESIZE_HPT_REQUIRED: 3226 return g_strdup("required"); 3227 } 3228 g_assert_not_reached(); 3229 } 3230 3231 static void spapr_set_resize_hpt(Object *obj, const char *value, Error **errp) 3232 { 3233 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3234 3235 if (strcmp(value, "default") == 0) { 3236 spapr->resize_hpt = SPAPR_RESIZE_HPT_DEFAULT; 3237 } else if (strcmp(value, "disabled") == 0) { 3238 spapr->resize_hpt = SPAPR_RESIZE_HPT_DISABLED; 3239 } else if (strcmp(value, "enabled") == 0) { 3240 spapr->resize_hpt = SPAPR_RESIZE_HPT_ENABLED; 3241 } else if (strcmp(value, "required") == 0) { 3242 spapr->resize_hpt = SPAPR_RESIZE_HPT_REQUIRED; 3243 } else { 3244 error_setg(errp, "Bad value for \"resize-hpt\" property"); 3245 } 3246 } 3247 3248 static bool spapr_get_vof(Object *obj, Error **errp) 3249 { 3250 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3251 3252 return spapr->vof != NULL; 3253 } 3254 3255 static void spapr_set_vof(Object *obj, bool value, Error **errp) 3256 { 3257 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3258 3259 if (spapr->vof) { 3260 vof_cleanup(spapr->vof); 3261 g_free(spapr->vof); 3262 spapr->vof = NULL; 3263 } 3264 if (!value) { 3265 return; 3266 } 3267 spapr->vof = g_malloc0(sizeof(*spapr->vof)); 3268 } 3269 3270 static char *spapr_get_ic_mode(Object *obj, Error **errp) 3271 { 3272 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3273 3274 if (spapr->irq == &spapr_irq_xics_legacy) { 3275 return g_strdup("legacy"); 3276 } else if (spapr->irq == &spapr_irq_xics) { 3277 return g_strdup("xics"); 3278 } else if (spapr->irq == &spapr_irq_xive) { 3279 return g_strdup("xive"); 3280 } else if (spapr->irq == &spapr_irq_dual) { 3281 return g_strdup("dual"); 3282 } 3283 g_assert_not_reached(); 3284 } 3285 3286 static void spapr_set_ic_mode(Object *obj, const char *value, Error **errp) 3287 { 3288 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3289 3290 if (SPAPR_MACHINE_GET_CLASS(spapr)->legacy_irq_allocation) { 3291 error_setg(errp, "This machine only uses the legacy XICS backend, don't pass ic-mode"); 3292 return; 3293 } 3294 3295 /* The legacy IRQ backend can not be set */ 3296 if (strcmp(value, "xics") == 0) { 3297 spapr->irq = &spapr_irq_xics; 3298 } else if (strcmp(value, "xive") == 0) { 3299 spapr->irq = &spapr_irq_xive; 3300 } else if (strcmp(value, "dual") == 0) { 3301 spapr->irq = &spapr_irq_dual; 3302 } else { 3303 error_setg(errp, "Bad value for \"ic-mode\" property"); 3304 } 3305 } 3306 3307 static char *spapr_get_host_model(Object *obj, Error **errp) 3308 { 3309 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3310 3311 return g_strdup(spapr->host_model); 3312 } 3313 3314 static void spapr_set_host_model(Object *obj, const char *value, Error **errp) 3315 { 3316 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3317 3318 g_free(spapr->host_model); 3319 spapr->host_model = g_strdup(value); 3320 } 3321 3322 static char *spapr_get_host_serial(Object *obj, Error **errp) 3323 { 3324 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3325 3326 return g_strdup(spapr->host_serial); 3327 } 3328 3329 static void spapr_set_host_serial(Object *obj, const char *value, Error **errp) 3330 { 3331 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3332 3333 g_free(spapr->host_serial); 3334 spapr->host_serial = g_strdup(value); 3335 } 3336 3337 static void spapr_instance_init(Object *obj) 3338 { 3339 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3340 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 3341 MachineState *ms = MACHINE(spapr); 3342 MachineClass *mc = MACHINE_GET_CLASS(ms); 3343 3344 /* 3345 * NVDIMM support went live in 5.1 without considering that, in 3346 * other archs, the user needs to enable NVDIMM support with the 3347 * 'nvdimm' machine option and the default behavior is NVDIMM 3348 * support disabled. It is too late to roll back to the standard 3349 * behavior without breaking 5.1 guests. 3350 */ 3351 if (mc->nvdimm_supported) { 3352 ms->nvdimms_state->is_enabled = true; 3353 } 3354 3355 spapr->htab_fd = -1; 3356 spapr->use_hotplug_event_source = true; 3357 spapr->kvm_type = g_strdup(DEFAULT_KVM_TYPE); 3358 object_property_add_str(obj, "kvm-type", 3359 spapr_get_kvm_type, spapr_set_kvm_type); 3360 object_property_set_description(obj, "kvm-type", 3361 "Specifies the KVM virtualization mode (auto," 3362 " hv, pr). Defaults to 'auto'. This mode will use" 3363 " any available KVM module loaded in the host," 3364 " where kvm_hv takes precedence if both kvm_hv and" 3365 " kvm_pr are loaded."); 3366 object_property_add_bool(obj, "modern-hotplug-events", 3367 spapr_get_modern_hotplug_events, 3368 spapr_set_modern_hotplug_events); 3369 object_property_set_description(obj, "modern-hotplug-events", 3370 "Use dedicated hotplug event mechanism in" 3371 " place of standard EPOW events when possible" 3372 " (required for memory hot-unplug support)"); 3373 ppc_compat_add_property(obj, "max-cpu-compat", &spapr->max_compat_pvr, 3374 "Maximum permitted CPU compatibility mode"); 3375 3376 object_property_add_str(obj, "resize-hpt", 3377 spapr_get_resize_hpt, spapr_set_resize_hpt); 3378 object_property_set_description(obj, "resize-hpt", 3379 "Resizing of the Hash Page Table (enabled, disabled, required)"); 3380 object_property_add_uint32_ptr(obj, "vsmt", 3381 &spapr->vsmt, OBJ_PROP_FLAG_READWRITE); 3382 object_property_set_description(obj, "vsmt", 3383 "Virtual SMT: KVM behaves as if this were" 3384 " the host's SMT mode"); 3385 3386 object_property_add_bool(obj, "vfio-no-msix-emulation", 3387 spapr_get_msix_emulation, NULL); 3388 3389 object_property_add_uint64_ptr(obj, "kernel-addr", 3390 &spapr->kernel_addr, OBJ_PROP_FLAG_READWRITE); 3391 object_property_set_description(obj, "kernel-addr", 3392 stringify(KERNEL_LOAD_ADDR) 3393 " for -kernel is the default"); 3394 spapr->kernel_addr = KERNEL_LOAD_ADDR; 3395 3396 object_property_add_bool(obj, "x-vof", spapr_get_vof, spapr_set_vof); 3397 object_property_set_description(obj, "x-vof", 3398 "Enable Virtual Open Firmware (experimental)"); 3399 3400 /* The machine class defines the default interrupt controller mode */ 3401 spapr->irq = smc->irq; 3402 object_property_add_str(obj, "ic-mode", spapr_get_ic_mode, 3403 spapr_set_ic_mode); 3404 object_property_set_description(obj, "ic-mode", 3405 "Specifies the interrupt controller mode (xics, xive, dual)"); 3406 3407 object_property_add_str(obj, "host-model", 3408 spapr_get_host_model, spapr_set_host_model); 3409 object_property_set_description(obj, "host-model", 3410 "Host model to advertise in guest device tree"); 3411 object_property_add_str(obj, "host-serial", 3412 spapr_get_host_serial, spapr_set_host_serial); 3413 object_property_set_description(obj, "host-serial", 3414 "Host serial number to advertise in guest device tree"); 3415 } 3416 3417 static void spapr_machine_finalizefn(Object *obj) 3418 { 3419 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 3420 3421 g_free(spapr->kvm_type); 3422 } 3423 3424 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 3425 { 3426 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 3427 PowerPCCPU *cpu = POWERPC_CPU(cs); 3428 CPUPPCState *env = &cpu->env; 3429 3430 cpu_synchronize_state(cs); 3431 /* If FWNMI is inactive, addr will be -1, which will deliver to 0x100 */ 3432 if (spapr->fwnmi_system_reset_addr != -1) { 3433 uint64_t rtas_addr, addr; 3434 3435 /* get rtas addr from fdt */ 3436 rtas_addr = spapr_get_rtas_addr(); 3437 if (!rtas_addr) { 3438 qemu_system_guest_panicked(NULL); 3439 return; 3440 } 3441 3442 addr = rtas_addr + RTAS_ERROR_LOG_MAX + cs->cpu_index * sizeof(uint64_t)*2; 3443 stq_be_phys(&address_space_memory, addr, env->gpr[3]); 3444 stq_be_phys(&address_space_memory, addr + sizeof(uint64_t), 0); 3445 env->gpr[3] = addr; 3446 } 3447 ppc_cpu_do_system_reset(cs); 3448 if (spapr->fwnmi_system_reset_addr != -1) { 3449 env->nip = spapr->fwnmi_system_reset_addr; 3450 } 3451 } 3452 3453 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 3454 { 3455 CPUState *cs; 3456 3457 CPU_FOREACH(cs) { 3458 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 3459 } 3460 } 3461 3462 int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3463 void *fdt, int *fdt_start_offset, Error **errp) 3464 { 3465 uint64_t addr; 3466 uint32_t node; 3467 3468 addr = spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; 3469 node = object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, 3470 &error_abort); 3471 *fdt_start_offset = spapr_dt_memory_node(spapr, fdt, node, addr, 3472 SPAPR_MEMORY_BLOCK_SIZE); 3473 return 0; 3474 } 3475 3476 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 3477 bool dedicated_hp_event_source) 3478 { 3479 SpaprDrc *drc; 3480 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 3481 int i; 3482 uint64_t addr = addr_start; 3483 bool hotplugged = spapr_drc_hotplugged(dev); 3484 3485 for (i = 0; i < nr_lmbs; i++) { 3486 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3487 addr / SPAPR_MEMORY_BLOCK_SIZE); 3488 g_assert(drc); 3489 3490 /* 3491 * memory_device_get_free_addr() provided a range of free addresses 3492 * that doesn't overlap with any existing mapping at pre-plug. The 3493 * corresponding LMB DRCs are thus assumed to be all attachable. 3494 */ 3495 spapr_drc_attach(drc, dev); 3496 if (!hotplugged) { 3497 spapr_drc_reset(drc); 3498 } 3499 addr += SPAPR_MEMORY_BLOCK_SIZE; 3500 } 3501 /* send hotplug notification to the 3502 * guest only in case of hotplugged memory 3503 */ 3504 if (hotplugged) { 3505 if (dedicated_hp_event_source) { 3506 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3507 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3508 g_assert(drc); 3509 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3510 nr_lmbs, 3511 spapr_drc_index(drc)); 3512 } else { 3513 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 3514 nr_lmbs); 3515 } 3516 } 3517 } 3518 3519 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3520 { 3521 SpaprMachineState *ms = SPAPR_MACHINE(hotplug_dev); 3522 PCDIMMDevice *dimm = PC_DIMM(dev); 3523 uint64_t size, addr; 3524 int64_t slot; 3525 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3526 3527 size = memory_device_get_region_size(MEMORY_DEVICE(dev), &error_abort); 3528 3529 pc_dimm_plug(dimm, MACHINE(ms)); 3530 3531 if (!is_nvdimm) { 3532 addr = object_property_get_uint(OBJECT(dimm), 3533 PC_DIMM_ADDR_PROP, &error_abort); 3534 spapr_add_lmbs(dev, addr, size, 3535 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT)); 3536 } else { 3537 slot = object_property_get_int(OBJECT(dimm), 3538 PC_DIMM_SLOT_PROP, &error_abort); 3539 /* We should have valid slot number at this point */ 3540 g_assert(slot >= 0); 3541 spapr_add_nvdimm(dev, slot); 3542 } 3543 } 3544 3545 static void spapr_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3546 Error **errp) 3547 { 3548 const SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(hotplug_dev); 3549 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3550 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 3551 PCDIMMDevice *dimm = PC_DIMM(dev); 3552 Error *local_err = NULL; 3553 uint64_t size; 3554 Object *memdev; 3555 hwaddr pagesize; 3556 3557 if (!smc->dr_lmb_enabled) { 3558 error_setg(errp, "Memory hotplug not supported for this machine"); 3559 return; 3560 } 3561 3562 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &local_err); 3563 if (local_err) { 3564 error_propagate(errp, local_err); 3565 return; 3566 } 3567 3568 if (is_nvdimm) { 3569 if (!spapr_nvdimm_validate(hotplug_dev, NVDIMM(dev), size, errp)) { 3570 return; 3571 } 3572 } else if (size % SPAPR_MEMORY_BLOCK_SIZE) { 3573 error_setg(errp, "Hotplugged memory size must be a multiple of " 3574 "%" PRIu64 " MB", SPAPR_MEMORY_BLOCK_SIZE / MiB); 3575 return; 3576 } 3577 3578 memdev = object_property_get_link(OBJECT(dimm), PC_DIMM_MEMDEV_PROP, 3579 &error_abort); 3580 pagesize = host_memory_backend_pagesize(MEMORY_BACKEND(memdev)); 3581 if (!spapr_check_pagesize(spapr, pagesize, errp)) { 3582 return; 3583 } 3584 3585 pc_dimm_pre_plug(dimm, MACHINE(hotplug_dev), NULL, errp); 3586 } 3587 3588 struct SpaprDimmState { 3589 PCDIMMDevice *dimm; 3590 uint32_t nr_lmbs; 3591 QTAILQ_ENTRY(SpaprDimmState) next; 3592 }; 3593 3594 static SpaprDimmState *spapr_pending_dimm_unplugs_find(SpaprMachineState *s, 3595 PCDIMMDevice *dimm) 3596 { 3597 SpaprDimmState *dimm_state = NULL; 3598 3599 QTAILQ_FOREACH(dimm_state, &s->pending_dimm_unplugs, next) { 3600 if (dimm_state->dimm == dimm) { 3601 break; 3602 } 3603 } 3604 return dimm_state; 3605 } 3606 3607 static SpaprDimmState *spapr_pending_dimm_unplugs_add(SpaprMachineState *spapr, 3608 uint32_t nr_lmbs, 3609 PCDIMMDevice *dimm) 3610 { 3611 SpaprDimmState *ds = NULL; 3612 3613 /* 3614 * If this request is for a DIMM whose removal had failed earlier 3615 * (due to guest's refusal to remove the LMBs), we would have this 3616 * dimm already in the pending_dimm_unplugs list. In that 3617 * case don't add again. 3618 */ 3619 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3620 if (!ds) { 3621 ds = g_new0(SpaprDimmState, 1); 3622 ds->nr_lmbs = nr_lmbs; 3623 ds->dimm = dimm; 3624 QTAILQ_INSERT_HEAD(&spapr->pending_dimm_unplugs, ds, next); 3625 } 3626 return ds; 3627 } 3628 3629 static void spapr_pending_dimm_unplugs_remove(SpaprMachineState *spapr, 3630 SpaprDimmState *dimm_state) 3631 { 3632 QTAILQ_REMOVE(&spapr->pending_dimm_unplugs, dimm_state, next); 3633 g_free(dimm_state); 3634 } 3635 3636 static SpaprDimmState *spapr_recover_pending_dimm_state(SpaprMachineState *ms, 3637 PCDIMMDevice *dimm) 3638 { 3639 SpaprDrc *drc; 3640 uint64_t size = memory_device_get_region_size(MEMORY_DEVICE(dimm), 3641 &error_abort); 3642 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3643 uint32_t avail_lmbs = 0; 3644 uint64_t addr_start, addr; 3645 int i; 3646 3647 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3648 &error_abort); 3649 3650 addr = addr_start; 3651 for (i = 0; i < nr_lmbs; i++) { 3652 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3653 addr / SPAPR_MEMORY_BLOCK_SIZE); 3654 g_assert(drc); 3655 if (drc->dev) { 3656 avail_lmbs++; 3657 } 3658 addr += SPAPR_MEMORY_BLOCK_SIZE; 3659 } 3660 3661 return spapr_pending_dimm_unplugs_add(ms, avail_lmbs, dimm); 3662 } 3663 3664 void spapr_memory_unplug_rollback(SpaprMachineState *spapr, DeviceState *dev) 3665 { 3666 SpaprDimmState *ds; 3667 PCDIMMDevice *dimm; 3668 SpaprDrc *drc; 3669 uint32_t nr_lmbs; 3670 uint64_t size, addr_start, addr; 3671 g_autofree char *qapi_error = NULL; 3672 int i; 3673 3674 if (!dev) { 3675 return; 3676 } 3677 3678 dimm = PC_DIMM(dev); 3679 ds = spapr_pending_dimm_unplugs_find(spapr, dimm); 3680 3681 /* 3682 * 'ds == NULL' would mean that the DIMM doesn't have a pending 3683 * unplug state, but one of its DRC is marked as unplug_requested. 3684 * This is bad and weird enough to g_assert() out. 3685 */ 3686 g_assert(ds); 3687 3688 spapr_pending_dimm_unplugs_remove(spapr, ds); 3689 3690 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3691 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3692 3693 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3694 &error_abort); 3695 3696 addr = addr_start; 3697 for (i = 0; i < nr_lmbs; i++) { 3698 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3699 addr / SPAPR_MEMORY_BLOCK_SIZE); 3700 g_assert(drc); 3701 3702 drc->unplug_requested = false; 3703 addr += SPAPR_MEMORY_BLOCK_SIZE; 3704 } 3705 3706 /* 3707 * Tell QAPI that something happened and the memory 3708 * hotunplug wasn't successful. Keep sending 3709 * MEM_UNPLUG_ERROR even while sending 3710 * DEVICE_UNPLUG_GUEST_ERROR until the deprecation of 3711 * MEM_UNPLUG_ERROR is due. 3712 */ 3713 qapi_error = g_strdup_printf("Memory hotunplug rejected by the guest " 3714 "for device %s", dev->id); 3715 3716 qapi_event_send_mem_unplug_error(dev->id ? : "", qapi_error); 3717 3718 qapi_event_send_device_unplug_guest_error(!!dev->id, dev->id, 3719 dev->canonical_path); 3720 } 3721 3722 /* Callback to be called during DRC release. */ 3723 void spapr_lmb_release(DeviceState *dev) 3724 { 3725 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3726 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_ctrl); 3727 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3728 3729 /* This information will get lost if a migration occurs 3730 * during the unplug process. In this case recover it. */ 3731 if (ds == NULL) { 3732 ds = spapr_recover_pending_dimm_state(spapr, PC_DIMM(dev)); 3733 g_assert(ds); 3734 /* The DRC being examined by the caller at least must be counted */ 3735 g_assert(ds->nr_lmbs); 3736 } 3737 3738 if (--ds->nr_lmbs) { 3739 return; 3740 } 3741 3742 /* 3743 * Now that all the LMBs have been removed by the guest, call the 3744 * unplug handler chain. This can never fail. 3745 */ 3746 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3747 object_unparent(OBJECT(dev)); 3748 } 3749 3750 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3751 { 3752 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3753 SpaprDimmState *ds = spapr_pending_dimm_unplugs_find(spapr, PC_DIMM(dev)); 3754 3755 /* We really shouldn't get this far without anything to unplug */ 3756 g_assert(ds); 3757 3758 pc_dimm_unplug(PC_DIMM(dev), MACHINE(hotplug_dev)); 3759 qdev_unrealize(dev); 3760 spapr_pending_dimm_unplugs_remove(spapr, ds); 3761 } 3762 3763 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 3764 DeviceState *dev, Error **errp) 3765 { 3766 SpaprMachineState *spapr = SPAPR_MACHINE(hotplug_dev); 3767 PCDIMMDevice *dimm = PC_DIMM(dev); 3768 uint32_t nr_lmbs; 3769 uint64_t size, addr_start, addr; 3770 int i; 3771 SpaprDrc *drc; 3772 3773 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) { 3774 error_setg(errp, "nvdimm device hot unplug is not supported yet."); 3775 return; 3776 } 3777 3778 size = memory_device_get_region_size(MEMORY_DEVICE(dimm), &error_abort); 3779 nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 3780 3781 addr_start = object_property_get_uint(OBJECT(dimm), PC_DIMM_ADDR_PROP, 3782 &error_abort); 3783 3784 /* 3785 * An existing pending dimm state for this DIMM means that there is an 3786 * unplug operation in progress, waiting for the spapr_lmb_release 3787 * callback to complete the job (BQL can't cover that far). In this case, 3788 * bail out to avoid detaching DRCs that were already released. 3789 */ 3790 if (spapr_pending_dimm_unplugs_find(spapr, dimm)) { 3791 error_setg(errp, "Memory unplug already in progress for device %s", 3792 dev->id); 3793 return; 3794 } 3795 3796 spapr_pending_dimm_unplugs_add(spapr, nr_lmbs, dimm); 3797 3798 addr = addr_start; 3799 for (i = 0; i < nr_lmbs; i++) { 3800 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3801 addr / SPAPR_MEMORY_BLOCK_SIZE); 3802 g_assert(drc); 3803 3804 spapr_drc_unplug_request(drc); 3805 addr += SPAPR_MEMORY_BLOCK_SIZE; 3806 } 3807 3808 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_LMB, 3809 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 3810 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 3811 nr_lmbs, spapr_drc_index(drc)); 3812 } 3813 3814 /* Callback to be called during DRC release. */ 3815 void spapr_core_release(DeviceState *dev) 3816 { 3817 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 3818 3819 /* Call the unplug handler chain. This can never fail. */ 3820 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 3821 object_unparent(OBJECT(dev)); 3822 } 3823 3824 static void spapr_core_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 3825 { 3826 MachineState *ms = MACHINE(hotplug_dev); 3827 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(ms); 3828 CPUCore *cc = CPU_CORE(dev); 3829 CPUArchId *core_slot = spapr_find_cpu_slot(ms, cc->core_id, NULL); 3830 3831 if (smc->pre_2_10_has_unused_icps) { 3832 SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev)); 3833 int i; 3834 3835 for (i = 0; i < cc->nr_threads; i++) { 3836 CPUState *cs = CPU(sc->threads[i]); 3837 3838 pre_2_10_vmstate_register_dummy_icp(cs->cpu_index); 3839 } 3840 } 3841 3842 assert(core_slot); 3843 core_slot->cpu = NULL; 3844 qdev_unrealize(dev); 3845 } 3846 3847 static 3848 void spapr_core_unplug_request(HotplugHandler *hotplug_dev, DeviceState *dev, 3849 Error **errp) 3850 { 3851 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3852 int index; 3853 SpaprDrc *drc; 3854 CPUCore *cc = CPU_CORE(dev); 3855 3856 if (!spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index)) { 3857 error_setg(errp, "Unable to find CPU core with core-id: %d", 3858 cc->core_id); 3859 return; 3860 } 3861 if (index == 0) { 3862 error_setg(errp, "Boot CPU core may not be unplugged"); 3863 return; 3864 } 3865 3866 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3867 spapr_vcpu_id(spapr, cc->core_id)); 3868 g_assert(drc); 3869 3870 if (!spapr_drc_unplug_requested(drc)) { 3871 spapr_drc_unplug_request(drc); 3872 } 3873 3874 /* 3875 * spapr_hotplug_req_remove_by_index is left unguarded, out of the 3876 * "!spapr_drc_unplug_requested" check, to allow for multiple IRQ 3877 * pulses removing the same CPU. Otherwise, in an failed hotunplug 3878 * attempt (e.g. the kernel will refuse to remove the last online 3879 * CPU), we will never attempt it again because unplug_requested 3880 * will still be 'true' in that case. 3881 */ 3882 spapr_hotplug_req_remove_by_index(drc); 3883 } 3884 3885 int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 3886 void *fdt, int *fdt_start_offset, Error **errp) 3887 { 3888 SpaprCpuCore *core = SPAPR_CPU_CORE(drc->dev); 3889 CPUState *cs = CPU(core->threads[0]); 3890 PowerPCCPU *cpu = POWERPC_CPU(cs); 3891 DeviceClass *dc = DEVICE_GET_CLASS(cs); 3892 int id = spapr_get_vcpu_id(cpu); 3893 g_autofree char *nodename = NULL; 3894 int offset; 3895 3896 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 3897 offset = fdt_add_subnode(fdt, 0, nodename); 3898 3899 spapr_dt_cpu(cs, fdt, offset, spapr); 3900 3901 /* 3902 * spapr_dt_cpu() does not fill the 'name' property in the 3903 * CPU node. The function is called during boot process, before 3904 * and after CAS, and overwriting the 'name' property written 3905 * by SLOF is not allowed. 3906 * 3907 * Write it manually after spapr_dt_cpu(). This makes the hotplug 3908 * CPUs more compatible with the coldplugged ones, which have 3909 * the 'name' property. Linux Kernel also relies on this 3910 * property to identify CPU nodes. 3911 */ 3912 _FDT((fdt_setprop_string(fdt, offset, "name", nodename))); 3913 3914 *fdt_start_offset = offset; 3915 return 0; 3916 } 3917 3918 static void spapr_core_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 3919 { 3920 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 3921 MachineClass *mc = MACHINE_GET_CLASS(spapr); 3922 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 3923 SpaprCpuCore *core = SPAPR_CPU_CORE(OBJECT(dev)); 3924 CPUCore *cc = CPU_CORE(dev); 3925 CPUState *cs; 3926 SpaprDrc *drc; 3927 CPUArchId *core_slot; 3928 int index; 3929 bool hotplugged = spapr_drc_hotplugged(dev); 3930 int i; 3931 3932 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 3933 g_assert(core_slot); /* Already checked in spapr_core_pre_plug() */ 3934 3935 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, 3936 spapr_vcpu_id(spapr, cc->core_id)); 3937 3938 g_assert(drc || !mc->has_hotpluggable_cpus); 3939 3940 if (drc) { 3941 /* 3942 * spapr_core_pre_plug() already buys us this is a brand new 3943 * core being plugged into a free slot. Nothing should already 3944 * be attached to the corresponding DRC. 3945 */ 3946 spapr_drc_attach(drc, dev); 3947 3948 if (hotplugged) { 3949 /* 3950 * Send hotplug notification interrupt to the guest only 3951 * in case of hotplugged CPUs. 3952 */ 3953 spapr_hotplug_req_add_by_index(drc); 3954 } else { 3955 spapr_drc_reset(drc); 3956 } 3957 } 3958 3959 core_slot->cpu = OBJECT(dev); 3960 3961 /* 3962 * Set compatibility mode to match the boot CPU, which was either set 3963 * by the machine reset code or by CAS. This really shouldn't fail at 3964 * this point. 3965 */ 3966 if (hotplugged) { 3967 for (i = 0; i < cc->nr_threads; i++) { 3968 ppc_set_compat(core->threads[i], POWERPC_CPU(first_cpu)->compat_pvr, 3969 &error_abort); 3970 } 3971 } 3972 3973 if (smc->pre_2_10_has_unused_icps) { 3974 for (i = 0; i < cc->nr_threads; i++) { 3975 cs = CPU(core->threads[i]); 3976 pre_2_10_vmstate_unregister_dummy_icp(cs->cpu_index); 3977 } 3978 } 3979 } 3980 3981 static void spapr_core_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 3982 Error **errp) 3983 { 3984 MachineState *machine = MACHINE(OBJECT(hotplug_dev)); 3985 MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev); 3986 CPUCore *cc = CPU_CORE(dev); 3987 const char *base_core_type = spapr_get_cpu_core_type(machine->cpu_type); 3988 const char *type = object_get_typename(OBJECT(dev)); 3989 CPUArchId *core_slot; 3990 int index; 3991 unsigned int smp_threads = machine->smp.threads; 3992 3993 if (dev->hotplugged && !mc->has_hotpluggable_cpus) { 3994 error_setg(errp, "CPU hotplug not supported for this machine"); 3995 return; 3996 } 3997 3998 if (strcmp(base_core_type, type)) { 3999 error_setg(errp, "CPU core type should be %s", base_core_type); 4000 return; 4001 } 4002 4003 if (cc->core_id % smp_threads) { 4004 error_setg(errp, "invalid core id %d", cc->core_id); 4005 return; 4006 } 4007 4008 /* 4009 * In general we should have homogeneous threads-per-core, but old 4010 * (pre hotplug support) machine types allow the last core to have 4011 * reduced threads as a compatibility hack for when we allowed 4012 * total vcpus not a multiple of threads-per-core. 4013 */ 4014 if (mc->has_hotpluggable_cpus && (cc->nr_threads != smp_threads)) { 4015 error_setg(errp, "invalid nr-threads %d, must be %d", cc->nr_threads, 4016 smp_threads); 4017 return; 4018 } 4019 4020 core_slot = spapr_find_cpu_slot(MACHINE(hotplug_dev), cc->core_id, &index); 4021 if (!core_slot) { 4022 error_setg(errp, "core id %d out of range", cc->core_id); 4023 return; 4024 } 4025 4026 if (core_slot->cpu) { 4027 error_setg(errp, "core %d already populated", cc->core_id); 4028 return; 4029 } 4030 4031 numa_cpu_pre_plug(core_slot, dev, errp); 4032 } 4033 4034 int spapr_phb_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 4035 void *fdt, int *fdt_start_offset, Error **errp) 4036 { 4037 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(drc->dev); 4038 int intc_phandle; 4039 4040 intc_phandle = spapr_irq_get_phandle(spapr, spapr->fdt_blob, errp); 4041 if (intc_phandle <= 0) { 4042 return -1; 4043 } 4044 4045 if (spapr_dt_phb(spapr, sphb, intc_phandle, fdt, fdt_start_offset)) { 4046 error_setg(errp, "unable to create FDT node for PHB %d", sphb->index); 4047 return -1; 4048 } 4049 4050 /* generally SLOF creates these, for hotplug it's up to QEMU */ 4051 _FDT(fdt_setprop_string(fdt, *fdt_start_offset, "name", "pci")); 4052 4053 return 0; 4054 } 4055 4056 static bool spapr_phb_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4057 Error **errp) 4058 { 4059 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4060 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4061 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4062 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 4063 SpaprDrc *drc; 4064 4065 if (dev->hotplugged && !smc->dr_phb_enabled) { 4066 error_setg(errp, "PHB hotplug not supported for this machine"); 4067 return false; 4068 } 4069 4070 if (sphb->index == (uint32_t)-1) { 4071 error_setg(errp, "\"index\" for PAPR PHB is mandatory"); 4072 return false; 4073 } 4074 4075 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4076 if (drc && drc->dev) { 4077 error_setg(errp, "PHB %d already attached", sphb->index); 4078 return false; 4079 } 4080 4081 /* 4082 * This will check that sphb->index doesn't exceed the maximum number of 4083 * PHBs for the current machine type. 4084 */ 4085 return 4086 smc->phb_placement(spapr, sphb->index, 4087 &sphb->buid, &sphb->io_win_addr, 4088 &sphb->mem_win_addr, &sphb->mem64_win_addr, 4089 windows_supported, sphb->dma_liobn, 4090 &sphb->nv2_gpa_win_addr, &sphb->nv2_atsd_win_addr, 4091 errp); 4092 } 4093 4094 static void spapr_phb_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4095 { 4096 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4097 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 4098 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4099 SpaprDrc *drc; 4100 bool hotplugged = spapr_drc_hotplugged(dev); 4101 4102 if (!smc->dr_phb_enabled) { 4103 return; 4104 } 4105 4106 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4107 /* hotplug hooks should check it's enabled before getting this far */ 4108 assert(drc); 4109 4110 /* spapr_phb_pre_plug() already checked the DRC is attachable */ 4111 spapr_drc_attach(drc, dev); 4112 4113 if (hotplugged) { 4114 spapr_hotplug_req_add_by_index(drc); 4115 } else { 4116 spapr_drc_reset(drc); 4117 } 4118 } 4119 4120 void spapr_phb_release(DeviceState *dev) 4121 { 4122 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 4123 4124 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 4125 object_unparent(OBJECT(dev)); 4126 } 4127 4128 static void spapr_phb_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4129 { 4130 qdev_unrealize(dev); 4131 } 4132 4133 static void spapr_phb_unplug_request(HotplugHandler *hotplug_dev, 4134 DeviceState *dev, Error **errp) 4135 { 4136 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(dev); 4137 SpaprDrc *drc; 4138 4139 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, sphb->index); 4140 assert(drc); 4141 4142 if (!spapr_drc_unplug_requested(drc)) { 4143 spapr_drc_unplug_request(drc); 4144 spapr_hotplug_req_remove_by_index(drc); 4145 } else { 4146 error_setg(errp, 4147 "PCI Host Bridge unplug already in progress for device %s", 4148 dev->id); 4149 } 4150 } 4151 4152 static 4153 bool spapr_tpm_proxy_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 4154 Error **errp) 4155 { 4156 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4157 4158 if (spapr->tpm_proxy != NULL) { 4159 error_setg(errp, "Only one TPM proxy can be specified for this machine"); 4160 return false; 4161 } 4162 4163 return true; 4164 } 4165 4166 static void spapr_tpm_proxy_plug(HotplugHandler *hotplug_dev, DeviceState *dev) 4167 { 4168 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4169 SpaprTpmProxy *tpm_proxy = SPAPR_TPM_PROXY(dev); 4170 4171 /* Already checked in spapr_tpm_proxy_pre_plug() */ 4172 g_assert(spapr->tpm_proxy == NULL); 4173 4174 spapr->tpm_proxy = tpm_proxy; 4175 } 4176 4177 static void spapr_tpm_proxy_unplug(HotplugHandler *hotplug_dev, DeviceState *dev) 4178 { 4179 SpaprMachineState *spapr = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4180 4181 qdev_unrealize(dev); 4182 object_unparent(OBJECT(dev)); 4183 spapr->tpm_proxy = NULL; 4184 } 4185 4186 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 4187 DeviceState *dev, Error **errp) 4188 { 4189 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4190 spapr_memory_plug(hotplug_dev, dev); 4191 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4192 spapr_core_plug(hotplug_dev, dev); 4193 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4194 spapr_phb_plug(hotplug_dev, dev); 4195 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4196 spapr_tpm_proxy_plug(hotplug_dev, dev); 4197 } 4198 } 4199 4200 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 4201 DeviceState *dev, Error **errp) 4202 { 4203 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4204 spapr_memory_unplug(hotplug_dev, dev); 4205 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4206 spapr_core_unplug(hotplug_dev, dev); 4207 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4208 spapr_phb_unplug(hotplug_dev, dev); 4209 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4210 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4211 } 4212 } 4213 4214 bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr) 4215 { 4216 return spapr_ovec_test(spapr->ov5_cas, OV5_HP_EVT) || 4217 /* 4218 * CAS will process all pending unplug requests. 4219 * 4220 * HACK: a guest could theoretically have cleared all bits in OV5, 4221 * but none of the guests we care for do. 4222 */ 4223 spapr_ovec_empty(spapr->ov5_cas); 4224 } 4225 4226 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 4227 DeviceState *dev, Error **errp) 4228 { 4229 SpaprMachineState *sms = SPAPR_MACHINE(OBJECT(hotplug_dev)); 4230 MachineClass *mc = MACHINE_GET_CLASS(sms); 4231 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4232 4233 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4234 if (spapr_memory_hot_unplug_supported(sms)) { 4235 spapr_memory_unplug_request(hotplug_dev, dev, errp); 4236 } else { 4237 error_setg(errp, "Memory hot unplug not supported for this guest"); 4238 } 4239 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4240 if (!mc->has_hotpluggable_cpus) { 4241 error_setg(errp, "CPU hot unplug not supported on this machine"); 4242 return; 4243 } 4244 spapr_core_unplug_request(hotplug_dev, dev, errp); 4245 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4246 if (!smc->dr_phb_enabled) { 4247 error_setg(errp, "PHB hot unplug not supported on this machine"); 4248 return; 4249 } 4250 spapr_phb_unplug_request(hotplug_dev, dev, errp); 4251 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4252 spapr_tpm_proxy_unplug(hotplug_dev, dev); 4253 } 4254 } 4255 4256 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 4257 DeviceState *dev, Error **errp) 4258 { 4259 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 4260 spapr_memory_pre_plug(hotplug_dev, dev, errp); 4261 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 4262 spapr_core_pre_plug(hotplug_dev, dev, errp); 4263 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 4264 spapr_phb_pre_plug(hotplug_dev, dev, errp); 4265 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4266 spapr_tpm_proxy_pre_plug(hotplug_dev, dev, errp); 4267 } 4268 } 4269 4270 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 4271 DeviceState *dev) 4272 { 4273 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 4274 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE) || 4275 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_PCI_HOST_BRIDGE) || 4276 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_TPM_PROXY)) { 4277 return HOTPLUG_HANDLER(machine); 4278 } 4279 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) { 4280 PCIDevice *pcidev = PCI_DEVICE(dev); 4281 PCIBus *root = pci_device_root_bus(pcidev); 4282 SpaprPhbState *phb = 4283 (SpaprPhbState *)object_dynamic_cast(OBJECT(BUS(root)->parent), 4284 TYPE_SPAPR_PCI_HOST_BRIDGE); 4285 4286 if (phb) { 4287 return HOTPLUG_HANDLER(phb); 4288 } 4289 } 4290 return NULL; 4291 } 4292 4293 static CpuInstanceProperties 4294 spapr_cpu_index_to_props(MachineState *machine, unsigned cpu_index) 4295 { 4296 CPUArchId *core_slot; 4297 MachineClass *mc = MACHINE_GET_CLASS(machine); 4298 4299 /* make sure possible_cpu are intialized */ 4300 mc->possible_cpu_arch_ids(machine); 4301 /* get CPU core slot containing thread that matches cpu_index */ 4302 core_slot = spapr_find_cpu_slot(machine, cpu_index, NULL); 4303 assert(core_slot); 4304 return core_slot->props; 4305 } 4306 4307 static int64_t spapr_get_default_cpu_node_id(const MachineState *ms, int idx) 4308 { 4309 return idx / ms->smp.cores % ms->numa_state->num_nodes; 4310 } 4311 4312 static const CPUArchIdList *spapr_possible_cpu_arch_ids(MachineState *machine) 4313 { 4314 int i; 4315 unsigned int smp_threads = machine->smp.threads; 4316 unsigned int smp_cpus = machine->smp.cpus; 4317 const char *core_type; 4318 int spapr_max_cores = machine->smp.max_cpus / smp_threads; 4319 MachineClass *mc = MACHINE_GET_CLASS(machine); 4320 4321 if (!mc->has_hotpluggable_cpus) { 4322 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 4323 } 4324 if (machine->possible_cpus) { 4325 assert(machine->possible_cpus->len == spapr_max_cores); 4326 return machine->possible_cpus; 4327 } 4328 4329 core_type = spapr_get_cpu_core_type(machine->cpu_type); 4330 if (!core_type) { 4331 error_report("Unable to find sPAPR CPU Core definition"); 4332 exit(1); 4333 } 4334 4335 machine->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 4336 sizeof(CPUArchId) * spapr_max_cores); 4337 machine->possible_cpus->len = spapr_max_cores; 4338 for (i = 0; i < machine->possible_cpus->len; i++) { 4339 int core_id = i * smp_threads; 4340 4341 machine->possible_cpus->cpus[i].type = core_type; 4342 machine->possible_cpus->cpus[i].vcpus_count = smp_threads; 4343 machine->possible_cpus->cpus[i].arch_id = core_id; 4344 machine->possible_cpus->cpus[i].props.has_core_id = true; 4345 machine->possible_cpus->cpus[i].props.core_id = core_id; 4346 } 4347 return machine->possible_cpus; 4348 } 4349 4350 static bool spapr_phb_placement(SpaprMachineState *spapr, uint32_t index, 4351 uint64_t *buid, hwaddr *pio, 4352 hwaddr *mmio32, hwaddr *mmio64, 4353 unsigned n_dma, uint32_t *liobns, 4354 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4355 { 4356 /* 4357 * New-style PHB window placement. 4358 * 4359 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 4360 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 4361 * windows. 4362 * 4363 * Some guest kernels can't work with MMIO windows above 1<<46 4364 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 4365 * 4366 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 4367 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 4368 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 4369 * 1TiB 64-bit MMIO windows for each PHB. 4370 */ 4371 const uint64_t base_buid = 0x800000020000000ULL; 4372 int i; 4373 4374 /* Sanity check natural alignments */ 4375 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4376 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 4377 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 4378 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 4379 /* Sanity check bounds */ 4380 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_IO_WIN_SIZE) > 4381 SPAPR_PCI_MEM32_WIN_SIZE); 4382 QEMU_BUILD_BUG_ON((SPAPR_MAX_PHBS * SPAPR_PCI_MEM32_WIN_SIZE) > 4383 SPAPR_PCI_MEM64_WIN_SIZE); 4384 4385 if (index >= SPAPR_MAX_PHBS) { 4386 error_setg(errp, "\"index\" for PAPR PHB is too large (max %llu)", 4387 SPAPR_MAX_PHBS - 1); 4388 return false; 4389 } 4390 4391 *buid = base_buid + index; 4392 for (i = 0; i < n_dma; ++i) { 4393 liobns[i] = SPAPR_PCI_LIOBN(index, i); 4394 } 4395 4396 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 4397 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 4398 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 4399 4400 *nv2gpa = SPAPR_PCI_NV2RAM64_WIN_BASE + index * SPAPR_PCI_NV2RAM64_WIN_SIZE; 4401 *nv2atsd = SPAPR_PCI_NV2ATSD_WIN_BASE + index * SPAPR_PCI_NV2ATSD_WIN_SIZE; 4402 return true; 4403 } 4404 4405 static ICSState *spapr_ics_get(XICSFabric *dev, int irq) 4406 { 4407 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4408 4409 return ics_valid_irq(spapr->ics, irq) ? spapr->ics : NULL; 4410 } 4411 4412 static void spapr_ics_resend(XICSFabric *dev) 4413 { 4414 SpaprMachineState *spapr = SPAPR_MACHINE(dev); 4415 4416 ics_resend(spapr->ics); 4417 } 4418 4419 static ICPState *spapr_icp_get(XICSFabric *xi, int vcpu_id) 4420 { 4421 PowerPCCPU *cpu = spapr_find_cpu(vcpu_id); 4422 4423 return cpu ? spapr_cpu_state(cpu)->icp : NULL; 4424 } 4425 4426 static void spapr_pic_print_info(InterruptStatsProvider *obj, 4427 Monitor *mon) 4428 { 4429 SpaprMachineState *spapr = SPAPR_MACHINE(obj); 4430 4431 spapr_irq_print_info(spapr, mon); 4432 monitor_printf(mon, "irqchip: %s\n", 4433 kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); 4434 } 4435 4436 /* 4437 * This is a XIVE only operation 4438 */ 4439 static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, 4440 uint8_t nvt_blk, uint32_t nvt_idx, 4441 bool cam_ignore, uint8_t priority, 4442 uint32_t logic_serv, XiveTCTXMatch *match) 4443 { 4444 SpaprMachineState *spapr = SPAPR_MACHINE(xfb); 4445 XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); 4446 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 4447 int count; 4448 4449 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 4450 priority, logic_serv, match); 4451 if (count < 0) { 4452 return count; 4453 } 4454 4455 /* 4456 * When we implement the save and restore of the thread interrupt 4457 * contexts in the enter/exit CPU handlers of the machine and the 4458 * escalations in QEMU, we should be able to handle non dispatched 4459 * vCPUs. 4460 * 4461 * Until this is done, the sPAPR machine should find at least one 4462 * matching context always. 4463 */ 4464 if (count == 0) { 4465 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVT %x/%x is not dispatched\n", 4466 nvt_blk, nvt_idx); 4467 } 4468 4469 return count; 4470 } 4471 4472 int spapr_get_vcpu_id(PowerPCCPU *cpu) 4473 { 4474 return cpu->vcpu_id; 4475 } 4476 4477 bool spapr_set_vcpu_id(PowerPCCPU *cpu, int cpu_index, Error **errp) 4478 { 4479 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 4480 MachineState *ms = MACHINE(spapr); 4481 int vcpu_id; 4482 4483 vcpu_id = spapr_vcpu_id(spapr, cpu_index); 4484 4485 if (kvm_enabled() && !kvm_vcpu_id_is_valid(vcpu_id)) { 4486 error_setg(errp, "Can't create CPU with id %d in KVM", vcpu_id); 4487 error_append_hint(errp, "Adjust the number of cpus to %d " 4488 "or try to raise the number of threads per core\n", 4489 vcpu_id * ms->smp.threads / spapr->vsmt); 4490 return false; 4491 } 4492 4493 cpu->vcpu_id = vcpu_id; 4494 return true; 4495 } 4496 4497 PowerPCCPU *spapr_find_cpu(int vcpu_id) 4498 { 4499 CPUState *cs; 4500 4501 CPU_FOREACH(cs) { 4502 PowerPCCPU *cpu = POWERPC_CPU(cs); 4503 4504 if (spapr_get_vcpu_id(cpu) == vcpu_id) { 4505 return cpu; 4506 } 4507 } 4508 4509 return NULL; 4510 } 4511 4512 static bool spapr_cpu_in_nested(PowerPCCPU *cpu) 4513 { 4514 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4515 4516 return spapr_cpu->in_nested; 4517 } 4518 4519 static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4520 { 4521 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4522 4523 /* These are only called by TCG, KVM maintains dispatch state */ 4524 4525 spapr_cpu->prod = false; 4526 if (spapr_cpu->vpa_addr) { 4527 CPUState *cs = CPU(cpu); 4528 uint32_t dispatch; 4529 4530 dispatch = ldl_be_phys(cs->as, 4531 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4532 dispatch++; 4533 if ((dispatch & 1) != 0) { 4534 qemu_log_mask(LOG_GUEST_ERROR, 4535 "VPA: incorrect dispatch counter value for " 4536 "dispatched partition %u, correcting.\n", dispatch); 4537 dispatch++; 4538 } 4539 stl_be_phys(cs->as, 4540 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4541 } 4542 } 4543 4544 static void spapr_cpu_exec_exit(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu) 4545 { 4546 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 4547 4548 if (spapr_cpu->vpa_addr) { 4549 CPUState *cs = CPU(cpu); 4550 uint32_t dispatch; 4551 4552 dispatch = ldl_be_phys(cs->as, 4553 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER); 4554 dispatch++; 4555 if ((dispatch & 1) != 1) { 4556 qemu_log_mask(LOG_GUEST_ERROR, 4557 "VPA: incorrect dispatch counter value for " 4558 "preempted partition %u, correcting.\n", dispatch); 4559 dispatch++; 4560 } 4561 stl_be_phys(cs->as, 4562 spapr_cpu->vpa_addr + VPA_DISPATCH_COUNTER, dispatch); 4563 } 4564 } 4565 4566 static void spapr_machine_class_init(ObjectClass *oc, void *data) 4567 { 4568 MachineClass *mc = MACHINE_CLASS(oc); 4569 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 4570 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 4571 NMIClass *nc = NMI_CLASS(oc); 4572 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 4573 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 4574 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 4575 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 4576 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 4577 VofMachineIfClass *vmc = VOF_MACHINE_CLASS(oc); 4578 4579 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 4580 mc->ignore_boot_device_suffixes = true; 4581 4582 /* 4583 * We set up the default / latest behaviour here. The class_init 4584 * functions for the specific versioned machine types can override 4585 * these details for backwards compatibility 4586 */ 4587 mc->init = spapr_machine_init; 4588 mc->reset = spapr_machine_reset; 4589 mc->block_default_type = IF_SCSI; 4590 4591 /* 4592 * Setting max_cpus to INT32_MAX. Both KVM and TCG max_cpus values 4593 * should be limited by the host capability instead of hardcoded. 4594 * max_cpus for KVM guests will be checked in kvm_init(), and TCG 4595 * guests are welcome to have as many CPUs as the host are capable 4596 * of emulate. 4597 */ 4598 mc->max_cpus = INT32_MAX; 4599 4600 mc->no_parallel = 1; 4601 mc->default_boot_order = ""; 4602 mc->default_ram_size = 512 * MiB; 4603 mc->default_ram_id = "ppc_spapr.ram"; 4604 mc->default_display = "std"; 4605 mc->kvm_type = spapr_kvm_type; 4606 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); 4607 mc->pci_allow_0_address = true; 4608 assert(!mc->get_hotplug_handler); 4609 mc->get_hotplug_handler = spapr_get_hotplug_handler; 4610 hc->pre_plug = spapr_machine_device_pre_plug; 4611 hc->plug = spapr_machine_device_plug; 4612 mc->cpu_index_to_instance_props = spapr_cpu_index_to_props; 4613 mc->get_default_cpu_node_id = spapr_get_default_cpu_node_id; 4614 mc->possible_cpu_arch_ids = spapr_possible_cpu_arch_ids; 4615 hc->unplug_request = spapr_machine_device_unplug_request; 4616 hc->unplug = spapr_machine_device_unplug; 4617 4618 smc->dr_lmb_enabled = true; 4619 smc->update_dt_enabled = true; 4620 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 4621 mc->has_hotpluggable_cpus = true; 4622 mc->nvdimm_supported = true; 4623 smc->resize_hpt_default = SPAPR_RESIZE_HPT_ENABLED; 4624 fwc->get_dev_path = spapr_get_fw_dev_path; 4625 nc->nmi_monitor_handler = spapr_nmi; 4626 smc->phb_placement = spapr_phb_placement; 4627 vhc->cpu_in_nested = spapr_cpu_in_nested; 4628 vhc->deliver_hv_excp = spapr_exit_nested; 4629 vhc->hypercall = emulate_spapr_hypercall; 4630 vhc->hpt_mask = spapr_hpt_mask; 4631 vhc->map_hptes = spapr_map_hptes; 4632 vhc->unmap_hptes = spapr_unmap_hptes; 4633 vhc->hpte_set_c = spapr_hpte_set_c; 4634 vhc->hpte_set_r = spapr_hpte_set_r; 4635 vhc->get_pate = spapr_get_pate; 4636 vhc->encode_hpt_for_kvm_pr = spapr_encode_hpt_for_kvm_pr; 4637 vhc->cpu_exec_enter = spapr_cpu_exec_enter; 4638 vhc->cpu_exec_exit = spapr_cpu_exec_exit; 4639 xic->ics_get = spapr_ics_get; 4640 xic->ics_resend = spapr_ics_resend; 4641 xic->icp_get = spapr_icp_get; 4642 ispc->print_info = spapr_pic_print_info; 4643 /* Force NUMA node memory size to be a multiple of 4644 * SPAPR_MEMORY_BLOCK_SIZE (256M) since that's the granularity 4645 * in which LMBs are represented and hot-added 4646 */ 4647 mc->numa_mem_align_shift = 28; 4648 mc->auto_enable_numa = true; 4649 4650 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_OFF; 4651 smc->default_caps.caps[SPAPR_CAP_VSX] = SPAPR_CAP_ON; 4652 smc->default_caps.caps[SPAPR_CAP_DFP] = SPAPR_CAP_ON; 4653 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4654 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4655 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_WORKAROUND; 4656 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 16; /* 64kiB */ 4657 smc->default_caps.caps[SPAPR_CAP_NESTED_KVM_HV] = SPAPR_CAP_OFF; 4658 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_ON; 4659 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_ON; 4660 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_ON; 4661 smc->default_caps.caps[SPAPR_CAP_RPT_INVALIDATE] = SPAPR_CAP_OFF; 4662 spapr_caps_add_properties(smc); 4663 smc->irq = &spapr_irq_dual; 4664 smc->dr_phb_enabled = true; 4665 smc->linux_pci_probe = true; 4666 smc->smp_threads_vsmt = true; 4667 smc->nr_xirqs = SPAPR_NR_XIRQS; 4668 xfc->match_nvt = spapr_match_nvt; 4669 vmc->client_architecture_support = spapr_vof_client_architecture_support; 4670 vmc->quiesce = spapr_vof_quiesce; 4671 vmc->setprop = spapr_vof_setprop; 4672 } 4673 4674 static const TypeInfo spapr_machine_info = { 4675 .name = TYPE_SPAPR_MACHINE, 4676 .parent = TYPE_MACHINE, 4677 .abstract = true, 4678 .instance_size = sizeof(SpaprMachineState), 4679 .instance_init = spapr_instance_init, 4680 .instance_finalize = spapr_machine_finalizefn, 4681 .class_size = sizeof(SpaprMachineClass), 4682 .class_init = spapr_machine_class_init, 4683 .interfaces = (InterfaceInfo[]) { 4684 { TYPE_FW_PATH_PROVIDER }, 4685 { TYPE_NMI }, 4686 { TYPE_HOTPLUG_HANDLER }, 4687 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 4688 { TYPE_XICS_FABRIC }, 4689 { TYPE_INTERRUPT_STATS_PROVIDER }, 4690 { TYPE_XIVE_FABRIC }, 4691 { TYPE_VOF_MACHINE_IF }, 4692 { } 4693 }, 4694 }; 4695 4696 static void spapr_machine_latest_class_options(MachineClass *mc) 4697 { 4698 mc->alias = "pseries"; 4699 mc->is_default = true; 4700 } 4701 4702 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 4703 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 4704 void *data) \ 4705 { \ 4706 MachineClass *mc = MACHINE_CLASS(oc); \ 4707 spapr_machine_##suffix##_class_options(mc); \ 4708 if (latest) { \ 4709 spapr_machine_latest_class_options(mc); \ 4710 } \ 4711 } \ 4712 static const TypeInfo spapr_machine_##suffix##_info = { \ 4713 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 4714 .parent = TYPE_SPAPR_MACHINE, \ 4715 .class_init = spapr_machine_##suffix##_class_init, \ 4716 }; \ 4717 static void spapr_machine_register_##suffix(void) \ 4718 { \ 4719 type_register(&spapr_machine_##suffix##_info); \ 4720 } \ 4721 type_init(spapr_machine_register_##suffix) 4722 4723 /* 4724 * pseries-7.1 4725 */ 4726 static void spapr_machine_7_1_class_options(MachineClass *mc) 4727 { 4728 /* Defaults for the latest behaviour inherited from the base class */ 4729 } 4730 4731 DEFINE_SPAPR_MACHINE(7_1, "7.1", true); 4732 4733 /* 4734 * pseries-7.0 4735 */ 4736 static void spapr_machine_7_0_class_options(MachineClass *mc) 4737 { 4738 spapr_machine_7_1_class_options(mc); 4739 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len); 4740 } 4741 4742 DEFINE_SPAPR_MACHINE(7_0, "7.0", false); 4743 4744 /* 4745 * pseries-6.2 4746 */ 4747 static void spapr_machine_6_2_class_options(MachineClass *mc) 4748 { 4749 spapr_machine_7_0_class_options(mc); 4750 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len); 4751 } 4752 4753 DEFINE_SPAPR_MACHINE(6_2, "6.2", false); 4754 4755 /* 4756 * pseries-6.1 4757 */ 4758 static void spapr_machine_6_1_class_options(MachineClass *mc) 4759 { 4760 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4761 4762 spapr_machine_6_2_class_options(mc); 4763 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len); 4764 smc->pre_6_2_numa_affinity = true; 4765 mc->smp_props.prefer_sockets = true; 4766 } 4767 4768 DEFINE_SPAPR_MACHINE(6_1, "6.1", false); 4769 4770 /* 4771 * pseries-6.0 4772 */ 4773 static void spapr_machine_6_0_class_options(MachineClass *mc) 4774 { 4775 spapr_machine_6_1_class_options(mc); 4776 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len); 4777 } 4778 4779 DEFINE_SPAPR_MACHINE(6_0, "6.0", false); 4780 4781 /* 4782 * pseries-5.2 4783 */ 4784 static void spapr_machine_5_2_class_options(MachineClass *mc) 4785 { 4786 spapr_machine_6_0_class_options(mc); 4787 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len); 4788 } 4789 4790 DEFINE_SPAPR_MACHINE(5_2, "5.2", false); 4791 4792 /* 4793 * pseries-5.1 4794 */ 4795 static void spapr_machine_5_1_class_options(MachineClass *mc) 4796 { 4797 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4798 4799 spapr_machine_5_2_class_options(mc); 4800 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); 4801 smc->pre_5_2_numa_associativity = true; 4802 } 4803 4804 DEFINE_SPAPR_MACHINE(5_1, "5.1", false); 4805 4806 /* 4807 * pseries-5.0 4808 */ 4809 static void spapr_machine_5_0_class_options(MachineClass *mc) 4810 { 4811 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4812 static GlobalProperty compat[] = { 4813 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-5.1-associativity", "on" }, 4814 }; 4815 4816 spapr_machine_5_1_class_options(mc); 4817 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len); 4818 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4819 mc->numa_mem_supported = true; 4820 smc->pre_5_1_assoc_refpoints = true; 4821 } 4822 4823 DEFINE_SPAPR_MACHINE(5_0, "5.0", false); 4824 4825 /* 4826 * pseries-4.2 4827 */ 4828 static void spapr_machine_4_2_class_options(MachineClass *mc) 4829 { 4830 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4831 4832 spapr_machine_5_0_class_options(mc); 4833 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len); 4834 smc->default_caps.caps[SPAPR_CAP_CCF_ASSIST] = SPAPR_CAP_OFF; 4835 smc->default_caps.caps[SPAPR_CAP_FWNMI] = SPAPR_CAP_OFF; 4836 smc->rma_limit = 16 * GiB; 4837 mc->nvdimm_supported = false; 4838 } 4839 4840 DEFINE_SPAPR_MACHINE(4_2, "4.2", false); 4841 4842 /* 4843 * pseries-4.1 4844 */ 4845 static void spapr_machine_4_1_class_options(MachineClass *mc) 4846 { 4847 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4848 static GlobalProperty compat[] = { 4849 /* Only allow 4kiB and 64kiB IOMMU pagesizes */ 4850 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pgsz", "0x11000" }, 4851 }; 4852 4853 spapr_machine_4_2_class_options(mc); 4854 smc->linux_pci_probe = false; 4855 smc->smp_threads_vsmt = false; 4856 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len); 4857 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4858 } 4859 4860 DEFINE_SPAPR_MACHINE(4_1, "4.1", false); 4861 4862 /* 4863 * pseries-4.0 4864 */ 4865 static bool phb_placement_4_0(SpaprMachineState *spapr, uint32_t index, 4866 uint64_t *buid, hwaddr *pio, 4867 hwaddr *mmio32, hwaddr *mmio64, 4868 unsigned n_dma, uint32_t *liobns, 4869 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 4870 { 4871 if (!spapr_phb_placement(spapr, index, buid, pio, mmio32, mmio64, n_dma, 4872 liobns, nv2gpa, nv2atsd, errp)) { 4873 return false; 4874 } 4875 4876 *nv2gpa = 0; 4877 *nv2atsd = 0; 4878 return true; 4879 } 4880 static void spapr_machine_4_0_class_options(MachineClass *mc) 4881 { 4882 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4883 4884 spapr_machine_4_1_class_options(mc); 4885 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len); 4886 smc->phb_placement = phb_placement_4_0; 4887 smc->irq = &spapr_irq_xics; 4888 smc->pre_4_1_migration = true; 4889 } 4890 4891 DEFINE_SPAPR_MACHINE(4_0, "4.0", false); 4892 4893 /* 4894 * pseries-3.1 4895 */ 4896 static void spapr_machine_3_1_class_options(MachineClass *mc) 4897 { 4898 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4899 4900 spapr_machine_4_0_class_options(mc); 4901 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len); 4902 4903 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 4904 smc->update_dt_enabled = false; 4905 smc->dr_phb_enabled = false; 4906 smc->broken_host_serial_model = true; 4907 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_BROKEN; 4908 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_BROKEN; 4909 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_BROKEN; 4910 smc->default_caps.caps[SPAPR_CAP_LARGE_DECREMENTER] = SPAPR_CAP_OFF; 4911 } 4912 4913 DEFINE_SPAPR_MACHINE(3_1, "3.1", false); 4914 4915 /* 4916 * pseries-3.0 4917 */ 4918 4919 static void spapr_machine_3_0_class_options(MachineClass *mc) 4920 { 4921 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4922 4923 spapr_machine_3_1_class_options(mc); 4924 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len); 4925 4926 smc->legacy_irq_allocation = true; 4927 smc->nr_xirqs = 0x400; 4928 smc->irq = &spapr_irq_xics_legacy; 4929 } 4930 4931 DEFINE_SPAPR_MACHINE(3_0, "3.0", false); 4932 4933 /* 4934 * pseries-2.12 4935 */ 4936 static void spapr_machine_2_12_class_options(MachineClass *mc) 4937 { 4938 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4939 static GlobalProperty compat[] = { 4940 { TYPE_POWERPC_CPU, "pre-3.0-migration", "on" }, 4941 { TYPE_SPAPR_CPU_CORE, "pre-3.0-migration", "on" }, 4942 }; 4943 4944 spapr_machine_3_0_class_options(mc); 4945 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len); 4946 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 4947 4948 /* We depend on kvm_enabled() to choose a default value for the 4949 * hpt-max-page-size capability. Of course we can't do it here 4950 * because this is too early and the HW accelerator isn't initialzed 4951 * yet. Postpone this to machine init (see default_caps_with_cpu()). 4952 */ 4953 smc->default_caps.caps[SPAPR_CAP_HPT_MAXPAGESIZE] = 0; 4954 } 4955 4956 DEFINE_SPAPR_MACHINE(2_12, "2.12", false); 4957 4958 static void spapr_machine_2_12_sxxm_class_options(MachineClass *mc) 4959 { 4960 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4961 4962 spapr_machine_2_12_class_options(mc); 4963 smc->default_caps.caps[SPAPR_CAP_CFPC] = SPAPR_CAP_WORKAROUND; 4964 smc->default_caps.caps[SPAPR_CAP_SBBC] = SPAPR_CAP_WORKAROUND; 4965 smc->default_caps.caps[SPAPR_CAP_IBS] = SPAPR_CAP_FIXED_CCD; 4966 } 4967 4968 DEFINE_SPAPR_MACHINE(2_12_sxxm, "2.12-sxxm", false); 4969 4970 /* 4971 * pseries-2.11 4972 */ 4973 4974 static void spapr_machine_2_11_class_options(MachineClass *mc) 4975 { 4976 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 4977 4978 spapr_machine_2_12_class_options(mc); 4979 smc->default_caps.caps[SPAPR_CAP_HTM] = SPAPR_CAP_ON; 4980 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len); 4981 } 4982 4983 DEFINE_SPAPR_MACHINE(2_11, "2.11", false); 4984 4985 /* 4986 * pseries-2.10 4987 */ 4988 4989 static void spapr_machine_2_10_class_options(MachineClass *mc) 4990 { 4991 spapr_machine_2_11_class_options(mc); 4992 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len); 4993 } 4994 4995 DEFINE_SPAPR_MACHINE(2_10, "2.10", false); 4996 4997 /* 4998 * pseries-2.9 4999 */ 5000 5001 static void spapr_machine_2_9_class_options(MachineClass *mc) 5002 { 5003 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5004 static GlobalProperty compat[] = { 5005 { TYPE_POWERPC_CPU, "pre-2.10-migration", "on" }, 5006 }; 5007 5008 spapr_machine_2_10_class_options(mc); 5009 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len); 5010 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5011 smc->pre_2_10_has_unused_icps = true; 5012 smc->resize_hpt_default = SPAPR_RESIZE_HPT_DISABLED; 5013 } 5014 5015 DEFINE_SPAPR_MACHINE(2_9, "2.9", false); 5016 5017 /* 5018 * pseries-2.8 5019 */ 5020 5021 static void spapr_machine_2_8_class_options(MachineClass *mc) 5022 { 5023 static GlobalProperty compat[] = { 5024 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pcie-extended-configuration-space", "off" }, 5025 }; 5026 5027 spapr_machine_2_9_class_options(mc); 5028 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); 5029 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5030 mc->numa_mem_align_shift = 23; 5031 } 5032 5033 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 5034 5035 /* 5036 * pseries-2.7 5037 */ 5038 5039 static bool phb_placement_2_7(SpaprMachineState *spapr, uint32_t index, 5040 uint64_t *buid, hwaddr *pio, 5041 hwaddr *mmio32, hwaddr *mmio64, 5042 unsigned n_dma, uint32_t *liobns, 5043 hwaddr *nv2gpa, hwaddr *nv2atsd, Error **errp) 5044 { 5045 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 5046 const uint64_t base_buid = 0x800000020000000ULL; 5047 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 5048 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 5049 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 5050 const uint32_t max_index = 255; 5051 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 5052 5053 uint64_t ram_top = MACHINE(spapr)->ram_size; 5054 hwaddr phb0_base, phb_base; 5055 int i; 5056 5057 /* Do we have device memory? */ 5058 if (MACHINE(spapr)->maxram_size > ram_top) { 5059 /* Can't just use maxram_size, because there may be an 5060 * alignment gap between normal and device memory regions 5061 */ 5062 ram_top = MACHINE(spapr)->device_memory->base + 5063 memory_region_size(&MACHINE(spapr)->device_memory->mr); 5064 } 5065 5066 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 5067 5068 if (index > max_index) { 5069 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 5070 max_index); 5071 return false; 5072 } 5073 5074 *buid = base_buid + index; 5075 for (i = 0; i < n_dma; ++i) { 5076 liobns[i] = SPAPR_PCI_LIOBN(index, i); 5077 } 5078 5079 phb_base = phb0_base + index * phb_spacing; 5080 *pio = phb_base + pio_offset; 5081 *mmio32 = phb_base + mmio_offset; 5082 /* 5083 * We don't set the 64-bit MMIO window, relying on the PHB's 5084 * fallback behaviour of automatically splitting a large "32-bit" 5085 * window into contiguous 32-bit and 64-bit windows 5086 */ 5087 5088 *nv2gpa = 0; 5089 *nv2atsd = 0; 5090 return true; 5091 } 5092 5093 static void spapr_machine_2_7_class_options(MachineClass *mc) 5094 { 5095 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5096 static GlobalProperty compat[] = { 5097 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0xf80000000", }, 5098 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem64_win_size", "0", }, 5099 { TYPE_POWERPC_CPU, "pre-2.8-migration", "on", }, 5100 { TYPE_SPAPR_PCI_HOST_BRIDGE, "pre-2.8-migration", "on", }, 5101 }; 5102 5103 spapr_machine_2_8_class_options(mc); 5104 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power7_v2.3"); 5105 mc->default_machine_opts = "modern-hotplug-events=off"; 5106 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len); 5107 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5108 smc->phb_placement = phb_placement_2_7; 5109 } 5110 5111 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 5112 5113 /* 5114 * pseries-2.6 5115 */ 5116 5117 static void spapr_machine_2_6_class_options(MachineClass *mc) 5118 { 5119 static GlobalProperty compat[] = { 5120 { TYPE_SPAPR_PCI_HOST_BRIDGE, "ddw", "off" }, 5121 }; 5122 5123 spapr_machine_2_7_class_options(mc); 5124 mc->has_hotpluggable_cpus = false; 5125 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); 5126 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5127 } 5128 5129 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 5130 5131 /* 5132 * pseries-2.5 5133 */ 5134 5135 static void spapr_machine_2_5_class_options(MachineClass *mc) 5136 { 5137 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5138 static GlobalProperty compat[] = { 5139 { "spapr-vlan", "use-rx-buffer-pools", "off" }, 5140 }; 5141 5142 spapr_machine_2_6_class_options(mc); 5143 smc->use_ohci_by_default = true; 5144 compat_props_add(mc->compat_props, hw_compat_2_5, hw_compat_2_5_len); 5145 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5146 } 5147 5148 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 5149 5150 /* 5151 * pseries-2.4 5152 */ 5153 5154 static void spapr_machine_2_4_class_options(MachineClass *mc) 5155 { 5156 SpaprMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 5157 5158 spapr_machine_2_5_class_options(mc); 5159 smc->dr_lmb_enabled = false; 5160 compat_props_add(mc->compat_props, hw_compat_2_4, hw_compat_2_4_len); 5161 } 5162 5163 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 5164 5165 /* 5166 * pseries-2.3 5167 */ 5168 5169 static void spapr_machine_2_3_class_options(MachineClass *mc) 5170 { 5171 static GlobalProperty compat[] = { 5172 { "spapr-pci-host-bridge", "dynamic-reconfiguration", "off" }, 5173 }; 5174 spapr_machine_2_4_class_options(mc); 5175 compat_props_add(mc->compat_props, hw_compat_2_3, hw_compat_2_3_len); 5176 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5177 } 5178 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 5179 5180 /* 5181 * pseries-2.2 5182 */ 5183 5184 static void spapr_machine_2_2_class_options(MachineClass *mc) 5185 { 5186 static GlobalProperty compat[] = { 5187 { TYPE_SPAPR_PCI_HOST_BRIDGE, "mem_win_size", "0x20000000" }, 5188 }; 5189 5190 spapr_machine_2_3_class_options(mc); 5191 compat_props_add(mc->compat_props, hw_compat_2_2, hw_compat_2_2_len); 5192 compat_props_add(mc->compat_props, compat, G_N_ELEMENTS(compat)); 5193 mc->default_machine_opts = "modern-hotplug-events=off,suppress-vmdesc=on"; 5194 } 5195 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 5196 5197 /* 5198 * pseries-2.1 5199 */ 5200 5201 static void spapr_machine_2_1_class_options(MachineClass *mc) 5202 { 5203 spapr_machine_2_2_class_options(mc); 5204 compat_props_add(mc->compat_props, hw_compat_2_1, hw_compat_2_1_len); 5205 } 5206 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 5207 5208 static void spapr_machine_register_types(void) 5209 { 5210 type_register_static(&spapr_machine_info); 5211 } 5212 5213 type_init(spapr_machine_register_types) 5214