1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/kvm.h" 40 #include "sysemu/device_tree.h" 41 #include "kvm_ppc.h" 42 #include "migration/migration.h" 43 #include "mmu-hash64.h" 44 #include "qom/cpu.h" 45 46 #include "hw/boards.h" 47 #include "hw/ppc/ppc.h" 48 #include "hw/loader.h" 49 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(const char *type, int nr_servers, 99 int nr_irqs, Error **errp) 100 { 101 Error *err = NULL; 102 DeviceState *dev; 103 104 dev = qdev_create(NULL, type); 105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 107 object_property_set_bool(OBJECT(dev), true, "realized", &err); 108 if (err) { 109 error_propagate(errp, err); 110 object_unparent(OBJECT(dev)); 111 return NULL; 112 } 113 return XICS_COMMON(dev); 114 } 115 116 static XICSState *xics_system_init(MachineState *machine, 117 int nr_servers, int nr_irqs, Error **errp) 118 { 119 XICSState *xics = NULL; 120 121 if (kvm_enabled()) { 122 Error *err = NULL; 123 124 if (machine_kernel_irqchip_allowed(machine)) { 125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, 126 &err); 127 } 128 if (machine_kernel_irqchip_required(machine) && !xics) { 129 error_reportf_err(err, 130 "kernel_irqchip requested but unavailable: "); 131 } else { 132 error_free(err); 133 } 134 } 135 136 if (!xics) { 137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); 138 } 139 140 return xics; 141 } 142 143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 144 int smt_threads) 145 { 146 int i, ret = 0; 147 uint32_t servers_prop[smt_threads]; 148 uint32_t gservers_prop[smt_threads * 2]; 149 int index = ppc_get_vcpu_dt_id(cpu); 150 151 if (cpu->cpu_version) { 152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version); 153 if (ret < 0) { 154 return ret; 155 } 156 } 157 158 /* Build interrupt servers and gservers properties */ 159 for (i = 0; i < smt_threads; i++) { 160 servers_prop[i] = cpu_to_be32(index + i); 161 /* Hack, direct the group queues back to cpu 0 */ 162 gservers_prop[i*2] = cpu_to_be32(index + i); 163 gservers_prop[i*2 + 1] = 0; 164 } 165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 166 servers_prop, sizeof(servers_prop)); 167 if (ret < 0) { 168 return ret; 169 } 170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 171 gservers_prop, sizeof(gservers_prop)); 172 173 return ret; 174 } 175 176 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 177 { 178 int ret = 0; 179 PowerPCCPU *cpu = POWERPC_CPU(cs); 180 int index = ppc_get_vcpu_dt_id(cpu); 181 uint32_t associativity[] = {cpu_to_be32(0x5), 182 cpu_to_be32(0x0), 183 cpu_to_be32(0x0), 184 cpu_to_be32(0x0), 185 cpu_to_be32(cs->numa_node), 186 cpu_to_be32(index)}; 187 188 /* Advertise NUMA via ibm,associativity */ 189 if (nb_numa_nodes > 1) { 190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 191 sizeof(associativity)); 192 } 193 194 return ret; 195 } 196 197 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 198 { 199 int ret = 0, offset, cpus_offset; 200 CPUState *cs; 201 char cpu_model[32]; 202 int smt = kvmppc_smt_threads(); 203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 204 205 CPU_FOREACH(cs) { 206 PowerPCCPU *cpu = POWERPC_CPU(cs); 207 DeviceClass *dc = DEVICE_GET_CLASS(cs); 208 int index = ppc_get_vcpu_dt_id(cpu); 209 210 if ((index % smt) != 0) { 211 continue; 212 } 213 214 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 215 216 cpus_offset = fdt_path_offset(fdt, "/cpus"); 217 if (cpus_offset < 0) { 218 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 219 "cpus"); 220 if (cpus_offset < 0) { 221 return cpus_offset; 222 } 223 } 224 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 225 if (offset < 0) { 226 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 227 if (offset < 0) { 228 return offset; 229 } 230 } 231 232 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 233 pft_size_prop, sizeof(pft_size_prop)); 234 if (ret < 0) { 235 return ret; 236 } 237 238 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 239 if (ret < 0) { 240 return ret; 241 } 242 243 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 244 ppc_get_compat_smt_threads(cpu)); 245 if (ret < 0) { 246 return ret; 247 } 248 } 249 return ret; 250 } 251 252 253 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop, 254 size_t maxsize) 255 { 256 size_t maxcells = maxsize / sizeof(uint32_t); 257 int i, j, count; 258 uint32_t *p = prop; 259 260 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) { 261 struct ppc_one_seg_page_size *sps = &env->sps.sps[i]; 262 263 if (!sps->page_shift) { 264 break; 265 } 266 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) { 267 if (sps->enc[count].page_shift == 0) { 268 break; 269 } 270 } 271 if ((p - prop) >= (maxcells - 3 - count * 2)) { 272 break; 273 } 274 *(p++) = cpu_to_be32(sps->page_shift); 275 *(p++) = cpu_to_be32(sps->slb_enc); 276 *(p++) = cpu_to_be32(count); 277 for (j = 0; j < count; j++) { 278 *(p++) = cpu_to_be32(sps->enc[j].page_shift); 279 *(p++) = cpu_to_be32(sps->enc[j].pte_enc); 280 } 281 } 282 283 return (p - prop) * sizeof(uint32_t); 284 } 285 286 static hwaddr spapr_node0_size(void) 287 { 288 MachineState *machine = MACHINE(qdev_get_machine()); 289 290 if (nb_numa_nodes) { 291 int i; 292 for (i = 0; i < nb_numa_nodes; ++i) { 293 if (numa_info[i].node_mem) { 294 return MIN(pow2floor(numa_info[i].node_mem), 295 machine->ram_size); 296 } 297 } 298 } 299 return machine->ram_size; 300 } 301 302 #define _FDT(exp) \ 303 do { \ 304 int ret = (exp); \ 305 if (ret < 0) { \ 306 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ 307 #exp, fdt_strerror(ret)); \ 308 exit(1); \ 309 } \ 310 } while (0) 311 312 static void add_str(GString *s, const gchar *s1) 313 { 314 g_string_append_len(s, s1, strlen(s1) + 1); 315 } 316 317 static void *spapr_create_fdt_skel(hwaddr initrd_base, 318 hwaddr initrd_size, 319 hwaddr kernel_size, 320 bool little_endian, 321 const char *kernel_cmdline, 322 uint32_t epow_irq) 323 { 324 void *fdt; 325 uint32_t start_prop = cpu_to_be32(initrd_base); 326 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); 327 GString *hypertas = g_string_sized_new(256); 328 GString *qemu_hypertas = g_string_sized_new(256); 329 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)}; 330 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)}; 331 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80}; 332 char *buf; 333 334 add_str(hypertas, "hcall-pft"); 335 add_str(hypertas, "hcall-term"); 336 add_str(hypertas, "hcall-dabr"); 337 add_str(hypertas, "hcall-interrupt"); 338 add_str(hypertas, "hcall-tce"); 339 add_str(hypertas, "hcall-vio"); 340 add_str(hypertas, "hcall-splpar"); 341 add_str(hypertas, "hcall-bulk"); 342 add_str(hypertas, "hcall-set-mode"); 343 add_str(hypertas, "hcall-sprg0"); 344 add_str(hypertas, "hcall-copy"); 345 add_str(hypertas, "hcall-debug"); 346 add_str(qemu_hypertas, "hcall-memop1"); 347 348 fdt = g_malloc0(FDT_MAX_SIZE); 349 _FDT((fdt_create(fdt, FDT_MAX_SIZE))); 350 351 if (kernel_size) { 352 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size))); 353 } 354 if (initrd_size) { 355 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size))); 356 } 357 _FDT((fdt_finish_reservemap(fdt))); 358 359 /* Root node */ 360 _FDT((fdt_begin_node(fdt, ""))); 361 _FDT((fdt_property_string(fdt, "device_type", "chrp"))); 362 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); 363 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries"))); 364 365 /* 366 * Add info to guest to indentify which host is it being run on 367 * and what is the uuid of the guest 368 */ 369 if (kvmppc_get_host_model(&buf)) { 370 _FDT((fdt_property_string(fdt, "host-model", buf))); 371 g_free(buf); 372 } 373 if (kvmppc_get_host_serial(&buf)) { 374 _FDT((fdt_property_string(fdt, "host-serial", buf))); 375 g_free(buf); 376 } 377 378 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1], 379 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4], 380 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7], 381 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10], 382 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13], 383 qemu_uuid[14], qemu_uuid[15]); 384 385 _FDT((fdt_property_string(fdt, "vm,uuid", buf))); 386 if (qemu_uuid_set) { 387 _FDT((fdt_property_string(fdt, "system-id", buf))); 388 } 389 g_free(buf); 390 391 if (qemu_get_vm_name()) { 392 _FDT((fdt_property_string(fdt, "ibm,partition-name", 393 qemu_get_vm_name()))); 394 } 395 396 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); 397 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); 398 399 /* /chosen */ 400 _FDT((fdt_begin_node(fdt, "chosen"))); 401 402 /* Set Form1_affinity */ 403 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5)))); 404 405 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); 406 _FDT((fdt_property(fdt, "linux,initrd-start", 407 &start_prop, sizeof(start_prop)))); 408 _FDT((fdt_property(fdt, "linux,initrd-end", 409 &end_prop, sizeof(end_prop)))); 410 if (kernel_size) { 411 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 412 cpu_to_be64(kernel_size) }; 413 414 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop)))); 415 if (little_endian) { 416 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0))); 417 } 418 } 419 if (boot_menu) { 420 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu))); 421 } 422 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width))); 423 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height))); 424 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth))); 425 426 _FDT((fdt_end_node(fdt))); 427 428 /* RTAS */ 429 _FDT((fdt_begin_node(fdt, "rtas"))); 430 431 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 432 add_str(hypertas, "hcall-multi-tce"); 433 } 434 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str, 435 hypertas->len))); 436 g_string_free(hypertas, TRUE); 437 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str, 438 qemu_hypertas->len))); 439 g_string_free(qemu_hypertas, TRUE); 440 441 _FDT((fdt_property(fdt, "ibm,associativity-reference-points", 442 refpoints, sizeof(refpoints)))); 443 444 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX))); 445 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate", 446 RTAS_EVENT_SCAN_RATE))); 447 448 if (msi_nonbroken) { 449 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0))); 450 } 451 452 /* 453 * According to PAPR, rtas ibm,os-term does not guarantee a return 454 * back to the guest cpu. 455 * 456 * While an additional ibm,extended-os-term property indicates that 457 * rtas call return will always occur. Set this property. 458 */ 459 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0))); 460 461 _FDT((fdt_end_node(fdt))); 462 463 /* interrupt controller */ 464 _FDT((fdt_begin_node(fdt, "interrupt-controller"))); 465 466 _FDT((fdt_property_string(fdt, "device_type", 467 "PowerPC-External-Interrupt-Presentation"))); 468 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); 469 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 470 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", 471 interrupt_server_ranges_prop, 472 sizeof(interrupt_server_ranges_prop)))); 473 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2))); 474 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP))); 475 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP))); 476 477 _FDT((fdt_end_node(fdt))); 478 479 /* vdevice */ 480 _FDT((fdt_begin_node(fdt, "vdevice"))); 481 482 _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); 483 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); 484 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); 485 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); 486 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); 487 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); 488 489 _FDT((fdt_end_node(fdt))); 490 491 /* event-sources */ 492 spapr_events_fdt_skel(fdt, epow_irq); 493 494 /* /hypervisor node */ 495 if (kvm_enabled()) { 496 uint8_t hypercall[16]; 497 498 /* indicate KVM hypercall interface */ 499 _FDT((fdt_begin_node(fdt, "hypervisor"))); 500 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm"))); 501 if (kvmppc_has_cap_fixup_hcalls()) { 502 /* 503 * Older KVM versions with older guest kernels were broken with the 504 * magic page, don't allow the guest to map it. 505 */ 506 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 507 sizeof(hypercall))) { 508 _FDT((fdt_property(fdt, "hcall-instructions", hypercall, 509 sizeof(hypercall)))); 510 } 511 } 512 _FDT((fdt_end_node(fdt))); 513 } 514 515 _FDT((fdt_end_node(fdt))); /* close root node */ 516 _FDT((fdt_finish(fdt))); 517 518 return fdt; 519 } 520 521 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 522 hwaddr size) 523 { 524 uint32_t associativity[] = { 525 cpu_to_be32(0x4), /* length */ 526 cpu_to_be32(0x0), cpu_to_be32(0x0), 527 cpu_to_be32(0x0), cpu_to_be32(nodeid) 528 }; 529 char mem_name[32]; 530 uint64_t mem_reg_property[2]; 531 int off; 532 533 mem_reg_property[0] = cpu_to_be64(start); 534 mem_reg_property[1] = cpu_to_be64(size); 535 536 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 537 off = fdt_add_subnode(fdt, 0, mem_name); 538 _FDT(off); 539 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 540 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 541 sizeof(mem_reg_property)))); 542 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 543 sizeof(associativity)))); 544 return off; 545 } 546 547 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 548 { 549 MachineState *machine = MACHINE(spapr); 550 hwaddr mem_start, node_size; 551 int i, nb_nodes = nb_numa_nodes; 552 NodeInfo *nodes = numa_info; 553 NodeInfo ramnode; 554 555 /* No NUMA nodes, assume there is just one node with whole RAM */ 556 if (!nb_numa_nodes) { 557 nb_nodes = 1; 558 ramnode.node_mem = machine->ram_size; 559 nodes = &ramnode; 560 } 561 562 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 563 if (!nodes[i].node_mem) { 564 continue; 565 } 566 if (mem_start >= machine->ram_size) { 567 node_size = 0; 568 } else { 569 node_size = nodes[i].node_mem; 570 if (node_size > machine->ram_size - mem_start) { 571 node_size = machine->ram_size - mem_start; 572 } 573 } 574 if (!mem_start) { 575 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 576 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 577 mem_start += spapr->rma_size; 578 node_size -= spapr->rma_size; 579 } 580 for ( ; node_size; ) { 581 hwaddr sizetmp = pow2floor(node_size); 582 583 /* mem_start != 0 here */ 584 if (ctzl(mem_start) < ctzl(sizetmp)) { 585 sizetmp = 1ULL << ctzl(mem_start); 586 } 587 588 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 589 node_size -= sizetmp; 590 mem_start += sizetmp; 591 } 592 } 593 594 return 0; 595 } 596 597 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 598 sPAPRMachineState *spapr) 599 { 600 PowerPCCPU *cpu = POWERPC_CPU(cs); 601 CPUPPCState *env = &cpu->env; 602 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 603 int index = ppc_get_vcpu_dt_id(cpu); 604 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 605 0xffffffff, 0xffffffff}; 606 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 607 : SPAPR_TIMEBASE_FREQ; 608 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 609 uint32_t page_sizes_prop[64]; 610 size_t page_sizes_prop_size; 611 uint32_t vcpus_per_socket = smp_threads * smp_cores; 612 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 613 sPAPRDRConnector *drc; 614 sPAPRDRConnectorClass *drck; 615 int drc_index; 616 617 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 618 if (drc) { 619 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 620 drc_index = drck->get_index(drc); 621 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 622 } 623 624 /* Note: we keep CI large pages off for now because a 64K capable guest 625 * provisioned with large pages might otherwise try to map a qemu 626 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 627 * even if that qemu runs on a 4k host. 628 * 629 * We can later add this bit back when we are confident this is not 630 * an issue (!HV KVM or 64K host) 631 */ 632 uint8_t pa_features_206[] = { 6, 0, 633 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 634 uint8_t pa_features_207[] = { 24, 0, 635 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 636 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 637 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 638 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 639 uint8_t *pa_features; 640 size_t pa_size; 641 642 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 643 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 644 645 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 646 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 647 env->dcache_line_size))); 648 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 649 env->dcache_line_size))); 650 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 651 env->icache_line_size))); 652 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 653 env->icache_line_size))); 654 655 if (pcc->l1_dcache_size) { 656 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 657 pcc->l1_dcache_size))); 658 } else { 659 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n"); 660 } 661 if (pcc->l1_icache_size) { 662 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 663 pcc->l1_icache_size))); 664 } else { 665 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n"); 666 } 667 668 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 669 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 670 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 671 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 672 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 673 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 674 675 if (env->spr_cb[SPR_PURR].oea_read) { 676 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 677 } 678 679 if (env->mmu_model & POWERPC_MMU_1TSEG) { 680 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 681 segs, sizeof(segs)))); 682 } 683 684 /* Advertise VMX/VSX (vector extensions) if available 685 * 0 / no property == no vector extensions 686 * 1 == VMX / Altivec available 687 * 2 == VSX available */ 688 if (env->insns_flags & PPC_ALTIVEC) { 689 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 690 691 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 692 } 693 694 /* Advertise DFP (Decimal Floating Point) if available 695 * 0 / no property == no DFP 696 * 1 == DFP available */ 697 if (env->insns_flags2 & PPC2_DFP) { 698 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 699 } 700 701 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop, 702 sizeof(page_sizes_prop)); 703 if (page_sizes_prop_size) { 704 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 705 page_sizes_prop, page_sizes_prop_size))); 706 } 707 708 /* Do the ibm,pa-features property, adjust it for ci-large-pages */ 709 if (env->mmu_model == POWERPC_MMU_2_06) { 710 pa_features = pa_features_206; 711 pa_size = sizeof(pa_features_206); 712 } else /* env->mmu_model == POWERPC_MMU_2_07 */ { 713 pa_features = pa_features_207; 714 pa_size = sizeof(pa_features_207); 715 } 716 if (env->ci_large_pages) { 717 pa_features[3] |= 0x20; 718 } 719 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 720 721 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 722 cs->cpu_index / vcpus_per_socket))); 723 724 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 725 pft_size_prop, sizeof(pft_size_prop)))); 726 727 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 728 729 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, 730 ppc_get_compat_smt_threads(cpu))); 731 } 732 733 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 734 { 735 CPUState *cs; 736 int cpus_offset; 737 char *nodename; 738 int smt = kvmppc_smt_threads(); 739 740 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 741 _FDT(cpus_offset); 742 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 743 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 744 745 /* 746 * We walk the CPUs in reverse order to ensure that CPU DT nodes 747 * created by fdt_add_subnode() end up in the right order in FDT 748 * for the guest kernel the enumerate the CPUs correctly. 749 */ 750 CPU_FOREACH_REVERSE(cs) { 751 PowerPCCPU *cpu = POWERPC_CPU(cs); 752 int index = ppc_get_vcpu_dt_id(cpu); 753 DeviceClass *dc = DEVICE_GET_CLASS(cs); 754 int offset; 755 756 if ((index % smt) != 0) { 757 continue; 758 } 759 760 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 761 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 762 g_free(nodename); 763 _FDT(offset); 764 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 765 } 766 767 } 768 769 /* 770 * Adds ibm,dynamic-reconfiguration-memory node. 771 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 772 * of this device tree node. 773 */ 774 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 775 { 776 MachineState *machine = MACHINE(spapr); 777 int ret, i, offset; 778 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 779 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 780 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 781 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 782 memory_region_size(&spapr->hotplug_memory.mr)) / 783 lmb_size; 784 uint32_t *int_buf, *cur_index, buf_len; 785 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 786 787 /* 788 * Don't create the node if there is no hotpluggable memory 789 */ 790 if (machine->ram_size == machine->maxram_size) { 791 return 0; 792 } 793 794 /* 795 * Allocate enough buffer size to fit in ibm,dynamic-memory 796 * or ibm,associativity-lookup-arrays 797 */ 798 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 799 * sizeof(uint32_t); 800 cur_index = int_buf = g_malloc0(buf_len); 801 802 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 803 804 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 805 sizeof(prop_lmb_size)); 806 if (ret < 0) { 807 goto out; 808 } 809 810 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 811 if (ret < 0) { 812 goto out; 813 } 814 815 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 816 if (ret < 0) { 817 goto out; 818 } 819 820 /* ibm,dynamic-memory */ 821 int_buf[0] = cpu_to_be32(nr_lmbs); 822 cur_index++; 823 for (i = 0; i < nr_lmbs; i++) { 824 uint64_t addr = i * lmb_size; 825 uint32_t *dynamic_memory = cur_index; 826 827 if (i >= hotplug_lmb_start) { 828 sPAPRDRConnector *drc; 829 sPAPRDRConnectorClass *drck; 830 831 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 832 g_assert(drc); 833 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 834 835 dynamic_memory[0] = cpu_to_be32(addr >> 32); 836 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 837 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 838 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 839 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 840 if (memory_region_present(get_system_memory(), addr)) { 841 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 842 } else { 843 dynamic_memory[5] = cpu_to_be32(0); 844 } 845 } else { 846 /* 847 * LMB information for RMA, boot time RAM and gap b/n RAM and 848 * hotplug memory region -- all these are marked as reserved 849 * and as having no valid DRC. 850 */ 851 dynamic_memory[0] = cpu_to_be32(addr >> 32); 852 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 853 dynamic_memory[2] = cpu_to_be32(0); 854 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 855 dynamic_memory[4] = cpu_to_be32(-1); 856 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 857 SPAPR_LMB_FLAGS_DRC_INVALID); 858 } 859 860 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 861 } 862 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 863 if (ret < 0) { 864 goto out; 865 } 866 867 /* ibm,associativity-lookup-arrays */ 868 cur_index = int_buf; 869 int_buf[0] = cpu_to_be32(nr_nodes); 870 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 871 cur_index += 2; 872 for (i = 0; i < nr_nodes; i++) { 873 uint32_t associativity[] = { 874 cpu_to_be32(0x0), 875 cpu_to_be32(0x0), 876 cpu_to_be32(0x0), 877 cpu_to_be32(i) 878 }; 879 memcpy(cur_index, associativity, sizeof(associativity)); 880 cur_index += 4; 881 } 882 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 883 (cur_index - int_buf) * sizeof(uint32_t)); 884 out: 885 g_free(int_buf); 886 return ret; 887 } 888 889 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 890 target_ulong addr, target_ulong size, 891 bool cpu_update, bool memory_update) 892 { 893 void *fdt, *fdt_skel; 894 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 895 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 896 897 size -= sizeof(hdr); 898 899 /* Create sceleton */ 900 fdt_skel = g_malloc0(size); 901 _FDT((fdt_create(fdt_skel, size))); 902 _FDT((fdt_begin_node(fdt_skel, ""))); 903 _FDT((fdt_end_node(fdt_skel))); 904 _FDT((fdt_finish(fdt_skel))); 905 fdt = g_malloc0(size); 906 _FDT((fdt_open_into(fdt_skel, fdt, size))); 907 g_free(fdt_skel); 908 909 /* Fixup cpu nodes */ 910 if (cpu_update) { 911 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 912 } 913 914 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 915 if (memory_update && smc->dr_lmb_enabled) { 916 _FDT((spapr_populate_drconf_memory(spapr, fdt))); 917 } 918 919 /* Pack resulting tree */ 920 _FDT((fdt_pack(fdt))); 921 922 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 923 trace_spapr_cas_failed(size); 924 return -1; 925 } 926 927 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 928 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 929 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 930 g_free(fdt); 931 932 return 0; 933 } 934 935 static void spapr_finalize_fdt(sPAPRMachineState *spapr, 936 hwaddr fdt_addr, 937 hwaddr rtas_addr, 938 hwaddr rtas_size) 939 { 940 MachineState *machine = MACHINE(qdev_get_machine()); 941 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 942 const char *boot_device = machine->boot_order; 943 int ret, i; 944 size_t cb = 0; 945 char *bootlist; 946 void *fdt; 947 sPAPRPHBState *phb; 948 949 fdt = g_malloc(FDT_MAX_SIZE); 950 951 /* open out the base tree into a temp buffer for the final tweaks */ 952 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); 953 954 ret = spapr_populate_memory(spapr, fdt); 955 if (ret < 0) { 956 fprintf(stderr, "couldn't setup memory nodes in fdt\n"); 957 exit(1); 958 } 959 960 ret = spapr_populate_vdevice(spapr->vio_bus, fdt); 961 if (ret < 0) { 962 fprintf(stderr, "couldn't setup vio devices in fdt\n"); 963 exit(1); 964 } 965 966 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 967 ret = spapr_rng_populate_dt(fdt); 968 if (ret < 0) { 969 fprintf(stderr, "could not set up rng device in the fdt\n"); 970 exit(1); 971 } 972 } 973 974 QLIST_FOREACH(phb, &spapr->phbs, list) { 975 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 976 if (ret < 0) { 977 error_report("couldn't setup PCI devices in fdt"); 978 exit(1); 979 } 980 } 981 982 /* RTAS */ 983 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); 984 if (ret < 0) { 985 fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); 986 } 987 988 /* cpus */ 989 spapr_populate_cpus_dt_node(fdt, spapr); 990 991 bootlist = get_boot_devices_list(&cb, true); 992 if (cb && bootlist) { 993 int offset = fdt_path_offset(fdt, "/chosen"); 994 if (offset < 0) { 995 exit(1); 996 } 997 for (i = 0; i < cb; i++) { 998 if (bootlist[i] == '\n') { 999 bootlist[i] = ' '; 1000 } 1001 1002 } 1003 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist); 1004 } 1005 1006 if (boot_device && strlen(boot_device)) { 1007 int offset = fdt_path_offset(fdt, "/chosen"); 1008 1009 if (offset < 0) { 1010 exit(1); 1011 } 1012 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device); 1013 } 1014 1015 if (!spapr->has_graphics) { 1016 spapr_populate_chosen_stdout(fdt, spapr->vio_bus); 1017 } 1018 1019 if (smc->dr_lmb_enabled) { 1020 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 1021 } 1022 1023 if (smc->dr_cpu_enabled) { 1024 int offset = fdt_path_offset(fdt, "/cpus"); 1025 ret = spapr_drc_populate_dt(fdt, offset, NULL, 1026 SPAPR_DR_CONNECTOR_TYPE_CPU); 1027 if (ret < 0) { 1028 error_report("Couldn't set up CPU DR device tree properties"); 1029 exit(1); 1030 } 1031 } 1032 1033 _FDT((fdt_pack(fdt))); 1034 1035 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1036 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1037 fdt_totalsize(fdt), FDT_MAX_SIZE); 1038 exit(1); 1039 } 1040 1041 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1042 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1043 1044 g_free(bootlist); 1045 g_free(fdt); 1046 } 1047 1048 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1049 { 1050 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1051 } 1052 1053 static void emulate_spapr_hypercall(PowerPCCPU *cpu) 1054 { 1055 CPUPPCState *env = &cpu->env; 1056 1057 if (msr_pr) { 1058 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1059 env->gpr[3] = H_PRIVILEGE; 1060 } else { 1061 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1062 } 1063 } 1064 1065 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1066 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1067 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1068 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1069 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1070 1071 /* 1072 * Get the fd to access the kernel htab, re-opening it if necessary 1073 */ 1074 static int get_htab_fd(sPAPRMachineState *spapr) 1075 { 1076 if (spapr->htab_fd >= 0) { 1077 return spapr->htab_fd; 1078 } 1079 1080 spapr->htab_fd = kvmppc_get_htab_fd(false); 1081 if (spapr->htab_fd < 0) { 1082 error_report("Unable to open fd for reading hash table from KVM: %s", 1083 strerror(errno)); 1084 } 1085 1086 return spapr->htab_fd; 1087 } 1088 1089 static void close_htab_fd(sPAPRMachineState *spapr) 1090 { 1091 if (spapr->htab_fd >= 0) { 1092 close(spapr->htab_fd); 1093 } 1094 spapr->htab_fd = -1; 1095 } 1096 1097 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1098 { 1099 int shift; 1100 1101 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1102 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1103 * that's much more than is needed for Linux guests */ 1104 shift = ctz64(pow2ceil(ramsize)) - 7; 1105 shift = MAX(shift, 18); /* Minimum architected size */ 1106 shift = MIN(shift, 46); /* Maximum architected size */ 1107 return shift; 1108 } 1109 1110 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1111 Error **errp) 1112 { 1113 long rc; 1114 1115 /* Clean up any HPT info from a previous boot */ 1116 g_free(spapr->htab); 1117 spapr->htab = NULL; 1118 spapr->htab_shift = 0; 1119 close_htab_fd(spapr); 1120 1121 rc = kvmppc_reset_htab(shift); 1122 if (rc < 0) { 1123 /* kernel-side HPT needed, but couldn't allocate one */ 1124 error_setg_errno(errp, errno, 1125 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1126 shift); 1127 /* This is almost certainly fatal, but if the caller really 1128 * wants to carry on with shift == 0, it's welcome to try */ 1129 } else if (rc > 0) { 1130 /* kernel-side HPT allocated */ 1131 if (rc != shift) { 1132 error_setg(errp, 1133 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1134 shift, rc); 1135 } 1136 1137 spapr->htab_shift = shift; 1138 spapr->htab = NULL; 1139 } else { 1140 /* kernel-side HPT not needed, allocate in userspace instead */ 1141 size_t size = 1ULL << shift; 1142 int i; 1143 1144 spapr->htab = qemu_memalign(size, size); 1145 if (!spapr->htab) { 1146 error_setg_errno(errp, errno, 1147 "Could not allocate HPT of order %d", shift); 1148 return; 1149 } 1150 1151 memset(spapr->htab, 0, size); 1152 spapr->htab_shift = shift; 1153 1154 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1155 DIRTY_HPTE(HPTE(spapr->htab, i)); 1156 } 1157 } 1158 } 1159 1160 static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1161 { 1162 bool matched = false; 1163 1164 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1165 matched = true; 1166 } 1167 1168 if (!matched) { 1169 error_report("Device %s is not supported by this machine yet.", 1170 qdev_fw_name(DEVICE(sbdev))); 1171 exit(1); 1172 } 1173 1174 return 0; 1175 } 1176 1177 static void ppc_spapr_reset(void) 1178 { 1179 MachineState *machine = MACHINE(qdev_get_machine()); 1180 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1181 PowerPCCPU *first_ppc_cpu; 1182 uint32_t rtas_limit; 1183 1184 /* Check for unknown sysbus devices */ 1185 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1186 1187 /* Allocate and/or reset the hash page table */ 1188 spapr_reallocate_hpt(spapr, 1189 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1190 &error_fatal); 1191 1192 /* Update the RMA size if necessary */ 1193 if (spapr->vrma_adjust) { 1194 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1195 spapr->htab_shift); 1196 } 1197 1198 qemu_devices_reset(); 1199 1200 /* 1201 * We place the device tree and RTAS just below either the top of the RMA, 1202 * or just below 2GB, whichever is lowere, so that it can be 1203 * processed with 32-bit real mode code if necessary 1204 */ 1205 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1206 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1207 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE; 1208 1209 /* Load the fdt */ 1210 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, 1211 spapr->rtas_size); 1212 1213 /* Copy RTAS over */ 1214 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob, 1215 spapr->rtas_size); 1216 1217 /* Set up the entry state */ 1218 first_ppc_cpu = POWERPC_CPU(first_cpu); 1219 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr; 1220 first_ppc_cpu->env.gpr[5] = 0; 1221 first_cpu->halted = 0; 1222 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1223 1224 } 1225 1226 static void spapr_create_nvram(sPAPRMachineState *spapr) 1227 { 1228 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1229 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1230 1231 if (dinfo) { 1232 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1233 &error_fatal); 1234 } 1235 1236 qdev_init_nofail(dev); 1237 1238 spapr->nvram = (struct sPAPRNVRAM *)dev; 1239 } 1240 1241 static void spapr_rtc_create(sPAPRMachineState *spapr) 1242 { 1243 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1244 1245 qdev_init_nofail(dev); 1246 spapr->rtc = dev; 1247 1248 object_property_add_alias(qdev_get_machine(), "rtc-time", 1249 OBJECT(spapr->rtc), "date", NULL); 1250 } 1251 1252 /* Returns whether we want to use VGA or not */ 1253 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1254 { 1255 switch (vga_interface_type) { 1256 case VGA_NONE: 1257 return false; 1258 case VGA_DEVICE: 1259 return true; 1260 case VGA_STD: 1261 case VGA_VIRTIO: 1262 return pci_vga_init(pci_bus) != NULL; 1263 default: 1264 error_setg(errp, 1265 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1266 return false; 1267 } 1268 } 1269 1270 static int spapr_post_load(void *opaque, int version_id) 1271 { 1272 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1273 int err = 0; 1274 1275 /* In earlier versions, there was no separate qdev for the PAPR 1276 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1277 * So when migrating from those versions, poke the incoming offset 1278 * value into the RTC device */ 1279 if (version_id < 3) { 1280 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1281 } 1282 1283 return err; 1284 } 1285 1286 static bool version_before_3(void *opaque, int version_id) 1287 { 1288 return version_id < 3; 1289 } 1290 1291 static const VMStateDescription vmstate_spapr = { 1292 .name = "spapr", 1293 .version_id = 3, 1294 .minimum_version_id = 1, 1295 .post_load = spapr_post_load, 1296 .fields = (VMStateField[]) { 1297 /* used to be @next_irq */ 1298 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1299 1300 /* RTC offset */ 1301 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1302 1303 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1304 VMSTATE_END_OF_LIST() 1305 }, 1306 }; 1307 1308 static int htab_save_setup(QEMUFile *f, void *opaque) 1309 { 1310 sPAPRMachineState *spapr = opaque; 1311 1312 /* "Iteration" header */ 1313 qemu_put_be32(f, spapr->htab_shift); 1314 1315 if (spapr->htab) { 1316 spapr->htab_save_index = 0; 1317 spapr->htab_first_pass = true; 1318 } else { 1319 assert(kvm_enabled()); 1320 } 1321 1322 1323 return 0; 1324 } 1325 1326 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1327 int64_t max_ns) 1328 { 1329 bool has_timeout = max_ns != -1; 1330 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1331 int index = spapr->htab_save_index; 1332 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1333 1334 assert(spapr->htab_first_pass); 1335 1336 do { 1337 int chunkstart; 1338 1339 /* Consume invalid HPTEs */ 1340 while ((index < htabslots) 1341 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1342 index++; 1343 CLEAN_HPTE(HPTE(spapr->htab, index)); 1344 } 1345 1346 /* Consume valid HPTEs */ 1347 chunkstart = index; 1348 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1349 && HPTE_VALID(HPTE(spapr->htab, index))) { 1350 index++; 1351 CLEAN_HPTE(HPTE(spapr->htab, index)); 1352 } 1353 1354 if (index > chunkstart) { 1355 int n_valid = index - chunkstart; 1356 1357 qemu_put_be32(f, chunkstart); 1358 qemu_put_be16(f, n_valid); 1359 qemu_put_be16(f, 0); 1360 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1361 HASH_PTE_SIZE_64 * n_valid); 1362 1363 if (has_timeout && 1364 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1365 break; 1366 } 1367 } 1368 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1369 1370 if (index >= htabslots) { 1371 assert(index == htabslots); 1372 index = 0; 1373 spapr->htab_first_pass = false; 1374 } 1375 spapr->htab_save_index = index; 1376 } 1377 1378 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1379 int64_t max_ns) 1380 { 1381 bool final = max_ns < 0; 1382 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1383 int examined = 0, sent = 0; 1384 int index = spapr->htab_save_index; 1385 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1386 1387 assert(!spapr->htab_first_pass); 1388 1389 do { 1390 int chunkstart, invalidstart; 1391 1392 /* Consume non-dirty HPTEs */ 1393 while ((index < htabslots) 1394 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1395 index++; 1396 examined++; 1397 } 1398 1399 chunkstart = index; 1400 /* Consume valid dirty HPTEs */ 1401 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1402 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1403 && HPTE_VALID(HPTE(spapr->htab, index))) { 1404 CLEAN_HPTE(HPTE(spapr->htab, index)); 1405 index++; 1406 examined++; 1407 } 1408 1409 invalidstart = index; 1410 /* Consume invalid dirty HPTEs */ 1411 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1412 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1413 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1414 CLEAN_HPTE(HPTE(spapr->htab, index)); 1415 index++; 1416 examined++; 1417 } 1418 1419 if (index > chunkstart) { 1420 int n_valid = invalidstart - chunkstart; 1421 int n_invalid = index - invalidstart; 1422 1423 qemu_put_be32(f, chunkstart); 1424 qemu_put_be16(f, n_valid); 1425 qemu_put_be16(f, n_invalid); 1426 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1427 HASH_PTE_SIZE_64 * n_valid); 1428 sent += index - chunkstart; 1429 1430 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1431 break; 1432 } 1433 } 1434 1435 if (examined >= htabslots) { 1436 break; 1437 } 1438 1439 if (index >= htabslots) { 1440 assert(index == htabslots); 1441 index = 0; 1442 } 1443 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1444 1445 if (index >= htabslots) { 1446 assert(index == htabslots); 1447 index = 0; 1448 } 1449 1450 spapr->htab_save_index = index; 1451 1452 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1453 } 1454 1455 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1456 #define MAX_KVM_BUF_SIZE 2048 1457 1458 static int htab_save_iterate(QEMUFile *f, void *opaque) 1459 { 1460 sPAPRMachineState *spapr = opaque; 1461 int fd; 1462 int rc = 0; 1463 1464 /* Iteration header */ 1465 qemu_put_be32(f, 0); 1466 1467 if (!spapr->htab) { 1468 assert(kvm_enabled()); 1469 1470 fd = get_htab_fd(spapr); 1471 if (fd < 0) { 1472 return fd; 1473 } 1474 1475 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1476 if (rc < 0) { 1477 return rc; 1478 } 1479 } else if (spapr->htab_first_pass) { 1480 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1481 } else { 1482 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1483 } 1484 1485 /* End marker */ 1486 qemu_put_be32(f, 0); 1487 qemu_put_be16(f, 0); 1488 qemu_put_be16(f, 0); 1489 1490 return rc; 1491 } 1492 1493 static int htab_save_complete(QEMUFile *f, void *opaque) 1494 { 1495 sPAPRMachineState *spapr = opaque; 1496 int fd; 1497 1498 /* Iteration header */ 1499 qemu_put_be32(f, 0); 1500 1501 if (!spapr->htab) { 1502 int rc; 1503 1504 assert(kvm_enabled()); 1505 1506 fd = get_htab_fd(spapr); 1507 if (fd < 0) { 1508 return fd; 1509 } 1510 1511 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1512 if (rc < 0) { 1513 return rc; 1514 } 1515 close_htab_fd(spapr); 1516 } else { 1517 if (spapr->htab_first_pass) { 1518 htab_save_first_pass(f, spapr, -1); 1519 } 1520 htab_save_later_pass(f, spapr, -1); 1521 } 1522 1523 /* End marker */ 1524 qemu_put_be32(f, 0); 1525 qemu_put_be16(f, 0); 1526 qemu_put_be16(f, 0); 1527 1528 return 0; 1529 } 1530 1531 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1532 { 1533 sPAPRMachineState *spapr = opaque; 1534 uint32_t section_hdr; 1535 int fd = -1; 1536 1537 if (version_id < 1 || version_id > 1) { 1538 error_report("htab_load() bad version"); 1539 return -EINVAL; 1540 } 1541 1542 section_hdr = qemu_get_be32(f); 1543 1544 if (section_hdr) { 1545 Error *local_err = NULL; 1546 1547 /* First section gives the htab size */ 1548 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1549 if (local_err) { 1550 error_report_err(local_err); 1551 return -EINVAL; 1552 } 1553 return 0; 1554 } 1555 1556 if (!spapr->htab) { 1557 assert(kvm_enabled()); 1558 1559 fd = kvmppc_get_htab_fd(true); 1560 if (fd < 0) { 1561 error_report("Unable to open fd to restore KVM hash table: %s", 1562 strerror(errno)); 1563 } 1564 } 1565 1566 while (true) { 1567 uint32_t index; 1568 uint16_t n_valid, n_invalid; 1569 1570 index = qemu_get_be32(f); 1571 n_valid = qemu_get_be16(f); 1572 n_invalid = qemu_get_be16(f); 1573 1574 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1575 /* End of Stream */ 1576 break; 1577 } 1578 1579 if ((index + n_valid + n_invalid) > 1580 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1581 /* Bad index in stream */ 1582 error_report( 1583 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1584 index, n_valid, n_invalid, spapr->htab_shift); 1585 return -EINVAL; 1586 } 1587 1588 if (spapr->htab) { 1589 if (n_valid) { 1590 qemu_get_buffer(f, HPTE(spapr->htab, index), 1591 HASH_PTE_SIZE_64 * n_valid); 1592 } 1593 if (n_invalid) { 1594 memset(HPTE(spapr->htab, index + n_valid), 0, 1595 HASH_PTE_SIZE_64 * n_invalid); 1596 } 1597 } else { 1598 int rc; 1599 1600 assert(fd >= 0); 1601 1602 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1603 if (rc < 0) { 1604 return rc; 1605 } 1606 } 1607 } 1608 1609 if (!spapr->htab) { 1610 assert(fd >= 0); 1611 close(fd); 1612 } 1613 1614 return 0; 1615 } 1616 1617 static SaveVMHandlers savevm_htab_handlers = { 1618 .save_live_setup = htab_save_setup, 1619 .save_live_iterate = htab_save_iterate, 1620 .save_live_complete_precopy = htab_save_complete, 1621 .load_state = htab_load, 1622 }; 1623 1624 static void spapr_boot_set(void *opaque, const char *boot_device, 1625 Error **errp) 1626 { 1627 MachineState *machine = MACHINE(qdev_get_machine()); 1628 machine->boot_order = g_strdup(boot_device); 1629 } 1630 1631 /* 1632 * Reset routine for LMB DR devices. 1633 * 1634 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1635 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1636 * when it walks all its children devices. LMB devices reset occurs 1637 * as part of spapr_ppc_reset(). 1638 */ 1639 static void spapr_drc_reset(void *opaque) 1640 { 1641 sPAPRDRConnector *drc = opaque; 1642 DeviceState *d = DEVICE(drc); 1643 1644 if (d) { 1645 device_reset(d); 1646 } 1647 } 1648 1649 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1650 { 1651 MachineState *machine = MACHINE(spapr); 1652 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1653 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1654 int i; 1655 1656 for (i = 0; i < nr_lmbs; i++) { 1657 sPAPRDRConnector *drc; 1658 uint64_t addr; 1659 1660 addr = i * lmb_size + spapr->hotplug_memory.base; 1661 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1662 addr/lmb_size); 1663 qemu_register_reset(spapr_drc_reset, drc); 1664 } 1665 } 1666 1667 /* 1668 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1669 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1670 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1671 */ 1672 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1673 { 1674 int i; 1675 1676 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1677 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1678 " is not aligned to %llu MiB", 1679 machine->ram_size, 1680 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1681 return; 1682 } 1683 1684 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1685 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1686 " is not aligned to %llu MiB", 1687 machine->ram_size, 1688 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1689 return; 1690 } 1691 1692 for (i = 0; i < nb_numa_nodes; i++) { 1693 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1694 error_setg(errp, 1695 "Node %d memory size 0x%" PRIx64 1696 " is not aligned to %llu MiB", 1697 i, numa_info[i].node_mem, 1698 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1699 return; 1700 } 1701 } 1702 } 1703 1704 /* pSeries LPAR / sPAPR hardware init */ 1705 static void ppc_spapr_init(MachineState *machine) 1706 { 1707 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1708 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1709 const char *kernel_filename = machine->kernel_filename; 1710 const char *kernel_cmdline = machine->kernel_cmdline; 1711 const char *initrd_filename = machine->initrd_filename; 1712 PCIHostState *phb; 1713 int i; 1714 MemoryRegion *sysmem = get_system_memory(); 1715 MemoryRegion *ram = g_new(MemoryRegion, 1); 1716 MemoryRegion *rma_region; 1717 void *rma = NULL; 1718 hwaddr rma_alloc_size; 1719 hwaddr node0_size = spapr_node0_size(); 1720 uint32_t initrd_base = 0; 1721 long kernel_size = 0, initrd_size = 0; 1722 long load_limit, fw_size; 1723 bool kernel_le = false; 1724 char *filename; 1725 int smt = kvmppc_smt_threads(); 1726 int spapr_cores = smp_cpus / smp_threads; 1727 int spapr_max_cores = max_cpus / smp_threads; 1728 1729 if (smc->dr_cpu_enabled) { 1730 if (smp_cpus % smp_threads) { 1731 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1732 smp_cpus, smp_threads); 1733 exit(1); 1734 } 1735 if (max_cpus % smp_threads) { 1736 error_report("max_cpus (%u) must be multiple of threads (%u)", 1737 max_cpus, smp_threads); 1738 exit(1); 1739 } 1740 } 1741 1742 msi_nonbroken = true; 1743 1744 QLIST_INIT(&spapr->phbs); 1745 1746 cpu_ppc_hypercall = emulate_spapr_hypercall; 1747 1748 /* Allocate RMA if necessary */ 1749 rma_alloc_size = kvmppc_alloc_rma(&rma); 1750 1751 if (rma_alloc_size == -1) { 1752 error_report("Unable to create RMA"); 1753 exit(1); 1754 } 1755 1756 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1757 spapr->rma_size = rma_alloc_size; 1758 } else { 1759 spapr->rma_size = node0_size; 1760 1761 /* With KVM, we don't actually know whether KVM supports an 1762 * unbounded RMA (PR KVM) or is limited by the hash table size 1763 * (HV KVM using VRMA), so we always assume the latter 1764 * 1765 * In that case, we also limit the initial allocations for RTAS 1766 * etc... to 256M since we have no way to know what the VRMA size 1767 * is going to be as it depends on the size of the hash table 1768 * isn't determined yet. 1769 */ 1770 if (kvm_enabled()) { 1771 spapr->vrma_adjust = 1; 1772 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1773 } 1774 1775 /* Actually we don't support unbounded RMA anymore since we 1776 * added proper emulation of HV mode. The max we can get is 1777 * 16G which also happens to be what we configure for PAPR 1778 * mode so make sure we don't do anything bigger than that 1779 */ 1780 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1781 } 1782 1783 if (spapr->rma_size > node0_size) { 1784 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1785 spapr->rma_size); 1786 exit(1); 1787 } 1788 1789 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1790 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1791 1792 /* Set up Interrupt Controller before we create the VCPUs */ 1793 spapr->xics = xics_system_init(machine, 1794 DIV_ROUND_UP(max_cpus * smt, smp_threads), 1795 XICS_IRQS_SPAPR, &error_fatal); 1796 1797 if (smc->dr_lmb_enabled) { 1798 spapr_validate_node_memory(machine, &error_fatal); 1799 } 1800 1801 /* init CPUs */ 1802 if (machine->cpu_model == NULL) { 1803 machine->cpu_model = kvm_enabled() ? "host" : "POWER7"; 1804 } 1805 1806 if (smc->dr_cpu_enabled) { 1807 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1808 1809 spapr->cores = g_new0(Object *, spapr_max_cores); 1810 for (i = 0; i < spapr_max_cores; i++) { 1811 int core_dt_id = i * smt; 1812 sPAPRDRConnector *drc = 1813 spapr_dr_connector_new(OBJECT(spapr), 1814 SPAPR_DR_CONNECTOR_TYPE_CPU, core_dt_id); 1815 1816 qemu_register_reset(spapr_drc_reset, drc); 1817 1818 if (i < spapr_cores) { 1819 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1820 Object *core; 1821 1822 if (!object_class_by_name(type)) { 1823 error_report("Unable to find sPAPR CPU Core definition"); 1824 exit(1); 1825 } 1826 1827 core = object_new(type); 1828 object_property_set_int(core, smp_threads, "nr-threads", 1829 &error_fatal); 1830 object_property_set_int(core, core_dt_id, CPU_CORE_PROP_CORE_ID, 1831 &error_fatal); 1832 object_property_set_bool(core, true, "realized", &error_fatal); 1833 } 1834 } 1835 g_free(type); 1836 } else { 1837 for (i = 0; i < smp_cpus; i++) { 1838 PowerPCCPU *cpu = cpu_ppc_init(machine->cpu_model); 1839 if (cpu == NULL) { 1840 error_report("Unable to find PowerPC CPU definition"); 1841 exit(1); 1842 } 1843 spapr_cpu_init(spapr, cpu, &error_fatal); 1844 } 1845 } 1846 1847 if (kvm_enabled()) { 1848 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1849 kvmppc_enable_logical_ci_hcalls(); 1850 kvmppc_enable_set_mode_hcall(); 1851 } 1852 1853 /* allocate RAM */ 1854 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1855 machine->ram_size); 1856 memory_region_add_subregion(sysmem, 0, ram); 1857 1858 if (rma_alloc_size && rma) { 1859 rma_region = g_new(MemoryRegion, 1); 1860 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1861 rma_alloc_size, rma); 1862 vmstate_register_ram_global(rma_region); 1863 memory_region_add_subregion(sysmem, 0, rma_region); 1864 } 1865 1866 /* initialize hotplug memory address space */ 1867 if (machine->ram_size < machine->maxram_size) { 1868 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1869 /* 1870 * Limit the number of hotpluggable memory slots to half the number 1871 * slots that KVM supports, leaving the other half for PCI and other 1872 * devices. However ensure that number of slots doesn't drop below 32. 1873 */ 1874 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 1875 SPAPR_MAX_RAM_SLOTS; 1876 1877 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 1878 max_memslots = SPAPR_MAX_RAM_SLOTS; 1879 } 1880 if (machine->ram_slots > max_memslots) { 1881 error_report("Specified number of memory slots %" 1882 PRIu64" exceeds max supported %d", 1883 machine->ram_slots, max_memslots); 1884 exit(1); 1885 } 1886 1887 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1888 SPAPR_HOTPLUG_MEM_ALIGN); 1889 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1890 "hotplug-memory", hotplug_mem_size); 1891 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1892 &spapr->hotplug_memory.mr); 1893 } 1894 1895 if (smc->dr_lmb_enabled) { 1896 spapr_create_lmb_dr_connectors(spapr); 1897 } 1898 1899 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1900 if (!filename) { 1901 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1902 exit(1); 1903 } 1904 spapr->rtas_size = get_image_size(filename); 1905 if (spapr->rtas_size < 0) { 1906 error_report("Could not get size of LPAR rtas '%s'", filename); 1907 exit(1); 1908 } 1909 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1910 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1911 error_report("Could not load LPAR rtas '%s'", filename); 1912 exit(1); 1913 } 1914 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1915 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1916 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1917 exit(1); 1918 } 1919 g_free(filename); 1920 1921 /* Set up EPOW events infrastructure */ 1922 spapr_events_init(spapr); 1923 1924 /* Set up the RTC RTAS interfaces */ 1925 spapr_rtc_create(spapr); 1926 1927 /* Set up VIO bus */ 1928 spapr->vio_bus = spapr_vio_bus_init(); 1929 1930 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 1931 if (serial_hds[i]) { 1932 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 1933 } 1934 } 1935 1936 /* We always have at least the nvram device on VIO */ 1937 spapr_create_nvram(spapr); 1938 1939 /* Set up PCI */ 1940 spapr_pci_rtas_init(); 1941 1942 phb = spapr_create_phb(spapr, 0); 1943 1944 for (i = 0; i < nb_nics; i++) { 1945 NICInfo *nd = &nd_table[i]; 1946 1947 if (!nd->model) { 1948 nd->model = g_strdup("ibmveth"); 1949 } 1950 1951 if (strcmp(nd->model, "ibmveth") == 0) { 1952 spapr_vlan_create(spapr->vio_bus, nd); 1953 } else { 1954 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 1955 } 1956 } 1957 1958 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 1959 spapr_vscsi_create(spapr->vio_bus); 1960 } 1961 1962 /* Graphics */ 1963 if (spapr_vga_init(phb->bus, &error_fatal)) { 1964 spapr->has_graphics = true; 1965 machine->usb |= defaults_enabled() && !machine->usb_disabled; 1966 } 1967 1968 if (machine->usb) { 1969 if (smc->use_ohci_by_default) { 1970 pci_create_simple(phb->bus, -1, "pci-ohci"); 1971 } else { 1972 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 1973 } 1974 1975 if (spapr->has_graphics) { 1976 USBBus *usb_bus = usb_bus_find(-1); 1977 1978 usb_create_simple(usb_bus, "usb-kbd"); 1979 usb_create_simple(usb_bus, "usb-mouse"); 1980 } 1981 } 1982 1983 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 1984 error_report( 1985 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 1986 MIN_RMA_SLOF); 1987 exit(1); 1988 } 1989 1990 if (kernel_filename) { 1991 uint64_t lowaddr = 0; 1992 1993 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, 1994 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE, 1995 0, 0); 1996 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) { 1997 kernel_size = load_elf(kernel_filename, 1998 translate_kernel_address, NULL, 1999 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2000 0, 0); 2001 kernel_le = kernel_size > 0; 2002 } 2003 if (kernel_size < 0) { 2004 error_report("error loading %s: %s", 2005 kernel_filename, load_elf_strerror(kernel_size)); 2006 exit(1); 2007 } 2008 2009 /* load initrd */ 2010 if (initrd_filename) { 2011 /* Try to locate the initrd in the gap between the kernel 2012 * and the firmware. Add a bit of space just in case 2013 */ 2014 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff; 2015 initrd_size = load_image_targphys(initrd_filename, initrd_base, 2016 load_limit - initrd_base); 2017 if (initrd_size < 0) { 2018 error_report("could not load initial ram disk '%s'", 2019 initrd_filename); 2020 exit(1); 2021 } 2022 } else { 2023 initrd_base = 0; 2024 initrd_size = 0; 2025 } 2026 } 2027 2028 if (bios_name == NULL) { 2029 bios_name = FW_FILE_NAME; 2030 } 2031 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2032 if (!filename) { 2033 error_report("Could not find LPAR firmware '%s'", bios_name); 2034 exit(1); 2035 } 2036 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2037 if (fw_size <= 0) { 2038 error_report("Could not load LPAR firmware '%s'", filename); 2039 exit(1); 2040 } 2041 g_free(filename); 2042 2043 /* FIXME: Should register things through the MachineState's qdev 2044 * interface, this is a legacy from the sPAPREnvironment structure 2045 * which predated MachineState but had a similar function */ 2046 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2047 register_savevm_live(NULL, "spapr/htab", -1, 1, 2048 &savevm_htab_handlers, spapr); 2049 2050 /* Prepare the device tree */ 2051 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size, 2052 kernel_size, kernel_le, 2053 kernel_cmdline, 2054 spapr->check_exception_irq); 2055 assert(spapr->fdt_skel != NULL); 2056 2057 /* used by RTAS */ 2058 QTAILQ_INIT(&spapr->ccs_list); 2059 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2060 2061 qemu_register_boot_set(spapr_boot_set, spapr); 2062 } 2063 2064 static int spapr_kvm_type(const char *vm_type) 2065 { 2066 if (!vm_type) { 2067 return 0; 2068 } 2069 2070 if (!strcmp(vm_type, "HV")) { 2071 return 1; 2072 } 2073 2074 if (!strcmp(vm_type, "PR")) { 2075 return 2; 2076 } 2077 2078 error_report("Unknown kvm-type specified '%s'", vm_type); 2079 exit(1); 2080 } 2081 2082 /* 2083 * Implementation of an interface to adjust firmware path 2084 * for the bootindex property handling. 2085 */ 2086 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2087 DeviceState *dev) 2088 { 2089 #define CAST(type, obj, name) \ 2090 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2091 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2092 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2093 2094 if (d) { 2095 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2096 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2097 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2098 2099 if (spapr) { 2100 /* 2101 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2102 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2103 * in the top 16 bits of the 64-bit LUN 2104 */ 2105 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2106 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2107 (uint64_t)id << 48); 2108 } else if (virtio) { 2109 /* 2110 * We use SRP luns of the form 01000000 | (target << 8) | lun 2111 * in the top 32 bits of the 64-bit LUN 2112 * Note: the quote above is from SLOF and it is wrong, 2113 * the actual binding is: 2114 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2115 */ 2116 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2117 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2118 (uint64_t)id << 32); 2119 } else if (usb) { 2120 /* 2121 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2122 * in the top 32 bits of the 64-bit LUN 2123 */ 2124 unsigned usb_port = atoi(usb->port->path); 2125 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2126 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2127 (uint64_t)id << 32); 2128 } 2129 } 2130 2131 if (phb) { 2132 /* Replace "pci" with "pci@800000020000000" */ 2133 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2134 } 2135 2136 return NULL; 2137 } 2138 2139 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2140 { 2141 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2142 2143 return g_strdup(spapr->kvm_type); 2144 } 2145 2146 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2147 { 2148 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2149 2150 g_free(spapr->kvm_type); 2151 spapr->kvm_type = g_strdup(value); 2152 } 2153 2154 static void spapr_machine_initfn(Object *obj) 2155 { 2156 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2157 2158 spapr->htab_fd = -1; 2159 object_property_add_str(obj, "kvm-type", 2160 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2161 object_property_set_description(obj, "kvm-type", 2162 "Specifies the KVM virtualization mode (HV, PR)", 2163 NULL); 2164 } 2165 2166 static void spapr_machine_finalizefn(Object *obj) 2167 { 2168 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2169 2170 g_free(spapr->kvm_type); 2171 } 2172 2173 static void ppc_cpu_do_nmi_on_cpu(void *arg) 2174 { 2175 CPUState *cs = arg; 2176 2177 cpu_synchronize_state(cs); 2178 ppc_cpu_do_system_reset(cs); 2179 } 2180 2181 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2182 { 2183 CPUState *cs; 2184 2185 CPU_FOREACH(cs) { 2186 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs); 2187 } 2188 } 2189 2190 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size, 2191 uint32_t node, Error **errp) 2192 { 2193 sPAPRDRConnector *drc; 2194 sPAPRDRConnectorClass *drck; 2195 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2196 int i, fdt_offset, fdt_size; 2197 void *fdt; 2198 2199 for (i = 0; i < nr_lmbs; i++) { 2200 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2201 addr/SPAPR_MEMORY_BLOCK_SIZE); 2202 g_assert(drc); 2203 2204 fdt = create_device_tree(&fdt_size); 2205 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2206 SPAPR_MEMORY_BLOCK_SIZE); 2207 2208 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2209 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2210 addr += SPAPR_MEMORY_BLOCK_SIZE; 2211 } 2212 /* send hotplug notification to the 2213 * guest only in case of hotplugged memory 2214 */ 2215 if (dev->hotplugged) { 2216 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs); 2217 } 2218 } 2219 2220 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2221 uint32_t node, Error **errp) 2222 { 2223 Error *local_err = NULL; 2224 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2225 PCDIMMDevice *dimm = PC_DIMM(dev); 2226 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2227 MemoryRegion *mr = ddc->get_memory_region(dimm); 2228 uint64_t align = memory_region_get_alignment(mr); 2229 uint64_t size = memory_region_size(mr); 2230 uint64_t addr; 2231 2232 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2233 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2234 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2235 goto out; 2236 } 2237 2238 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2239 if (local_err) { 2240 goto out; 2241 } 2242 2243 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2244 if (local_err) { 2245 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2246 goto out; 2247 } 2248 2249 spapr_add_lmbs(dev, addr, size, node, &error_abort); 2250 2251 out: 2252 error_propagate(errp, local_err); 2253 } 2254 2255 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2256 sPAPRMachineState *spapr) 2257 { 2258 PowerPCCPU *cpu = POWERPC_CPU(cs); 2259 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2260 int id = ppc_get_vcpu_dt_id(cpu); 2261 void *fdt; 2262 int offset, fdt_size; 2263 char *nodename; 2264 2265 fdt = create_device_tree(&fdt_size); 2266 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2267 offset = fdt_add_subnode(fdt, 0, nodename); 2268 2269 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2270 g_free(nodename); 2271 2272 *fdt_offset = offset; 2273 return fdt; 2274 } 2275 2276 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2277 DeviceState *dev, Error **errp) 2278 { 2279 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2280 2281 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2282 int node; 2283 2284 if (!smc->dr_lmb_enabled) { 2285 error_setg(errp, "Memory hotplug not supported for this machine"); 2286 return; 2287 } 2288 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2289 if (*errp) { 2290 return; 2291 } 2292 if (node < 0 || node >= MAX_NODES) { 2293 error_setg(errp, "Invaild node %d", node); 2294 return; 2295 } 2296 2297 /* 2298 * Currently PowerPC kernel doesn't allow hot-adding memory to 2299 * memory-less node, but instead will silently add the memory 2300 * to the first node that has some memory. This causes two 2301 * unexpected behaviours for the user. 2302 * 2303 * - Memory gets hotplugged to a different node than what the user 2304 * specified. 2305 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2306 * to memory-less node, a reboot will set things accordingly 2307 * and the previously hotplugged memory now ends in the right node. 2308 * This appears as if some memory moved from one node to another. 2309 * 2310 * So until kernel starts supporting memory hotplug to memory-less 2311 * nodes, just prevent such attempts upfront in QEMU. 2312 */ 2313 if (nb_numa_nodes && !numa_info[node].node_mem) { 2314 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2315 node); 2316 return; 2317 } 2318 2319 spapr_memory_plug(hotplug_dev, dev, node, errp); 2320 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2321 spapr_core_plug(hotplug_dev, dev, errp); 2322 } 2323 } 2324 2325 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2326 DeviceState *dev, Error **errp) 2327 { 2328 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2329 2330 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2331 error_setg(errp, "Memory hot unplug not supported by sPAPR"); 2332 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2333 if (!smc->dr_cpu_enabled) { 2334 error_setg(errp, "CPU hot unplug not supported on this machine"); 2335 return; 2336 } 2337 spapr_core_unplug(hotplug_dev, dev, errp); 2338 } 2339 } 2340 2341 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2342 DeviceState *dev, Error **errp) 2343 { 2344 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2345 spapr_core_pre_plug(hotplug_dev, dev, errp); 2346 } 2347 } 2348 2349 static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine, 2350 DeviceState *dev) 2351 { 2352 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2353 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2354 return HOTPLUG_HANDLER(machine); 2355 } 2356 return NULL; 2357 } 2358 2359 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2360 { 2361 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2362 * socket means much for the paravirtualized PAPR platform) */ 2363 return cpu_index / smp_threads / smp_cores; 2364 } 2365 2366 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) 2367 { 2368 int i; 2369 HotpluggableCPUList *head = NULL; 2370 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2371 int spapr_max_cores = max_cpus / smp_threads; 2372 int smt = kvmppc_smt_threads(); 2373 2374 for (i = 0; i < spapr_max_cores; i++) { 2375 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); 2376 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 2377 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); 2378 2379 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); 2380 cpu_item->vcpus_count = smp_threads; 2381 cpu_props->has_core_id = true; 2382 cpu_props->core_id = i * smt; 2383 /* TODO: add 'has_node/node' here to describe 2384 to which node core belongs */ 2385 2386 cpu_item->props = cpu_props; 2387 if (spapr->cores[i]) { 2388 cpu_item->has_qom_path = true; 2389 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); 2390 } 2391 list_item->value = cpu_item; 2392 list_item->next = head; 2393 head = list_item; 2394 } 2395 return head; 2396 } 2397 2398 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2399 { 2400 MachineClass *mc = MACHINE_CLASS(oc); 2401 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2402 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2403 NMIClass *nc = NMI_CLASS(oc); 2404 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2405 2406 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2407 2408 /* 2409 * We set up the default / latest behaviour here. The class_init 2410 * functions for the specific versioned machine types can override 2411 * these details for backwards compatibility 2412 */ 2413 mc->init = ppc_spapr_init; 2414 mc->reset = ppc_spapr_reset; 2415 mc->block_default_type = IF_SCSI; 2416 mc->max_cpus = MAX_CPUMASK_BITS; 2417 mc->no_parallel = 1; 2418 mc->default_boot_order = ""; 2419 mc->default_ram_size = 512 * M_BYTE; 2420 mc->kvm_type = spapr_kvm_type; 2421 mc->has_dynamic_sysbus = true; 2422 mc->pci_allow_0_address = true; 2423 mc->get_hotplug_handler = spapr_get_hotpug_handler; 2424 hc->pre_plug = spapr_machine_device_pre_plug; 2425 hc->plug = spapr_machine_device_plug; 2426 hc->unplug = spapr_machine_device_unplug; 2427 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2428 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; 2429 2430 smc->dr_lmb_enabled = true; 2431 smc->dr_cpu_enabled = true; 2432 fwc->get_dev_path = spapr_get_fw_dev_path; 2433 nc->nmi_monitor_handler = spapr_nmi; 2434 } 2435 2436 static const TypeInfo spapr_machine_info = { 2437 .name = TYPE_SPAPR_MACHINE, 2438 .parent = TYPE_MACHINE, 2439 .abstract = true, 2440 .instance_size = sizeof(sPAPRMachineState), 2441 .instance_init = spapr_machine_initfn, 2442 .instance_finalize = spapr_machine_finalizefn, 2443 .class_size = sizeof(sPAPRMachineClass), 2444 .class_init = spapr_machine_class_init, 2445 .interfaces = (InterfaceInfo[]) { 2446 { TYPE_FW_PATH_PROVIDER }, 2447 { TYPE_NMI }, 2448 { TYPE_HOTPLUG_HANDLER }, 2449 { } 2450 }, 2451 }; 2452 2453 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2454 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2455 void *data) \ 2456 { \ 2457 MachineClass *mc = MACHINE_CLASS(oc); \ 2458 spapr_machine_##suffix##_class_options(mc); \ 2459 if (latest) { \ 2460 mc->alias = "pseries"; \ 2461 mc->is_default = 1; \ 2462 } \ 2463 } \ 2464 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2465 { \ 2466 MachineState *machine = MACHINE(obj); \ 2467 spapr_machine_##suffix##_instance_options(machine); \ 2468 } \ 2469 static const TypeInfo spapr_machine_##suffix##_info = { \ 2470 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2471 .parent = TYPE_SPAPR_MACHINE, \ 2472 .class_init = spapr_machine_##suffix##_class_init, \ 2473 .instance_init = spapr_machine_##suffix##_instance_init, \ 2474 }; \ 2475 static void spapr_machine_register_##suffix(void) \ 2476 { \ 2477 type_register(&spapr_machine_##suffix##_info); \ 2478 } \ 2479 type_init(spapr_machine_register_##suffix) 2480 2481 /* 2482 * pseries-2.7 2483 */ 2484 static void spapr_machine_2_7_instance_options(MachineState *machine) 2485 { 2486 } 2487 2488 static void spapr_machine_2_7_class_options(MachineClass *mc) 2489 { 2490 /* Defaults for the latest behaviour inherited from the base class */ 2491 } 2492 2493 DEFINE_SPAPR_MACHINE(2_7, "2.7", true); 2494 2495 /* 2496 * pseries-2.6 2497 */ 2498 #define SPAPR_COMPAT_2_6 \ 2499 HW_COMPAT_2_6 \ 2500 { \ 2501 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2502 .property = "ddw",\ 2503 .value = stringify(off),\ 2504 }, 2505 2506 static void spapr_machine_2_6_instance_options(MachineState *machine) 2507 { 2508 } 2509 2510 static void spapr_machine_2_6_class_options(MachineClass *mc) 2511 { 2512 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2513 2514 spapr_machine_2_7_class_options(mc); 2515 smc->dr_cpu_enabled = false; 2516 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 2517 } 2518 2519 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 2520 2521 /* 2522 * pseries-2.5 2523 */ 2524 #define SPAPR_COMPAT_2_5 \ 2525 HW_COMPAT_2_5 \ 2526 { \ 2527 .driver = "spapr-vlan", \ 2528 .property = "use-rx-buffer-pools", \ 2529 .value = "off", \ 2530 }, 2531 2532 static void spapr_machine_2_5_instance_options(MachineState *machine) 2533 { 2534 } 2535 2536 static void spapr_machine_2_5_class_options(MachineClass *mc) 2537 { 2538 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2539 2540 spapr_machine_2_6_class_options(mc); 2541 smc->use_ohci_by_default = true; 2542 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2543 } 2544 2545 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2546 2547 /* 2548 * pseries-2.4 2549 */ 2550 #define SPAPR_COMPAT_2_4 \ 2551 HW_COMPAT_2_4 2552 2553 static void spapr_machine_2_4_instance_options(MachineState *machine) 2554 { 2555 spapr_machine_2_5_instance_options(machine); 2556 } 2557 2558 static void spapr_machine_2_4_class_options(MachineClass *mc) 2559 { 2560 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2561 2562 spapr_machine_2_5_class_options(mc); 2563 smc->dr_lmb_enabled = false; 2564 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2565 } 2566 2567 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2568 2569 /* 2570 * pseries-2.3 2571 */ 2572 #define SPAPR_COMPAT_2_3 \ 2573 HW_COMPAT_2_3 \ 2574 {\ 2575 .driver = "spapr-pci-host-bridge",\ 2576 .property = "dynamic-reconfiguration",\ 2577 .value = "off",\ 2578 }, 2579 2580 static void spapr_machine_2_3_instance_options(MachineState *machine) 2581 { 2582 spapr_machine_2_4_instance_options(machine); 2583 savevm_skip_section_footers(); 2584 global_state_set_optional(); 2585 savevm_skip_configuration(); 2586 } 2587 2588 static void spapr_machine_2_3_class_options(MachineClass *mc) 2589 { 2590 spapr_machine_2_4_class_options(mc); 2591 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 2592 } 2593 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 2594 2595 /* 2596 * pseries-2.2 2597 */ 2598 2599 #define SPAPR_COMPAT_2_2 \ 2600 HW_COMPAT_2_2 \ 2601 {\ 2602 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2603 .property = "mem_win_size",\ 2604 .value = "0x20000000",\ 2605 }, 2606 2607 static void spapr_machine_2_2_instance_options(MachineState *machine) 2608 { 2609 spapr_machine_2_3_instance_options(machine); 2610 machine->suppress_vmdesc = true; 2611 } 2612 2613 static void spapr_machine_2_2_class_options(MachineClass *mc) 2614 { 2615 spapr_machine_2_3_class_options(mc); 2616 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 2617 } 2618 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 2619 2620 /* 2621 * pseries-2.1 2622 */ 2623 #define SPAPR_COMPAT_2_1 \ 2624 HW_COMPAT_2_1 2625 2626 static void spapr_machine_2_1_instance_options(MachineState *machine) 2627 { 2628 spapr_machine_2_2_instance_options(machine); 2629 } 2630 2631 static void spapr_machine_2_1_class_options(MachineClass *mc) 2632 { 2633 spapr_machine_2_2_class_options(mc); 2634 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 2635 } 2636 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 2637 2638 static void spapr_machine_register_types(void) 2639 { 2640 type_register_static(&spapr_machine_info); 2641 } 2642 2643 type_init(spapr_machine_register_types) 2644