1 /* 2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator 3 * 4 * Copyright (c) 2004-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * Copyright (c) 2010 David Gibson, IBM Corporation. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 */ 27 #include "qemu/osdep.h" 28 #include "qapi/error.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/numa.h" 31 #include "hw/hw.h" 32 #include "qemu/log.h" 33 #include "hw/fw-path-provider.h" 34 #include "elf.h" 35 #include "net/net.h" 36 #include "sysemu/device_tree.h" 37 #include "sysemu/block-backend.h" 38 #include "sysemu/cpus.h" 39 #include "sysemu/hw_accel.h" 40 #include "kvm_ppc.h" 41 #include "migration/migration.h" 42 #include "mmu-hash64.h" 43 #include "qom/cpu.h" 44 45 #include "hw/boards.h" 46 #include "hw/ppc/ppc.h" 47 #include "hw/loader.h" 48 49 #include "hw/ppc/fdt.h" 50 #include "hw/ppc/spapr.h" 51 #include "hw/ppc/spapr_vio.h" 52 #include "hw/pci-host/spapr.h" 53 #include "hw/ppc/xics.h" 54 #include "hw/pci/msi.h" 55 56 #include "hw/pci/pci.h" 57 #include "hw/scsi/scsi.h" 58 #include "hw/virtio/virtio-scsi.h" 59 60 #include "exec/address-spaces.h" 61 #include "hw/usb.h" 62 #include "qemu/config-file.h" 63 #include "qemu/error-report.h" 64 #include "trace.h" 65 #include "hw/nmi.h" 66 67 #include "hw/compat.h" 68 #include "qemu/cutils.h" 69 #include "hw/ppc/spapr_cpu_core.h" 70 #include "qmp-commands.h" 71 72 #include <libfdt.h> 73 74 /* SLOF memory layout: 75 * 76 * SLOF raw image loaded at 0, copies its romfs right below the flat 77 * device-tree, then position SLOF itself 31M below that 78 * 79 * So we set FW_OVERHEAD to 40MB which should account for all of that 80 * and more 81 * 82 * We load our kernel at 4M, leaving space for SLOF initial image 83 */ 84 #define FDT_MAX_SIZE 0x100000 85 #define RTAS_MAX_SIZE 0x10000 86 #define RTAS_MAX_ADDR 0x80000000 /* RTAS must stay below that */ 87 #define FW_MAX_SIZE 0x400000 88 #define FW_FILE_NAME "slof.bin" 89 #define FW_OVERHEAD 0x2800000 90 #define KERNEL_LOAD_ADDR FW_MAX_SIZE 91 92 #define MIN_RMA_SLOF 128UL 93 94 #define PHANDLE_XICP 0x00001111 95 96 #define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift)) 97 98 static XICSState *try_create_xics(const char *type, int nr_servers, 99 int nr_irqs, Error **errp) 100 { 101 Error *err = NULL; 102 DeviceState *dev; 103 104 dev = qdev_create(NULL, type); 105 qdev_prop_set_uint32(dev, "nr_servers", nr_servers); 106 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs); 107 object_property_set_bool(OBJECT(dev), true, "realized", &err); 108 if (err) { 109 error_propagate(errp, err); 110 object_unparent(OBJECT(dev)); 111 return NULL; 112 } 113 return XICS_COMMON(dev); 114 } 115 116 static XICSState *xics_system_init(MachineState *machine, 117 int nr_servers, int nr_irqs, Error **errp) 118 { 119 XICSState *xics = NULL; 120 121 if (kvm_enabled()) { 122 Error *err = NULL; 123 124 if (machine_kernel_irqchip_allowed(machine)) { 125 xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs, 126 &err); 127 } 128 if (machine_kernel_irqchip_required(machine) && !xics) { 129 error_reportf_err(err, 130 "kernel_irqchip requested but unavailable: "); 131 } else { 132 error_free(err); 133 } 134 } 135 136 if (!xics) { 137 xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp); 138 } 139 140 return xics; 141 } 142 143 static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu, 144 int smt_threads) 145 { 146 int i, ret = 0; 147 uint32_t servers_prop[smt_threads]; 148 uint32_t gservers_prop[smt_threads * 2]; 149 int index = ppc_get_vcpu_dt_id(cpu); 150 151 if (cpu->compat_pvr) { 152 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->compat_pvr); 153 if (ret < 0) { 154 return ret; 155 } 156 } 157 158 /* Build interrupt servers and gservers properties */ 159 for (i = 0; i < smt_threads; i++) { 160 servers_prop[i] = cpu_to_be32(index + i); 161 /* Hack, direct the group queues back to cpu 0 */ 162 gservers_prop[i*2] = cpu_to_be32(index + i); 163 gservers_prop[i*2 + 1] = 0; 164 } 165 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 166 servers_prop, sizeof(servers_prop)); 167 if (ret < 0) { 168 return ret; 169 } 170 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s", 171 gservers_prop, sizeof(gservers_prop)); 172 173 return ret; 174 } 175 176 static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs) 177 { 178 int ret = 0; 179 PowerPCCPU *cpu = POWERPC_CPU(cs); 180 int index = ppc_get_vcpu_dt_id(cpu); 181 uint32_t associativity[] = {cpu_to_be32(0x5), 182 cpu_to_be32(0x0), 183 cpu_to_be32(0x0), 184 cpu_to_be32(0x0), 185 cpu_to_be32(cs->numa_node), 186 cpu_to_be32(index)}; 187 188 /* Advertise NUMA via ibm,associativity */ 189 if (nb_numa_nodes > 1) { 190 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity, 191 sizeof(associativity)); 192 } 193 194 return ret; 195 } 196 197 static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr) 198 { 199 int ret = 0, offset, cpus_offset; 200 CPUState *cs; 201 char cpu_model[32]; 202 int smt = kvmppc_smt_threads(); 203 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 204 205 CPU_FOREACH(cs) { 206 PowerPCCPU *cpu = POWERPC_CPU(cs); 207 DeviceClass *dc = DEVICE_GET_CLASS(cs); 208 int index = ppc_get_vcpu_dt_id(cpu); 209 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 210 211 if ((index % smt) != 0) { 212 continue; 213 } 214 215 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index); 216 217 cpus_offset = fdt_path_offset(fdt, "/cpus"); 218 if (cpus_offset < 0) { 219 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 220 "cpus"); 221 if (cpus_offset < 0) { 222 return cpus_offset; 223 } 224 } 225 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model); 226 if (offset < 0) { 227 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model); 228 if (offset < 0) { 229 return offset; 230 } 231 } 232 233 ret = fdt_setprop(fdt, offset, "ibm,pft-size", 234 pft_size_prop, sizeof(pft_size_prop)); 235 if (ret < 0) { 236 return ret; 237 } 238 239 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs); 240 if (ret < 0) { 241 return ret; 242 } 243 244 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt); 245 if (ret < 0) { 246 return ret; 247 } 248 } 249 return ret; 250 } 251 252 static hwaddr spapr_node0_size(void) 253 { 254 MachineState *machine = MACHINE(qdev_get_machine()); 255 256 if (nb_numa_nodes) { 257 int i; 258 for (i = 0; i < nb_numa_nodes; ++i) { 259 if (numa_info[i].node_mem) { 260 return MIN(pow2floor(numa_info[i].node_mem), 261 machine->ram_size); 262 } 263 } 264 } 265 return machine->ram_size; 266 } 267 268 static void add_str(GString *s, const gchar *s1) 269 { 270 g_string_append_len(s, s1, strlen(s1) + 1); 271 } 272 273 static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, 274 hwaddr size) 275 { 276 uint32_t associativity[] = { 277 cpu_to_be32(0x4), /* length */ 278 cpu_to_be32(0x0), cpu_to_be32(0x0), 279 cpu_to_be32(0x0), cpu_to_be32(nodeid) 280 }; 281 char mem_name[32]; 282 uint64_t mem_reg_property[2]; 283 int off; 284 285 mem_reg_property[0] = cpu_to_be64(start); 286 mem_reg_property[1] = cpu_to_be64(size); 287 288 sprintf(mem_name, "memory@" TARGET_FMT_lx, start); 289 off = fdt_add_subnode(fdt, 0, mem_name); 290 _FDT(off); 291 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 292 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 293 sizeof(mem_reg_property)))); 294 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity, 295 sizeof(associativity)))); 296 return off; 297 } 298 299 static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt) 300 { 301 MachineState *machine = MACHINE(spapr); 302 hwaddr mem_start, node_size; 303 int i, nb_nodes = nb_numa_nodes; 304 NodeInfo *nodes = numa_info; 305 NodeInfo ramnode; 306 307 /* No NUMA nodes, assume there is just one node with whole RAM */ 308 if (!nb_numa_nodes) { 309 nb_nodes = 1; 310 ramnode.node_mem = machine->ram_size; 311 nodes = &ramnode; 312 } 313 314 for (i = 0, mem_start = 0; i < nb_nodes; ++i) { 315 if (!nodes[i].node_mem) { 316 continue; 317 } 318 if (mem_start >= machine->ram_size) { 319 node_size = 0; 320 } else { 321 node_size = nodes[i].node_mem; 322 if (node_size > machine->ram_size - mem_start) { 323 node_size = machine->ram_size - mem_start; 324 } 325 } 326 if (!mem_start) { 327 /* ppc_spapr_init() checks for rma_size <= node0_size already */ 328 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); 329 mem_start += spapr->rma_size; 330 node_size -= spapr->rma_size; 331 } 332 for ( ; node_size; ) { 333 hwaddr sizetmp = pow2floor(node_size); 334 335 /* mem_start != 0 here */ 336 if (ctzl(mem_start) < ctzl(sizetmp)) { 337 sizetmp = 1ULL << ctzl(mem_start); 338 } 339 340 spapr_populate_memory_node(fdt, i, mem_start, sizetmp); 341 node_size -= sizetmp; 342 mem_start += sizetmp; 343 } 344 } 345 346 return 0; 347 } 348 349 /* Populate the "ibm,pa-features" property */ 350 static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset) 351 { 352 uint8_t pa_features_206[] = { 6, 0, 353 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; 354 uint8_t pa_features_207[] = { 24, 0, 355 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, 356 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 357 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 358 0x80, 0x00, 0x80, 0x00, 0x00, 0x00 }; 359 uint8_t *pa_features; 360 size_t pa_size; 361 362 switch (env->mmu_model) { 363 case POWERPC_MMU_2_06: 364 case POWERPC_MMU_2_06a: 365 pa_features = pa_features_206; 366 pa_size = sizeof(pa_features_206); 367 break; 368 case POWERPC_MMU_2_07: 369 case POWERPC_MMU_2_07a: 370 pa_features = pa_features_207; 371 pa_size = sizeof(pa_features_207); 372 break; 373 default: 374 return; 375 } 376 377 if (env->ci_large_pages) { 378 /* 379 * Note: we keep CI large pages off by default because a 64K capable 380 * guest provisioned with large pages might otherwise try to map a qemu 381 * framebuffer (or other kind of memory mapped PCI BAR) using 64K pages 382 * even if that qemu runs on a 4k host. 383 * We dd this bit back here if we are confident this is not an issue 384 */ 385 pa_features[3] |= 0x20; 386 } 387 if (kvmppc_has_cap_htm() && pa_size > 24) { 388 pa_features[24] |= 0x80; /* Transactional memory support */ 389 } 390 391 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size))); 392 } 393 394 static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, 395 sPAPRMachineState *spapr) 396 { 397 PowerPCCPU *cpu = POWERPC_CPU(cs); 398 CPUPPCState *env = &cpu->env; 399 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 400 int index = ppc_get_vcpu_dt_id(cpu); 401 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 402 0xffffffff, 0xffffffff}; 403 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() 404 : SPAPR_TIMEBASE_FREQ; 405 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000; 406 uint32_t page_sizes_prop[64]; 407 size_t page_sizes_prop_size; 408 uint32_t vcpus_per_socket = smp_threads * smp_cores; 409 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)}; 410 int compat_smt = MIN(smp_threads, ppc_compat_max_threads(cpu)); 411 sPAPRDRConnector *drc; 412 sPAPRDRConnectorClass *drck; 413 int drc_index; 414 415 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_CPU, index); 416 if (drc) { 417 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 418 drc_index = drck->get_index(drc); 419 _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index))); 420 } 421 422 _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); 423 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 424 425 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 426 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 427 env->dcache_line_size))); 428 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 429 env->dcache_line_size))); 430 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 431 env->icache_line_size))); 432 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 433 env->icache_line_size))); 434 435 if (pcc->l1_dcache_size) { 436 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 437 pcc->l1_dcache_size))); 438 } else { 439 error_report("Warning: Unknown L1 dcache size for cpu"); 440 } 441 if (pcc->l1_icache_size) { 442 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 443 pcc->l1_icache_size))); 444 } else { 445 error_report("Warning: Unknown L1 icache size for cpu"); 446 } 447 448 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 449 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 450 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr))); 451 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 452 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 453 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 454 455 if (env->spr_cb[SPR_PURR].oea_read) { 456 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 457 } 458 459 if (env->mmu_model & POWERPC_MMU_1TSEG) { 460 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 461 segs, sizeof(segs)))); 462 } 463 464 /* Advertise VMX/VSX (vector extensions) if available 465 * 0 / no property == no vector extensions 466 * 1 == VMX / Altivec available 467 * 2 == VSX available */ 468 if (env->insns_flags & PPC_ALTIVEC) { 469 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 470 471 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 472 } 473 474 /* Advertise DFP (Decimal Floating Point) if available 475 * 0 / no property == no DFP 476 * 1 == DFP available */ 477 if (env->insns_flags2 & PPC2_DFP) { 478 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 479 } 480 481 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 482 sizeof(page_sizes_prop)); 483 if (page_sizes_prop_size) { 484 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 485 page_sizes_prop, page_sizes_prop_size))); 486 } 487 488 spapr_populate_pa_features(env, fdt, offset); 489 490 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", 491 cs->cpu_index / vcpus_per_socket))); 492 493 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", 494 pft_size_prop, sizeof(pft_size_prop)))); 495 496 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs)); 497 498 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); 499 } 500 501 static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr) 502 { 503 CPUState *cs; 504 int cpus_offset; 505 char *nodename; 506 int smt = kvmppc_smt_threads(); 507 508 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 509 _FDT(cpus_offset); 510 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 511 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 512 513 /* 514 * We walk the CPUs in reverse order to ensure that CPU DT nodes 515 * created by fdt_add_subnode() end up in the right order in FDT 516 * for the guest kernel the enumerate the CPUs correctly. 517 */ 518 CPU_FOREACH_REVERSE(cs) { 519 PowerPCCPU *cpu = POWERPC_CPU(cs); 520 int index = ppc_get_vcpu_dt_id(cpu); 521 DeviceClass *dc = DEVICE_GET_CLASS(cs); 522 int offset; 523 524 if ((index % smt) != 0) { 525 continue; 526 } 527 528 nodename = g_strdup_printf("%s@%x", dc->fw_name, index); 529 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 530 g_free(nodename); 531 _FDT(offset); 532 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 533 } 534 535 } 536 537 /* 538 * Adds ibm,dynamic-reconfiguration-memory node. 539 * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation 540 * of this device tree node. 541 */ 542 static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt) 543 { 544 MachineState *machine = MACHINE(spapr); 545 int ret, i, offset; 546 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 547 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)}; 548 uint32_t hotplug_lmb_start = spapr->hotplug_memory.base / lmb_size; 549 uint32_t nr_lmbs = (spapr->hotplug_memory.base + 550 memory_region_size(&spapr->hotplug_memory.mr)) / 551 lmb_size; 552 uint32_t *int_buf, *cur_index, buf_len; 553 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 554 555 /* 556 * Don't create the node if there is no hotpluggable memory 557 */ 558 if (machine->ram_size == machine->maxram_size) { 559 return 0; 560 } 561 562 /* 563 * Allocate enough buffer size to fit in ibm,dynamic-memory 564 * or ibm,associativity-lookup-arrays 565 */ 566 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2) 567 * sizeof(uint32_t); 568 cur_index = int_buf = g_malloc0(buf_len); 569 570 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory"); 571 572 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size, 573 sizeof(prop_lmb_size)); 574 if (ret < 0) { 575 goto out; 576 } 577 578 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff); 579 if (ret < 0) { 580 goto out; 581 } 582 583 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0); 584 if (ret < 0) { 585 goto out; 586 } 587 588 /* ibm,dynamic-memory */ 589 int_buf[0] = cpu_to_be32(nr_lmbs); 590 cur_index++; 591 for (i = 0; i < nr_lmbs; i++) { 592 uint64_t addr = i * lmb_size; 593 uint32_t *dynamic_memory = cur_index; 594 595 if (i >= hotplug_lmb_start) { 596 sPAPRDRConnector *drc; 597 sPAPRDRConnectorClass *drck; 598 599 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, i); 600 g_assert(drc); 601 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 602 603 dynamic_memory[0] = cpu_to_be32(addr >> 32); 604 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 605 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc)); 606 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 607 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL)); 608 if (memory_region_present(get_system_memory(), addr)) { 609 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED); 610 } else { 611 dynamic_memory[5] = cpu_to_be32(0); 612 } 613 } else { 614 /* 615 * LMB information for RMA, boot time RAM and gap b/n RAM and 616 * hotplug memory region -- all these are marked as reserved 617 * and as having no valid DRC. 618 */ 619 dynamic_memory[0] = cpu_to_be32(addr >> 32); 620 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff); 621 dynamic_memory[2] = cpu_to_be32(0); 622 dynamic_memory[3] = cpu_to_be32(0); /* reserved */ 623 dynamic_memory[4] = cpu_to_be32(-1); 624 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_RESERVED | 625 SPAPR_LMB_FLAGS_DRC_INVALID); 626 } 627 628 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE; 629 } 630 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len); 631 if (ret < 0) { 632 goto out; 633 } 634 635 /* ibm,associativity-lookup-arrays */ 636 cur_index = int_buf; 637 int_buf[0] = cpu_to_be32(nr_nodes); 638 int_buf[1] = cpu_to_be32(4); /* Number of entries per associativity list */ 639 cur_index += 2; 640 for (i = 0; i < nr_nodes; i++) { 641 uint32_t associativity[] = { 642 cpu_to_be32(0x0), 643 cpu_to_be32(0x0), 644 cpu_to_be32(0x0), 645 cpu_to_be32(i) 646 }; 647 memcpy(cur_index, associativity, sizeof(associativity)); 648 cur_index += 4; 649 } 650 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 651 (cur_index - int_buf) * sizeof(uint32_t)); 652 out: 653 g_free(int_buf); 654 return ret; 655 } 656 657 static int spapr_dt_cas_updates(sPAPRMachineState *spapr, void *fdt, 658 sPAPROptionVector *ov5_updates) 659 { 660 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 661 int ret = 0, offset; 662 663 /* Generate ibm,dynamic-reconfiguration-memory node if required */ 664 if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { 665 g_assert(smc->dr_lmb_enabled); 666 ret = spapr_populate_drconf_memory(spapr, fdt); 667 if (ret) { 668 goto out; 669 } 670 } 671 672 offset = fdt_path_offset(fdt, "/chosen"); 673 if (offset < 0) { 674 offset = fdt_add_subnode(fdt, 0, "chosen"); 675 if (offset < 0) { 676 return offset; 677 } 678 } 679 ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, 680 "ibm,architecture-vec-5"); 681 682 out: 683 return ret; 684 } 685 686 int spapr_h_cas_compose_response(sPAPRMachineState *spapr, 687 target_ulong addr, target_ulong size, 688 sPAPROptionVector *ov5_updates) 689 { 690 void *fdt, *fdt_skel; 691 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 }; 692 693 size -= sizeof(hdr); 694 695 /* Create sceleton */ 696 fdt_skel = g_malloc0(size); 697 _FDT((fdt_create(fdt_skel, size))); 698 _FDT((fdt_begin_node(fdt_skel, ""))); 699 _FDT((fdt_end_node(fdt_skel))); 700 _FDT((fdt_finish(fdt_skel))); 701 fdt = g_malloc0(size); 702 _FDT((fdt_open_into(fdt_skel, fdt, size))); 703 g_free(fdt_skel); 704 705 /* Fixup cpu nodes */ 706 _FDT((spapr_fixup_cpu_dt(fdt, spapr))); 707 708 if (spapr_dt_cas_updates(spapr, fdt, ov5_updates)) { 709 return -1; 710 } 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 if (fdt_totalsize(fdt) + sizeof(hdr) > size) { 716 trace_spapr_cas_failed(size); 717 return -1; 718 } 719 720 cpu_physical_memory_write(addr, &hdr, sizeof(hdr)); 721 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt)); 722 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr)); 723 g_free(fdt); 724 725 return 0; 726 } 727 728 static void spapr_dt_rtas(sPAPRMachineState *spapr, void *fdt) 729 { 730 int rtas; 731 GString *hypertas = g_string_sized_new(256); 732 GString *qemu_hypertas = g_string_sized_new(256); 733 uint32_t refpoints[] = { cpu_to_be32(0x4), cpu_to_be32(0x4) }; 734 uint64_t max_hotplug_addr = spapr->hotplug_memory.base + 735 memory_region_size(&spapr->hotplug_memory.mr); 736 uint32_t lrdr_capacity[] = { 737 cpu_to_be32(max_hotplug_addr >> 32), 738 cpu_to_be32(max_hotplug_addr & 0xffffffff), 739 0, cpu_to_be32(SPAPR_MEMORY_BLOCK_SIZE), 740 cpu_to_be32(max_cpus / smp_threads), 741 }; 742 743 _FDT(rtas = fdt_add_subnode(fdt, 0, "rtas")); 744 745 /* hypertas */ 746 add_str(hypertas, "hcall-pft"); 747 add_str(hypertas, "hcall-term"); 748 add_str(hypertas, "hcall-dabr"); 749 add_str(hypertas, "hcall-interrupt"); 750 add_str(hypertas, "hcall-tce"); 751 add_str(hypertas, "hcall-vio"); 752 add_str(hypertas, "hcall-splpar"); 753 add_str(hypertas, "hcall-bulk"); 754 add_str(hypertas, "hcall-set-mode"); 755 add_str(hypertas, "hcall-sprg0"); 756 add_str(hypertas, "hcall-copy"); 757 add_str(hypertas, "hcall-debug"); 758 add_str(qemu_hypertas, "hcall-memop1"); 759 760 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) { 761 add_str(hypertas, "hcall-multi-tce"); 762 } 763 _FDT(fdt_setprop(fdt, rtas, "ibm,hypertas-functions", 764 hypertas->str, hypertas->len)); 765 g_string_free(hypertas, TRUE); 766 _FDT(fdt_setprop(fdt, rtas, "qemu,hypertas-functions", 767 qemu_hypertas->str, qemu_hypertas->len)); 768 g_string_free(qemu_hypertas, TRUE); 769 770 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 771 refpoints, sizeof(refpoints))); 772 773 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-error-log-max", 774 RTAS_ERROR_LOG_MAX)); 775 _FDT(fdt_setprop_cell(fdt, rtas, "rtas-event-scan-rate", 776 RTAS_EVENT_SCAN_RATE)); 777 778 if (msi_nonbroken) { 779 _FDT(fdt_setprop(fdt, rtas, "ibm,change-msix-capable", NULL, 0)); 780 } 781 782 /* 783 * According to PAPR, rtas ibm,os-term does not guarantee a return 784 * back to the guest cpu. 785 * 786 * While an additional ibm,extended-os-term property indicates 787 * that rtas call return will always occur. Set this property. 788 */ 789 _FDT(fdt_setprop(fdt, rtas, "ibm,extended-os-term", NULL, 0)); 790 791 _FDT(fdt_setprop(fdt, rtas, "ibm,lrdr-capacity", 792 lrdr_capacity, sizeof(lrdr_capacity))); 793 794 spapr_dt_rtas_tokens(fdt, rtas); 795 } 796 797 static void spapr_dt_chosen(sPAPRMachineState *spapr, void *fdt) 798 { 799 MachineState *machine = MACHINE(spapr); 800 int chosen; 801 const char *boot_device = machine->boot_order; 802 char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus); 803 size_t cb = 0; 804 char *bootlist = get_boot_devices_list(&cb, true); 805 806 _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); 807 808 _FDT(fdt_setprop_string(fdt, chosen, "bootargs", machine->kernel_cmdline)); 809 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-start", 810 spapr->initrd_base)); 811 _FDT(fdt_setprop_cell(fdt, chosen, "linux,initrd-end", 812 spapr->initrd_base + spapr->initrd_size)); 813 814 if (spapr->kernel_size) { 815 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR), 816 cpu_to_be64(spapr->kernel_size) }; 817 818 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel", 819 &kprop, sizeof(kprop))); 820 if (spapr->kernel_le) { 821 _FDT(fdt_setprop(fdt, chosen, "qemu,boot-kernel-le", NULL, 0)); 822 } 823 } 824 if (boot_menu) { 825 _FDT((fdt_setprop_cell(fdt, chosen, "qemu,boot-menu", boot_menu))); 826 } 827 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-width", graphic_width)); 828 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-height", graphic_height)); 829 _FDT(fdt_setprop_cell(fdt, chosen, "qemu,graphic-depth", graphic_depth)); 830 831 if (cb && bootlist) { 832 int i; 833 834 for (i = 0; i < cb; i++) { 835 if (bootlist[i] == '\n') { 836 bootlist[i] = ' '; 837 } 838 } 839 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-list", bootlist)); 840 } 841 842 if (boot_device && strlen(boot_device)) { 843 _FDT(fdt_setprop_string(fdt, chosen, "qemu,boot-device", boot_device)); 844 } 845 846 if (!spapr->has_graphics && stdout_path) { 847 _FDT(fdt_setprop_string(fdt, chosen, "linux,stdout-path", stdout_path)); 848 } 849 850 g_free(stdout_path); 851 g_free(bootlist); 852 } 853 854 static void spapr_dt_hypervisor(sPAPRMachineState *spapr, void *fdt) 855 { 856 /* The /hypervisor node isn't in PAPR - this is a hack to allow PR 857 * KVM to work under pHyp with some guest co-operation */ 858 int hypervisor; 859 uint8_t hypercall[16]; 860 861 _FDT(hypervisor = fdt_add_subnode(fdt, 0, "hypervisor")); 862 /* indicate KVM hypercall interface */ 863 _FDT(fdt_setprop_string(fdt, hypervisor, "compatible", "linux,kvm")); 864 if (kvmppc_has_cap_fixup_hcalls()) { 865 /* 866 * Older KVM versions with older guest kernels were broken 867 * with the magic page, don't allow the guest to map it. 868 */ 869 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall, 870 sizeof(hypercall))) { 871 _FDT(fdt_setprop(fdt, hypervisor, "hcall-instructions", 872 hypercall, sizeof(hypercall))); 873 } 874 } 875 } 876 877 static void *spapr_build_fdt(sPAPRMachineState *spapr, 878 hwaddr rtas_addr, 879 hwaddr rtas_size) 880 { 881 MachineState *machine = MACHINE(qdev_get_machine()); 882 MachineClass *mc = MACHINE_GET_CLASS(machine); 883 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 884 int ret; 885 void *fdt; 886 sPAPRPHBState *phb; 887 char *buf; 888 889 fdt = g_malloc0(FDT_MAX_SIZE); 890 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 891 892 /* Root node */ 893 _FDT(fdt_setprop_string(fdt, 0, "device_type", "chrp")); 894 _FDT(fdt_setprop_string(fdt, 0, "model", "IBM pSeries (emulated by qemu)")); 895 _FDT(fdt_setprop_string(fdt, 0, "compatible", "qemu,pseries")); 896 897 /* 898 * Add info to guest to indentify which host is it being run on 899 * and what is the uuid of the guest 900 */ 901 if (kvmppc_get_host_model(&buf)) { 902 _FDT(fdt_setprop_string(fdt, 0, "host-model", buf)); 903 g_free(buf); 904 } 905 if (kvmppc_get_host_serial(&buf)) { 906 _FDT(fdt_setprop_string(fdt, 0, "host-serial", buf)); 907 g_free(buf); 908 } 909 910 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 911 912 _FDT(fdt_setprop_string(fdt, 0, "vm,uuid", buf)); 913 if (qemu_uuid_set) { 914 _FDT(fdt_setprop_string(fdt, 0, "system-id", buf)); 915 } 916 g_free(buf); 917 918 if (qemu_get_vm_name()) { 919 _FDT(fdt_setprop_string(fdt, 0, "ibm,partition-name", 920 qemu_get_vm_name())); 921 } 922 923 _FDT(fdt_setprop_cell(fdt, 0, "#address-cells", 2)); 924 _FDT(fdt_setprop_cell(fdt, 0, "#size-cells", 2)); 925 926 /* /interrupt controller */ 927 spapr_dt_xics(spapr->xics, fdt, PHANDLE_XICP); 928 929 ret = spapr_populate_memory(spapr, fdt); 930 if (ret < 0) { 931 error_report("couldn't setup memory nodes in fdt"); 932 exit(1); 933 } 934 935 /* /vdevice */ 936 spapr_dt_vdevice(spapr->vio_bus, fdt); 937 938 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { 939 ret = spapr_rng_populate_dt(fdt); 940 if (ret < 0) { 941 error_report("could not set up rng device in the fdt"); 942 exit(1); 943 } 944 } 945 946 QLIST_FOREACH(phb, &spapr->phbs, list) { 947 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt); 948 if (ret < 0) { 949 error_report("couldn't setup PCI devices in fdt"); 950 exit(1); 951 } 952 } 953 954 /* cpus */ 955 spapr_populate_cpus_dt_node(fdt, spapr); 956 957 if (smc->dr_lmb_enabled) { 958 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); 959 } 960 961 if (mc->query_hotpluggable_cpus) { 962 int offset = fdt_path_offset(fdt, "/cpus"); 963 ret = spapr_drc_populate_dt(fdt, offset, NULL, 964 SPAPR_DR_CONNECTOR_TYPE_CPU); 965 if (ret < 0) { 966 error_report("Couldn't set up CPU DR device tree properties"); 967 exit(1); 968 } 969 } 970 971 /* /event-sources */ 972 spapr_dt_events(spapr, fdt); 973 974 /* /rtas */ 975 spapr_dt_rtas(spapr, fdt); 976 977 /* /chosen */ 978 spapr_dt_chosen(spapr, fdt); 979 980 /* /hypervisor */ 981 if (kvm_enabled()) { 982 spapr_dt_hypervisor(spapr, fdt); 983 } 984 985 /* Build memory reserve map */ 986 if (spapr->kernel_size) { 987 _FDT((fdt_add_mem_rsv(fdt, KERNEL_LOAD_ADDR, spapr->kernel_size))); 988 } 989 if (spapr->initrd_size) { 990 _FDT((fdt_add_mem_rsv(fdt, spapr->initrd_base, spapr->initrd_size))); 991 } 992 993 /* ibm,client-architecture-support updates */ 994 ret = spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); 995 if (ret < 0) { 996 error_report("couldn't setup CAS properties fdt"); 997 exit(1); 998 } 999 1000 return fdt; 1001 } 1002 1003 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 1004 { 1005 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; 1006 } 1007 1008 static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp, 1009 PowerPCCPU *cpu) 1010 { 1011 CPUPPCState *env = &cpu->env; 1012 1013 if (msr_pr) { 1014 hcall_dprintf("Hypercall made with MSR[PR]=1\n"); 1015 env->gpr[3] = H_PRIVILEGE; 1016 } else { 1017 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); 1018 } 1019 } 1020 1021 #define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2)) 1022 #define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID) 1023 #define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY) 1024 #define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY)) 1025 #define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY)) 1026 1027 /* 1028 * Get the fd to access the kernel htab, re-opening it if necessary 1029 */ 1030 static int get_htab_fd(sPAPRMachineState *spapr) 1031 { 1032 if (spapr->htab_fd >= 0) { 1033 return spapr->htab_fd; 1034 } 1035 1036 spapr->htab_fd = kvmppc_get_htab_fd(false); 1037 if (spapr->htab_fd < 0) { 1038 error_report("Unable to open fd for reading hash table from KVM: %s", 1039 strerror(errno)); 1040 } 1041 1042 return spapr->htab_fd; 1043 } 1044 1045 static void close_htab_fd(sPAPRMachineState *spapr) 1046 { 1047 if (spapr->htab_fd >= 0) { 1048 close(spapr->htab_fd); 1049 } 1050 spapr->htab_fd = -1; 1051 } 1052 1053 static int spapr_hpt_shift_for_ramsize(uint64_t ramsize) 1054 { 1055 int shift; 1056 1057 /* We aim for a hash table of size 1/128 the size of RAM (rounded 1058 * up). The PAPR recommendation is actually 1/64 of RAM size, but 1059 * that's much more than is needed for Linux guests */ 1060 shift = ctz64(pow2ceil(ramsize)) - 7; 1061 shift = MAX(shift, 18); /* Minimum architected size */ 1062 shift = MIN(shift, 46); /* Maximum architected size */ 1063 return shift; 1064 } 1065 1066 static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift, 1067 Error **errp) 1068 { 1069 long rc; 1070 1071 /* Clean up any HPT info from a previous boot */ 1072 g_free(spapr->htab); 1073 spapr->htab = NULL; 1074 spapr->htab_shift = 0; 1075 close_htab_fd(spapr); 1076 1077 rc = kvmppc_reset_htab(shift); 1078 if (rc < 0) { 1079 /* kernel-side HPT needed, but couldn't allocate one */ 1080 error_setg_errno(errp, errno, 1081 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)", 1082 shift); 1083 /* This is almost certainly fatal, but if the caller really 1084 * wants to carry on with shift == 0, it's welcome to try */ 1085 } else if (rc > 0) { 1086 /* kernel-side HPT allocated */ 1087 if (rc != shift) { 1088 error_setg(errp, 1089 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)", 1090 shift, rc); 1091 } 1092 1093 spapr->htab_shift = shift; 1094 spapr->htab = NULL; 1095 } else { 1096 /* kernel-side HPT not needed, allocate in userspace instead */ 1097 size_t size = 1ULL << shift; 1098 int i; 1099 1100 spapr->htab = qemu_memalign(size, size); 1101 if (!spapr->htab) { 1102 error_setg_errno(errp, errno, 1103 "Could not allocate HPT of order %d", shift); 1104 return; 1105 } 1106 1107 memset(spapr->htab, 0, size); 1108 spapr->htab_shift = shift; 1109 1110 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) { 1111 DIRTY_HPTE(HPTE(spapr->htab, i)); 1112 } 1113 } 1114 } 1115 1116 static void find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque) 1117 { 1118 bool matched = false; 1119 1120 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) { 1121 matched = true; 1122 } 1123 1124 if (!matched) { 1125 error_report("Device %s is not supported by this machine yet.", 1126 qdev_fw_name(DEVICE(sbdev))); 1127 exit(1); 1128 } 1129 } 1130 1131 static void ppc_spapr_reset(void) 1132 { 1133 MachineState *machine = MACHINE(qdev_get_machine()); 1134 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1135 PowerPCCPU *first_ppc_cpu; 1136 uint32_t rtas_limit; 1137 hwaddr rtas_addr, fdt_addr; 1138 void *fdt; 1139 int rc; 1140 1141 /* Check for unknown sysbus devices */ 1142 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL); 1143 1144 /* Allocate and/or reset the hash page table */ 1145 spapr_reallocate_hpt(spapr, 1146 spapr_hpt_shift_for_ramsize(machine->maxram_size), 1147 &error_fatal); 1148 1149 /* Update the RMA size if necessary */ 1150 if (spapr->vrma_adjust) { 1151 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(), 1152 spapr->htab_shift); 1153 } 1154 1155 qemu_devices_reset(); 1156 1157 /* 1158 * We place the device tree and RTAS just below either the top of the RMA, 1159 * or just below 2GB, whichever is lowere, so that it can be 1160 * processed with 32-bit real mode code if necessary 1161 */ 1162 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR); 1163 rtas_addr = rtas_limit - RTAS_MAX_SIZE; 1164 fdt_addr = rtas_addr - FDT_MAX_SIZE; 1165 1166 /* if this reset wasn't generated by CAS, we should reset our 1167 * negotiated options and start from scratch */ 1168 if (!spapr->cas_reboot) { 1169 spapr_ovec_cleanup(spapr->ov5_cas); 1170 spapr->ov5_cas = spapr_ovec_new(); 1171 } 1172 1173 fdt = spapr_build_fdt(spapr, rtas_addr, spapr->rtas_size); 1174 1175 spapr_load_rtas(spapr, fdt, rtas_addr); 1176 1177 rc = fdt_pack(fdt); 1178 1179 /* Should only fail if we've built a corrupted tree */ 1180 assert(rc == 0); 1181 1182 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) { 1183 error_report("FDT too big ! 0x%x bytes (max is 0x%x)", 1184 fdt_totalsize(fdt), FDT_MAX_SIZE); 1185 exit(1); 1186 } 1187 1188 /* Load the fdt */ 1189 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 1190 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); 1191 g_free(fdt); 1192 1193 /* Set up the entry state */ 1194 first_ppc_cpu = POWERPC_CPU(first_cpu); 1195 first_ppc_cpu->env.gpr[3] = fdt_addr; 1196 first_ppc_cpu->env.gpr[5] = 0; 1197 first_cpu->halted = 0; 1198 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT; 1199 1200 spapr->cas_reboot = false; 1201 } 1202 1203 static void spapr_create_nvram(sPAPRMachineState *spapr) 1204 { 1205 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram"); 1206 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); 1207 1208 if (dinfo) { 1209 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 1210 &error_fatal); 1211 } 1212 1213 qdev_init_nofail(dev); 1214 1215 spapr->nvram = (struct sPAPRNVRAM *)dev; 1216 } 1217 1218 static void spapr_rtc_create(sPAPRMachineState *spapr) 1219 { 1220 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC); 1221 1222 qdev_init_nofail(dev); 1223 spapr->rtc = dev; 1224 1225 object_property_add_alias(qdev_get_machine(), "rtc-time", 1226 OBJECT(spapr->rtc), "date", NULL); 1227 } 1228 1229 /* Returns whether we want to use VGA or not */ 1230 static bool spapr_vga_init(PCIBus *pci_bus, Error **errp) 1231 { 1232 switch (vga_interface_type) { 1233 case VGA_NONE: 1234 return false; 1235 case VGA_DEVICE: 1236 return true; 1237 case VGA_STD: 1238 case VGA_VIRTIO: 1239 return pci_vga_init(pci_bus) != NULL; 1240 default: 1241 error_setg(errp, 1242 "Unsupported VGA mode, only -vga std or -vga virtio is supported"); 1243 return false; 1244 } 1245 } 1246 1247 static int spapr_post_load(void *opaque, int version_id) 1248 { 1249 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque; 1250 int err = 0; 1251 1252 /* In earlier versions, there was no separate qdev for the PAPR 1253 * RTC, so the RTC offset was stored directly in sPAPREnvironment. 1254 * So when migrating from those versions, poke the incoming offset 1255 * value into the RTC device */ 1256 if (version_id < 3) { 1257 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset); 1258 } 1259 1260 return err; 1261 } 1262 1263 static bool version_before_3(void *opaque, int version_id) 1264 { 1265 return version_id < 3; 1266 } 1267 1268 static bool spapr_ov5_cas_needed(void *opaque) 1269 { 1270 sPAPRMachineState *spapr = opaque; 1271 sPAPROptionVector *ov5_mask = spapr_ovec_new(); 1272 sPAPROptionVector *ov5_legacy = spapr_ovec_new(); 1273 sPAPROptionVector *ov5_removed = spapr_ovec_new(); 1274 bool cas_needed; 1275 1276 /* Prior to the introduction of sPAPROptionVector, we had two option 1277 * vectors we dealt with: OV5_FORM1_AFFINITY, and OV5_DRCONF_MEMORY. 1278 * Both of these options encode machine topology into the device-tree 1279 * in such a way that the now-booted OS should still be able to interact 1280 * appropriately with QEMU regardless of what options were actually 1281 * negotiatied on the source side. 1282 * 1283 * As such, we can avoid migrating the CAS-negotiated options if these 1284 * are the only options available on the current machine/platform. 1285 * Since these are the only options available for pseries-2.7 and 1286 * earlier, this allows us to maintain old->new/new->old migration 1287 * compatibility. 1288 * 1289 * For QEMU 2.8+, there are additional CAS-negotiatable options available 1290 * via default pseries-2.8 machines and explicit command-line parameters. 1291 * Some of these options, like OV5_HP_EVT, *do* require QEMU to be aware 1292 * of the actual CAS-negotiated values to continue working properly. For 1293 * example, availability of memory unplug depends on knowing whether 1294 * OV5_HP_EVT was negotiated via CAS. 1295 * 1296 * Thus, for any cases where the set of available CAS-negotiatable 1297 * options extends beyond OV5_FORM1_AFFINITY and OV5_DRCONF_MEMORY, we 1298 * include the CAS-negotiated options in the migration stream. 1299 */ 1300 spapr_ovec_set(ov5_mask, OV5_FORM1_AFFINITY); 1301 spapr_ovec_set(ov5_mask, OV5_DRCONF_MEMORY); 1302 1303 /* spapr_ovec_diff returns true if bits were removed. we avoid using 1304 * the mask itself since in the future it's possible "legacy" bits may be 1305 * removed via machine options, which could generate a false positive 1306 * that breaks migration. 1307 */ 1308 spapr_ovec_intersect(ov5_legacy, spapr->ov5, ov5_mask); 1309 cas_needed = spapr_ovec_diff(ov5_removed, spapr->ov5, ov5_legacy); 1310 1311 spapr_ovec_cleanup(ov5_mask); 1312 spapr_ovec_cleanup(ov5_legacy); 1313 spapr_ovec_cleanup(ov5_removed); 1314 1315 return cas_needed; 1316 } 1317 1318 static const VMStateDescription vmstate_spapr_ov5_cas = { 1319 .name = "spapr_option_vector_ov5_cas", 1320 .version_id = 1, 1321 .minimum_version_id = 1, 1322 .needed = spapr_ov5_cas_needed, 1323 .fields = (VMStateField[]) { 1324 VMSTATE_STRUCT_POINTER_V(ov5_cas, sPAPRMachineState, 1, 1325 vmstate_spapr_ovec, sPAPROptionVector), 1326 VMSTATE_END_OF_LIST() 1327 }, 1328 }; 1329 1330 static const VMStateDescription vmstate_spapr = { 1331 .name = "spapr", 1332 .version_id = 3, 1333 .minimum_version_id = 1, 1334 .post_load = spapr_post_load, 1335 .fields = (VMStateField[]) { 1336 /* used to be @next_irq */ 1337 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4), 1338 1339 /* RTC offset */ 1340 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3), 1341 1342 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2), 1343 VMSTATE_END_OF_LIST() 1344 }, 1345 .subsections = (const VMStateDescription*[]) { 1346 &vmstate_spapr_ov5_cas, 1347 NULL 1348 } 1349 }; 1350 1351 static int htab_save_setup(QEMUFile *f, void *opaque) 1352 { 1353 sPAPRMachineState *spapr = opaque; 1354 1355 /* "Iteration" header */ 1356 qemu_put_be32(f, spapr->htab_shift); 1357 1358 if (spapr->htab) { 1359 spapr->htab_save_index = 0; 1360 spapr->htab_first_pass = true; 1361 } else { 1362 assert(kvm_enabled()); 1363 } 1364 1365 1366 return 0; 1367 } 1368 1369 static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr, 1370 int64_t max_ns) 1371 { 1372 bool has_timeout = max_ns != -1; 1373 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1374 int index = spapr->htab_save_index; 1375 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1376 1377 assert(spapr->htab_first_pass); 1378 1379 do { 1380 int chunkstart; 1381 1382 /* Consume invalid HPTEs */ 1383 while ((index < htabslots) 1384 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1385 index++; 1386 CLEAN_HPTE(HPTE(spapr->htab, index)); 1387 } 1388 1389 /* Consume valid HPTEs */ 1390 chunkstart = index; 1391 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1392 && HPTE_VALID(HPTE(spapr->htab, index))) { 1393 index++; 1394 CLEAN_HPTE(HPTE(spapr->htab, index)); 1395 } 1396 1397 if (index > chunkstart) { 1398 int n_valid = index - chunkstart; 1399 1400 qemu_put_be32(f, chunkstart); 1401 qemu_put_be16(f, n_valid); 1402 qemu_put_be16(f, 0); 1403 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1404 HASH_PTE_SIZE_64 * n_valid); 1405 1406 if (has_timeout && 1407 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1408 break; 1409 } 1410 } 1411 } while ((index < htabslots) && !qemu_file_rate_limit(f)); 1412 1413 if (index >= htabslots) { 1414 assert(index == htabslots); 1415 index = 0; 1416 spapr->htab_first_pass = false; 1417 } 1418 spapr->htab_save_index = index; 1419 } 1420 1421 static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr, 1422 int64_t max_ns) 1423 { 1424 bool final = max_ns < 0; 1425 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64; 1426 int examined = 0, sent = 0; 1427 int index = spapr->htab_save_index; 1428 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME); 1429 1430 assert(!spapr->htab_first_pass); 1431 1432 do { 1433 int chunkstart, invalidstart; 1434 1435 /* Consume non-dirty HPTEs */ 1436 while ((index < htabslots) 1437 && !HPTE_DIRTY(HPTE(spapr->htab, index))) { 1438 index++; 1439 examined++; 1440 } 1441 1442 chunkstart = index; 1443 /* Consume valid dirty HPTEs */ 1444 while ((index < htabslots) && (index - chunkstart < USHRT_MAX) 1445 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1446 && HPTE_VALID(HPTE(spapr->htab, index))) { 1447 CLEAN_HPTE(HPTE(spapr->htab, index)); 1448 index++; 1449 examined++; 1450 } 1451 1452 invalidstart = index; 1453 /* Consume invalid dirty HPTEs */ 1454 while ((index < htabslots) && (index - invalidstart < USHRT_MAX) 1455 && HPTE_DIRTY(HPTE(spapr->htab, index)) 1456 && !HPTE_VALID(HPTE(spapr->htab, index))) { 1457 CLEAN_HPTE(HPTE(spapr->htab, index)); 1458 index++; 1459 examined++; 1460 } 1461 1462 if (index > chunkstart) { 1463 int n_valid = invalidstart - chunkstart; 1464 int n_invalid = index - invalidstart; 1465 1466 qemu_put_be32(f, chunkstart); 1467 qemu_put_be16(f, n_valid); 1468 qemu_put_be16(f, n_invalid); 1469 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart), 1470 HASH_PTE_SIZE_64 * n_valid); 1471 sent += index - chunkstart; 1472 1473 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) { 1474 break; 1475 } 1476 } 1477 1478 if (examined >= htabslots) { 1479 break; 1480 } 1481 1482 if (index >= htabslots) { 1483 assert(index == htabslots); 1484 index = 0; 1485 } 1486 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final)); 1487 1488 if (index >= htabslots) { 1489 assert(index == htabslots); 1490 index = 0; 1491 } 1492 1493 spapr->htab_save_index = index; 1494 1495 return (examined >= htabslots) && (sent == 0) ? 1 : 0; 1496 } 1497 1498 #define MAX_ITERATION_NS 5000000 /* 5 ms */ 1499 #define MAX_KVM_BUF_SIZE 2048 1500 1501 static int htab_save_iterate(QEMUFile *f, void *opaque) 1502 { 1503 sPAPRMachineState *spapr = opaque; 1504 int fd; 1505 int rc = 0; 1506 1507 /* Iteration header */ 1508 qemu_put_be32(f, 0); 1509 1510 if (!spapr->htab) { 1511 assert(kvm_enabled()); 1512 1513 fd = get_htab_fd(spapr); 1514 if (fd < 0) { 1515 return fd; 1516 } 1517 1518 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS); 1519 if (rc < 0) { 1520 return rc; 1521 } 1522 } else if (spapr->htab_first_pass) { 1523 htab_save_first_pass(f, spapr, MAX_ITERATION_NS); 1524 } else { 1525 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS); 1526 } 1527 1528 /* End marker */ 1529 qemu_put_be32(f, 0); 1530 qemu_put_be16(f, 0); 1531 qemu_put_be16(f, 0); 1532 1533 return rc; 1534 } 1535 1536 static int htab_save_complete(QEMUFile *f, void *opaque) 1537 { 1538 sPAPRMachineState *spapr = opaque; 1539 int fd; 1540 1541 /* Iteration header */ 1542 qemu_put_be32(f, 0); 1543 1544 if (!spapr->htab) { 1545 int rc; 1546 1547 assert(kvm_enabled()); 1548 1549 fd = get_htab_fd(spapr); 1550 if (fd < 0) { 1551 return fd; 1552 } 1553 1554 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1); 1555 if (rc < 0) { 1556 return rc; 1557 } 1558 } else { 1559 if (spapr->htab_first_pass) { 1560 htab_save_first_pass(f, spapr, -1); 1561 } 1562 htab_save_later_pass(f, spapr, -1); 1563 } 1564 1565 /* End marker */ 1566 qemu_put_be32(f, 0); 1567 qemu_put_be16(f, 0); 1568 qemu_put_be16(f, 0); 1569 1570 return 0; 1571 } 1572 1573 static int htab_load(QEMUFile *f, void *opaque, int version_id) 1574 { 1575 sPAPRMachineState *spapr = opaque; 1576 uint32_t section_hdr; 1577 int fd = -1; 1578 1579 if (version_id < 1 || version_id > 1) { 1580 error_report("htab_load() bad version"); 1581 return -EINVAL; 1582 } 1583 1584 section_hdr = qemu_get_be32(f); 1585 1586 if (section_hdr) { 1587 Error *local_err = NULL; 1588 1589 /* First section gives the htab size */ 1590 spapr_reallocate_hpt(spapr, section_hdr, &local_err); 1591 if (local_err) { 1592 error_report_err(local_err); 1593 return -EINVAL; 1594 } 1595 return 0; 1596 } 1597 1598 if (!spapr->htab) { 1599 assert(kvm_enabled()); 1600 1601 fd = kvmppc_get_htab_fd(true); 1602 if (fd < 0) { 1603 error_report("Unable to open fd to restore KVM hash table: %s", 1604 strerror(errno)); 1605 } 1606 } 1607 1608 while (true) { 1609 uint32_t index; 1610 uint16_t n_valid, n_invalid; 1611 1612 index = qemu_get_be32(f); 1613 n_valid = qemu_get_be16(f); 1614 n_invalid = qemu_get_be16(f); 1615 1616 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) { 1617 /* End of Stream */ 1618 break; 1619 } 1620 1621 if ((index + n_valid + n_invalid) > 1622 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) { 1623 /* Bad index in stream */ 1624 error_report( 1625 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)", 1626 index, n_valid, n_invalid, spapr->htab_shift); 1627 return -EINVAL; 1628 } 1629 1630 if (spapr->htab) { 1631 if (n_valid) { 1632 qemu_get_buffer(f, HPTE(spapr->htab, index), 1633 HASH_PTE_SIZE_64 * n_valid); 1634 } 1635 if (n_invalid) { 1636 memset(HPTE(spapr->htab, index + n_valid), 0, 1637 HASH_PTE_SIZE_64 * n_invalid); 1638 } 1639 } else { 1640 int rc; 1641 1642 assert(fd >= 0); 1643 1644 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid); 1645 if (rc < 0) { 1646 return rc; 1647 } 1648 } 1649 } 1650 1651 if (!spapr->htab) { 1652 assert(fd >= 0); 1653 close(fd); 1654 } 1655 1656 return 0; 1657 } 1658 1659 static void htab_cleanup(void *opaque) 1660 { 1661 sPAPRMachineState *spapr = opaque; 1662 1663 close_htab_fd(spapr); 1664 } 1665 1666 static SaveVMHandlers savevm_htab_handlers = { 1667 .save_live_setup = htab_save_setup, 1668 .save_live_iterate = htab_save_iterate, 1669 .save_live_complete_precopy = htab_save_complete, 1670 .cleanup = htab_cleanup, 1671 .load_state = htab_load, 1672 }; 1673 1674 static void spapr_boot_set(void *opaque, const char *boot_device, 1675 Error **errp) 1676 { 1677 MachineState *machine = MACHINE(qdev_get_machine()); 1678 machine->boot_order = g_strdup(boot_device); 1679 } 1680 1681 /* 1682 * Reset routine for LMB DR devices. 1683 * 1684 * Unlike PCI DR devices, LMB DR devices explicitly register this reset 1685 * routine. Reset for PCI DR devices will be handled by PHB reset routine 1686 * when it walks all its children devices. LMB devices reset occurs 1687 * as part of spapr_ppc_reset(). 1688 */ 1689 static void spapr_drc_reset(void *opaque) 1690 { 1691 sPAPRDRConnector *drc = opaque; 1692 DeviceState *d = DEVICE(drc); 1693 1694 if (d) { 1695 device_reset(d); 1696 } 1697 } 1698 1699 static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr) 1700 { 1701 MachineState *machine = MACHINE(spapr); 1702 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE; 1703 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size; 1704 int i; 1705 1706 for (i = 0; i < nr_lmbs; i++) { 1707 sPAPRDRConnector *drc; 1708 uint64_t addr; 1709 1710 addr = i * lmb_size + spapr->hotplug_memory.base; 1711 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB, 1712 addr/lmb_size); 1713 qemu_register_reset(spapr_drc_reset, drc); 1714 } 1715 } 1716 1717 /* 1718 * If RAM size, maxmem size and individual node mem sizes aren't aligned 1719 * to SPAPR_MEMORY_BLOCK_SIZE(256MB), then refuse to start the guest 1720 * since we can't support such unaligned sizes with DRCONF_MEMORY. 1721 */ 1722 static void spapr_validate_node_memory(MachineState *machine, Error **errp) 1723 { 1724 int i; 1725 1726 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1727 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT 1728 " is not aligned to %llu MiB", 1729 machine->ram_size, 1730 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1731 return; 1732 } 1733 1734 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) { 1735 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT 1736 " is not aligned to %llu MiB", 1737 machine->ram_size, 1738 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1739 return; 1740 } 1741 1742 for (i = 0; i < nb_numa_nodes; i++) { 1743 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) { 1744 error_setg(errp, 1745 "Node %d memory size 0x%" PRIx64 1746 " is not aligned to %llu MiB", 1747 i, numa_info[i].node_mem, 1748 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE); 1749 return; 1750 } 1751 } 1752 } 1753 1754 static void spapr_init_cpus(sPAPRMachineState *spapr) 1755 { 1756 MachineState *machine = MACHINE(spapr); 1757 MachineClass *mc = MACHINE_GET_CLASS(machine); 1758 char *type = spapr_get_cpu_core_type(machine->cpu_model); 1759 int smt = kvmppc_smt_threads(); 1760 int spapr_max_cores, spapr_cores; 1761 int i; 1762 1763 if (!type) { 1764 error_report("Unable to find sPAPR CPU Core definition"); 1765 exit(1); 1766 } 1767 1768 if (mc->query_hotpluggable_cpus) { 1769 if (smp_cpus % smp_threads) { 1770 error_report("smp_cpus (%u) must be multiple of threads (%u)", 1771 smp_cpus, smp_threads); 1772 exit(1); 1773 } 1774 if (max_cpus % smp_threads) { 1775 error_report("max_cpus (%u) must be multiple of threads (%u)", 1776 max_cpus, smp_threads); 1777 exit(1); 1778 } 1779 1780 spapr_max_cores = max_cpus / smp_threads; 1781 spapr_cores = smp_cpus / smp_threads; 1782 } else { 1783 if (max_cpus != smp_cpus) { 1784 error_report("This machine version does not support CPU hotplug"); 1785 exit(1); 1786 } 1787 1788 spapr_max_cores = QEMU_ALIGN_UP(smp_cpus, smp_threads) / smp_threads; 1789 spapr_cores = spapr_max_cores; 1790 } 1791 1792 spapr->cores = g_new0(Object *, spapr_max_cores); 1793 for (i = 0; i < spapr_max_cores; i++) { 1794 int core_id = i * smp_threads; 1795 1796 if (mc->query_hotpluggable_cpus) { 1797 sPAPRDRConnector *drc = 1798 spapr_dr_connector_new(OBJECT(spapr), 1799 SPAPR_DR_CONNECTOR_TYPE_CPU, 1800 (core_id / smp_threads) * smt); 1801 1802 qemu_register_reset(spapr_drc_reset, drc); 1803 } 1804 1805 if (i < spapr_cores) { 1806 Object *core = object_new(type); 1807 int nr_threads = smp_threads; 1808 1809 /* Handle the partially filled core for older machine types */ 1810 if ((i + 1) * smp_threads >= smp_cpus) { 1811 nr_threads = smp_cpus - i * smp_threads; 1812 } 1813 1814 object_property_set_int(core, nr_threads, "nr-threads", 1815 &error_fatal); 1816 object_property_set_int(core, core_id, CPU_CORE_PROP_CORE_ID, 1817 &error_fatal); 1818 object_property_set_bool(core, true, "realized", &error_fatal); 1819 } 1820 } 1821 g_free(type); 1822 } 1823 1824 /* pSeries LPAR / sPAPR hardware init */ 1825 static void ppc_spapr_init(MachineState *machine) 1826 { 1827 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 1828 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); 1829 const char *kernel_filename = machine->kernel_filename; 1830 const char *initrd_filename = machine->initrd_filename; 1831 PCIHostState *phb; 1832 int i; 1833 MemoryRegion *sysmem = get_system_memory(); 1834 MemoryRegion *ram = g_new(MemoryRegion, 1); 1835 MemoryRegion *rma_region; 1836 void *rma = NULL; 1837 hwaddr rma_alloc_size; 1838 hwaddr node0_size = spapr_node0_size(); 1839 long load_limit, fw_size; 1840 char *filename; 1841 int smt = kvmppc_smt_threads(); 1842 1843 msi_nonbroken = true; 1844 1845 QLIST_INIT(&spapr->phbs); 1846 1847 /* Allocate RMA if necessary */ 1848 rma_alloc_size = kvmppc_alloc_rma(&rma); 1849 1850 if (rma_alloc_size == -1) { 1851 error_report("Unable to create RMA"); 1852 exit(1); 1853 } 1854 1855 if (rma_alloc_size && (rma_alloc_size < node0_size)) { 1856 spapr->rma_size = rma_alloc_size; 1857 } else { 1858 spapr->rma_size = node0_size; 1859 1860 /* With KVM, we don't actually know whether KVM supports an 1861 * unbounded RMA (PR KVM) or is limited by the hash table size 1862 * (HV KVM using VRMA), so we always assume the latter 1863 * 1864 * In that case, we also limit the initial allocations for RTAS 1865 * etc... to 256M since we have no way to know what the VRMA size 1866 * is going to be as it depends on the size of the hash table 1867 * isn't determined yet. 1868 */ 1869 if (kvm_enabled()) { 1870 spapr->vrma_adjust = 1; 1871 spapr->rma_size = MIN(spapr->rma_size, 0x10000000); 1872 } 1873 1874 /* Actually we don't support unbounded RMA anymore since we 1875 * added proper emulation of HV mode. The max we can get is 1876 * 16G which also happens to be what we configure for PAPR 1877 * mode so make sure we don't do anything bigger than that 1878 */ 1879 spapr->rma_size = MIN(spapr->rma_size, 0x400000000ull); 1880 } 1881 1882 if (spapr->rma_size > node0_size) { 1883 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")", 1884 spapr->rma_size); 1885 exit(1); 1886 } 1887 1888 /* Setup a load limit for the ramdisk leaving room for SLOF and FDT */ 1889 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD; 1890 1891 /* Set up Interrupt Controller before we create the VCPUs */ 1892 spapr->xics = xics_system_init(machine, 1893 DIV_ROUND_UP(max_cpus * smt, smp_threads), 1894 XICS_IRQS_SPAPR, &error_fatal); 1895 1896 /* Set up containers for ibm,client-set-architecture negotiated options */ 1897 spapr->ov5 = spapr_ovec_new(); 1898 spapr->ov5_cas = spapr_ovec_new(); 1899 1900 if (smc->dr_lmb_enabled) { 1901 spapr_ovec_set(spapr->ov5, OV5_DRCONF_MEMORY); 1902 spapr_validate_node_memory(machine, &error_fatal); 1903 } 1904 1905 spapr_ovec_set(spapr->ov5, OV5_FORM1_AFFINITY); 1906 1907 /* advertise support for dedicated HP event source to guests */ 1908 if (spapr->use_hotplug_event_source) { 1909 spapr_ovec_set(spapr->ov5, OV5_HP_EVT); 1910 } 1911 1912 /* init CPUs */ 1913 if (machine->cpu_model == NULL) { 1914 machine->cpu_model = kvm_enabled() ? "host" : smc->tcg_default_cpu; 1915 } 1916 1917 ppc_cpu_parse_features(machine->cpu_model); 1918 1919 spapr_init_cpus(spapr); 1920 1921 if (kvm_enabled()) { 1922 /* Enable H_LOGICAL_CI_* so SLOF can talk to in-kernel devices */ 1923 kvmppc_enable_logical_ci_hcalls(); 1924 kvmppc_enable_set_mode_hcall(); 1925 1926 /* H_CLEAR_MOD/_REF are mandatory in PAPR, but off by default */ 1927 kvmppc_enable_clear_ref_mod_hcalls(); 1928 } 1929 1930 /* allocate RAM */ 1931 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", 1932 machine->ram_size); 1933 memory_region_add_subregion(sysmem, 0, ram); 1934 1935 if (rma_alloc_size && rma) { 1936 rma_region = g_new(MemoryRegion, 1); 1937 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma", 1938 rma_alloc_size, rma); 1939 vmstate_register_ram_global(rma_region); 1940 memory_region_add_subregion(sysmem, 0, rma_region); 1941 } 1942 1943 /* initialize hotplug memory address space */ 1944 if (machine->ram_size < machine->maxram_size) { 1945 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size; 1946 /* 1947 * Limit the number of hotpluggable memory slots to half the number 1948 * slots that KVM supports, leaving the other half for PCI and other 1949 * devices. However ensure that number of slots doesn't drop below 32. 1950 */ 1951 int max_memslots = kvm_enabled() ? kvm_get_max_memslots() / 2 : 1952 SPAPR_MAX_RAM_SLOTS; 1953 1954 if (max_memslots < SPAPR_MAX_RAM_SLOTS) { 1955 max_memslots = SPAPR_MAX_RAM_SLOTS; 1956 } 1957 if (machine->ram_slots > max_memslots) { 1958 error_report("Specified number of memory slots %" 1959 PRIu64" exceeds max supported %d", 1960 machine->ram_slots, max_memslots); 1961 exit(1); 1962 } 1963 1964 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size, 1965 SPAPR_HOTPLUG_MEM_ALIGN); 1966 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr), 1967 "hotplug-memory", hotplug_mem_size); 1968 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base, 1969 &spapr->hotplug_memory.mr); 1970 } 1971 1972 if (smc->dr_lmb_enabled) { 1973 spapr_create_lmb_dr_connectors(spapr); 1974 } 1975 1976 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); 1977 if (!filename) { 1978 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin"); 1979 exit(1); 1980 } 1981 spapr->rtas_size = get_image_size(filename); 1982 if (spapr->rtas_size < 0) { 1983 error_report("Could not get size of LPAR rtas '%s'", filename); 1984 exit(1); 1985 } 1986 spapr->rtas_blob = g_malloc(spapr->rtas_size); 1987 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) { 1988 error_report("Could not load LPAR rtas '%s'", filename); 1989 exit(1); 1990 } 1991 if (spapr->rtas_size > RTAS_MAX_SIZE) { 1992 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)", 1993 (size_t)spapr->rtas_size, RTAS_MAX_SIZE); 1994 exit(1); 1995 } 1996 g_free(filename); 1997 1998 /* Set up RTAS event infrastructure */ 1999 spapr_events_init(spapr); 2000 2001 /* Set up the RTC RTAS interfaces */ 2002 spapr_rtc_create(spapr); 2003 2004 /* Set up VIO bus */ 2005 spapr->vio_bus = spapr_vio_bus_init(); 2006 2007 for (i = 0; i < MAX_SERIAL_PORTS; i++) { 2008 if (serial_hds[i]) { 2009 spapr_vty_create(spapr->vio_bus, serial_hds[i]); 2010 } 2011 } 2012 2013 /* We always have at least the nvram device on VIO */ 2014 spapr_create_nvram(spapr); 2015 2016 /* Set up PCI */ 2017 spapr_pci_rtas_init(); 2018 2019 phb = spapr_create_phb(spapr, 0); 2020 2021 for (i = 0; i < nb_nics; i++) { 2022 NICInfo *nd = &nd_table[i]; 2023 2024 if (!nd->model) { 2025 nd->model = g_strdup("ibmveth"); 2026 } 2027 2028 if (strcmp(nd->model, "ibmveth") == 0) { 2029 spapr_vlan_create(spapr->vio_bus, nd); 2030 } else { 2031 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL); 2032 } 2033 } 2034 2035 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { 2036 spapr_vscsi_create(spapr->vio_bus); 2037 } 2038 2039 /* Graphics */ 2040 if (spapr_vga_init(phb->bus, &error_fatal)) { 2041 spapr->has_graphics = true; 2042 machine->usb |= defaults_enabled() && !machine->usb_disabled; 2043 } 2044 2045 if (machine->usb) { 2046 if (smc->use_ohci_by_default) { 2047 pci_create_simple(phb->bus, -1, "pci-ohci"); 2048 } else { 2049 pci_create_simple(phb->bus, -1, "nec-usb-xhci"); 2050 } 2051 2052 if (spapr->has_graphics) { 2053 USBBus *usb_bus = usb_bus_find(-1); 2054 2055 usb_create_simple(usb_bus, "usb-kbd"); 2056 usb_create_simple(usb_bus, "usb-mouse"); 2057 } 2058 } 2059 2060 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) { 2061 error_report( 2062 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)", 2063 MIN_RMA_SLOF); 2064 exit(1); 2065 } 2066 2067 if (kernel_filename) { 2068 uint64_t lowaddr = 0; 2069 2070 spapr->kernel_size = load_elf(kernel_filename, translate_kernel_address, 2071 NULL, NULL, &lowaddr, NULL, 1, 2072 PPC_ELF_MACHINE, 0, 0); 2073 if (spapr->kernel_size == ELF_LOAD_WRONG_ENDIAN) { 2074 spapr->kernel_size = load_elf(kernel_filename, 2075 translate_kernel_address, NULL, NULL, 2076 &lowaddr, NULL, 0, PPC_ELF_MACHINE, 2077 0, 0); 2078 spapr->kernel_le = spapr->kernel_size > 0; 2079 } 2080 if (spapr->kernel_size < 0) { 2081 error_report("error loading %s: %s", kernel_filename, 2082 load_elf_strerror(spapr->kernel_size)); 2083 exit(1); 2084 } 2085 2086 /* load initrd */ 2087 if (initrd_filename) { 2088 /* Try to locate the initrd in the gap between the kernel 2089 * and the firmware. Add a bit of space just in case 2090 */ 2091 spapr->initrd_base = (KERNEL_LOAD_ADDR + spapr->kernel_size 2092 + 0x1ffff) & ~0xffff; 2093 spapr->initrd_size = load_image_targphys(initrd_filename, 2094 spapr->initrd_base, 2095 load_limit 2096 - spapr->initrd_base); 2097 if (spapr->initrd_size < 0) { 2098 error_report("could not load initial ram disk '%s'", 2099 initrd_filename); 2100 exit(1); 2101 } 2102 } 2103 } 2104 2105 if (bios_name == NULL) { 2106 bios_name = FW_FILE_NAME; 2107 } 2108 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 2109 if (!filename) { 2110 error_report("Could not find LPAR firmware '%s'", bios_name); 2111 exit(1); 2112 } 2113 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); 2114 if (fw_size <= 0) { 2115 error_report("Could not load LPAR firmware '%s'", filename); 2116 exit(1); 2117 } 2118 g_free(filename); 2119 2120 /* FIXME: Should register things through the MachineState's qdev 2121 * interface, this is a legacy from the sPAPREnvironment structure 2122 * which predated MachineState but had a similar function */ 2123 vmstate_register(NULL, 0, &vmstate_spapr, spapr); 2124 register_savevm_live(NULL, "spapr/htab", -1, 1, 2125 &savevm_htab_handlers, spapr); 2126 2127 /* used by RTAS */ 2128 QTAILQ_INIT(&spapr->ccs_list); 2129 qemu_register_reset(spapr_ccs_reset_hook, spapr); 2130 2131 qemu_register_boot_set(spapr_boot_set, spapr); 2132 } 2133 2134 static int spapr_kvm_type(const char *vm_type) 2135 { 2136 if (!vm_type) { 2137 return 0; 2138 } 2139 2140 if (!strcmp(vm_type, "HV")) { 2141 return 1; 2142 } 2143 2144 if (!strcmp(vm_type, "PR")) { 2145 return 2; 2146 } 2147 2148 error_report("Unknown kvm-type specified '%s'", vm_type); 2149 exit(1); 2150 } 2151 2152 /* 2153 * Implementation of an interface to adjust firmware path 2154 * for the bootindex property handling. 2155 */ 2156 static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus, 2157 DeviceState *dev) 2158 { 2159 #define CAST(type, obj, name) \ 2160 ((type *)object_dynamic_cast(OBJECT(obj), (name))) 2161 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE); 2162 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE); 2163 2164 if (d) { 2165 void *spapr = CAST(void, bus->parent, "spapr-vscsi"); 2166 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI); 2167 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE); 2168 2169 if (spapr) { 2170 /* 2171 * Replace "channel@0/disk@0,0" with "disk@8000000000000000": 2172 * We use SRP luns of the form 8000 | (bus << 8) | (id << 5) | lun 2173 * in the top 16 bits of the 64-bit LUN 2174 */ 2175 unsigned id = 0x8000 | (d->id << 8) | d->lun; 2176 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2177 (uint64_t)id << 48); 2178 } else if (virtio) { 2179 /* 2180 * We use SRP luns of the form 01000000 | (target << 8) | lun 2181 * in the top 32 bits of the 64-bit LUN 2182 * Note: the quote above is from SLOF and it is wrong, 2183 * the actual binding is: 2184 * swap 0100 or 10 << or 20 << ( target lun-id -- srplun ) 2185 */ 2186 unsigned id = 0x1000000 | (d->id << 16) | d->lun; 2187 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2188 (uint64_t)id << 32); 2189 } else if (usb) { 2190 /* 2191 * We use SRP luns of the form 01000000 | (usb-port << 16) | lun 2192 * in the top 32 bits of the 64-bit LUN 2193 */ 2194 unsigned usb_port = atoi(usb->port->path); 2195 unsigned id = 0x1000000 | (usb_port << 16) | d->lun; 2196 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev), 2197 (uint64_t)id << 32); 2198 } 2199 } 2200 2201 /* 2202 * SLOF probes the USB devices, and if it recognizes that the device is a 2203 * storage device, it changes its name to "storage" instead of "usb-host", 2204 * and additionally adds a child node for the SCSI LUN, so the correct 2205 * boot path in SLOF is something like .../storage@1/disk@xxx" instead. 2206 */ 2207 if (strcmp("usb-host", qdev_fw_name(dev)) == 0) { 2208 USBDevice *usbdev = CAST(USBDevice, dev, TYPE_USB_DEVICE); 2209 if (usb_host_dev_is_scsi_storage(usbdev)) { 2210 return g_strdup_printf("storage@%s/disk", usbdev->port->path); 2211 } 2212 } 2213 2214 if (phb) { 2215 /* Replace "pci" with "pci@800000020000000" */ 2216 return g_strdup_printf("pci@%"PRIX64, phb->buid); 2217 } 2218 2219 return NULL; 2220 } 2221 2222 static char *spapr_get_kvm_type(Object *obj, Error **errp) 2223 { 2224 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2225 2226 return g_strdup(spapr->kvm_type); 2227 } 2228 2229 static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp) 2230 { 2231 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2232 2233 g_free(spapr->kvm_type); 2234 spapr->kvm_type = g_strdup(value); 2235 } 2236 2237 static bool spapr_get_modern_hotplug_events(Object *obj, Error **errp) 2238 { 2239 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2240 2241 return spapr->use_hotplug_event_source; 2242 } 2243 2244 static void spapr_set_modern_hotplug_events(Object *obj, bool value, 2245 Error **errp) 2246 { 2247 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2248 2249 spapr->use_hotplug_event_source = value; 2250 } 2251 2252 static void spapr_machine_initfn(Object *obj) 2253 { 2254 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2255 2256 spapr->htab_fd = -1; 2257 spapr->use_hotplug_event_source = true; 2258 object_property_add_str(obj, "kvm-type", 2259 spapr_get_kvm_type, spapr_set_kvm_type, NULL); 2260 object_property_set_description(obj, "kvm-type", 2261 "Specifies the KVM virtualization mode (HV, PR)", 2262 NULL); 2263 object_property_add_bool(obj, "modern-hotplug-events", 2264 spapr_get_modern_hotplug_events, 2265 spapr_set_modern_hotplug_events, 2266 NULL); 2267 object_property_set_description(obj, "modern-hotplug-events", 2268 "Use dedicated hotplug event mechanism in" 2269 " place of standard EPOW events when possible" 2270 " (required for memory hot-unplug support)", 2271 NULL); 2272 } 2273 2274 static void spapr_machine_finalizefn(Object *obj) 2275 { 2276 sPAPRMachineState *spapr = SPAPR_MACHINE(obj); 2277 2278 g_free(spapr->kvm_type); 2279 } 2280 2281 void spapr_do_system_reset_on_cpu(CPUState *cs, run_on_cpu_data arg) 2282 { 2283 cpu_synchronize_state(cs); 2284 ppc_cpu_do_system_reset(cs); 2285 } 2286 2287 static void spapr_nmi(NMIState *n, int cpu_index, Error **errp) 2288 { 2289 CPUState *cs; 2290 2291 CPU_FOREACH(cs) { 2292 async_run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 2293 } 2294 } 2295 2296 static void spapr_add_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2297 uint32_t node, bool dedicated_hp_event_source, 2298 Error **errp) 2299 { 2300 sPAPRDRConnector *drc; 2301 sPAPRDRConnectorClass *drck; 2302 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE; 2303 int i, fdt_offset, fdt_size; 2304 void *fdt; 2305 uint64_t addr = addr_start; 2306 2307 for (i = 0; i < nr_lmbs; i++) { 2308 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2309 addr/SPAPR_MEMORY_BLOCK_SIZE); 2310 g_assert(drc); 2311 2312 fdt = create_device_tree(&fdt_size); 2313 fdt_offset = spapr_populate_memory_node(fdt, node, addr, 2314 SPAPR_MEMORY_BLOCK_SIZE); 2315 2316 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2317 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp); 2318 addr += SPAPR_MEMORY_BLOCK_SIZE; 2319 if (!dev->hotplugged) { 2320 /* guests expect coldplugged LMBs to be pre-allocated */ 2321 drck->set_allocation_state(drc, SPAPR_DR_ALLOCATION_STATE_USABLE); 2322 drck->set_isolation_state(drc, SPAPR_DR_ISOLATION_STATE_UNISOLATED); 2323 } 2324 } 2325 /* send hotplug notification to the 2326 * guest only in case of hotplugged memory 2327 */ 2328 if (dev->hotplugged) { 2329 if (dedicated_hp_event_source) { 2330 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2331 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2332 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2333 spapr_hotplug_req_add_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2334 nr_lmbs, 2335 drck->get_index(drc)); 2336 } else { 2337 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, 2338 nr_lmbs); 2339 } 2340 } 2341 } 2342 2343 static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 2344 uint32_t node, Error **errp) 2345 { 2346 Error *local_err = NULL; 2347 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2348 PCDIMMDevice *dimm = PC_DIMM(dev); 2349 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2350 MemoryRegion *mr = ddc->get_memory_region(dimm); 2351 uint64_t align = memory_region_get_alignment(mr); 2352 uint64_t size = memory_region_size(mr); 2353 uint64_t addr; 2354 2355 if (size % SPAPR_MEMORY_BLOCK_SIZE) { 2356 error_setg(&local_err, "Hotplugged memory size must be a multiple of " 2357 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE); 2358 goto out; 2359 } 2360 2361 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err); 2362 if (local_err) { 2363 goto out; 2364 } 2365 2366 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2367 if (local_err) { 2368 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2369 goto out; 2370 } 2371 2372 spapr_add_lmbs(dev, addr, size, node, 2373 spapr_ovec_test(ms->ov5_cas, OV5_HP_EVT), 2374 &error_abort); 2375 2376 out: 2377 error_propagate(errp, local_err); 2378 } 2379 2380 typedef struct sPAPRDIMMState { 2381 uint32_t nr_lmbs; 2382 } sPAPRDIMMState; 2383 2384 static void spapr_lmb_release(DeviceState *dev, void *opaque) 2385 { 2386 sPAPRDIMMState *ds = (sPAPRDIMMState *)opaque; 2387 HotplugHandler *hotplug_ctrl; 2388 2389 if (--ds->nr_lmbs) { 2390 return; 2391 } 2392 2393 g_free(ds); 2394 2395 /* 2396 * Now that all the LMBs have been removed by the guest, call the 2397 * pc-dimm unplug handler to cleanup up the pc-dimm device. 2398 */ 2399 hotplug_ctrl = qdev_get_hotplug_handler(dev); 2400 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 2401 } 2402 2403 static void spapr_del_lmbs(DeviceState *dev, uint64_t addr_start, uint64_t size, 2404 Error **errp) 2405 { 2406 sPAPRDRConnector *drc; 2407 sPAPRDRConnectorClass *drck; 2408 uint32_t nr_lmbs = size / SPAPR_MEMORY_BLOCK_SIZE; 2409 int i; 2410 sPAPRDIMMState *ds = g_malloc0(sizeof(sPAPRDIMMState)); 2411 uint64_t addr = addr_start; 2412 2413 ds->nr_lmbs = nr_lmbs; 2414 for (i = 0; i < nr_lmbs; i++) { 2415 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2416 addr / SPAPR_MEMORY_BLOCK_SIZE); 2417 g_assert(drc); 2418 2419 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2420 drck->detach(drc, dev, spapr_lmb_release, ds, errp); 2421 addr += SPAPR_MEMORY_BLOCK_SIZE; 2422 } 2423 2424 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB, 2425 addr_start / SPAPR_MEMORY_BLOCK_SIZE); 2426 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc); 2427 spapr_hotplug_req_remove_by_count_indexed(SPAPR_DR_CONNECTOR_TYPE_LMB, 2428 nr_lmbs, 2429 drck->get_index(drc)); 2430 } 2431 2432 static void spapr_memory_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, 2433 Error **errp) 2434 { 2435 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev); 2436 PCDIMMDevice *dimm = PC_DIMM(dev); 2437 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2438 MemoryRegion *mr = ddc->get_memory_region(dimm); 2439 2440 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr); 2441 object_unparent(OBJECT(dev)); 2442 } 2443 2444 static void spapr_memory_unplug_request(HotplugHandler *hotplug_dev, 2445 DeviceState *dev, Error **errp) 2446 { 2447 Error *local_err = NULL; 2448 PCDIMMDevice *dimm = PC_DIMM(dev); 2449 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm); 2450 MemoryRegion *mr = ddc->get_memory_region(dimm); 2451 uint64_t size = memory_region_size(mr); 2452 uint64_t addr; 2453 2454 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err); 2455 if (local_err) { 2456 goto out; 2457 } 2458 2459 spapr_del_lmbs(dev, addr, size, &error_abort); 2460 out: 2461 error_propagate(errp, local_err); 2462 } 2463 2464 void *spapr_populate_hotplug_cpu_dt(CPUState *cs, int *fdt_offset, 2465 sPAPRMachineState *spapr) 2466 { 2467 PowerPCCPU *cpu = POWERPC_CPU(cs); 2468 DeviceClass *dc = DEVICE_GET_CLASS(cs); 2469 int id = ppc_get_vcpu_dt_id(cpu); 2470 void *fdt; 2471 int offset, fdt_size; 2472 char *nodename; 2473 2474 fdt = create_device_tree(&fdt_size); 2475 nodename = g_strdup_printf("%s@%x", dc->fw_name, id); 2476 offset = fdt_add_subnode(fdt, 0, nodename); 2477 2478 spapr_populate_cpu_dt(cs, fdt, offset, spapr); 2479 g_free(nodename); 2480 2481 *fdt_offset = offset; 2482 return fdt; 2483 } 2484 2485 static void spapr_machine_device_plug(HotplugHandler *hotplug_dev, 2486 DeviceState *dev, Error **errp) 2487 { 2488 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine()); 2489 2490 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2491 int node; 2492 2493 if (!smc->dr_lmb_enabled) { 2494 error_setg(errp, "Memory hotplug not supported for this machine"); 2495 return; 2496 } 2497 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp); 2498 if (*errp) { 2499 return; 2500 } 2501 if (node < 0 || node >= MAX_NODES) { 2502 error_setg(errp, "Invaild node %d", node); 2503 return; 2504 } 2505 2506 /* 2507 * Currently PowerPC kernel doesn't allow hot-adding memory to 2508 * memory-less node, but instead will silently add the memory 2509 * to the first node that has some memory. This causes two 2510 * unexpected behaviours for the user. 2511 * 2512 * - Memory gets hotplugged to a different node than what the user 2513 * specified. 2514 * - Since pc-dimm subsystem in QEMU still thinks that memory belongs 2515 * to memory-less node, a reboot will set things accordingly 2516 * and the previously hotplugged memory now ends in the right node. 2517 * This appears as if some memory moved from one node to another. 2518 * 2519 * So until kernel starts supporting memory hotplug to memory-less 2520 * nodes, just prevent such attempts upfront in QEMU. 2521 */ 2522 if (nb_numa_nodes && !numa_info[node].node_mem) { 2523 error_setg(errp, "Can't hotplug memory to memory-less node %d", 2524 node); 2525 return; 2526 } 2527 2528 spapr_memory_plug(hotplug_dev, dev, node, errp); 2529 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2530 spapr_core_plug(hotplug_dev, dev, errp); 2531 } 2532 } 2533 2534 static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev, 2535 DeviceState *dev, Error **errp) 2536 { 2537 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2538 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2539 2540 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2541 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2542 spapr_memory_unplug(hotplug_dev, dev, errp); 2543 } else { 2544 error_setg(errp, "Memory hot unplug not supported for this guest"); 2545 } 2546 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2547 if (!mc->query_hotpluggable_cpus) { 2548 error_setg(errp, "CPU hot unplug not supported on this machine"); 2549 return; 2550 } 2551 spapr_core_unplug(hotplug_dev, dev, errp); 2552 } 2553 } 2554 2555 static void spapr_machine_device_unplug_request(HotplugHandler *hotplug_dev, 2556 DeviceState *dev, Error **errp) 2557 { 2558 sPAPRMachineState *sms = SPAPR_MACHINE(qdev_get_machine()); 2559 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 2560 2561 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) { 2562 if (spapr_ovec_test(sms->ov5_cas, OV5_HP_EVT)) { 2563 spapr_memory_unplug_request(hotplug_dev, dev, errp); 2564 } else { 2565 /* NOTE: this means there is a window after guest reset, prior to 2566 * CAS negotiation, where unplug requests will fail due to the 2567 * capability not being detected yet. This is a bit different than 2568 * the case with PCI unplug, where the events will be queued and 2569 * eventually handled by the guest after boot 2570 */ 2571 error_setg(errp, "Memory hot unplug not supported for this guest"); 2572 } 2573 } else if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2574 if (!mc->query_hotpluggable_cpus) { 2575 error_setg(errp, "CPU hot unplug not supported on this machine"); 2576 return; 2577 } 2578 spapr_core_unplug(hotplug_dev, dev, errp); 2579 } 2580 } 2581 2582 static void spapr_machine_device_pre_plug(HotplugHandler *hotplug_dev, 2583 DeviceState *dev, Error **errp) 2584 { 2585 if (object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2586 spapr_core_pre_plug(hotplug_dev, dev, errp); 2587 } 2588 } 2589 2590 static HotplugHandler *spapr_get_hotplug_handler(MachineState *machine, 2591 DeviceState *dev) 2592 { 2593 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) || 2594 object_dynamic_cast(OBJECT(dev), TYPE_SPAPR_CPU_CORE)) { 2595 return HOTPLUG_HANDLER(machine); 2596 } 2597 return NULL; 2598 } 2599 2600 static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index) 2601 { 2602 /* Allocate to NUMA nodes on a "socket" basis (not that concept of 2603 * socket means much for the paravirtualized PAPR platform) */ 2604 return cpu_index / smp_threads / smp_cores; 2605 } 2606 2607 static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine) 2608 { 2609 int i; 2610 HotpluggableCPUList *head = NULL; 2611 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2612 int spapr_max_cores = max_cpus / smp_threads; 2613 2614 for (i = 0; i < spapr_max_cores; i++) { 2615 HotpluggableCPUList *list_item = g_new0(typeof(*list_item), 1); 2616 HotpluggableCPU *cpu_item = g_new0(typeof(*cpu_item), 1); 2617 CpuInstanceProperties *cpu_props = g_new0(typeof(*cpu_props), 1); 2618 2619 cpu_item->type = spapr_get_cpu_core_type(machine->cpu_model); 2620 cpu_item->vcpus_count = smp_threads; 2621 cpu_props->has_core_id = true; 2622 cpu_props->core_id = i * smp_threads; 2623 /* TODO: add 'has_node/node' here to describe 2624 to which node core belongs */ 2625 2626 cpu_item->props = cpu_props; 2627 if (spapr->cores[i]) { 2628 cpu_item->has_qom_path = true; 2629 cpu_item->qom_path = object_get_canonical_path(spapr->cores[i]); 2630 } 2631 list_item->value = cpu_item; 2632 list_item->next = head; 2633 head = list_item; 2634 } 2635 return head; 2636 } 2637 2638 static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index, 2639 uint64_t *buid, hwaddr *pio, 2640 hwaddr *mmio32, hwaddr *mmio64, 2641 unsigned n_dma, uint32_t *liobns, Error **errp) 2642 { 2643 /* 2644 * New-style PHB window placement. 2645 * 2646 * Goals: Gives large (1TiB), naturally aligned 64-bit MMIO window 2647 * for each PHB, in addition to 2GiB 32-bit MMIO and 64kiB PIO 2648 * windows. 2649 * 2650 * Some guest kernels can't work with MMIO windows above 1<<46 2651 * (64TiB), so we place up to 31 PHBs in the area 32TiB..64TiB 2652 * 2653 * 32TiB..(33TiB+1984kiB) contains the 64kiB PIO windows for each 2654 * PHB stacked together. (32TiB+2GiB)..(32TiB+64GiB) contains the 2655 * 2GiB 32-bit MMIO windows for each PHB. Then 33..64TiB has the 2656 * 1TiB 64-bit MMIO windows for each PHB. 2657 */ 2658 const uint64_t base_buid = 0x800000020000000ULL; 2659 const int max_phbs = 2660 (SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / SPAPR_PCI_MEM64_WIN_SIZE - 1; 2661 int i; 2662 2663 /* Sanity check natural alignments */ 2664 QEMU_BUILD_BUG_ON((SPAPR_PCI_BASE % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2665 QEMU_BUILD_BUG_ON((SPAPR_PCI_LIMIT % SPAPR_PCI_MEM64_WIN_SIZE) != 0); 2666 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM64_WIN_SIZE % SPAPR_PCI_MEM32_WIN_SIZE) != 0); 2667 QEMU_BUILD_BUG_ON((SPAPR_PCI_MEM32_WIN_SIZE % SPAPR_PCI_IO_WIN_SIZE) != 0); 2668 /* Sanity check bounds */ 2669 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_IO_WIN_SIZE) > SPAPR_PCI_MEM32_WIN_SIZE); 2670 QEMU_BUILD_BUG_ON((max_phbs * SPAPR_PCI_MEM32_WIN_SIZE) > SPAPR_PCI_MEM64_WIN_SIZE); 2671 2672 if (index >= max_phbs) { 2673 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 2674 max_phbs - 1); 2675 return; 2676 } 2677 2678 *buid = base_buid + index; 2679 for (i = 0; i < n_dma; ++i) { 2680 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2681 } 2682 2683 *pio = SPAPR_PCI_BASE + index * SPAPR_PCI_IO_WIN_SIZE; 2684 *mmio32 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM32_WIN_SIZE; 2685 *mmio64 = SPAPR_PCI_BASE + (index + 1) * SPAPR_PCI_MEM64_WIN_SIZE; 2686 } 2687 2688 static void spapr_machine_class_init(ObjectClass *oc, void *data) 2689 { 2690 MachineClass *mc = MACHINE_CLASS(oc); 2691 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc); 2692 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc); 2693 NMIClass *nc = NMI_CLASS(oc); 2694 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 2695 PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_CLASS(oc); 2696 2697 mc->desc = "pSeries Logical Partition (PAPR compliant)"; 2698 2699 /* 2700 * We set up the default / latest behaviour here. The class_init 2701 * functions for the specific versioned machine types can override 2702 * these details for backwards compatibility 2703 */ 2704 mc->init = ppc_spapr_init; 2705 mc->reset = ppc_spapr_reset; 2706 mc->block_default_type = IF_SCSI; 2707 mc->max_cpus = 255; 2708 mc->no_parallel = 1; 2709 mc->default_boot_order = ""; 2710 mc->default_ram_size = 512 * M_BYTE; 2711 mc->kvm_type = spapr_kvm_type; 2712 mc->has_dynamic_sysbus = true; 2713 mc->pci_allow_0_address = true; 2714 mc->get_hotplug_handler = spapr_get_hotplug_handler; 2715 hc->pre_plug = spapr_machine_device_pre_plug; 2716 hc->plug = spapr_machine_device_plug; 2717 hc->unplug = spapr_machine_device_unplug; 2718 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id; 2719 hc->unplug_request = spapr_machine_device_unplug_request; 2720 2721 smc->dr_lmb_enabled = true; 2722 smc->tcg_default_cpu = "POWER8"; 2723 mc->query_hotpluggable_cpus = spapr_query_hotpluggable_cpus; 2724 fwc->get_dev_path = spapr_get_fw_dev_path; 2725 nc->nmi_monitor_handler = spapr_nmi; 2726 smc->phb_placement = spapr_phb_placement; 2727 vhc->hypercall = emulate_spapr_hypercall; 2728 } 2729 2730 static const TypeInfo spapr_machine_info = { 2731 .name = TYPE_SPAPR_MACHINE, 2732 .parent = TYPE_MACHINE, 2733 .abstract = true, 2734 .instance_size = sizeof(sPAPRMachineState), 2735 .instance_init = spapr_machine_initfn, 2736 .instance_finalize = spapr_machine_finalizefn, 2737 .class_size = sizeof(sPAPRMachineClass), 2738 .class_init = spapr_machine_class_init, 2739 .interfaces = (InterfaceInfo[]) { 2740 { TYPE_FW_PATH_PROVIDER }, 2741 { TYPE_NMI }, 2742 { TYPE_HOTPLUG_HANDLER }, 2743 { TYPE_PPC_VIRTUAL_HYPERVISOR }, 2744 { } 2745 }, 2746 }; 2747 2748 #define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \ 2749 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \ 2750 void *data) \ 2751 { \ 2752 MachineClass *mc = MACHINE_CLASS(oc); \ 2753 spapr_machine_##suffix##_class_options(mc); \ 2754 if (latest) { \ 2755 mc->alias = "pseries"; \ 2756 mc->is_default = 1; \ 2757 } \ 2758 } \ 2759 static void spapr_machine_##suffix##_instance_init(Object *obj) \ 2760 { \ 2761 MachineState *machine = MACHINE(obj); \ 2762 spapr_machine_##suffix##_instance_options(machine); \ 2763 } \ 2764 static const TypeInfo spapr_machine_##suffix##_info = { \ 2765 .name = MACHINE_TYPE_NAME("pseries-" verstr), \ 2766 .parent = TYPE_SPAPR_MACHINE, \ 2767 .class_init = spapr_machine_##suffix##_class_init, \ 2768 .instance_init = spapr_machine_##suffix##_instance_init, \ 2769 }; \ 2770 static void spapr_machine_register_##suffix(void) \ 2771 { \ 2772 type_register(&spapr_machine_##suffix##_info); \ 2773 } \ 2774 type_init(spapr_machine_register_##suffix) 2775 2776 /* 2777 * pseries-2.9 2778 */ 2779 static void spapr_machine_2_9_instance_options(MachineState *machine) 2780 { 2781 } 2782 2783 static void spapr_machine_2_9_class_options(MachineClass *mc) 2784 { 2785 /* Defaults for the latest behaviour inherited from the base class */ 2786 } 2787 2788 DEFINE_SPAPR_MACHINE(2_9, "2.9", true); 2789 2790 /* 2791 * pseries-2.8 2792 */ 2793 #define SPAPR_COMPAT_2_8 \ 2794 HW_COMPAT_2_8 2795 2796 static void spapr_machine_2_8_instance_options(MachineState *machine) 2797 { 2798 spapr_machine_2_9_instance_options(machine); 2799 } 2800 2801 static void spapr_machine_2_8_class_options(MachineClass *mc) 2802 { 2803 spapr_machine_2_9_class_options(mc); 2804 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_8); 2805 } 2806 2807 DEFINE_SPAPR_MACHINE(2_8, "2.8", false); 2808 2809 /* 2810 * pseries-2.7 2811 */ 2812 #define SPAPR_COMPAT_2_7 \ 2813 HW_COMPAT_2_7 \ 2814 { \ 2815 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 2816 .property = "mem_win_size", \ 2817 .value = stringify(SPAPR_PCI_2_7_MMIO_WIN_SIZE),\ 2818 }, \ 2819 { \ 2820 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 2821 .property = "mem64_win_size", \ 2822 .value = "0", \ 2823 }, \ 2824 { \ 2825 .driver = TYPE_POWERPC_CPU, \ 2826 .property = "pre-2.8-migration", \ 2827 .value = "on", \ 2828 }, \ 2829 { \ 2830 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE, \ 2831 .property = "pre-2.8-migration", \ 2832 .value = "on", \ 2833 }, 2834 2835 static void phb_placement_2_7(sPAPRMachineState *spapr, uint32_t index, 2836 uint64_t *buid, hwaddr *pio, 2837 hwaddr *mmio32, hwaddr *mmio64, 2838 unsigned n_dma, uint32_t *liobns, Error **errp) 2839 { 2840 /* Legacy PHB placement for pseries-2.7 and earlier machine types */ 2841 const uint64_t base_buid = 0x800000020000000ULL; 2842 const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */ 2843 const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */ 2844 const hwaddr pio_offset = 0x80000000; /* 2 GiB */ 2845 const uint32_t max_index = 255; 2846 const hwaddr phb0_alignment = 0x10000000000ULL; /* 1 TiB */ 2847 2848 uint64_t ram_top = MACHINE(spapr)->ram_size; 2849 hwaddr phb0_base, phb_base; 2850 int i; 2851 2852 /* Do we have hotpluggable memory? */ 2853 if (MACHINE(spapr)->maxram_size > ram_top) { 2854 /* Can't just use maxram_size, because there may be an 2855 * alignment gap between normal and hotpluggable memory 2856 * regions */ 2857 ram_top = spapr->hotplug_memory.base + 2858 memory_region_size(&spapr->hotplug_memory.mr); 2859 } 2860 2861 phb0_base = QEMU_ALIGN_UP(ram_top, phb0_alignment); 2862 2863 if (index > max_index) { 2864 error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)", 2865 max_index); 2866 return; 2867 } 2868 2869 *buid = base_buid + index; 2870 for (i = 0; i < n_dma; ++i) { 2871 liobns[i] = SPAPR_PCI_LIOBN(index, i); 2872 } 2873 2874 phb_base = phb0_base + index * phb_spacing; 2875 *pio = phb_base + pio_offset; 2876 *mmio32 = phb_base + mmio_offset; 2877 /* 2878 * We don't set the 64-bit MMIO window, relying on the PHB's 2879 * fallback behaviour of automatically splitting a large "32-bit" 2880 * window into contiguous 32-bit and 64-bit windows 2881 */ 2882 } 2883 2884 static void spapr_machine_2_7_instance_options(MachineState *machine) 2885 { 2886 sPAPRMachineState *spapr = SPAPR_MACHINE(machine); 2887 2888 spapr_machine_2_8_instance_options(machine); 2889 spapr->use_hotplug_event_source = false; 2890 } 2891 2892 static void spapr_machine_2_7_class_options(MachineClass *mc) 2893 { 2894 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2895 2896 spapr_machine_2_8_class_options(mc); 2897 smc->tcg_default_cpu = "POWER7"; 2898 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_7); 2899 smc->phb_placement = phb_placement_2_7; 2900 } 2901 2902 DEFINE_SPAPR_MACHINE(2_7, "2.7", false); 2903 2904 /* 2905 * pseries-2.6 2906 */ 2907 #define SPAPR_COMPAT_2_6 \ 2908 HW_COMPAT_2_6 \ 2909 { \ 2910 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 2911 .property = "ddw",\ 2912 .value = stringify(off),\ 2913 }, 2914 2915 static void spapr_machine_2_6_instance_options(MachineState *machine) 2916 { 2917 spapr_machine_2_7_instance_options(machine); 2918 } 2919 2920 static void spapr_machine_2_6_class_options(MachineClass *mc) 2921 { 2922 spapr_machine_2_7_class_options(mc); 2923 mc->query_hotpluggable_cpus = NULL; 2924 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_6); 2925 } 2926 2927 DEFINE_SPAPR_MACHINE(2_6, "2.6", false); 2928 2929 /* 2930 * pseries-2.5 2931 */ 2932 #define SPAPR_COMPAT_2_5 \ 2933 HW_COMPAT_2_5 \ 2934 { \ 2935 .driver = "spapr-vlan", \ 2936 .property = "use-rx-buffer-pools", \ 2937 .value = "off", \ 2938 }, 2939 2940 static void spapr_machine_2_5_instance_options(MachineState *machine) 2941 { 2942 spapr_machine_2_6_instance_options(machine); 2943 } 2944 2945 static void spapr_machine_2_5_class_options(MachineClass *mc) 2946 { 2947 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2948 2949 spapr_machine_2_6_class_options(mc); 2950 smc->use_ohci_by_default = true; 2951 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5); 2952 } 2953 2954 DEFINE_SPAPR_MACHINE(2_5, "2.5", false); 2955 2956 /* 2957 * pseries-2.4 2958 */ 2959 #define SPAPR_COMPAT_2_4 \ 2960 HW_COMPAT_2_4 2961 2962 static void spapr_machine_2_4_instance_options(MachineState *machine) 2963 { 2964 spapr_machine_2_5_instance_options(machine); 2965 } 2966 2967 static void spapr_machine_2_4_class_options(MachineClass *mc) 2968 { 2969 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc); 2970 2971 spapr_machine_2_5_class_options(mc); 2972 smc->dr_lmb_enabled = false; 2973 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4); 2974 } 2975 2976 DEFINE_SPAPR_MACHINE(2_4, "2.4", false); 2977 2978 /* 2979 * pseries-2.3 2980 */ 2981 #define SPAPR_COMPAT_2_3 \ 2982 HW_COMPAT_2_3 \ 2983 {\ 2984 .driver = "spapr-pci-host-bridge",\ 2985 .property = "dynamic-reconfiguration",\ 2986 .value = "off",\ 2987 }, 2988 2989 static void spapr_machine_2_3_instance_options(MachineState *machine) 2990 { 2991 spapr_machine_2_4_instance_options(machine); 2992 savevm_skip_section_footers(); 2993 global_state_set_optional(); 2994 savevm_skip_configuration(); 2995 } 2996 2997 static void spapr_machine_2_3_class_options(MachineClass *mc) 2998 { 2999 spapr_machine_2_4_class_options(mc); 3000 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3); 3001 } 3002 DEFINE_SPAPR_MACHINE(2_3, "2.3", false); 3003 3004 /* 3005 * pseries-2.2 3006 */ 3007 3008 #define SPAPR_COMPAT_2_2 \ 3009 HW_COMPAT_2_2 \ 3010 {\ 3011 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\ 3012 .property = "mem_win_size",\ 3013 .value = "0x20000000",\ 3014 }, 3015 3016 static void spapr_machine_2_2_instance_options(MachineState *machine) 3017 { 3018 spapr_machine_2_3_instance_options(machine); 3019 machine->suppress_vmdesc = true; 3020 } 3021 3022 static void spapr_machine_2_2_class_options(MachineClass *mc) 3023 { 3024 spapr_machine_2_3_class_options(mc); 3025 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2); 3026 } 3027 DEFINE_SPAPR_MACHINE(2_2, "2.2", false); 3028 3029 /* 3030 * pseries-2.1 3031 */ 3032 #define SPAPR_COMPAT_2_1 \ 3033 HW_COMPAT_2_1 3034 3035 static void spapr_machine_2_1_instance_options(MachineState *machine) 3036 { 3037 spapr_machine_2_2_instance_options(machine); 3038 } 3039 3040 static void spapr_machine_2_1_class_options(MachineClass *mc) 3041 { 3042 spapr_machine_2_2_class_options(mc); 3043 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1); 3044 } 3045 DEFINE_SPAPR_MACHINE(2_1, "2.1", false); 3046 3047 static void spapr_machine_register_types(void) 3048 { 3049 type_register_static(&spapr_machine_info); 3050 } 3051 3052 type_init(spapr_machine_register_types) 3053