1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "qemu/error-report.h" 7 #include "cpu.h" 8 #include "exec/exec-all.h" 9 #include "helper_regs.h" 10 #include "hw/ppc/spapr.h" 11 #include "mmu-hash64.h" 12 #include "cpu-models.h" 13 #include "trace.h" 14 #include "kvm_ppc.h" 15 #include "hw/ppc/spapr_ovec.h" 16 #include "qemu/error-report.h" 17 #include "mmu-book3s-v3.h" 18 19 struct SPRSyncState { 20 int spr; 21 target_ulong value; 22 target_ulong mask; 23 }; 24 25 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 26 { 27 struct SPRSyncState *s = arg.host_ptr; 28 PowerPCCPU *cpu = POWERPC_CPU(cs); 29 CPUPPCState *env = &cpu->env; 30 31 cpu_synchronize_state(cs); 32 env->spr[s->spr] &= ~s->mask; 33 env->spr[s->spr] |= s->value; 34 } 35 36 static void set_spr(CPUState *cs, int spr, target_ulong value, 37 target_ulong mask) 38 { 39 struct SPRSyncState s = { 40 .spr = spr, 41 .value = value, 42 .mask = mask 43 }; 44 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 45 } 46 47 static bool has_spr(PowerPCCPU *cpu, int spr) 48 { 49 /* We can test whether the SPR is defined by checking for a valid name */ 50 return cpu->env.spr_cb[spr].name != NULL; 51 } 52 53 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 54 { 55 /* 56 * hash value/pteg group index is normalized by HPT mask 57 */ 58 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 59 return false; 60 } 61 return true; 62 } 63 64 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 65 { 66 MachineState *machine = MACHINE(spapr); 67 MemoryHotplugState *hpms = &spapr->hotplug_memory; 68 69 if (addr < machine->ram_size) { 70 return true; 71 } 72 if ((addr >= hpms->base) 73 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 74 return true; 75 } 76 77 return false; 78 } 79 80 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 81 target_ulong opcode, target_ulong *args) 82 { 83 target_ulong flags = args[0]; 84 target_ulong ptex = args[1]; 85 target_ulong pteh = args[2]; 86 target_ulong ptel = args[3]; 87 unsigned apshift; 88 target_ulong raddr; 89 target_ulong slot; 90 const ppc_hash_pte64_t *hptes; 91 92 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 93 if (!apshift) { 94 /* Bad page size encoding */ 95 return H_PARAMETER; 96 } 97 98 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 99 100 if (is_ram_address(spapr, raddr)) { 101 /* Regular RAM - should have WIMG=0010 */ 102 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 103 return H_PARAMETER; 104 } 105 } else { 106 target_ulong wimg_flags; 107 /* Looks like an IO address */ 108 /* FIXME: What WIMG combinations could be sensible for IO? 109 * For now we allow WIMG=010x, but are there others? */ 110 /* FIXME: Should we check against registered IO addresses? */ 111 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 112 113 if (wimg_flags != HPTE64_R_I && 114 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 115 return H_PARAMETER; 116 } 117 } 118 119 pteh &= ~0x60ULL; 120 121 if (!valid_ptex(cpu, ptex)) { 122 return H_PARAMETER; 123 } 124 125 slot = ptex & 7ULL; 126 ptex = ptex & ~7ULL; 127 128 if (likely((flags & H_EXACT) == 0)) { 129 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 130 for (slot = 0; slot < 8; slot++) { 131 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 132 break; 133 } 134 } 135 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 136 if (slot == 8) { 137 return H_PTEG_FULL; 138 } 139 } else { 140 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 141 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 142 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 143 return H_PTEG_FULL; 144 } 145 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 146 } 147 148 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 149 150 args[0] = ptex + slot; 151 return H_SUCCESS; 152 } 153 154 typedef enum { 155 REMOVE_SUCCESS = 0, 156 REMOVE_NOT_FOUND = 1, 157 REMOVE_PARM = 2, 158 REMOVE_HW = 3, 159 } RemoveResult; 160 161 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 162 target_ulong avpn, 163 target_ulong flags, 164 target_ulong *vp, target_ulong *rp) 165 { 166 const ppc_hash_pte64_t *hptes; 167 target_ulong v, r; 168 169 if (!valid_ptex(cpu, ptex)) { 170 return REMOVE_PARM; 171 } 172 173 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 174 v = ppc_hash64_hpte0(cpu, hptes, 0); 175 r = ppc_hash64_hpte1(cpu, hptes, 0); 176 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 177 178 if ((v & HPTE64_V_VALID) == 0 || 179 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 180 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 181 return REMOVE_NOT_FOUND; 182 } 183 *vp = v; 184 *rp = r; 185 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 186 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 187 return REMOVE_SUCCESS; 188 } 189 190 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 191 target_ulong opcode, target_ulong *args) 192 { 193 CPUPPCState *env = &cpu->env; 194 target_ulong flags = args[0]; 195 target_ulong ptex = args[1]; 196 target_ulong avpn = args[2]; 197 RemoveResult ret; 198 199 ret = remove_hpte(cpu, ptex, avpn, flags, 200 &args[0], &args[1]); 201 202 switch (ret) { 203 case REMOVE_SUCCESS: 204 check_tlb_flush(env, true); 205 return H_SUCCESS; 206 207 case REMOVE_NOT_FOUND: 208 return H_NOT_FOUND; 209 210 case REMOVE_PARM: 211 return H_PARAMETER; 212 213 case REMOVE_HW: 214 return H_HARDWARE; 215 } 216 217 g_assert_not_reached(); 218 } 219 220 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 221 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 222 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 223 #define H_BULK_REMOVE_END 0xc000000000000000ULL 224 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 225 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 226 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 227 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 228 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 229 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 230 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 231 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 232 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 233 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 234 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 235 236 #define H_BULK_REMOVE_MAX_BATCH 4 237 238 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 239 target_ulong opcode, target_ulong *args) 240 { 241 CPUPPCState *env = &cpu->env; 242 int i; 243 target_ulong rc = H_SUCCESS; 244 245 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 246 target_ulong *tsh = &args[i*2]; 247 target_ulong tsl = args[i*2 + 1]; 248 target_ulong v, r, ret; 249 250 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 251 break; 252 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 253 return H_PARAMETER; 254 } 255 256 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 257 *tsh |= H_BULK_REMOVE_RESPONSE; 258 259 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 260 *tsh |= H_BULK_REMOVE_PARM; 261 return H_PARAMETER; 262 } 263 264 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 265 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 266 &v, &r); 267 268 *tsh |= ret << 60; 269 270 switch (ret) { 271 case REMOVE_SUCCESS: 272 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 273 break; 274 275 case REMOVE_PARM: 276 rc = H_PARAMETER; 277 goto exit; 278 279 case REMOVE_HW: 280 rc = H_HARDWARE; 281 goto exit; 282 } 283 } 284 exit: 285 check_tlb_flush(env, true); 286 287 return rc; 288 } 289 290 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 291 target_ulong opcode, target_ulong *args) 292 { 293 CPUPPCState *env = &cpu->env; 294 target_ulong flags = args[0]; 295 target_ulong ptex = args[1]; 296 target_ulong avpn = args[2]; 297 const ppc_hash_pte64_t *hptes; 298 target_ulong v, r; 299 300 if (!valid_ptex(cpu, ptex)) { 301 return H_PARAMETER; 302 } 303 304 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 305 v = ppc_hash64_hpte0(cpu, hptes, 0); 306 r = ppc_hash64_hpte1(cpu, hptes, 0); 307 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 308 309 if ((v & HPTE64_V_VALID) == 0 || 310 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 311 return H_NOT_FOUND; 312 } 313 314 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 315 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 316 r |= (flags << 55) & HPTE64_R_PP0; 317 r |= (flags << 48) & HPTE64_R_KEY_HI; 318 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 319 ppc_hash64_store_hpte(cpu, ptex, 320 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 321 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 322 /* Flush the tlb */ 323 check_tlb_flush(env, true); 324 /* Don't need a memory barrier, due to qemu's global lock */ 325 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 326 return H_SUCCESS; 327 } 328 329 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 330 target_ulong opcode, target_ulong *args) 331 { 332 target_ulong flags = args[0]; 333 target_ulong ptex = args[1]; 334 uint8_t *hpte; 335 int i, ridx, n_entries = 1; 336 337 if (!valid_ptex(cpu, ptex)) { 338 return H_PARAMETER; 339 } 340 341 if (flags & H_READ_4) { 342 /* Clear the two low order bits */ 343 ptex &= ~(3ULL); 344 n_entries = 4; 345 } 346 347 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 348 349 for (i = 0, ridx = 0; i < n_entries; i++) { 350 args[ridx++] = ldq_p(hpte); 351 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 352 hpte += HASH_PTE_SIZE_64; 353 } 354 355 return H_SUCCESS; 356 } 357 358 struct sPAPRPendingHPT { 359 /* These fields are read-only after initialization */ 360 int shift; 361 QemuThread thread; 362 363 /* These fields are protected by the BQL */ 364 bool complete; 365 366 /* These fields are private to the preparation thread if 367 * !complete, otherwise protected by the BQL */ 368 int ret; 369 void *hpt; 370 }; 371 372 static void free_pending_hpt(sPAPRPendingHPT *pending) 373 { 374 if (pending->hpt) { 375 qemu_vfree(pending->hpt); 376 } 377 378 g_free(pending); 379 } 380 381 static void *hpt_prepare_thread(void *opaque) 382 { 383 sPAPRPendingHPT *pending = opaque; 384 size_t size = 1ULL << pending->shift; 385 386 pending->hpt = qemu_memalign(size, size); 387 if (pending->hpt) { 388 memset(pending->hpt, 0, size); 389 pending->ret = H_SUCCESS; 390 } else { 391 pending->ret = H_NO_MEM; 392 } 393 394 qemu_mutex_lock_iothread(); 395 396 if (SPAPR_MACHINE(qdev_get_machine())->pending_hpt == pending) { 397 /* Ready to go */ 398 pending->complete = true; 399 } else { 400 /* We've been cancelled, clean ourselves up */ 401 free_pending_hpt(pending); 402 } 403 404 qemu_mutex_unlock_iothread(); 405 return NULL; 406 } 407 408 /* Must be called with BQL held */ 409 static void cancel_hpt_prepare(sPAPRMachineState *spapr) 410 { 411 sPAPRPendingHPT *pending = spapr->pending_hpt; 412 413 /* Let the thread know it's cancelled */ 414 spapr->pending_hpt = NULL; 415 416 if (!pending) { 417 /* Nothing to do */ 418 return; 419 } 420 421 if (!pending->complete) { 422 /* thread will clean itself up */ 423 return; 424 } 425 426 free_pending_hpt(pending); 427 } 428 429 /* Convert a return code from the KVM ioctl()s implementing resize HPT 430 * into a PAPR hypercall return code */ 431 static target_ulong resize_hpt_convert_rc(int ret) 432 { 433 if (ret >= 100000) { 434 return H_LONG_BUSY_ORDER_100_SEC; 435 } else if (ret >= 10000) { 436 return H_LONG_BUSY_ORDER_10_SEC; 437 } else if (ret >= 1000) { 438 return H_LONG_BUSY_ORDER_1_SEC; 439 } else if (ret >= 100) { 440 return H_LONG_BUSY_ORDER_100_MSEC; 441 } else if (ret >= 10) { 442 return H_LONG_BUSY_ORDER_10_MSEC; 443 } else if (ret > 0) { 444 return H_LONG_BUSY_ORDER_1_MSEC; 445 } 446 447 switch (ret) { 448 case 0: 449 return H_SUCCESS; 450 case -EPERM: 451 return H_AUTHORITY; 452 case -EINVAL: 453 return H_PARAMETER; 454 case -ENXIO: 455 return H_CLOSED; 456 case -ENOSPC: 457 return H_PTEG_FULL; 458 case -EBUSY: 459 return H_BUSY; 460 case -ENOMEM: 461 return H_NO_MEM; 462 default: 463 return H_HARDWARE; 464 } 465 } 466 467 static target_ulong h_resize_hpt_prepare(PowerPCCPU *cpu, 468 sPAPRMachineState *spapr, 469 target_ulong opcode, 470 target_ulong *args) 471 { 472 target_ulong flags = args[0]; 473 int shift = args[1]; 474 sPAPRPendingHPT *pending = spapr->pending_hpt; 475 uint64_t current_ram_size = MACHINE(spapr)->ram_size; 476 int rc; 477 478 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 479 return H_AUTHORITY; 480 } 481 482 if (!spapr->htab_shift) { 483 /* Radix guest, no HPT */ 484 return H_NOT_AVAILABLE; 485 } 486 487 trace_spapr_h_resize_hpt_prepare(flags, shift); 488 489 if (flags != 0) { 490 return H_PARAMETER; 491 } 492 493 if (shift && ((shift < 18) || (shift > 46))) { 494 return H_PARAMETER; 495 } 496 497 current_ram_size = pc_existing_dimms_capacity(&error_fatal); 498 499 /* We only allow the guest to allocate an HPT one order above what 500 * we'd normally give them (to stop a small guest claiming a huge 501 * chunk of resources in the HPT */ 502 if (shift > (spapr_hpt_shift_for_ramsize(current_ram_size) + 1)) { 503 return H_RESOURCE; 504 } 505 506 rc = kvmppc_resize_hpt_prepare(cpu, flags, shift); 507 if (rc != -ENOSYS) { 508 return resize_hpt_convert_rc(rc); 509 } 510 511 if (pending) { 512 /* something already in progress */ 513 if (pending->shift == shift) { 514 /* and it's suitable */ 515 if (pending->complete) { 516 return pending->ret; 517 } else { 518 return H_LONG_BUSY_ORDER_100_MSEC; 519 } 520 } 521 522 /* not suitable, cancel and replace */ 523 cancel_hpt_prepare(spapr); 524 } 525 526 if (!shift) { 527 /* nothing to do */ 528 return H_SUCCESS; 529 } 530 531 /* start new prepare */ 532 533 pending = g_new0(sPAPRPendingHPT, 1); 534 pending->shift = shift; 535 pending->ret = H_HARDWARE; 536 537 qemu_thread_create(&pending->thread, "sPAPR HPT prepare", 538 hpt_prepare_thread, pending, QEMU_THREAD_DETACHED); 539 540 spapr->pending_hpt = pending; 541 542 /* In theory we could estimate the time more accurately based on 543 * the new size, but there's not much point */ 544 return H_LONG_BUSY_ORDER_100_MSEC; 545 } 546 547 static uint64_t new_hpte_load0(void *htab, uint64_t pteg, int slot) 548 { 549 uint8_t *addr = htab; 550 551 addr += pteg * HASH_PTEG_SIZE_64; 552 addr += slot * HASH_PTE_SIZE_64; 553 return ldq_p(addr); 554 } 555 556 static void new_hpte_store(void *htab, uint64_t pteg, int slot, 557 uint64_t pte0, uint64_t pte1) 558 { 559 uint8_t *addr = htab; 560 561 addr += pteg * HASH_PTEG_SIZE_64; 562 addr += slot * HASH_PTE_SIZE_64; 563 564 stq_p(addr, pte0); 565 stq_p(addr + HASH_PTE_SIZE_64 / 2, pte1); 566 } 567 568 static int rehash_hpte(PowerPCCPU *cpu, 569 const ppc_hash_pte64_t *hptes, 570 void *old_hpt, uint64_t oldsize, 571 void *new_hpt, uint64_t newsize, 572 uint64_t pteg, int slot) 573 { 574 uint64_t old_hash_mask = (oldsize >> 7) - 1; 575 uint64_t new_hash_mask = (newsize >> 7) - 1; 576 target_ulong pte0 = ppc_hash64_hpte0(cpu, hptes, slot); 577 target_ulong pte1; 578 uint64_t avpn; 579 unsigned base_pg_shift; 580 uint64_t hash, new_pteg, replace_pte0; 581 582 if (!(pte0 & HPTE64_V_VALID) || !(pte0 & HPTE64_V_BOLTED)) { 583 return H_SUCCESS; 584 } 585 586 pte1 = ppc_hash64_hpte1(cpu, hptes, slot); 587 588 base_pg_shift = ppc_hash64_hpte_page_shift_noslb(cpu, pte0, pte1); 589 assert(base_pg_shift); /* H_ENTER shouldn't allow a bad encoding */ 590 avpn = HPTE64_V_AVPN_VAL(pte0) & ~(((1ULL << base_pg_shift) - 1) >> 23); 591 592 if (pte0 & HPTE64_V_SECONDARY) { 593 pteg = ~pteg; 594 } 595 596 if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_256M) { 597 uint64_t offset, vsid; 598 599 /* We only have 28 - 23 bits of offset in avpn */ 600 offset = (avpn & 0x1f) << 23; 601 vsid = avpn >> 5; 602 /* We can find more bits from the pteg value */ 603 if (base_pg_shift < 23) { 604 offset |= ((vsid ^ pteg) & old_hash_mask) << base_pg_shift; 605 } 606 607 hash = vsid ^ (offset >> base_pg_shift); 608 } else if ((pte0 & HPTE64_V_SSIZE) == HPTE64_V_SSIZE_1T) { 609 uint64_t offset, vsid; 610 611 /* We only have 40 - 23 bits of seg_off in avpn */ 612 offset = (avpn & 0x1ffff) << 23; 613 vsid = avpn >> 17; 614 if (base_pg_shift < 23) { 615 offset |= ((vsid ^ (vsid << 25) ^ pteg) & old_hash_mask) 616 << base_pg_shift; 617 } 618 619 hash = vsid ^ (vsid << 25) ^ (offset >> base_pg_shift); 620 } else { 621 error_report("rehash_pte: Bad segment size in HPTE"); 622 return H_HARDWARE; 623 } 624 625 new_pteg = hash & new_hash_mask; 626 if (pte0 & HPTE64_V_SECONDARY) { 627 assert(~pteg == (hash & old_hash_mask)); 628 new_pteg = ~new_pteg; 629 } else { 630 assert(pteg == (hash & old_hash_mask)); 631 } 632 assert((oldsize != newsize) || (pteg == new_pteg)); 633 replace_pte0 = new_hpte_load0(new_hpt, new_pteg, slot); 634 /* 635 * Strictly speaking, we don't need all these tests, since we only 636 * ever rehash bolted HPTEs. We might in future handle non-bolted 637 * HPTEs, though so make the logic correct for those cases as 638 * well. 639 */ 640 if (replace_pte0 & HPTE64_V_VALID) { 641 assert(newsize < oldsize); 642 if (replace_pte0 & HPTE64_V_BOLTED) { 643 if (pte0 & HPTE64_V_BOLTED) { 644 /* Bolted collision, nothing we can do */ 645 return H_PTEG_FULL; 646 } else { 647 /* Discard this hpte */ 648 return H_SUCCESS; 649 } 650 } 651 } 652 653 new_hpte_store(new_hpt, new_pteg, slot, pte0, pte1); 654 return H_SUCCESS; 655 } 656 657 static int rehash_hpt(PowerPCCPU *cpu, 658 void *old_hpt, uint64_t oldsize, 659 void *new_hpt, uint64_t newsize) 660 { 661 uint64_t n_ptegs = oldsize >> 7; 662 uint64_t pteg; 663 int slot; 664 int rc; 665 666 for (pteg = 0; pteg < n_ptegs; pteg++) { 667 hwaddr ptex = pteg * HPTES_PER_GROUP; 668 const ppc_hash_pte64_t *hptes 669 = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 670 671 if (!hptes) { 672 return H_HARDWARE; 673 } 674 675 for (slot = 0; slot < HPTES_PER_GROUP; slot++) { 676 rc = rehash_hpte(cpu, hptes, old_hpt, oldsize, new_hpt, newsize, 677 pteg, slot); 678 if (rc != H_SUCCESS) { 679 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 680 return rc; 681 } 682 } 683 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 684 } 685 686 return H_SUCCESS; 687 } 688 689 static void do_push_sregs_to_kvm_pr(CPUState *cs, run_on_cpu_data data) 690 { 691 int ret; 692 693 cpu_synchronize_state(cs); 694 695 ret = kvmppc_put_books_sregs(POWERPC_CPU(cs)); 696 if (ret < 0) { 697 error_report("failed to push sregs to KVM: %s", strerror(-ret)); 698 exit(1); 699 } 700 } 701 702 static void push_sregs_to_kvm_pr(sPAPRMachineState *spapr) 703 { 704 CPUState *cs; 705 706 /* 707 * This is a hack for the benefit of KVM PR - it abuses the SDR1 708 * slot in kvm_sregs to communicate the userspace address of the 709 * HPT 710 */ 711 if (!kvm_enabled() || !spapr->htab) { 712 return; 713 } 714 715 CPU_FOREACH(cs) { 716 run_on_cpu(cs, do_push_sregs_to_kvm_pr, RUN_ON_CPU_NULL); 717 } 718 } 719 720 static target_ulong h_resize_hpt_commit(PowerPCCPU *cpu, 721 sPAPRMachineState *spapr, 722 target_ulong opcode, 723 target_ulong *args) 724 { 725 target_ulong flags = args[0]; 726 target_ulong shift = args[1]; 727 sPAPRPendingHPT *pending = spapr->pending_hpt; 728 int rc; 729 size_t newsize; 730 731 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_DISABLED) { 732 return H_AUTHORITY; 733 } 734 735 trace_spapr_h_resize_hpt_commit(flags, shift); 736 737 rc = kvmppc_resize_hpt_commit(cpu, flags, shift); 738 if (rc != -ENOSYS) { 739 return resize_hpt_convert_rc(rc); 740 } 741 742 if (flags != 0) { 743 return H_PARAMETER; 744 } 745 746 if (!pending || (pending->shift != shift)) { 747 /* no matching prepare */ 748 return H_CLOSED; 749 } 750 751 if (!pending->complete) { 752 /* prepare has not completed */ 753 return H_BUSY; 754 } 755 756 /* Shouldn't have got past PREPARE without an HPT */ 757 g_assert(spapr->htab_shift); 758 759 newsize = 1ULL << pending->shift; 760 rc = rehash_hpt(cpu, spapr->htab, HTAB_SIZE(spapr), 761 pending->hpt, newsize); 762 if (rc == H_SUCCESS) { 763 qemu_vfree(spapr->htab); 764 spapr->htab = pending->hpt; 765 spapr->htab_shift = pending->shift; 766 767 push_sregs_to_kvm_pr(spapr); 768 769 pending->hpt = NULL; /* so it's not free()d */ 770 } 771 772 /* Clean up */ 773 spapr->pending_hpt = NULL; 774 free_pending_hpt(pending); 775 776 return rc; 777 } 778 779 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 780 target_ulong opcode, target_ulong *args) 781 { 782 cpu_synchronize_state(CPU(cpu)); 783 cpu->env.spr[SPR_SPRG0] = args[0]; 784 785 return H_SUCCESS; 786 } 787 788 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 789 target_ulong opcode, target_ulong *args) 790 { 791 if (!has_spr(cpu, SPR_DABR)) { 792 return H_HARDWARE; /* DABR register not available */ 793 } 794 cpu_synchronize_state(CPU(cpu)); 795 796 if (has_spr(cpu, SPR_DABRX)) { 797 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 798 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 799 return H_RESERVED_DABR; 800 } 801 802 cpu->env.spr[SPR_DABR] = args[0]; 803 return H_SUCCESS; 804 } 805 806 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 807 target_ulong opcode, target_ulong *args) 808 { 809 target_ulong dabrx = args[1]; 810 811 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 812 return H_HARDWARE; 813 } 814 815 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 816 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 817 return H_PARAMETER; 818 } 819 820 cpu_synchronize_state(CPU(cpu)); 821 cpu->env.spr[SPR_DABRX] = dabrx; 822 cpu->env.spr[SPR_DABR] = args[0]; 823 824 return H_SUCCESS; 825 } 826 827 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 828 target_ulong opcode, target_ulong *args) 829 { 830 target_ulong flags = args[0]; 831 hwaddr dst = args[1]; 832 hwaddr src = args[2]; 833 hwaddr len = TARGET_PAGE_SIZE; 834 uint8_t *pdst, *psrc; 835 target_long ret = H_SUCCESS; 836 837 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 838 | H_COPY_PAGE | H_ZERO_PAGE)) { 839 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 840 flags); 841 return H_PARAMETER; 842 } 843 844 /* Map-in destination */ 845 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 846 return H_PARAMETER; 847 } 848 pdst = cpu_physical_memory_map(dst, &len, 1); 849 if (!pdst || len != TARGET_PAGE_SIZE) { 850 return H_PARAMETER; 851 } 852 853 if (flags & H_COPY_PAGE) { 854 /* Map-in source, copy to destination, and unmap source again */ 855 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 856 ret = H_PARAMETER; 857 goto unmap_out; 858 } 859 psrc = cpu_physical_memory_map(src, &len, 0); 860 if (!psrc || len != TARGET_PAGE_SIZE) { 861 ret = H_PARAMETER; 862 goto unmap_out; 863 } 864 memcpy(pdst, psrc, len); 865 cpu_physical_memory_unmap(psrc, len, 0, len); 866 } else if (flags & H_ZERO_PAGE) { 867 memset(pdst, 0, len); /* Just clear the destination page */ 868 } 869 870 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 871 kvmppc_dcbst_range(cpu, pdst, len); 872 } 873 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 874 if (kvm_enabled()) { 875 kvmppc_icbi_range(cpu, pdst, len); 876 } else { 877 tb_flush(CPU(cpu)); 878 } 879 } 880 881 unmap_out: 882 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 883 return ret; 884 } 885 886 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 887 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 888 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 889 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 890 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 891 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 892 893 #define VPA_MIN_SIZE 640 894 #define VPA_SIZE_OFFSET 0x4 895 #define VPA_SHARED_PROC_OFFSET 0x9 896 #define VPA_SHARED_PROC_VAL 0x2 897 898 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 899 { 900 CPUState *cs = CPU(ppc_env_get_cpu(env)); 901 uint16_t size; 902 uint8_t tmp; 903 904 if (vpa == 0) { 905 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 906 return H_HARDWARE; 907 } 908 909 if (vpa % env->dcache_line_size) { 910 return H_PARAMETER; 911 } 912 /* FIXME: bounds check the address */ 913 914 size = lduw_be_phys(cs->as, vpa + 0x4); 915 916 if (size < VPA_MIN_SIZE) { 917 return H_PARAMETER; 918 } 919 920 /* VPA is not allowed to cross a page boundary */ 921 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 922 return H_PARAMETER; 923 } 924 925 env->vpa_addr = vpa; 926 927 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 928 tmp |= VPA_SHARED_PROC_VAL; 929 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 930 931 return H_SUCCESS; 932 } 933 934 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 935 { 936 if (env->slb_shadow_addr) { 937 return H_RESOURCE; 938 } 939 940 if (env->dtl_addr) { 941 return H_RESOURCE; 942 } 943 944 env->vpa_addr = 0; 945 return H_SUCCESS; 946 } 947 948 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 949 { 950 CPUState *cs = CPU(ppc_env_get_cpu(env)); 951 uint32_t size; 952 953 if (addr == 0) { 954 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 955 return H_HARDWARE; 956 } 957 958 size = ldl_be_phys(cs->as, addr + 0x4); 959 if (size < 0x8) { 960 return H_PARAMETER; 961 } 962 963 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 964 return H_PARAMETER; 965 } 966 967 if (!env->vpa_addr) { 968 return H_RESOURCE; 969 } 970 971 env->slb_shadow_addr = addr; 972 env->slb_shadow_size = size; 973 974 return H_SUCCESS; 975 } 976 977 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 978 { 979 env->slb_shadow_addr = 0; 980 env->slb_shadow_size = 0; 981 return H_SUCCESS; 982 } 983 984 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 985 { 986 CPUState *cs = CPU(ppc_env_get_cpu(env)); 987 uint32_t size; 988 989 if (addr == 0) { 990 hcall_dprintf("Can't cope with DTL at logical 0\n"); 991 return H_HARDWARE; 992 } 993 994 size = ldl_be_phys(cs->as, addr + 0x4); 995 996 if (size < 48) { 997 return H_PARAMETER; 998 } 999 1000 if (!env->vpa_addr) { 1001 return H_RESOURCE; 1002 } 1003 1004 env->dtl_addr = addr; 1005 env->dtl_size = size; 1006 1007 return H_SUCCESS; 1008 } 1009 1010 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 1011 { 1012 env->dtl_addr = 0; 1013 env->dtl_size = 0; 1014 1015 return H_SUCCESS; 1016 } 1017 1018 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1019 target_ulong opcode, target_ulong *args) 1020 { 1021 target_ulong flags = args[0]; 1022 target_ulong procno = args[1]; 1023 target_ulong vpa = args[2]; 1024 target_ulong ret = H_PARAMETER; 1025 CPUPPCState *tenv; 1026 PowerPCCPU *tcpu; 1027 1028 tcpu = spapr_find_cpu(procno); 1029 if (!tcpu) { 1030 return H_PARAMETER; 1031 } 1032 tenv = &tcpu->env; 1033 1034 switch (flags) { 1035 case FLAGS_REGISTER_VPA: 1036 ret = register_vpa(tenv, vpa); 1037 break; 1038 1039 case FLAGS_DEREGISTER_VPA: 1040 ret = deregister_vpa(tenv, vpa); 1041 break; 1042 1043 case FLAGS_REGISTER_SLBSHADOW: 1044 ret = register_slb_shadow(tenv, vpa); 1045 break; 1046 1047 case FLAGS_DEREGISTER_SLBSHADOW: 1048 ret = deregister_slb_shadow(tenv, vpa); 1049 break; 1050 1051 case FLAGS_REGISTER_DTL: 1052 ret = register_dtl(tenv, vpa); 1053 break; 1054 1055 case FLAGS_DEREGISTER_DTL: 1056 ret = deregister_dtl(tenv, vpa); 1057 break; 1058 } 1059 1060 return ret; 1061 } 1062 1063 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1064 target_ulong opcode, target_ulong *args) 1065 { 1066 CPUPPCState *env = &cpu->env; 1067 CPUState *cs = CPU(cpu); 1068 1069 env->msr |= (1ULL << MSR_EE); 1070 hreg_compute_hflags(env); 1071 if (!cpu_has_work(cs)) { 1072 cs->halted = 1; 1073 cs->exception_index = EXCP_HLT; 1074 cs->exit_request = 1; 1075 } 1076 return H_SUCCESS; 1077 } 1078 1079 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1080 target_ulong opcode, target_ulong *args) 1081 { 1082 target_ulong rtas_r3 = args[0]; 1083 uint32_t token = rtas_ld(rtas_r3, 0); 1084 uint32_t nargs = rtas_ld(rtas_r3, 1); 1085 uint32_t nret = rtas_ld(rtas_r3, 2); 1086 1087 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 1088 nret, rtas_r3 + 12 + 4*nargs); 1089 } 1090 1091 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1092 target_ulong opcode, target_ulong *args) 1093 { 1094 CPUState *cs = CPU(cpu); 1095 target_ulong size = args[0]; 1096 target_ulong addr = args[1]; 1097 1098 switch (size) { 1099 case 1: 1100 args[0] = ldub_phys(cs->as, addr); 1101 return H_SUCCESS; 1102 case 2: 1103 args[0] = lduw_phys(cs->as, addr); 1104 return H_SUCCESS; 1105 case 4: 1106 args[0] = ldl_phys(cs->as, addr); 1107 return H_SUCCESS; 1108 case 8: 1109 args[0] = ldq_phys(cs->as, addr); 1110 return H_SUCCESS; 1111 } 1112 return H_PARAMETER; 1113 } 1114 1115 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1116 target_ulong opcode, target_ulong *args) 1117 { 1118 CPUState *cs = CPU(cpu); 1119 1120 target_ulong size = args[0]; 1121 target_ulong addr = args[1]; 1122 target_ulong val = args[2]; 1123 1124 switch (size) { 1125 case 1: 1126 stb_phys(cs->as, addr, val); 1127 return H_SUCCESS; 1128 case 2: 1129 stw_phys(cs->as, addr, val); 1130 return H_SUCCESS; 1131 case 4: 1132 stl_phys(cs->as, addr, val); 1133 return H_SUCCESS; 1134 case 8: 1135 stq_phys(cs->as, addr, val); 1136 return H_SUCCESS; 1137 } 1138 return H_PARAMETER; 1139 } 1140 1141 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1142 target_ulong opcode, target_ulong *args) 1143 { 1144 CPUState *cs = CPU(cpu); 1145 1146 target_ulong dst = args[0]; /* Destination address */ 1147 target_ulong src = args[1]; /* Source address */ 1148 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 1149 target_ulong count = args[3]; /* Element count */ 1150 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 1151 uint64_t tmp; 1152 unsigned int mask = (1 << esize) - 1; 1153 int step = 1 << esize; 1154 1155 if (count > 0x80000000) { 1156 return H_PARAMETER; 1157 } 1158 1159 if ((dst & mask) || (src & mask) || (op > 1)) { 1160 return H_PARAMETER; 1161 } 1162 1163 if (dst >= src && dst < (src + (count << esize))) { 1164 dst = dst + ((count - 1) << esize); 1165 src = src + ((count - 1) << esize); 1166 step = -step; 1167 } 1168 1169 while (count--) { 1170 switch (esize) { 1171 case 0: 1172 tmp = ldub_phys(cs->as, src); 1173 break; 1174 case 1: 1175 tmp = lduw_phys(cs->as, src); 1176 break; 1177 case 2: 1178 tmp = ldl_phys(cs->as, src); 1179 break; 1180 case 3: 1181 tmp = ldq_phys(cs->as, src); 1182 break; 1183 default: 1184 return H_PARAMETER; 1185 } 1186 if (op == 1) { 1187 tmp = ~tmp; 1188 } 1189 switch (esize) { 1190 case 0: 1191 stb_phys(cs->as, dst, tmp); 1192 break; 1193 case 1: 1194 stw_phys(cs->as, dst, tmp); 1195 break; 1196 case 2: 1197 stl_phys(cs->as, dst, tmp); 1198 break; 1199 case 3: 1200 stq_phys(cs->as, dst, tmp); 1201 break; 1202 } 1203 dst = dst + step; 1204 src = src + step; 1205 } 1206 1207 return H_SUCCESS; 1208 } 1209 1210 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1211 target_ulong opcode, target_ulong *args) 1212 { 1213 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1214 return H_SUCCESS; 1215 } 1216 1217 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1218 target_ulong opcode, target_ulong *args) 1219 { 1220 /* Nothing to do on emulation, KVM will trap this in the kernel */ 1221 return H_SUCCESS; 1222 } 1223 1224 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 1225 target_ulong mflags, 1226 target_ulong value1, 1227 target_ulong value2) 1228 { 1229 CPUState *cs; 1230 1231 if (value1) { 1232 return H_P3; 1233 } 1234 if (value2) { 1235 return H_P4; 1236 } 1237 1238 switch (mflags) { 1239 case H_SET_MODE_ENDIAN_BIG: 1240 CPU_FOREACH(cs) { 1241 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 1242 } 1243 spapr_pci_switch_vga(true); 1244 return H_SUCCESS; 1245 1246 case H_SET_MODE_ENDIAN_LITTLE: 1247 CPU_FOREACH(cs) { 1248 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 1249 } 1250 spapr_pci_switch_vga(false); 1251 return H_SUCCESS; 1252 } 1253 1254 return H_UNSUPPORTED_FLAG; 1255 } 1256 1257 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 1258 target_ulong mflags, 1259 target_ulong value1, 1260 target_ulong value2) 1261 { 1262 CPUState *cs; 1263 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 1264 1265 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 1266 return H_P2; 1267 } 1268 if (value1) { 1269 return H_P3; 1270 } 1271 if (value2) { 1272 return H_P4; 1273 } 1274 1275 if (mflags == AIL_RESERVED) { 1276 return H_UNSUPPORTED_FLAG; 1277 } 1278 1279 CPU_FOREACH(cs) { 1280 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 1281 } 1282 1283 return H_SUCCESS; 1284 } 1285 1286 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1287 target_ulong opcode, target_ulong *args) 1288 { 1289 target_ulong resource = args[1]; 1290 target_ulong ret = H_P2; 1291 1292 switch (resource) { 1293 case H_SET_MODE_RESOURCE_LE: 1294 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 1295 break; 1296 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 1297 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 1298 args[2], args[3]); 1299 break; 1300 } 1301 1302 return ret; 1303 } 1304 1305 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1306 target_ulong opcode, target_ulong *args) 1307 { 1308 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1309 opcode, " (H_CLEAN_SLB)"); 1310 return H_FUNCTION; 1311 } 1312 1313 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 1314 target_ulong opcode, target_ulong *args) 1315 { 1316 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 1317 opcode, " (H_INVALIDATE_PID)"); 1318 return H_FUNCTION; 1319 } 1320 1321 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 1322 uint64_t patbe_old, uint64_t patbe_new) 1323 { 1324 /* 1325 * We have 4 Options: 1326 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 1327 * HASH->RADIX : Free HPT 1328 * RADIX->HASH : Allocate HPT 1329 * NOTHING->HASH : Allocate HPT 1330 * Note: NOTHING implies the case where we said the guest could choose 1331 * later and so assumed radix and now it's called H_REG_PROC_TBL 1332 */ 1333 1334 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 1335 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 1336 } else if (!(patbe_old & PATBE1_GR)) { 1337 /* HASH->RADIX : Free HPT */ 1338 spapr_free_hpt(spapr); 1339 } else if (!(patbe_new & PATBE1_GR)) { 1340 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 1341 spapr_setup_hpt_and_vrma(spapr); 1342 } 1343 return; 1344 } 1345 1346 #define FLAGS_MASK 0x01FULL 1347 #define FLAG_MODIFY 0x10 1348 #define FLAG_REGISTER 0x08 1349 #define FLAG_RADIX 0x04 1350 #define FLAG_HASH_PROC_TBL 0x02 1351 #define FLAG_GTSE 0x01 1352 1353 static target_ulong h_register_process_table(PowerPCCPU *cpu, 1354 sPAPRMachineState *spapr, 1355 target_ulong opcode, 1356 target_ulong *args) 1357 { 1358 CPUState *cs; 1359 target_ulong flags = args[0]; 1360 target_ulong proc_tbl = args[1]; 1361 target_ulong page_size = args[2]; 1362 target_ulong table_size = args[3]; 1363 uint64_t cproc; 1364 1365 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 1366 return H_PARAMETER; 1367 } 1368 if (flags & FLAG_MODIFY) { 1369 if (flags & FLAG_REGISTER) { 1370 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 1371 if (proc_tbl & 0xfff || proc_tbl >> 60) { 1372 return H_P2; 1373 } else if (page_size) { 1374 return H_P3; 1375 } else if (table_size > 24) { 1376 return H_P4; 1377 } 1378 cproc = PATBE1_GR | proc_tbl | table_size; 1379 } else { /* Register new HPT process table */ 1380 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 1381 /* TODO - Not Supported */ 1382 /* Technically caused by flag bits => H_PARAMETER */ 1383 return H_PARAMETER; 1384 } else { /* Hash with SLB */ 1385 if (proc_tbl >> 38) { 1386 return H_P2; 1387 } else if (page_size & ~0x7) { 1388 return H_P3; 1389 } else if (table_size > 24) { 1390 return H_P4; 1391 } 1392 } 1393 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 1394 } 1395 1396 } else { /* Deregister current process table */ 1397 /* Set to benign value: (current GR) | 0. This allows 1398 * deregistration in KVM to succeed even if the radix bit in flags 1399 * doesn't match the radix bit in the old PATB. */ 1400 cproc = spapr->patb_entry & PATBE1_GR; 1401 } 1402 } else { /* Maintain current registration */ 1403 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 1404 /* Technically caused by flag bits => H_PARAMETER */ 1405 return H_PARAMETER; /* Existing Process Table Mismatch */ 1406 } 1407 cproc = spapr->patb_entry; 1408 } 1409 1410 /* Check if we need to setup OR free the hpt */ 1411 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 1412 1413 spapr->patb_entry = cproc; /* Save new process table */ 1414 1415 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 1416 CPU_FOREACH(cs) { 1417 set_spr(cs, SPR_LPCR, 1418 ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 1419 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 1420 LPCR_UPRT | LPCR_GTSE); 1421 } 1422 1423 if (kvm_enabled()) { 1424 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1425 flags & FLAG_GTSE, cproc); 1426 } 1427 return H_SUCCESS; 1428 } 1429 1430 #define H_SIGNAL_SYS_RESET_ALL -1 1431 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1432 1433 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1434 sPAPRMachineState *spapr, 1435 target_ulong opcode, target_ulong *args) 1436 { 1437 target_long target = args[0]; 1438 CPUState *cs; 1439 1440 if (target < 0) { 1441 /* Broadcast */ 1442 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1443 return H_PARAMETER; 1444 } 1445 1446 CPU_FOREACH(cs) { 1447 PowerPCCPU *c = POWERPC_CPU(cs); 1448 1449 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1450 if (c == cpu) { 1451 continue; 1452 } 1453 } 1454 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1455 } 1456 return H_SUCCESS; 1457 1458 } else { 1459 /* Unicast */ 1460 cs = CPU(spapr_find_cpu(target)); 1461 if (cs) { 1462 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1463 return H_SUCCESS; 1464 } 1465 return H_PARAMETER; 1466 } 1467 } 1468 1469 static uint32_t cas_check_pvr(sPAPRMachineState *spapr, PowerPCCPU *cpu, 1470 target_ulong *addr, bool *raw_mode_supported, 1471 Error **errp) 1472 { 1473 bool explicit_match = false; /* Matched the CPU's real PVR */ 1474 uint32_t max_compat = spapr->max_compat_pvr; 1475 uint32_t best_compat = 0; 1476 int i; 1477 1478 /* 1479 * We scan the supplied table of PVRs looking for two things 1480 * 1. Is our real CPU PVR in the list? 1481 * 2. What's the "best" listed logical PVR 1482 */ 1483 for (i = 0; i < 512; ++i) { 1484 uint32_t pvr, pvr_mask; 1485 1486 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1487 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1488 *addr += 8; 1489 1490 if (~pvr_mask & pvr) { 1491 break; /* Terminator record */ 1492 } 1493 1494 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1495 explicit_match = true; 1496 } else { 1497 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1498 best_compat = pvr; 1499 } 1500 } 1501 } 1502 1503 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1504 /* We couldn't find a suitable compatibility mode, and either 1505 * the guest doesn't support "raw" mode for this CPU, or raw 1506 * mode is disabled because a maximum compat mode is set */ 1507 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1508 return 0; 1509 } 1510 1511 *raw_mode_supported = explicit_match; 1512 1513 /* Parsing finished */ 1514 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1515 1516 return best_compat; 1517 } 1518 1519 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1520 sPAPRMachineState *spapr, 1521 target_ulong opcode, 1522 target_ulong *args) 1523 { 1524 /* Working address in data buffer */ 1525 target_ulong addr = ppc64_phys_to_real(args[0]); 1526 target_ulong ov_table; 1527 uint32_t cas_pvr; 1528 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1529 bool guest_radix; 1530 Error *local_err = NULL; 1531 bool raw_mode_supported = false; 1532 1533 cas_pvr = cas_check_pvr(spapr, cpu, &addr, &raw_mode_supported, &local_err); 1534 if (local_err) { 1535 error_report_err(local_err); 1536 return H_HARDWARE; 1537 } 1538 1539 /* Update CPUs */ 1540 if (cpu->compat_pvr != cas_pvr) { 1541 ppc_set_compat_all(cas_pvr, &local_err); 1542 if (local_err) { 1543 /* We fail to set compat mode (likely because running with KVM PR), 1544 * but maybe we can fallback to raw mode if the guest supports it. 1545 */ 1546 if (!raw_mode_supported) { 1547 error_report_err(local_err); 1548 return H_HARDWARE; 1549 } 1550 local_err = NULL; 1551 } 1552 } 1553 1554 /* For the future use: here @ov_table points to the first option vector */ 1555 ov_table = addr; 1556 1557 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1558 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1559 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1560 error_report("guest requested hash and radix MMU, which is invalid."); 1561 exit(EXIT_FAILURE); 1562 } 1563 /* The radix/hash bit in byte 24 requires special handling: */ 1564 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1565 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1566 1567 /* 1568 * HPT resizing is a bit of a special case, because when enabled 1569 * we assume an HPT guest will support it until it says it 1570 * doesn't, instead of assuming it won't support it until it says 1571 * it does. Strictly speaking that approach could break for 1572 * guests which don't make a CAS call, but those are so old we 1573 * don't care about them. Without that assumption we'd have to 1574 * make at least a temporary allocation of an HPT sized for max 1575 * memory, which could be impossibly difficult under KVM HV if 1576 * maxram is large. 1577 */ 1578 if (!guest_radix && !spapr_ovec_test(ov5_guest, OV5_HPT_RESIZE)) { 1579 int maxshift = spapr_hpt_shift_for_ramsize(MACHINE(spapr)->maxram_size); 1580 1581 if (spapr->resize_hpt == SPAPR_RESIZE_HPT_REQUIRED) { 1582 error_report( 1583 "h_client_architecture_support: Guest doesn't support HPT resizing, but resize-hpt=required"); 1584 exit(1); 1585 } 1586 1587 if (spapr->htab_shift < maxshift) { 1588 /* Guest doesn't know about HPT resizing, so we 1589 * pre-emptively resize for the maximum permitted RAM. At 1590 * the point this is called, nothing should have been 1591 * entered into the existing HPT */ 1592 spapr_reallocate_hpt(spapr, maxshift, &error_fatal); 1593 push_sregs_to_kvm_pr(spapr); 1594 } 1595 } 1596 1597 /* NOTE: there are actually a number of ov5 bits where input from the 1598 * guest is always zero, and the platform/QEMU enables them independently 1599 * of guest input. To model these properly we'd want some sort of mask, 1600 * but since they only currently apply to memory migration as defined 1601 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1602 * to worry about this for now. 1603 */ 1604 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1605 1606 /* also clear the radix/hash bit from the current ov5_cas bits to 1607 * be in sync with the newly ov5 bits. Else the radix bit will be 1608 * seen as being removed and this will generate a reset loop 1609 */ 1610 spapr_ovec_clear(ov5_cas_old, OV5_MMU_RADIX_300); 1611 1612 /* full range of negotiated ov5 capabilities */ 1613 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1614 spapr_ovec_cleanup(ov5_guest); 1615 /* capabilities that have been added since CAS-generated guest reset. 1616 * if capabilities have since been removed, generate another reset 1617 */ 1618 ov5_updates = spapr_ovec_new(); 1619 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1620 ov5_cas_old, spapr->ov5_cas); 1621 /* Now that processing is finished, set the radix/hash bit for the 1622 * guest if it requested a valid mode; otherwise terminate the boot. */ 1623 if (guest_radix) { 1624 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1625 error_report("Guest requested unavailable MMU mode (radix)."); 1626 exit(EXIT_FAILURE); 1627 } 1628 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1629 } else { 1630 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1631 && !kvmppc_has_cap_mmu_hash_v3()) { 1632 error_report("Guest requested unavailable MMU mode (hash)."); 1633 exit(EXIT_FAILURE); 1634 } 1635 } 1636 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1637 OV1_PPC_3_00); 1638 if (!spapr->cas_reboot) { 1639 spapr->cas_reboot = 1640 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1641 ov5_updates) != 0); 1642 } 1643 spapr_ovec_cleanup(ov5_updates); 1644 1645 if (spapr->cas_reboot) { 1646 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1647 } else { 1648 /* If ppc_spapr_reset() did not set up a HPT but one is necessary 1649 * (because the guest isn't going to use radix) then set it up here. */ 1650 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1651 /* legacy hash or new hash: */ 1652 spapr_setup_hpt_and_vrma(spapr); 1653 } 1654 } 1655 1656 return H_SUCCESS; 1657 } 1658 1659 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1660 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1661 1662 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1663 { 1664 spapr_hcall_fn *slot; 1665 1666 if (opcode <= MAX_HCALL_OPCODE) { 1667 assert((opcode & 0x3) == 0); 1668 1669 slot = &papr_hypercall_table[opcode / 4]; 1670 } else { 1671 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1672 1673 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1674 } 1675 1676 assert(!(*slot)); 1677 *slot = fn; 1678 } 1679 1680 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1681 target_ulong *args) 1682 { 1683 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1684 1685 if ((opcode <= MAX_HCALL_OPCODE) 1686 && ((opcode & 0x3) == 0)) { 1687 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1688 1689 if (fn) { 1690 return fn(cpu, spapr, opcode, args); 1691 } 1692 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1693 (opcode <= KVMPPC_HCALL_MAX)) { 1694 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1695 1696 if (fn) { 1697 return fn(cpu, spapr, opcode, args); 1698 } 1699 } 1700 1701 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1702 opcode); 1703 return H_FUNCTION; 1704 } 1705 1706 static void hypercall_register_types(void) 1707 { 1708 /* hcall-pft */ 1709 spapr_register_hypercall(H_ENTER, h_enter); 1710 spapr_register_hypercall(H_REMOVE, h_remove); 1711 spapr_register_hypercall(H_PROTECT, h_protect); 1712 spapr_register_hypercall(H_READ, h_read); 1713 1714 /* hcall-bulk */ 1715 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1716 1717 /* hcall-hpt-resize */ 1718 spapr_register_hypercall(H_RESIZE_HPT_PREPARE, h_resize_hpt_prepare); 1719 spapr_register_hypercall(H_RESIZE_HPT_COMMIT, h_resize_hpt_commit); 1720 1721 /* hcall-splpar */ 1722 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1723 spapr_register_hypercall(H_CEDE, h_cede); 1724 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1725 1726 /* processor register resource access h-calls */ 1727 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1728 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1729 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1730 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1731 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1732 1733 /* In Memory Table MMU h-calls */ 1734 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1735 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1736 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1737 1738 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1739 * here between the "CI" and the "CACHE" variants, they will use whatever 1740 * mapping attributes qemu is using. When using KVM, the kernel will 1741 * enforce the attributes more strongly 1742 */ 1743 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1744 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1745 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1746 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1747 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1748 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1749 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1750 1751 /* qemu/KVM-PPC specific hcalls */ 1752 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1753 1754 /* ibm,client-architecture-support support */ 1755 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1756 } 1757 1758 type_init(hypercall_register_types) 1759