1 #include "qemu/osdep.h" 2 #include "qapi/error.h" 3 #include "sysemu/hw_accel.h" 4 #include "sysemu/sysemu.h" 5 #include "qemu/log.h" 6 #include "cpu.h" 7 #include "exec/exec-all.h" 8 #include "helper_regs.h" 9 #include "hw/ppc/spapr.h" 10 #include "mmu-hash64.h" 11 #include "cpu-models.h" 12 #include "trace.h" 13 #include "kvm_ppc.h" 14 #include "hw/ppc/spapr_ovec.h" 15 #include "qemu/error-report.h" 16 #include "mmu-book3s-v3.h" 17 18 struct SPRSyncState { 19 int spr; 20 target_ulong value; 21 target_ulong mask; 22 }; 23 24 static void do_spr_sync(CPUState *cs, run_on_cpu_data arg) 25 { 26 struct SPRSyncState *s = arg.host_ptr; 27 PowerPCCPU *cpu = POWERPC_CPU(cs); 28 CPUPPCState *env = &cpu->env; 29 30 cpu_synchronize_state(cs); 31 env->spr[s->spr] &= ~s->mask; 32 env->spr[s->spr] |= s->value; 33 } 34 35 static void set_spr(CPUState *cs, int spr, target_ulong value, 36 target_ulong mask) 37 { 38 struct SPRSyncState s = { 39 .spr = spr, 40 .value = value, 41 .mask = mask 42 }; 43 run_on_cpu(cs, do_spr_sync, RUN_ON_CPU_HOST_PTR(&s)); 44 } 45 46 static bool has_spr(PowerPCCPU *cpu, int spr) 47 { 48 /* We can test whether the SPR is defined by checking for a valid name */ 49 return cpu->env.spr_cb[spr].name != NULL; 50 } 51 52 static inline bool valid_ptex(PowerPCCPU *cpu, target_ulong ptex) 53 { 54 /* 55 * hash value/pteg group index is normalized by HPT mask 56 */ 57 if (((ptex & ~7ULL) / HPTES_PER_GROUP) & ~ppc_hash64_hpt_mask(cpu)) { 58 return false; 59 } 60 return true; 61 } 62 63 static bool is_ram_address(sPAPRMachineState *spapr, hwaddr addr) 64 { 65 MachineState *machine = MACHINE(spapr); 66 MemoryHotplugState *hpms = &spapr->hotplug_memory; 67 68 if (addr < machine->ram_size) { 69 return true; 70 } 71 if ((addr >= hpms->base) 72 && ((addr - hpms->base) < memory_region_size(&hpms->mr))) { 73 return true; 74 } 75 76 return false; 77 } 78 79 static target_ulong h_enter(PowerPCCPU *cpu, sPAPRMachineState *spapr, 80 target_ulong opcode, target_ulong *args) 81 { 82 target_ulong flags = args[0]; 83 target_ulong ptex = args[1]; 84 target_ulong pteh = args[2]; 85 target_ulong ptel = args[3]; 86 unsigned apshift; 87 target_ulong raddr; 88 target_ulong slot; 89 const ppc_hash_pte64_t *hptes; 90 91 apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel); 92 if (!apshift) { 93 /* Bad page size encoding */ 94 return H_PARAMETER; 95 } 96 97 raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1); 98 99 if (is_ram_address(spapr, raddr)) { 100 /* Regular RAM - should have WIMG=0010 */ 101 if ((ptel & HPTE64_R_WIMG) != HPTE64_R_M) { 102 return H_PARAMETER; 103 } 104 } else { 105 target_ulong wimg_flags; 106 /* Looks like an IO address */ 107 /* FIXME: What WIMG combinations could be sensible for IO? 108 * For now we allow WIMG=010x, but are there others? */ 109 /* FIXME: Should we check against registered IO addresses? */ 110 wimg_flags = (ptel & (HPTE64_R_W | HPTE64_R_I | HPTE64_R_M)); 111 112 if (wimg_flags != HPTE64_R_I && 113 wimg_flags != (HPTE64_R_I | HPTE64_R_M)) { 114 return H_PARAMETER; 115 } 116 } 117 118 pteh &= ~0x60ULL; 119 120 if (!valid_ptex(cpu, ptex)) { 121 return H_PARAMETER; 122 } 123 124 slot = ptex & 7ULL; 125 ptex = ptex & ~7ULL; 126 127 if (likely((flags & H_EXACT) == 0)) { 128 hptes = ppc_hash64_map_hptes(cpu, ptex, HPTES_PER_GROUP); 129 for (slot = 0; slot < 8; slot++) { 130 if (!(ppc_hash64_hpte0(cpu, hptes, slot) & HPTE64_V_VALID)) { 131 break; 132 } 133 } 134 ppc_hash64_unmap_hptes(cpu, hptes, ptex, HPTES_PER_GROUP); 135 if (slot == 8) { 136 return H_PTEG_FULL; 137 } 138 } else { 139 hptes = ppc_hash64_map_hptes(cpu, ptex + slot, 1); 140 if (ppc_hash64_hpte0(cpu, hptes, 0) & HPTE64_V_VALID) { 141 ppc_hash64_unmap_hptes(cpu, hptes, ptex + slot, 1); 142 return H_PTEG_FULL; 143 } 144 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 145 } 146 147 ppc_hash64_store_hpte(cpu, ptex + slot, pteh | HPTE64_V_HPTE_DIRTY, ptel); 148 149 args[0] = ptex + slot; 150 return H_SUCCESS; 151 } 152 153 typedef enum { 154 REMOVE_SUCCESS = 0, 155 REMOVE_NOT_FOUND = 1, 156 REMOVE_PARM = 2, 157 REMOVE_HW = 3, 158 } RemoveResult; 159 160 static RemoveResult remove_hpte(PowerPCCPU *cpu, target_ulong ptex, 161 target_ulong avpn, 162 target_ulong flags, 163 target_ulong *vp, target_ulong *rp) 164 { 165 const ppc_hash_pte64_t *hptes; 166 target_ulong v, r; 167 168 if (!valid_ptex(cpu, ptex)) { 169 return REMOVE_PARM; 170 } 171 172 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 173 v = ppc_hash64_hpte0(cpu, hptes, 0); 174 r = ppc_hash64_hpte1(cpu, hptes, 0); 175 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 176 177 if ((v & HPTE64_V_VALID) == 0 || 178 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || 179 ((flags & H_ANDCOND) && (v & avpn) != 0)) { 180 return REMOVE_NOT_FOUND; 181 } 182 *vp = v; 183 *rp = r; 184 ppc_hash64_store_hpte(cpu, ptex, HPTE64_V_HPTE_DIRTY, 0); 185 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 186 return REMOVE_SUCCESS; 187 } 188 189 static target_ulong h_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 190 target_ulong opcode, target_ulong *args) 191 { 192 CPUPPCState *env = &cpu->env; 193 target_ulong flags = args[0]; 194 target_ulong ptex = args[1]; 195 target_ulong avpn = args[2]; 196 RemoveResult ret; 197 198 ret = remove_hpte(cpu, ptex, avpn, flags, 199 &args[0], &args[1]); 200 201 switch (ret) { 202 case REMOVE_SUCCESS: 203 check_tlb_flush(env, true); 204 return H_SUCCESS; 205 206 case REMOVE_NOT_FOUND: 207 return H_NOT_FOUND; 208 209 case REMOVE_PARM: 210 return H_PARAMETER; 211 212 case REMOVE_HW: 213 return H_HARDWARE; 214 } 215 216 g_assert_not_reached(); 217 } 218 219 #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL 220 #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL 221 #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL 222 #define H_BULK_REMOVE_END 0xc000000000000000ULL 223 #define H_BULK_REMOVE_CODE 0x3000000000000000ULL 224 #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL 225 #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL 226 #define H_BULK_REMOVE_PARM 0x2000000000000000ULL 227 #define H_BULK_REMOVE_HW 0x3000000000000000ULL 228 #define H_BULK_REMOVE_RC 0x0c00000000000000ULL 229 #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL 230 #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL 231 #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL 232 #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL 233 #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL 234 235 #define H_BULK_REMOVE_MAX_BATCH 4 236 237 static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPRMachineState *spapr, 238 target_ulong opcode, target_ulong *args) 239 { 240 CPUPPCState *env = &cpu->env; 241 int i; 242 target_ulong rc = H_SUCCESS; 243 244 for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { 245 target_ulong *tsh = &args[i*2]; 246 target_ulong tsl = args[i*2 + 1]; 247 target_ulong v, r, ret; 248 249 if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { 250 break; 251 } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { 252 return H_PARAMETER; 253 } 254 255 *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; 256 *tsh |= H_BULK_REMOVE_RESPONSE; 257 258 if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { 259 *tsh |= H_BULK_REMOVE_PARM; 260 return H_PARAMETER; 261 } 262 263 ret = remove_hpte(cpu, *tsh & H_BULK_REMOVE_PTEX, tsl, 264 (*tsh & H_BULK_REMOVE_FLAGS) >> 26, 265 &v, &r); 266 267 *tsh |= ret << 60; 268 269 switch (ret) { 270 case REMOVE_SUCCESS: 271 *tsh |= (r & (HPTE64_R_C | HPTE64_R_R)) << 43; 272 break; 273 274 case REMOVE_PARM: 275 rc = H_PARAMETER; 276 goto exit; 277 278 case REMOVE_HW: 279 rc = H_HARDWARE; 280 goto exit; 281 } 282 } 283 exit: 284 check_tlb_flush(env, true); 285 286 return rc; 287 } 288 289 static target_ulong h_protect(PowerPCCPU *cpu, sPAPRMachineState *spapr, 290 target_ulong opcode, target_ulong *args) 291 { 292 CPUPPCState *env = &cpu->env; 293 target_ulong flags = args[0]; 294 target_ulong ptex = args[1]; 295 target_ulong avpn = args[2]; 296 const ppc_hash_pte64_t *hptes; 297 target_ulong v, r; 298 299 if (!valid_ptex(cpu, ptex)) { 300 return H_PARAMETER; 301 } 302 303 hptes = ppc_hash64_map_hptes(cpu, ptex, 1); 304 v = ppc_hash64_hpte0(cpu, hptes, 0); 305 r = ppc_hash64_hpte1(cpu, hptes, 0); 306 ppc_hash64_unmap_hptes(cpu, hptes, ptex, 1); 307 308 if ((v & HPTE64_V_VALID) == 0 || 309 ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { 310 return H_NOT_FOUND; 311 } 312 313 r &= ~(HPTE64_R_PP0 | HPTE64_R_PP | HPTE64_R_N | 314 HPTE64_R_KEY_HI | HPTE64_R_KEY_LO); 315 r |= (flags << 55) & HPTE64_R_PP0; 316 r |= (flags << 48) & HPTE64_R_KEY_HI; 317 r |= flags & (HPTE64_R_PP | HPTE64_R_N | HPTE64_R_KEY_LO); 318 ppc_hash64_store_hpte(cpu, ptex, 319 (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0); 320 ppc_hash64_tlb_flush_hpte(cpu, ptex, v, r); 321 /* Flush the tlb */ 322 check_tlb_flush(env, true); 323 /* Don't need a memory barrier, due to qemu's global lock */ 324 ppc_hash64_store_hpte(cpu, ptex, v | HPTE64_V_HPTE_DIRTY, r); 325 return H_SUCCESS; 326 } 327 328 static target_ulong h_read(PowerPCCPU *cpu, sPAPRMachineState *spapr, 329 target_ulong opcode, target_ulong *args) 330 { 331 target_ulong flags = args[0]; 332 target_ulong ptex = args[1]; 333 uint8_t *hpte; 334 int i, ridx, n_entries = 1; 335 336 if (!valid_ptex(cpu, ptex)) { 337 return H_PARAMETER; 338 } 339 340 if (flags & H_READ_4) { 341 /* Clear the two low order bits */ 342 ptex &= ~(3ULL); 343 n_entries = 4; 344 } 345 346 hpte = spapr->htab + (ptex * HASH_PTE_SIZE_64); 347 348 for (i = 0, ridx = 0; i < n_entries; i++) { 349 args[ridx++] = ldq_p(hpte); 350 args[ridx++] = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); 351 hpte += HASH_PTE_SIZE_64; 352 } 353 354 return H_SUCCESS; 355 } 356 357 static target_ulong h_set_sprg0(PowerPCCPU *cpu, sPAPRMachineState *spapr, 358 target_ulong opcode, target_ulong *args) 359 { 360 cpu_synchronize_state(CPU(cpu)); 361 cpu->env.spr[SPR_SPRG0] = args[0]; 362 363 return H_SUCCESS; 364 } 365 366 static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 367 target_ulong opcode, target_ulong *args) 368 { 369 if (!has_spr(cpu, SPR_DABR)) { 370 return H_HARDWARE; /* DABR register not available */ 371 } 372 cpu_synchronize_state(CPU(cpu)); 373 374 if (has_spr(cpu, SPR_DABRX)) { 375 cpu->env.spr[SPR_DABRX] = 0x3; /* Use Problem and Privileged state */ 376 } else if (!(args[0] & 0x4)) { /* Breakpoint Translation set? */ 377 return H_RESERVED_DABR; 378 } 379 380 cpu->env.spr[SPR_DABR] = args[0]; 381 return H_SUCCESS; 382 } 383 384 static target_ulong h_set_xdabr(PowerPCCPU *cpu, sPAPRMachineState *spapr, 385 target_ulong opcode, target_ulong *args) 386 { 387 target_ulong dabrx = args[1]; 388 389 if (!has_spr(cpu, SPR_DABR) || !has_spr(cpu, SPR_DABRX)) { 390 return H_HARDWARE; 391 } 392 393 if ((dabrx & ~0xfULL) != 0 || (dabrx & H_DABRX_HYPERVISOR) != 0 394 || (dabrx & (H_DABRX_KERNEL | H_DABRX_USER)) == 0) { 395 return H_PARAMETER; 396 } 397 398 cpu_synchronize_state(CPU(cpu)); 399 cpu->env.spr[SPR_DABRX] = dabrx; 400 cpu->env.spr[SPR_DABR] = args[0]; 401 402 return H_SUCCESS; 403 } 404 405 static target_ulong h_page_init(PowerPCCPU *cpu, sPAPRMachineState *spapr, 406 target_ulong opcode, target_ulong *args) 407 { 408 target_ulong flags = args[0]; 409 hwaddr dst = args[1]; 410 hwaddr src = args[2]; 411 hwaddr len = TARGET_PAGE_SIZE; 412 uint8_t *pdst, *psrc; 413 target_long ret = H_SUCCESS; 414 415 if (flags & ~(H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE 416 | H_COPY_PAGE | H_ZERO_PAGE)) { 417 qemu_log_mask(LOG_UNIMP, "h_page_init: Bad flags (" TARGET_FMT_lx "\n", 418 flags); 419 return H_PARAMETER; 420 } 421 422 /* Map-in destination */ 423 if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { 424 return H_PARAMETER; 425 } 426 pdst = cpu_physical_memory_map(dst, &len, 1); 427 if (!pdst || len != TARGET_PAGE_SIZE) { 428 return H_PARAMETER; 429 } 430 431 if (flags & H_COPY_PAGE) { 432 /* Map-in source, copy to destination, and unmap source again */ 433 if (!is_ram_address(spapr, src) || (src & ~TARGET_PAGE_MASK) != 0) { 434 ret = H_PARAMETER; 435 goto unmap_out; 436 } 437 psrc = cpu_physical_memory_map(src, &len, 0); 438 if (!psrc || len != TARGET_PAGE_SIZE) { 439 ret = H_PARAMETER; 440 goto unmap_out; 441 } 442 memcpy(pdst, psrc, len); 443 cpu_physical_memory_unmap(psrc, len, 0, len); 444 } else if (flags & H_ZERO_PAGE) { 445 memset(pdst, 0, len); /* Just clear the destination page */ 446 } 447 448 if (kvm_enabled() && (flags & H_ICACHE_SYNCHRONIZE) != 0) { 449 kvmppc_dcbst_range(cpu, pdst, len); 450 } 451 if (flags & (H_ICACHE_SYNCHRONIZE | H_ICACHE_INVALIDATE)) { 452 if (kvm_enabled()) { 453 kvmppc_icbi_range(cpu, pdst, len); 454 } else { 455 tb_flush(CPU(cpu)); 456 } 457 } 458 459 unmap_out: 460 cpu_physical_memory_unmap(pdst, TARGET_PAGE_SIZE, 1, len); 461 return ret; 462 } 463 464 #define FLAGS_REGISTER_VPA 0x0000200000000000ULL 465 #define FLAGS_REGISTER_DTL 0x0000400000000000ULL 466 #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL 467 #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL 468 #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL 469 #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL 470 471 #define VPA_MIN_SIZE 640 472 #define VPA_SIZE_OFFSET 0x4 473 #define VPA_SHARED_PROC_OFFSET 0x9 474 #define VPA_SHARED_PROC_VAL 0x2 475 476 static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) 477 { 478 CPUState *cs = CPU(ppc_env_get_cpu(env)); 479 uint16_t size; 480 uint8_t tmp; 481 482 if (vpa == 0) { 483 hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); 484 return H_HARDWARE; 485 } 486 487 if (vpa % env->dcache_line_size) { 488 return H_PARAMETER; 489 } 490 /* FIXME: bounds check the address */ 491 492 size = lduw_be_phys(cs->as, vpa + 0x4); 493 494 if (size < VPA_MIN_SIZE) { 495 return H_PARAMETER; 496 } 497 498 /* VPA is not allowed to cross a page boundary */ 499 if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { 500 return H_PARAMETER; 501 } 502 503 env->vpa_addr = vpa; 504 505 tmp = ldub_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET); 506 tmp |= VPA_SHARED_PROC_VAL; 507 stb_phys(cs->as, env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); 508 509 return H_SUCCESS; 510 } 511 512 static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) 513 { 514 if (env->slb_shadow_addr) { 515 return H_RESOURCE; 516 } 517 518 if (env->dtl_addr) { 519 return H_RESOURCE; 520 } 521 522 env->vpa_addr = 0; 523 return H_SUCCESS; 524 } 525 526 static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) 527 { 528 CPUState *cs = CPU(ppc_env_get_cpu(env)); 529 uint32_t size; 530 531 if (addr == 0) { 532 hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); 533 return H_HARDWARE; 534 } 535 536 size = ldl_be_phys(cs->as, addr + 0x4); 537 if (size < 0x8) { 538 return H_PARAMETER; 539 } 540 541 if ((addr / 4096) != ((addr + size - 1) / 4096)) { 542 return H_PARAMETER; 543 } 544 545 if (!env->vpa_addr) { 546 return H_RESOURCE; 547 } 548 549 env->slb_shadow_addr = addr; 550 env->slb_shadow_size = size; 551 552 return H_SUCCESS; 553 } 554 555 static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) 556 { 557 env->slb_shadow_addr = 0; 558 env->slb_shadow_size = 0; 559 return H_SUCCESS; 560 } 561 562 static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) 563 { 564 CPUState *cs = CPU(ppc_env_get_cpu(env)); 565 uint32_t size; 566 567 if (addr == 0) { 568 hcall_dprintf("Can't cope with DTL at logical 0\n"); 569 return H_HARDWARE; 570 } 571 572 size = ldl_be_phys(cs->as, addr + 0x4); 573 574 if (size < 48) { 575 return H_PARAMETER; 576 } 577 578 if (!env->vpa_addr) { 579 return H_RESOURCE; 580 } 581 582 env->dtl_addr = addr; 583 env->dtl_size = size; 584 585 return H_SUCCESS; 586 } 587 588 static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) 589 { 590 env->dtl_addr = 0; 591 env->dtl_size = 0; 592 593 return H_SUCCESS; 594 } 595 596 static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPRMachineState *spapr, 597 target_ulong opcode, target_ulong *args) 598 { 599 target_ulong flags = args[0]; 600 target_ulong procno = args[1]; 601 target_ulong vpa = args[2]; 602 target_ulong ret = H_PARAMETER; 603 CPUPPCState *tenv; 604 PowerPCCPU *tcpu; 605 606 tcpu = ppc_get_vcpu_by_dt_id(procno); 607 if (!tcpu) { 608 return H_PARAMETER; 609 } 610 tenv = &tcpu->env; 611 612 switch (flags) { 613 case FLAGS_REGISTER_VPA: 614 ret = register_vpa(tenv, vpa); 615 break; 616 617 case FLAGS_DEREGISTER_VPA: 618 ret = deregister_vpa(tenv, vpa); 619 break; 620 621 case FLAGS_REGISTER_SLBSHADOW: 622 ret = register_slb_shadow(tenv, vpa); 623 break; 624 625 case FLAGS_DEREGISTER_SLBSHADOW: 626 ret = deregister_slb_shadow(tenv, vpa); 627 break; 628 629 case FLAGS_REGISTER_DTL: 630 ret = register_dtl(tenv, vpa); 631 break; 632 633 case FLAGS_DEREGISTER_DTL: 634 ret = deregister_dtl(tenv, vpa); 635 break; 636 } 637 638 return ret; 639 } 640 641 static target_ulong h_cede(PowerPCCPU *cpu, sPAPRMachineState *spapr, 642 target_ulong opcode, target_ulong *args) 643 { 644 CPUPPCState *env = &cpu->env; 645 CPUState *cs = CPU(cpu); 646 647 env->msr |= (1ULL << MSR_EE); 648 hreg_compute_hflags(env); 649 if (!cpu_has_work(cs)) { 650 cs->halted = 1; 651 cs->exception_index = EXCP_HLT; 652 cs->exit_request = 1; 653 } 654 return H_SUCCESS; 655 } 656 657 static target_ulong h_rtas(PowerPCCPU *cpu, sPAPRMachineState *spapr, 658 target_ulong opcode, target_ulong *args) 659 { 660 target_ulong rtas_r3 = args[0]; 661 uint32_t token = rtas_ld(rtas_r3, 0); 662 uint32_t nargs = rtas_ld(rtas_r3, 1); 663 uint32_t nret = rtas_ld(rtas_r3, 2); 664 665 return spapr_rtas_call(cpu, spapr, token, nargs, rtas_r3 + 12, 666 nret, rtas_r3 + 12 + 4*nargs); 667 } 668 669 static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPRMachineState *spapr, 670 target_ulong opcode, target_ulong *args) 671 { 672 CPUState *cs = CPU(cpu); 673 target_ulong size = args[0]; 674 target_ulong addr = args[1]; 675 676 switch (size) { 677 case 1: 678 args[0] = ldub_phys(cs->as, addr); 679 return H_SUCCESS; 680 case 2: 681 args[0] = lduw_phys(cs->as, addr); 682 return H_SUCCESS; 683 case 4: 684 args[0] = ldl_phys(cs->as, addr); 685 return H_SUCCESS; 686 case 8: 687 args[0] = ldq_phys(cs->as, addr); 688 return H_SUCCESS; 689 } 690 return H_PARAMETER; 691 } 692 693 static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPRMachineState *spapr, 694 target_ulong opcode, target_ulong *args) 695 { 696 CPUState *cs = CPU(cpu); 697 698 target_ulong size = args[0]; 699 target_ulong addr = args[1]; 700 target_ulong val = args[2]; 701 702 switch (size) { 703 case 1: 704 stb_phys(cs->as, addr, val); 705 return H_SUCCESS; 706 case 2: 707 stw_phys(cs->as, addr, val); 708 return H_SUCCESS; 709 case 4: 710 stl_phys(cs->as, addr, val); 711 return H_SUCCESS; 712 case 8: 713 stq_phys(cs->as, addr, val); 714 return H_SUCCESS; 715 } 716 return H_PARAMETER; 717 } 718 719 static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPRMachineState *spapr, 720 target_ulong opcode, target_ulong *args) 721 { 722 CPUState *cs = CPU(cpu); 723 724 target_ulong dst = args[0]; /* Destination address */ 725 target_ulong src = args[1]; /* Source address */ 726 target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ 727 target_ulong count = args[3]; /* Element count */ 728 target_ulong op = args[4]; /* 0 = copy, 1 = invert */ 729 uint64_t tmp; 730 unsigned int mask = (1 << esize) - 1; 731 int step = 1 << esize; 732 733 if (count > 0x80000000) { 734 return H_PARAMETER; 735 } 736 737 if ((dst & mask) || (src & mask) || (op > 1)) { 738 return H_PARAMETER; 739 } 740 741 if (dst >= src && dst < (src + (count << esize))) { 742 dst = dst + ((count - 1) << esize); 743 src = src + ((count - 1) << esize); 744 step = -step; 745 } 746 747 while (count--) { 748 switch (esize) { 749 case 0: 750 tmp = ldub_phys(cs->as, src); 751 break; 752 case 1: 753 tmp = lduw_phys(cs->as, src); 754 break; 755 case 2: 756 tmp = ldl_phys(cs->as, src); 757 break; 758 case 3: 759 tmp = ldq_phys(cs->as, src); 760 break; 761 default: 762 return H_PARAMETER; 763 } 764 if (op == 1) { 765 tmp = ~tmp; 766 } 767 switch (esize) { 768 case 0: 769 stb_phys(cs->as, dst, tmp); 770 break; 771 case 1: 772 stw_phys(cs->as, dst, tmp); 773 break; 774 case 2: 775 stl_phys(cs->as, dst, tmp); 776 break; 777 case 3: 778 stq_phys(cs->as, dst, tmp); 779 break; 780 } 781 dst = dst + step; 782 src = src + step; 783 } 784 785 return H_SUCCESS; 786 } 787 788 static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPRMachineState *spapr, 789 target_ulong opcode, target_ulong *args) 790 { 791 /* Nothing to do on emulation, KVM will trap this in the kernel */ 792 return H_SUCCESS; 793 } 794 795 static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPRMachineState *spapr, 796 target_ulong opcode, target_ulong *args) 797 { 798 /* Nothing to do on emulation, KVM will trap this in the kernel */ 799 return H_SUCCESS; 800 } 801 802 static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, 803 target_ulong mflags, 804 target_ulong value1, 805 target_ulong value2) 806 { 807 CPUState *cs; 808 809 if (value1) { 810 return H_P3; 811 } 812 if (value2) { 813 return H_P4; 814 } 815 816 switch (mflags) { 817 case H_SET_MODE_ENDIAN_BIG: 818 CPU_FOREACH(cs) { 819 set_spr(cs, SPR_LPCR, 0, LPCR_ILE); 820 } 821 spapr_pci_switch_vga(true); 822 return H_SUCCESS; 823 824 case H_SET_MODE_ENDIAN_LITTLE: 825 CPU_FOREACH(cs) { 826 set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE); 827 } 828 spapr_pci_switch_vga(false); 829 return H_SUCCESS; 830 } 831 832 return H_UNSUPPORTED_FLAG; 833 } 834 835 static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, 836 target_ulong mflags, 837 target_ulong value1, 838 target_ulong value2) 839 { 840 CPUState *cs; 841 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 842 843 if (!(pcc->insns_flags2 & PPC2_ISA207S)) { 844 return H_P2; 845 } 846 if (value1) { 847 return H_P3; 848 } 849 if (value2) { 850 return H_P4; 851 } 852 853 if (mflags == AIL_RESERVED) { 854 return H_UNSUPPORTED_FLAG; 855 } 856 857 CPU_FOREACH(cs) { 858 set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SHIFT, LPCR_AIL); 859 } 860 861 return H_SUCCESS; 862 } 863 864 static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPRMachineState *spapr, 865 target_ulong opcode, target_ulong *args) 866 { 867 target_ulong resource = args[1]; 868 target_ulong ret = H_P2; 869 870 switch (resource) { 871 case H_SET_MODE_RESOURCE_LE: 872 ret = h_set_mode_resource_le(cpu, args[0], args[2], args[3]); 873 break; 874 case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: 875 ret = h_set_mode_resource_addr_trans_mode(cpu, args[0], 876 args[2], args[3]); 877 break; 878 } 879 880 return ret; 881 } 882 883 static target_ulong h_clean_slb(PowerPCCPU *cpu, sPAPRMachineState *spapr, 884 target_ulong opcode, target_ulong *args) 885 { 886 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 887 opcode, " (H_CLEAN_SLB)"); 888 return H_FUNCTION; 889 } 890 891 static target_ulong h_invalidate_pid(PowerPCCPU *cpu, sPAPRMachineState *spapr, 892 target_ulong opcode, target_ulong *args) 893 { 894 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x"TARGET_FMT_lx"%s\n", 895 opcode, " (H_INVALIDATE_PID)"); 896 return H_FUNCTION; 897 } 898 899 static void spapr_check_setup_free_hpt(sPAPRMachineState *spapr, 900 uint64_t patbe_old, uint64_t patbe_new) 901 { 902 /* 903 * We have 4 Options: 904 * HASH->HASH || RADIX->RADIX || NOTHING->RADIX : Do Nothing 905 * HASH->RADIX : Free HPT 906 * RADIX->HASH : Allocate HPT 907 * NOTHING->HASH : Allocate HPT 908 * Note: NOTHING implies the case where we said the guest could choose 909 * later and so assumed radix and now it's called H_REG_PROC_TBL 910 */ 911 912 if ((patbe_old & PATBE1_GR) == (patbe_new & PATBE1_GR)) { 913 /* We assume RADIX, so this catches all the "Do Nothing" cases */ 914 } else if (!(patbe_old & PATBE1_GR)) { 915 /* HASH->RADIX : Free HPT */ 916 spapr_free_hpt(spapr); 917 } else if (!(patbe_new & PATBE1_GR)) { 918 /* RADIX->HASH || NOTHING->HASH : Allocate HPT */ 919 spapr_setup_hpt_and_vrma(spapr); 920 } 921 return; 922 } 923 924 #define FLAGS_MASK 0x01FULL 925 #define FLAG_MODIFY 0x10 926 #define FLAG_REGISTER 0x08 927 #define FLAG_RADIX 0x04 928 #define FLAG_HASH_PROC_TBL 0x02 929 #define FLAG_GTSE 0x01 930 931 static target_ulong h_register_process_table(PowerPCCPU *cpu, 932 sPAPRMachineState *spapr, 933 target_ulong opcode, 934 target_ulong *args) 935 { 936 CPUState *cs; 937 target_ulong flags = args[0]; 938 target_ulong proc_tbl = args[1]; 939 target_ulong page_size = args[2]; 940 target_ulong table_size = args[3]; 941 uint64_t cproc; 942 943 if (flags & ~FLAGS_MASK) { /* Check no reserved bits are set */ 944 return H_PARAMETER; 945 } 946 if (flags & FLAG_MODIFY) { 947 if (flags & FLAG_REGISTER) { 948 if (flags & FLAG_RADIX) { /* Register new RADIX process table */ 949 if (proc_tbl & 0xfff || proc_tbl >> 60) { 950 return H_P2; 951 } else if (page_size) { 952 return H_P3; 953 } else if (table_size > 24) { 954 return H_P4; 955 } 956 cproc = PATBE1_GR | proc_tbl | table_size; 957 } else { /* Register new HPT process table */ 958 if (flags & FLAG_HASH_PROC_TBL) { /* Hash with Segment Tables */ 959 /* TODO - Not Supported */ 960 /* Technically caused by flag bits => H_PARAMETER */ 961 return H_PARAMETER; 962 } else { /* Hash with SLB */ 963 if (proc_tbl >> 38) { 964 return H_P2; 965 } else if (page_size & ~0x7) { 966 return H_P3; 967 } else if (table_size > 24) { 968 return H_P4; 969 } 970 } 971 cproc = (proc_tbl << 25) | page_size << 5 | table_size; 972 } 973 974 } else { /* Deregister current process table */ 975 /* Set to benign value: (current GR) | 0. This allows 976 * deregistration in KVM to succeed even if the radix bit in flags 977 * doesn't match the radix bit in the old PATB. */ 978 cproc = spapr->patb_entry & PATBE1_GR; 979 } 980 } else { /* Maintain current registration */ 981 if (!(flags & FLAG_RADIX) != !(spapr->patb_entry & PATBE1_GR)) { 982 /* Technically caused by flag bits => H_PARAMETER */ 983 return H_PARAMETER; /* Existing Process Table Mismatch */ 984 } 985 cproc = spapr->patb_entry; 986 } 987 988 /* Check if we need to setup OR free the hpt */ 989 spapr_check_setup_free_hpt(spapr, spapr->patb_entry, cproc); 990 991 spapr->patb_entry = cproc; /* Save new process table */ 992 993 /* Update the UPRT and GTSE bits in the LPCR for all cpus */ 994 CPU_FOREACH(cs) { 995 set_spr(cs, SPR_LPCR, 996 ((flags & (FLAG_RADIX | FLAG_HASH_PROC_TBL)) ? LPCR_UPRT : 0) | 997 ((flags & FLAG_GTSE) ? LPCR_GTSE : 0), 998 LPCR_UPRT | LPCR_GTSE); 999 } 1000 1001 if (kvm_enabled()) { 1002 return kvmppc_configure_v3_mmu(cpu, flags & FLAG_RADIX, 1003 flags & FLAG_GTSE, cproc); 1004 } 1005 return H_SUCCESS; 1006 } 1007 1008 #define H_SIGNAL_SYS_RESET_ALL -1 1009 #define H_SIGNAL_SYS_RESET_ALLBUTSELF -2 1010 1011 static target_ulong h_signal_sys_reset(PowerPCCPU *cpu, 1012 sPAPRMachineState *spapr, 1013 target_ulong opcode, target_ulong *args) 1014 { 1015 target_long target = args[0]; 1016 CPUState *cs; 1017 1018 if (target < 0) { 1019 /* Broadcast */ 1020 if (target < H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1021 return H_PARAMETER; 1022 } 1023 1024 CPU_FOREACH(cs) { 1025 PowerPCCPU *c = POWERPC_CPU(cs); 1026 1027 if (target == H_SIGNAL_SYS_RESET_ALLBUTSELF) { 1028 if (c == cpu) { 1029 continue; 1030 } 1031 } 1032 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1033 } 1034 return H_SUCCESS; 1035 1036 } else { 1037 /* Unicast */ 1038 CPU_FOREACH(cs) { 1039 if (cpu->cpu_dt_id == target) { 1040 run_on_cpu(cs, spapr_do_system_reset_on_cpu, RUN_ON_CPU_NULL); 1041 return H_SUCCESS; 1042 } 1043 } 1044 return H_PARAMETER; 1045 } 1046 } 1047 1048 static uint32_t cas_check_pvr(PowerPCCPU *cpu, target_ulong *addr, 1049 Error **errp) 1050 { 1051 bool explicit_match = false; /* Matched the CPU's real PVR */ 1052 uint32_t max_compat = cpu->max_compat; 1053 uint32_t best_compat = 0; 1054 int i; 1055 1056 /* 1057 * We scan the supplied table of PVRs looking for two things 1058 * 1. Is our real CPU PVR in the list? 1059 * 2. What's the "best" listed logical PVR 1060 */ 1061 for (i = 0; i < 512; ++i) { 1062 uint32_t pvr, pvr_mask; 1063 1064 pvr_mask = ldl_be_phys(&address_space_memory, *addr); 1065 pvr = ldl_be_phys(&address_space_memory, *addr + 4); 1066 *addr += 8; 1067 1068 if (~pvr_mask & pvr) { 1069 break; /* Terminator record */ 1070 } 1071 1072 if ((cpu->env.spr[SPR_PVR] & pvr_mask) == (pvr & pvr_mask)) { 1073 explicit_match = true; 1074 } else { 1075 if (ppc_check_compat(cpu, pvr, best_compat, max_compat)) { 1076 best_compat = pvr; 1077 } 1078 } 1079 } 1080 1081 if ((best_compat == 0) && (!explicit_match || max_compat)) { 1082 /* We couldn't find a suitable compatibility mode, and either 1083 * the guest doesn't support "raw" mode for this CPU, or raw 1084 * mode is disabled because a maximum compat mode is set */ 1085 error_setg(errp, "Couldn't negotiate a suitable PVR during CAS"); 1086 return 0; 1087 } 1088 1089 /* Parsing finished */ 1090 trace_spapr_cas_pvr(cpu->compat_pvr, explicit_match, best_compat); 1091 1092 return best_compat; 1093 } 1094 1095 static target_ulong h_client_architecture_support(PowerPCCPU *cpu, 1096 sPAPRMachineState *spapr, 1097 target_ulong opcode, 1098 target_ulong *args) 1099 { 1100 /* Working address in data buffer */ 1101 target_ulong addr = ppc64_phys_to_real(args[0]); 1102 target_ulong ov_table; 1103 uint32_t cas_pvr; 1104 sPAPROptionVector *ov1_guest, *ov5_guest, *ov5_cas_old, *ov5_updates; 1105 bool guest_radix; 1106 Error *local_err = NULL; 1107 1108 cas_pvr = cas_check_pvr(cpu, &addr, &local_err); 1109 if (local_err) { 1110 error_report_err(local_err); 1111 return H_HARDWARE; 1112 } 1113 1114 /* Update CPUs */ 1115 if (cpu->compat_pvr != cas_pvr) { 1116 ppc_set_compat_all(cas_pvr, &local_err); 1117 if (local_err) { 1118 error_report_err(local_err); 1119 return H_HARDWARE; 1120 } 1121 } 1122 1123 /* For the future use: here @ov_table points to the first option vector */ 1124 ov_table = addr; 1125 1126 ov1_guest = spapr_ovec_parse_vector(ov_table, 1); 1127 ov5_guest = spapr_ovec_parse_vector(ov_table, 5); 1128 if (spapr_ovec_test(ov5_guest, OV5_MMU_BOTH)) { 1129 error_report("guest requested hash and radix MMU, which is invalid."); 1130 exit(EXIT_FAILURE); 1131 } 1132 /* The radix/hash bit in byte 24 requires special handling: */ 1133 guest_radix = spapr_ovec_test(ov5_guest, OV5_MMU_RADIX_300); 1134 spapr_ovec_clear(ov5_guest, OV5_MMU_RADIX_300); 1135 1136 /* NOTE: there are actually a number of ov5 bits where input from the 1137 * guest is always zero, and the platform/QEMU enables them independently 1138 * of guest input. To model these properly we'd want some sort of mask, 1139 * but since they only currently apply to memory migration as defined 1140 * by LoPAPR 1.1, 14.5.4.8, which QEMU doesn't implement, we don't need 1141 * to worry about this for now. 1142 */ 1143 ov5_cas_old = spapr_ovec_clone(spapr->ov5_cas); 1144 /* full range of negotiated ov5 capabilities */ 1145 spapr_ovec_intersect(spapr->ov5_cas, spapr->ov5, ov5_guest); 1146 spapr_ovec_cleanup(ov5_guest); 1147 /* capabilities that have been added since CAS-generated guest reset. 1148 * if capabilities have since been removed, generate another reset 1149 */ 1150 ov5_updates = spapr_ovec_new(); 1151 spapr->cas_reboot = spapr_ovec_diff(ov5_updates, 1152 ov5_cas_old, spapr->ov5_cas); 1153 /* Now that processing is finished, set the radix/hash bit for the 1154 * guest if it requested a valid mode; otherwise terminate the boot. */ 1155 if (guest_radix) { 1156 if (kvm_enabled() && !kvmppc_has_cap_mmu_radix()) { 1157 error_report("Guest requested unavailable MMU mode (radix)."); 1158 exit(EXIT_FAILURE); 1159 } 1160 spapr_ovec_set(spapr->ov5_cas, OV5_MMU_RADIX_300); 1161 } else { 1162 if (kvm_enabled() && kvmppc_has_cap_mmu_radix() 1163 && !kvmppc_has_cap_mmu_hash_v3()) { 1164 error_report("Guest requested unavailable MMU mode (hash)."); 1165 exit(EXIT_FAILURE); 1166 } 1167 } 1168 spapr->cas_legacy_guest_workaround = !spapr_ovec_test(ov1_guest, 1169 OV1_PPC_3_00); 1170 if (!spapr->cas_reboot) { 1171 spapr->cas_reboot = 1172 (spapr_h_cas_compose_response(spapr, args[1], args[2], 1173 ov5_updates) != 0); 1174 } 1175 spapr_ovec_cleanup(ov5_updates); 1176 1177 if (spapr->cas_reboot) { 1178 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 1179 } else { 1180 /* If ppc_spapr_reset() did not set up a HPT but one is necessary 1181 * (because the guest isn't going to use radix) then set it up here. */ 1182 if ((spapr->patb_entry & PATBE1_GR) && !guest_radix) { 1183 /* legacy hash or new hash: */ 1184 spapr_setup_hpt_and_vrma(spapr); 1185 } 1186 } 1187 1188 return H_SUCCESS; 1189 } 1190 1191 static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; 1192 static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; 1193 1194 void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) 1195 { 1196 spapr_hcall_fn *slot; 1197 1198 if (opcode <= MAX_HCALL_OPCODE) { 1199 assert((opcode & 0x3) == 0); 1200 1201 slot = &papr_hypercall_table[opcode / 4]; 1202 } else { 1203 assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); 1204 1205 slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1206 } 1207 1208 assert(!(*slot)); 1209 *slot = fn; 1210 } 1211 1212 target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, 1213 target_ulong *args) 1214 { 1215 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1216 1217 if ((opcode <= MAX_HCALL_OPCODE) 1218 && ((opcode & 0x3) == 0)) { 1219 spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; 1220 1221 if (fn) { 1222 return fn(cpu, spapr, opcode, args); 1223 } 1224 } else if ((opcode >= KVMPPC_HCALL_BASE) && 1225 (opcode <= KVMPPC_HCALL_MAX)) { 1226 spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; 1227 1228 if (fn) { 1229 return fn(cpu, spapr, opcode, args); 1230 } 1231 } 1232 1233 qemu_log_mask(LOG_UNIMP, "Unimplemented SPAPR hcall 0x" TARGET_FMT_lx "\n", 1234 opcode); 1235 return H_FUNCTION; 1236 } 1237 1238 static void hypercall_register_types(void) 1239 { 1240 /* hcall-pft */ 1241 spapr_register_hypercall(H_ENTER, h_enter); 1242 spapr_register_hypercall(H_REMOVE, h_remove); 1243 spapr_register_hypercall(H_PROTECT, h_protect); 1244 spapr_register_hypercall(H_READ, h_read); 1245 1246 /* hcall-bulk */ 1247 spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); 1248 1249 /* hcall-splpar */ 1250 spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); 1251 spapr_register_hypercall(H_CEDE, h_cede); 1252 spapr_register_hypercall(H_SIGNAL_SYS_RESET, h_signal_sys_reset); 1253 1254 /* processor register resource access h-calls */ 1255 spapr_register_hypercall(H_SET_SPRG0, h_set_sprg0); 1256 spapr_register_hypercall(H_SET_DABR, h_set_dabr); 1257 spapr_register_hypercall(H_SET_XDABR, h_set_xdabr); 1258 spapr_register_hypercall(H_PAGE_INIT, h_page_init); 1259 spapr_register_hypercall(H_SET_MODE, h_set_mode); 1260 1261 /* In Memory Table MMU h-calls */ 1262 spapr_register_hypercall(H_CLEAN_SLB, h_clean_slb); 1263 spapr_register_hypercall(H_INVALIDATE_PID, h_invalidate_pid); 1264 spapr_register_hypercall(H_REGISTER_PROC_TBL, h_register_process_table); 1265 1266 /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate 1267 * here between the "CI" and the "CACHE" variants, they will use whatever 1268 * mapping attributes qemu is using. When using KVM, the kernel will 1269 * enforce the attributes more strongly 1270 */ 1271 spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); 1272 spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); 1273 spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); 1274 spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); 1275 spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); 1276 spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); 1277 spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); 1278 1279 /* qemu/KVM-PPC specific hcalls */ 1280 spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); 1281 1282 /* ibm,client-architecture-support support */ 1283 spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support); 1284 } 1285 1286 type_init(hypercall_register_types) 1287