1 #include "qemu/osdep.h" 2 #include "qemu/cutils.h" 3 #include "exec/exec-all.h" 4 #include "helper_regs.h" 5 #include "hw/ppc/ppc.h" 6 #include "hw/ppc/spapr.h" 7 #include "hw/ppc/spapr_cpu_core.h" 8 #include "hw/ppc/spapr_nested.h" 9 #include "mmu-book3s-v3.h" 10 11 void spapr_nested_reset(SpaprMachineState *spapr) 12 { 13 if (spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 14 spapr_unregister_nested_hv(); 15 spapr_register_nested_hv(); 16 } 17 } 18 19 #ifdef CONFIG_TCG 20 21 bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, 22 target_ulong lpid, ppc_v3_pate_t *entry) 23 { 24 uint64_t patb, pats; 25 26 assert(lpid != 0); 27 28 patb = spapr->nested_ptcr & PTCR_PATB; 29 pats = spapr->nested_ptcr & PTCR_PATS; 30 31 /* Check if partition table is properly aligned */ 32 if (patb & MAKE_64BIT_MASK(0, pats + 12)) { 33 return false; 34 } 35 36 /* Calculate number of entries */ 37 pats = 1ull << (pats + 12 - 4); 38 if (pats <= lpid) { 39 return false; 40 } 41 42 /* Grab entry */ 43 patb += 16 * lpid; 44 entry->dw0 = ldq_phys(CPU(cpu)->as, patb); 45 entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); 46 return true; 47 } 48 49 #define PRTS_MASK 0x1f 50 51 static target_ulong h_set_ptbl(PowerPCCPU *cpu, 52 SpaprMachineState *spapr, 53 target_ulong opcode, 54 target_ulong *args) 55 { 56 target_ulong ptcr = args[0]; 57 58 if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) { 59 return H_FUNCTION; 60 } 61 62 if ((ptcr & PRTS_MASK) + 12 - 4 > 12) { 63 return H_PARAMETER; 64 } 65 66 spapr->nested_ptcr = ptcr; /* Save new partition table */ 67 68 return H_SUCCESS; 69 } 70 71 static target_ulong h_tlb_invalidate(PowerPCCPU *cpu, 72 SpaprMachineState *spapr, 73 target_ulong opcode, 74 target_ulong *args) 75 { 76 /* 77 * The spapr virtual hypervisor nested HV implementation retains no L2 78 * translation state except for TLB. And the TLB is always invalidated 79 * across L1<->L2 transitions, so nothing is required here. 80 */ 81 82 return H_SUCCESS; 83 } 84 85 static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, 86 SpaprMachineState *spapr, 87 target_ulong opcode, 88 target_ulong *args) 89 { 90 /* 91 * This HCALL is not required, L1 KVM will take a slow path and walk the 92 * page tables manually to do the data copy. 93 */ 94 return H_FUNCTION; 95 } 96 97 static void nested_save_state(struct nested_ppc_state *save, PowerPCCPU *cpu) 98 { 99 CPUPPCState *env = &cpu->env; 100 101 memcpy(save->gpr, env->gpr, sizeof(save->gpr)); 102 103 save->lr = env->lr; 104 save->ctr = env->ctr; 105 save->cfar = env->cfar; 106 save->msr = env->msr; 107 save->nip = env->nip; 108 109 save->cr = ppc_get_cr(env); 110 save->xer = cpu_read_xer(env); 111 112 save->lpcr = env->spr[SPR_LPCR]; 113 save->lpidr = env->spr[SPR_LPIDR]; 114 save->pcr = env->spr[SPR_PCR]; 115 save->dpdes = env->spr[SPR_DPDES]; 116 save->hfscr = env->spr[SPR_HFSCR]; 117 save->srr0 = env->spr[SPR_SRR0]; 118 save->srr1 = env->spr[SPR_SRR1]; 119 save->sprg0 = env->spr[SPR_SPRG0]; 120 save->sprg1 = env->spr[SPR_SPRG1]; 121 save->sprg2 = env->spr[SPR_SPRG2]; 122 save->sprg3 = env->spr[SPR_SPRG3]; 123 save->pidr = env->spr[SPR_BOOKS_PID]; 124 save->ppr = env->spr[SPR_PPR]; 125 126 save->tb_offset = env->tb_env->tb_offset; 127 } 128 129 static void nested_load_state(PowerPCCPU *cpu, struct nested_ppc_state *load) 130 { 131 CPUState *cs = CPU(cpu); 132 CPUPPCState *env = &cpu->env; 133 134 memcpy(env->gpr, load->gpr, sizeof(env->gpr)); 135 136 env->lr = load->lr; 137 env->ctr = load->ctr; 138 env->cfar = load->cfar; 139 env->msr = load->msr; 140 env->nip = load->nip; 141 142 ppc_set_cr(env, load->cr); 143 cpu_write_xer(env, load->xer); 144 145 env->spr[SPR_LPCR] = load->lpcr; 146 env->spr[SPR_LPIDR] = load->lpidr; 147 env->spr[SPR_PCR] = load->pcr; 148 env->spr[SPR_DPDES] = load->dpdes; 149 env->spr[SPR_HFSCR] = load->hfscr; 150 env->spr[SPR_SRR0] = load->srr0; 151 env->spr[SPR_SRR1] = load->srr1; 152 env->spr[SPR_SPRG0] = load->sprg0; 153 env->spr[SPR_SPRG1] = load->sprg1; 154 env->spr[SPR_SPRG2] = load->sprg2; 155 env->spr[SPR_SPRG3] = load->sprg3; 156 env->spr[SPR_BOOKS_PID] = load->pidr; 157 env->spr[SPR_PPR] = load->ppr; 158 159 env->tb_env->tb_offset = load->tb_offset; 160 161 /* 162 * MSR updated, compute hflags and possible interrupts. 163 */ 164 hreg_compute_hflags(env); 165 ppc_maybe_interrupt(env); 166 167 /* 168 * Nested HV does not tag TLB entries between L1 and L2, so must 169 * flush on transition. 170 */ 171 tlb_flush(cs); 172 env->reserve_addr = -1; /* Reset the reservation */ 173 } 174 175 /* 176 * When this handler returns, the environment is switched to the L2 guest 177 * and TCG begins running that. spapr_exit_nested() performs the switch from 178 * L2 back to L1 and returns from the H_ENTER_NESTED hcall. 179 */ 180 static target_ulong h_enter_nested(PowerPCCPU *cpu, 181 SpaprMachineState *spapr, 182 target_ulong opcode, 183 target_ulong *args) 184 { 185 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 186 CPUPPCState *env = &cpu->env; 187 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 188 struct nested_ppc_state l2_state; 189 target_ulong hv_ptr = args[0]; 190 target_ulong regs_ptr = args[1]; 191 target_ulong hdec, now = cpu_ppc_load_tbl(env); 192 target_ulong lpcr, lpcr_mask; 193 struct kvmppc_hv_guest_state *hvstate; 194 struct kvmppc_hv_guest_state hv_state; 195 struct kvmppc_pt_regs *regs; 196 hwaddr len; 197 198 if (spapr->nested_ptcr == 0) { 199 return H_NOT_AVAILABLE; 200 } 201 202 len = sizeof(*hvstate); 203 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false, 204 MEMTXATTRS_UNSPECIFIED); 205 if (len != sizeof(*hvstate)) { 206 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false); 207 return H_PARAMETER; 208 } 209 210 memcpy(&hv_state, hvstate, len); 211 212 address_space_unmap(CPU(cpu)->as, hvstate, len, len, false); 213 214 /* 215 * We accept versions 1 and 2. Version 2 fields are unused because TCG 216 * does not implement DAWR*. 217 */ 218 if (hv_state.version > HV_GUEST_STATE_VERSION) { 219 return H_PARAMETER; 220 } 221 222 if (hv_state.lpid == 0) { 223 return H_PARAMETER; 224 } 225 226 spapr_cpu->nested_host_state = g_try_new(struct nested_ppc_state, 1); 227 if (!spapr_cpu->nested_host_state) { 228 return H_NO_MEM; 229 } 230 231 assert(env->spr[SPR_LPIDR] == 0); 232 assert(env->spr[SPR_DPDES] == 0); 233 nested_save_state(spapr_cpu->nested_host_state, cpu); 234 235 len = sizeof(*regs); 236 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false, 237 MEMTXATTRS_UNSPECIFIED); 238 if (!regs || len != sizeof(*regs)) { 239 address_space_unmap(CPU(cpu)->as, regs, len, 0, false); 240 g_free(spapr_cpu->nested_host_state); 241 return H_P2; 242 } 243 244 len = sizeof(l2_state.gpr); 245 assert(len == sizeof(regs->gpr)); 246 memcpy(l2_state.gpr, regs->gpr, len); 247 248 l2_state.lr = regs->link; 249 l2_state.ctr = regs->ctr; 250 l2_state.xer = regs->xer; 251 l2_state.cr = regs->ccr; 252 l2_state.msr = regs->msr; 253 l2_state.nip = regs->nip; 254 255 address_space_unmap(CPU(cpu)->as, regs, len, len, false); 256 257 l2_state.cfar = hv_state.cfar; 258 l2_state.lpidr = hv_state.lpid; 259 260 lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; 261 lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); 262 lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; 263 lpcr &= ~LPCR_LPES0; 264 l2_state.lpcr = lpcr & pcc->lpcr_mask; 265 266 l2_state.pcr = hv_state.pcr; 267 /* hv_state.amor is not used */ 268 l2_state.dpdes = hv_state.dpdes; 269 l2_state.hfscr = hv_state.hfscr; 270 /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ 271 l2_state.srr0 = hv_state.srr0; 272 l2_state.srr1 = hv_state.srr1; 273 l2_state.sprg0 = hv_state.sprg[0]; 274 l2_state.sprg1 = hv_state.sprg[1]; 275 l2_state.sprg2 = hv_state.sprg[2]; 276 l2_state.sprg3 = hv_state.sprg[3]; 277 l2_state.pidr = hv_state.pidr; 278 l2_state.ppr = hv_state.ppr; 279 l2_state.tb_offset = env->tb_env->tb_offset + hv_state.tb_offset; 280 281 /* 282 * Switch to the nested guest environment and start the "hdec" timer. 283 */ 284 nested_load_state(cpu, &l2_state); 285 286 hdec = hv_state.hdec_expiry - now; 287 cpu_ppc_hdecr_init(env); 288 cpu_ppc_store_hdecr(env, hdec); 289 290 /* 291 * The hv_state.vcpu_token is not needed. It is used by the KVM 292 * implementation to remember which L2 vCPU last ran on which physical 293 * CPU so as to invalidate process scope translations if it is moved 294 * between physical CPUs. For now TLBs are always flushed on L1<->L2 295 * transitions so this is not a problem. 296 * 297 * Could validate that the same vcpu_token does not attempt to run on 298 * different L1 vCPUs at the same time, but that would be a L1 KVM bug 299 * and it's not obviously worth a new data structure to do it. 300 */ 301 302 spapr_cpu->in_nested = true; 303 304 /* 305 * The spapr hcall helper sets env->gpr[3] to the return value, but at 306 * this point the L1 is not returning from the hcall but rather we 307 * start running the L2, so r3 must not be clobbered, so return env->gpr[3] 308 * to leave it unchanged. 309 */ 310 return env->gpr[3]; 311 } 312 313 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 314 { 315 CPUPPCState *env = &cpu->env; 316 SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); 317 struct nested_ppc_state l2_state; 318 target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; 319 target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; 320 target_ulong hsrr0, hsrr1, hdar, asdr, hdsisr; 321 struct kvmppc_hv_guest_state *hvstate; 322 struct kvmppc_pt_regs *regs; 323 hwaddr len; 324 325 assert(spapr_cpu->in_nested); 326 327 nested_save_state(&l2_state, cpu); 328 hsrr0 = env->spr[SPR_HSRR0]; 329 hsrr1 = env->spr[SPR_HSRR1]; 330 hdar = env->spr[SPR_HDAR]; 331 hdsisr = env->spr[SPR_HDSISR]; 332 asdr = env->spr[SPR_ASDR]; 333 334 /* 335 * Switch back to the host environment (including for any error). 336 */ 337 assert(env->spr[SPR_LPIDR] != 0); 338 nested_load_state(cpu, spapr_cpu->nested_host_state); 339 env->gpr[3] = env->excp_vectors[excp]; /* hcall return value */ 340 341 cpu_ppc_hdecr_exit(env); 342 343 spapr_cpu->in_nested = false; 344 345 g_free(spapr_cpu->nested_host_state); 346 spapr_cpu->nested_host_state = NULL; 347 348 len = sizeof(*hvstate); 349 hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, 350 MEMTXATTRS_UNSPECIFIED); 351 if (len != sizeof(*hvstate)) { 352 address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); 353 env->gpr[3] = H_PARAMETER; 354 return; 355 } 356 357 hvstate->cfar = l2_state.cfar; 358 hvstate->lpcr = l2_state.lpcr; 359 hvstate->pcr = l2_state.pcr; 360 hvstate->dpdes = l2_state.dpdes; 361 hvstate->hfscr = l2_state.hfscr; 362 363 if (excp == POWERPC_EXCP_HDSI) { 364 hvstate->hdar = hdar; 365 hvstate->hdsisr = hdsisr; 366 hvstate->asdr = asdr; 367 } else if (excp == POWERPC_EXCP_HISI) { 368 hvstate->asdr = asdr; 369 } 370 371 /* HEIR should be implemented for HV mode and saved here. */ 372 hvstate->srr0 = l2_state.srr0; 373 hvstate->srr1 = l2_state.srr1; 374 hvstate->sprg[0] = l2_state.sprg0; 375 hvstate->sprg[1] = l2_state.sprg1; 376 hvstate->sprg[2] = l2_state.sprg2; 377 hvstate->sprg[3] = l2_state.sprg3; 378 hvstate->pidr = l2_state.pidr; 379 hvstate->ppr = l2_state.ppr; 380 381 /* Is it okay to specify write length larger than actual data written? */ 382 address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); 383 384 len = sizeof(*regs); 385 regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, 386 MEMTXATTRS_UNSPECIFIED); 387 if (!regs || len != sizeof(*regs)) { 388 address_space_unmap(CPU(cpu)->as, regs, len, 0, true); 389 env->gpr[3] = H_P2; 390 return; 391 } 392 393 len = sizeof(env->gpr); 394 assert(len == sizeof(regs->gpr)); 395 memcpy(regs->gpr, l2_state.gpr, len); 396 397 regs->link = l2_state.lr; 398 regs->ctr = l2_state.ctr; 399 regs->xer = l2_state.xer; 400 regs->ccr = l2_state.cr; 401 402 if (excp == POWERPC_EXCP_MCHECK || 403 excp == POWERPC_EXCP_RESET || 404 excp == POWERPC_EXCP_SYSCALL) { 405 regs->nip = l2_state.srr0; 406 regs->msr = l2_state.srr1 & env->msr_mask; 407 } else { 408 regs->nip = hsrr0; 409 regs->msr = hsrr1 & env->msr_mask; 410 } 411 412 /* Is it okay to specify write length larger than actual data written? */ 413 address_space_unmap(CPU(cpu)->as, regs, len, len, true); 414 } 415 416 void spapr_register_nested_hv(void) 417 { 418 spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl); 419 spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested); 420 spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate); 421 spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest); 422 } 423 424 void spapr_unregister_nested_hv(void) 425 { 426 spapr_unregister_hypercall(KVMPPC_H_SET_PARTITION_TABLE); 427 spapr_unregister_hypercall(KVMPPC_H_ENTER_NESTED); 428 spapr_unregister_hypercall(KVMPPC_H_TLB_INVALIDATE); 429 spapr_unregister_hypercall(KVMPPC_H_COPY_TOFROM_GUEST); 430 } 431 #else 432 void spapr_exit_nested(PowerPCCPU *cpu, int excp) 433 { 434 g_assert_not_reached(); 435 } 436 437 void spapr_register_nested_hv(void) 438 { 439 /* DO NOTHING */ 440 } 441 442 void spapr_unregister_nested_hv(void) 443 { 444 /* DO NOTHING */ 445 } 446 447 bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu, 448 target_ulong lpid, ppc_v3_pate_t *entry) 449 { 450 return false; 451 } 452 #endif 453