1 /* 2 * QEMU PowerPC pSeries Logical Partition NUMA associativity handling 3 * 4 * Copyright IBM Corp. 2020 5 * 6 * Authors: 7 * Daniel Henrique Barboza <danielhb413@gmail.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "qemu-common.h" 15 #include "hw/ppc/spapr_numa.h" 16 #include "hw/pci-host/spapr.h" 17 #include "hw/ppc/fdt.h" 18 19 /* Moved from hw/ppc/spapr_pci_nvlink2.c */ 20 #define SPAPR_GPU_NUMA_ID (cpu_to_be32(1)) 21 22 /* 23 * Retrieves max_dist_ref_points of the current NUMA affinity. 24 */ 25 static int get_max_dist_ref_points(SpaprMachineState *spapr) 26 { 27 return FORM1_DIST_REF_POINTS; 28 } 29 30 /* 31 * Retrieves numa_assoc_size of the current NUMA affinity. 32 */ 33 static int get_numa_assoc_size(SpaprMachineState *spapr) 34 { 35 return FORM1_NUMA_ASSOC_SIZE; 36 } 37 38 /* 39 * Retrieves vcpu_assoc_size of the current NUMA affinity. 40 * 41 * vcpu_assoc_size is the size of ibm,associativity array 42 * for CPUs, which has an extra element (vcpu_id) in the end. 43 */ 44 static int get_vcpu_assoc_size(SpaprMachineState *spapr) 45 { 46 return get_numa_assoc_size(spapr) + 1; 47 } 48 49 /* 50 * Retrieves the ibm,associativity array of NUMA node 'node_id' 51 * for the current NUMA affinity. 52 */ 53 static const uint32_t *get_associativity(SpaprMachineState *spapr, int node_id) 54 { 55 return spapr->FORM1_assoc_array[node_id]; 56 } 57 58 static bool spapr_numa_is_symmetrical(MachineState *ms) 59 { 60 int src, dst; 61 int nb_numa_nodes = ms->numa_state->num_nodes; 62 NodeInfo *numa_info = ms->numa_state->nodes; 63 64 for (src = 0; src < nb_numa_nodes; src++) { 65 for (dst = src; dst < nb_numa_nodes; dst++) { 66 if (numa_info[src].distance[dst] != 67 numa_info[dst].distance[src]) { 68 return false; 69 } 70 } 71 } 72 73 return true; 74 } 75 76 /* 77 * NVLink2-connected GPU RAM needs to be placed on a separate NUMA node. 78 * We assign a new numa ID per GPU in spapr_pci_collect_nvgpu() which is 79 * called from vPHB reset handler so we initialize the counter here. 80 * If no NUMA is configured from the QEMU side, we start from 1 as GPU RAM 81 * must be equally distant from any other node. 82 * The final value of spapr->gpu_numa_id is going to be written to 83 * max-associativity-domains in spapr_build_fdt(). 84 */ 85 unsigned int spapr_numa_initial_nvgpu_numa_id(MachineState *machine) 86 { 87 return MAX(1, machine->numa_state->num_nodes); 88 } 89 90 /* 91 * This function will translate the user distances into 92 * what the kernel understand as possible values: 10 93 * (local distance), 20, 40, 80 and 160, and return the equivalent 94 * NUMA level for each. Current heuristic is: 95 * - local distance (10) returns numa_level = 0x4, meaning there is 96 * no rounding for local distance 97 * - distances between 11 and 30 inclusive -> rounded to 20, 98 * numa_level = 0x3 99 * - distances between 31 and 60 inclusive -> rounded to 40, 100 * numa_level = 0x2 101 * - distances between 61 and 120 inclusive -> rounded to 80, 102 * numa_level = 0x1 103 * - everything above 120 returns numa_level = 0 to indicate that 104 * there is no match. This will be calculated as disntace = 160 105 * by the kernel (as of v5.9) 106 */ 107 static uint8_t spapr_numa_get_numa_level(uint8_t distance) 108 { 109 if (distance == 10) { 110 return 0x4; 111 } else if (distance > 11 && distance <= 30) { 112 return 0x3; 113 } else if (distance > 31 && distance <= 60) { 114 return 0x2; 115 } else if (distance > 61 && distance <= 120) { 116 return 0x1; 117 } 118 119 return 0; 120 } 121 122 static void spapr_numa_define_FORM1_domains(SpaprMachineState *spapr) 123 { 124 MachineState *ms = MACHINE(spapr); 125 NodeInfo *numa_info = ms->numa_state->nodes; 126 int nb_numa_nodes = ms->numa_state->num_nodes; 127 int src, dst, i, j; 128 129 /* 130 * Fill all associativity domains of non-zero NUMA nodes with 131 * node_id. This is required because the default value (0) is 132 * considered a match with associativity domains of node 0. 133 */ 134 for (i = 1; i < nb_numa_nodes; i++) { 135 for (j = 1; j < FORM1_DIST_REF_POINTS; j++) { 136 spapr->FORM1_assoc_array[i][j] = cpu_to_be32(i); 137 } 138 } 139 140 for (src = 0; src < nb_numa_nodes; src++) { 141 for (dst = src; dst < nb_numa_nodes; dst++) { 142 /* 143 * This is how the associativity domain between A and B 144 * is calculated: 145 * 146 * - get the distance D between them 147 * - get the correspondent NUMA level 'n_level' for D 148 * - all associativity arrays were initialized with their own 149 * numa_ids, and we're calculating the distance in node_id 150 * ascending order, starting from node id 0 (the first node 151 * retrieved by numa_state). This will have a cascade effect in 152 * the algorithm because the associativity domains that node 0 153 * defines will be carried over to other nodes, and node 1 154 * associativities will be carried over after taking node 0 155 * associativities into account, and so on. This happens because 156 * we'll assign assoc_src as the associativity domain of dst 157 * as well, for all NUMA levels beyond and including n_level. 158 * 159 * The PPC kernel expects the associativity domains of node 0 to 160 * be always 0, and this algorithm will grant that by default. 161 */ 162 uint8_t distance = numa_info[src].distance[dst]; 163 uint8_t n_level = spapr_numa_get_numa_level(distance); 164 uint32_t assoc_src; 165 166 /* 167 * n_level = 0 means that the distance is greater than our last 168 * rounded value (120). In this case there is no NUMA level match 169 * between src and dst and we can skip the remaining of the loop. 170 * 171 * The Linux kernel will assume that the distance between src and 172 * dst, in this case of no match, is 10 (local distance) doubled 173 * for each NUMA it didn't match. We have FORM1_DIST_REF_POINTS 174 * levels (4), so this gives us 10*2*2*2*2 = 160. 175 * 176 * This logic can be seen in the Linux kernel source code, as of 177 * v5.9, in arch/powerpc/mm/numa.c, function __node_distance(). 178 */ 179 if (n_level == 0) { 180 continue; 181 } 182 183 /* 184 * We must assign all assoc_src to dst, starting from n_level 185 * and going up to 0x1. 186 */ 187 for (i = n_level; i > 0; i--) { 188 assoc_src = spapr->FORM1_assoc_array[src][i]; 189 spapr->FORM1_assoc_array[dst][i] = assoc_src; 190 } 191 } 192 } 193 194 } 195 196 /* 197 * Set NUMA machine state data based on FORM1 affinity semantics. 198 */ 199 static void spapr_numa_FORM1_affinity_init(SpaprMachineState *spapr, 200 MachineState *machine) 201 { 202 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 203 int nb_numa_nodes = machine->numa_state->num_nodes; 204 int i, j, max_nodes_with_gpus; 205 206 /* 207 * For all associativity arrays: first position is the size, 208 * position FORM1_DIST_REF_POINTS is always the numa_id, 209 * represented by the index 'i'. 210 * 211 * This will break on sparse NUMA setups, when/if QEMU starts 212 * to support it, because there will be no more guarantee that 213 * 'i' will be a valid node_id set by the user. 214 */ 215 for (i = 0; i < nb_numa_nodes; i++) { 216 spapr->FORM1_assoc_array[i][0] = cpu_to_be32(FORM1_DIST_REF_POINTS); 217 spapr->FORM1_assoc_array[i][FORM1_DIST_REF_POINTS] = cpu_to_be32(i); 218 } 219 220 /* 221 * Initialize NVLink GPU associativity arrays. We know that 222 * the first GPU will take the first available NUMA id, and 223 * we'll have a maximum of NVGPU_MAX_NUM GPUs in the machine. 224 * At this point we're not sure if there are GPUs or not, but 225 * let's initialize the associativity arrays and allow NVLink 226 * GPUs to be handled like regular NUMA nodes later on. 227 */ 228 max_nodes_with_gpus = nb_numa_nodes + NVGPU_MAX_NUM; 229 230 for (i = nb_numa_nodes; i < max_nodes_with_gpus; i++) { 231 spapr->FORM1_assoc_array[i][0] = cpu_to_be32(FORM1_DIST_REF_POINTS); 232 233 for (j = 1; j < FORM1_DIST_REF_POINTS; j++) { 234 uint32_t gpu_assoc = smc->pre_5_1_assoc_refpoints ? 235 SPAPR_GPU_NUMA_ID : cpu_to_be32(i); 236 spapr->FORM1_assoc_array[i][j] = gpu_assoc; 237 } 238 239 spapr->FORM1_assoc_array[i][FORM1_DIST_REF_POINTS] = cpu_to_be32(i); 240 } 241 242 /* 243 * Guests pseries-5.1 and older uses zeroed associativity domains, 244 * i.e. no domain definition based on NUMA distance input. 245 * 246 * Same thing with guests that have only one NUMA node. 247 */ 248 if (smc->pre_5_2_numa_associativity || 249 machine->numa_state->num_nodes <= 1) { 250 return; 251 } 252 253 if (!spapr_numa_is_symmetrical(machine)) { 254 error_report("Asymmetrical NUMA topologies aren't supported " 255 "in the pSeries machine"); 256 exit(EXIT_FAILURE); 257 } 258 259 spapr_numa_define_FORM1_domains(spapr); 260 } 261 262 void spapr_numa_associativity_init(SpaprMachineState *spapr, 263 MachineState *machine) 264 { 265 spapr_numa_FORM1_affinity_init(spapr, machine); 266 } 267 268 void spapr_numa_write_associativity_dt(SpaprMachineState *spapr, void *fdt, 269 int offset, int nodeid) 270 { 271 const uint32_t *associativity = get_associativity(spapr, nodeid); 272 273 _FDT((fdt_setprop(fdt, offset, "ibm,associativity", 274 associativity, 275 get_numa_assoc_size(spapr) * sizeof(uint32_t)))); 276 } 277 278 static uint32_t *spapr_numa_get_vcpu_assoc(SpaprMachineState *spapr, 279 PowerPCCPU *cpu) 280 { 281 const uint32_t *associativity = get_associativity(spapr, cpu->node_id); 282 int max_distance_ref_points = get_max_dist_ref_points(spapr); 283 int vcpu_assoc_size = get_vcpu_assoc_size(spapr); 284 uint32_t *vcpu_assoc = g_new(uint32_t, vcpu_assoc_size); 285 int index = spapr_get_vcpu_id(cpu); 286 287 /* 288 * VCPUs have an extra 'cpu_id' value in ibm,associativity 289 * compared to other resources. Increment the size at index 290 * 0, put cpu_id last, then copy the remaining associativity 291 * domains. 292 */ 293 vcpu_assoc[0] = cpu_to_be32(max_distance_ref_points + 1); 294 vcpu_assoc[vcpu_assoc_size - 1] = cpu_to_be32(index); 295 memcpy(vcpu_assoc + 1, associativity + 1, 296 (vcpu_assoc_size - 2) * sizeof(uint32_t)); 297 298 return vcpu_assoc; 299 } 300 301 int spapr_numa_fixup_cpu_dt(SpaprMachineState *spapr, void *fdt, 302 int offset, PowerPCCPU *cpu) 303 { 304 g_autofree uint32_t *vcpu_assoc = NULL; 305 int vcpu_assoc_size = get_vcpu_assoc_size(spapr); 306 307 vcpu_assoc = spapr_numa_get_vcpu_assoc(spapr, cpu); 308 309 /* Advertise NUMA via ibm,associativity */ 310 return fdt_setprop(fdt, offset, "ibm,associativity", vcpu_assoc, 311 vcpu_assoc_size * sizeof(uint32_t)); 312 } 313 314 315 int spapr_numa_write_assoc_lookup_arrays(SpaprMachineState *spapr, void *fdt, 316 int offset) 317 { 318 MachineState *machine = MACHINE(spapr); 319 int max_distance_ref_points = get_max_dist_ref_points(spapr); 320 int nb_numa_nodes = machine->numa_state->num_nodes; 321 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1; 322 uint32_t *int_buf, *cur_index, buf_len; 323 int ret, i; 324 325 /* ibm,associativity-lookup-arrays */ 326 buf_len = (nr_nodes * max_distance_ref_points + 2) * sizeof(uint32_t); 327 cur_index = int_buf = g_malloc0(buf_len); 328 int_buf[0] = cpu_to_be32(nr_nodes); 329 /* Number of entries per associativity list */ 330 int_buf[1] = cpu_to_be32(max_distance_ref_points); 331 cur_index += 2; 332 for (i = 0; i < nr_nodes; i++) { 333 /* 334 * For the lookup-array we use the ibm,associativity array of the 335 * current NUMA affinity, without the first element (size). 336 */ 337 const uint32_t *associativity = get_associativity(spapr, i); 338 memcpy(cur_index, ++associativity, 339 sizeof(uint32_t) * max_distance_ref_points); 340 cur_index += max_distance_ref_points; 341 } 342 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf, 343 (cur_index - int_buf) * sizeof(uint32_t)); 344 g_free(int_buf); 345 346 return ret; 347 } 348 349 static void spapr_numa_FORM1_write_rtas_dt(SpaprMachineState *spapr, 350 void *fdt, int rtas) 351 { 352 MachineState *ms = MACHINE(spapr); 353 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 354 uint32_t number_nvgpus_nodes = spapr->gpu_numa_id - 355 spapr_numa_initial_nvgpu_numa_id(ms); 356 uint32_t refpoints[] = { 357 cpu_to_be32(0x4), 358 cpu_to_be32(0x3), 359 cpu_to_be32(0x2), 360 cpu_to_be32(0x1), 361 }; 362 uint32_t nr_refpoints = ARRAY_SIZE(refpoints); 363 uint32_t maxdomain = ms->numa_state->num_nodes + number_nvgpus_nodes; 364 uint32_t maxdomains[] = { 365 cpu_to_be32(4), 366 cpu_to_be32(maxdomain), 367 cpu_to_be32(maxdomain), 368 cpu_to_be32(maxdomain), 369 cpu_to_be32(maxdomain) 370 }; 371 372 if (smc->pre_5_2_numa_associativity || 373 ms->numa_state->num_nodes <= 1) { 374 uint32_t legacy_refpoints[] = { 375 cpu_to_be32(0x4), 376 cpu_to_be32(0x4), 377 cpu_to_be32(0x2), 378 }; 379 uint32_t legacy_maxdomain = spapr->gpu_numa_id > 1 ? 1 : 0; 380 uint32_t legacy_maxdomains[] = { 381 cpu_to_be32(4), 382 cpu_to_be32(legacy_maxdomain), 383 cpu_to_be32(legacy_maxdomain), 384 cpu_to_be32(legacy_maxdomain), 385 cpu_to_be32(spapr->gpu_numa_id), 386 }; 387 388 G_STATIC_ASSERT(sizeof(legacy_refpoints) <= sizeof(refpoints)); 389 G_STATIC_ASSERT(sizeof(legacy_maxdomains) <= sizeof(maxdomains)); 390 391 nr_refpoints = 3; 392 393 memcpy(refpoints, legacy_refpoints, sizeof(legacy_refpoints)); 394 memcpy(maxdomains, legacy_maxdomains, sizeof(legacy_maxdomains)); 395 396 /* pseries-5.0 and older reference-points array is {0x4, 0x4} */ 397 if (smc->pre_5_1_assoc_refpoints) { 398 nr_refpoints = 2; 399 } 400 } 401 402 _FDT(fdt_setprop(fdt, rtas, "ibm,associativity-reference-points", 403 refpoints, nr_refpoints * sizeof(refpoints[0]))); 404 405 _FDT(fdt_setprop(fdt, rtas, "ibm,max-associativity-domains", 406 maxdomains, sizeof(maxdomains))); 407 } 408 409 /* 410 * Helper that writes ibm,associativity-reference-points and 411 * max-associativity-domains in the RTAS pointed by @rtas 412 * in the DT @fdt. 413 */ 414 void spapr_numa_write_rtas_dt(SpaprMachineState *spapr, void *fdt, int rtas) 415 { 416 spapr_numa_FORM1_write_rtas_dt(spapr, fdt, rtas); 417 } 418 419 static target_ulong h_home_node_associativity(PowerPCCPU *cpu, 420 SpaprMachineState *spapr, 421 target_ulong opcode, 422 target_ulong *args) 423 { 424 g_autofree uint32_t *vcpu_assoc = NULL; 425 target_ulong flags = args[0]; 426 target_ulong procno = args[1]; 427 PowerPCCPU *tcpu; 428 int idx, assoc_idx; 429 int vcpu_assoc_size = get_vcpu_assoc_size(spapr); 430 431 /* only support procno from H_REGISTER_VPA */ 432 if (flags != 0x1) { 433 return H_FUNCTION; 434 } 435 436 tcpu = spapr_find_cpu(procno); 437 if (tcpu == NULL) { 438 return H_P2; 439 } 440 441 /* 442 * Given that we want to be flexible with the sizes and indexes, 443 * we must consider that there is a hard limit of how many 444 * associativities domain we can fit in R4 up to R9, which would be 445 * 12 associativity domains for vcpus. Assert and bail if that's 446 * not the case. 447 */ 448 g_assert((vcpu_assoc_size - 1) <= 12); 449 450 vcpu_assoc = spapr_numa_get_vcpu_assoc(spapr, tcpu); 451 /* assoc_idx starts at 1 to skip associativity size */ 452 assoc_idx = 1; 453 454 #define ASSOCIATIVITY(a, b) (((uint64_t)(a) << 32) | \ 455 ((uint64_t)(b) & 0xffffffff)) 456 457 for (idx = 0; idx < 6; idx++) { 458 int32_t a, b; 459 460 /* 461 * vcpu_assoc[] will contain the associativity domains for tcpu, 462 * including tcpu->node_id and procno, meaning that we don't 463 * need to use these variables here. 464 * 465 * We'll read 2 values at a time to fill up the ASSOCIATIVITY() 466 * macro. The ternary will fill the remaining registers with -1 467 * after we went through vcpu_assoc[]. 468 */ 469 a = assoc_idx < vcpu_assoc_size ? 470 be32_to_cpu(vcpu_assoc[assoc_idx++]) : -1; 471 b = assoc_idx < vcpu_assoc_size ? 472 be32_to_cpu(vcpu_assoc[assoc_idx++]) : -1; 473 474 args[idx] = ASSOCIATIVITY(a, b); 475 } 476 #undef ASSOCIATIVITY 477 478 return H_SUCCESS; 479 } 480 481 static void spapr_numa_register_types(void) 482 { 483 /* Virtual Processor Home Node */ 484 spapr_register_hypercall(H_HOME_NODE_ASSOCIATIVITY, 485 h_home_node_associativity); 486 } 487 488 type_init(spapr_numa_register_types) 489