1 /* 2 * QEMU sPAPR PCI host originated from Uninorth PCI host 3 * 4 * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. 5 * Copyright (C) 2011 David Gibson, IBM Corporation. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qapi/error.h" 28 #include "cpu.h" 29 #include "hw/hw.h" 30 #include "hw/irq.h" 31 #include "hw/sysbus.h" 32 #include "hw/pci/pci.h" 33 #include "hw/pci/msi.h" 34 #include "hw/pci/msix.h" 35 #include "hw/pci/pci_host.h" 36 #include "hw/ppc/spapr.h" 37 #include "hw/pci-host/spapr.h" 38 #include "exec/address-spaces.h" 39 #include "exec/ram_addr.h" 40 #include <libfdt.h> 41 #include "trace.h" 42 #include "qemu/error-report.h" 43 #include "qemu/module.h" 44 #include "qapi/qmp/qerror.h" 45 #include "hw/ppc/fdt.h" 46 #include "hw/pci/pci_bridge.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/pci/pci_ids.h" 49 #include "hw/ppc/spapr_drc.h" 50 #include "sysemu/device_tree.h" 51 #include "sysemu/kvm.h" 52 #include "sysemu/hostmem.h" 53 #include "sysemu/numa.h" 54 55 /* Copied from the kernel arch/powerpc/platforms/pseries/msi.c */ 56 #define RTAS_QUERY_FN 0 57 #define RTAS_CHANGE_FN 1 58 #define RTAS_RESET_FN 2 59 #define RTAS_CHANGE_MSI_FN 3 60 #define RTAS_CHANGE_MSIX_FN 4 61 62 /* Interrupt types to return on RTAS_CHANGE_* */ 63 #define RTAS_TYPE_MSI 1 64 #define RTAS_TYPE_MSIX 2 65 66 SpaprPhbState *spapr_pci_find_phb(SpaprMachineState *spapr, uint64_t buid) 67 { 68 SpaprPhbState *sphb; 69 70 QLIST_FOREACH(sphb, &spapr->phbs, list) { 71 if (sphb->buid != buid) { 72 continue; 73 } 74 return sphb; 75 } 76 77 return NULL; 78 } 79 80 PCIDevice *spapr_pci_find_dev(SpaprMachineState *spapr, uint64_t buid, 81 uint32_t config_addr) 82 { 83 SpaprPhbState *sphb = spapr_pci_find_phb(spapr, buid); 84 PCIHostState *phb = PCI_HOST_BRIDGE(sphb); 85 int bus_num = (config_addr >> 16) & 0xFF; 86 int devfn = (config_addr >> 8) & 0xFF; 87 88 if (!phb) { 89 return NULL; 90 } 91 92 return pci_find_device(phb->bus, bus_num, devfn); 93 } 94 95 static uint32_t rtas_pci_cfgaddr(uint32_t arg) 96 { 97 /* This handles the encoding of extended config space addresses */ 98 return ((arg >> 20) & 0xf00) | (arg & 0xff); 99 } 100 101 static void finish_read_pci_config(SpaprMachineState *spapr, uint64_t buid, 102 uint32_t addr, uint32_t size, 103 target_ulong rets) 104 { 105 PCIDevice *pci_dev; 106 uint32_t val; 107 108 if ((size != 1) && (size != 2) && (size != 4)) { 109 /* access must be 1, 2 or 4 bytes */ 110 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 111 return; 112 } 113 114 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 115 addr = rtas_pci_cfgaddr(addr); 116 117 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 118 /* Access must be to a valid device, within bounds and 119 * naturally aligned */ 120 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 121 return; 122 } 123 124 val = pci_host_config_read_common(pci_dev, addr, 125 pci_config_size(pci_dev), size); 126 127 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 128 rtas_st(rets, 1, val); 129 } 130 131 static void rtas_ibm_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 132 uint32_t token, uint32_t nargs, 133 target_ulong args, 134 uint32_t nret, target_ulong rets) 135 { 136 uint64_t buid; 137 uint32_t size, addr; 138 139 if ((nargs != 4) || (nret != 2)) { 140 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 141 return; 142 } 143 144 buid = rtas_ldq(args, 1); 145 size = rtas_ld(args, 3); 146 addr = rtas_ld(args, 0); 147 148 finish_read_pci_config(spapr, buid, addr, size, rets); 149 } 150 151 static void rtas_read_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 152 uint32_t token, uint32_t nargs, 153 target_ulong args, 154 uint32_t nret, target_ulong rets) 155 { 156 uint32_t size, addr; 157 158 if ((nargs != 2) || (nret != 2)) { 159 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 160 return; 161 } 162 163 size = rtas_ld(args, 1); 164 addr = rtas_ld(args, 0); 165 166 finish_read_pci_config(spapr, 0, addr, size, rets); 167 } 168 169 static void finish_write_pci_config(SpaprMachineState *spapr, uint64_t buid, 170 uint32_t addr, uint32_t size, 171 uint32_t val, target_ulong rets) 172 { 173 PCIDevice *pci_dev; 174 175 if ((size != 1) && (size != 2) && (size != 4)) { 176 /* access must be 1, 2 or 4 bytes */ 177 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 178 return; 179 } 180 181 pci_dev = spapr_pci_find_dev(spapr, buid, addr); 182 addr = rtas_pci_cfgaddr(addr); 183 184 if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { 185 /* Access must be to a valid device, within bounds and 186 * naturally aligned */ 187 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 188 return; 189 } 190 191 pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), 192 val, size); 193 194 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 195 } 196 197 static void rtas_ibm_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 198 uint32_t token, uint32_t nargs, 199 target_ulong args, 200 uint32_t nret, target_ulong rets) 201 { 202 uint64_t buid; 203 uint32_t val, size, addr; 204 205 if ((nargs != 5) || (nret != 1)) { 206 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 207 return; 208 } 209 210 buid = rtas_ldq(args, 1); 211 val = rtas_ld(args, 4); 212 size = rtas_ld(args, 3); 213 addr = rtas_ld(args, 0); 214 215 finish_write_pci_config(spapr, buid, addr, size, val, rets); 216 } 217 218 static void rtas_write_pci_config(PowerPCCPU *cpu, SpaprMachineState *spapr, 219 uint32_t token, uint32_t nargs, 220 target_ulong args, 221 uint32_t nret, target_ulong rets) 222 { 223 uint32_t val, size, addr; 224 225 if ((nargs != 3) || (nret != 1)) { 226 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 227 return; 228 } 229 230 231 val = rtas_ld(args, 2); 232 size = rtas_ld(args, 1); 233 addr = rtas_ld(args, 0); 234 235 finish_write_pci_config(spapr, 0, addr, size, val, rets); 236 } 237 238 /* 239 * Set MSI/MSIX message data. 240 * This is required for msi_notify()/msix_notify() which 241 * will write at the addresses via spapr_msi_write(). 242 * 243 * If hwaddr == 0, all entries will have .data == first_irq i.e. 244 * table will be reset. 245 */ 246 static void spapr_msi_setmsg(PCIDevice *pdev, hwaddr addr, bool msix, 247 unsigned first_irq, unsigned req_num) 248 { 249 unsigned i; 250 MSIMessage msg = { .address = addr, .data = first_irq }; 251 252 if (!msix) { 253 msi_set_message(pdev, msg); 254 trace_spapr_pci_msi_setup(pdev->name, 0, msg.address); 255 return; 256 } 257 258 for (i = 0; i < req_num; ++i) { 259 msix_set_message(pdev, i, msg); 260 trace_spapr_pci_msi_setup(pdev->name, i, msg.address); 261 if (addr) { 262 ++msg.data; 263 } 264 } 265 } 266 267 static void rtas_ibm_change_msi(PowerPCCPU *cpu, SpaprMachineState *spapr, 268 uint32_t token, uint32_t nargs, 269 target_ulong args, uint32_t nret, 270 target_ulong rets) 271 { 272 SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(spapr); 273 uint32_t config_addr = rtas_ld(args, 0); 274 uint64_t buid = rtas_ldq(args, 1); 275 unsigned int func = rtas_ld(args, 3); 276 unsigned int req_num = rtas_ld(args, 4); /* 0 == remove all */ 277 unsigned int seq_num = rtas_ld(args, 5); 278 unsigned int ret_intr_type; 279 unsigned int irq, max_irqs = 0; 280 SpaprPhbState *phb = NULL; 281 PCIDevice *pdev = NULL; 282 spapr_pci_msi *msi; 283 int *config_addr_key; 284 Error *err = NULL; 285 int i; 286 287 /* Fins SpaprPhbState */ 288 phb = spapr_pci_find_phb(spapr, buid); 289 if (phb) { 290 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 291 } 292 if (!phb || !pdev) { 293 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 294 return; 295 } 296 297 switch (func) { 298 case RTAS_CHANGE_FN: 299 if (msi_present(pdev)) { 300 ret_intr_type = RTAS_TYPE_MSI; 301 } else if (msix_present(pdev)) { 302 ret_intr_type = RTAS_TYPE_MSIX; 303 } else { 304 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 305 return; 306 } 307 break; 308 case RTAS_CHANGE_MSI_FN: 309 if (msi_present(pdev)) { 310 ret_intr_type = RTAS_TYPE_MSI; 311 } else { 312 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 313 return; 314 } 315 break; 316 case RTAS_CHANGE_MSIX_FN: 317 if (msix_present(pdev)) { 318 ret_intr_type = RTAS_TYPE_MSIX; 319 } else { 320 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 321 return; 322 } 323 break; 324 default: 325 error_report("rtas_ibm_change_msi(%u) is not implemented", func); 326 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 327 return; 328 } 329 330 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 331 332 /* Releasing MSIs */ 333 if (!req_num) { 334 if (!msi) { 335 trace_spapr_pci_msi("Releasing wrong config", config_addr); 336 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 337 return; 338 } 339 340 if (!smc->legacy_irq_allocation) { 341 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 342 } 343 spapr_irq_free(spapr, msi->first_irq, msi->num); 344 if (msi_present(pdev)) { 345 spapr_msi_setmsg(pdev, 0, false, 0, 0); 346 } 347 if (msix_present(pdev)) { 348 spapr_msi_setmsg(pdev, 0, true, 0, 0); 349 } 350 g_hash_table_remove(phb->msi, &config_addr); 351 352 trace_spapr_pci_msi("Released MSIs", config_addr); 353 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 354 rtas_st(rets, 1, 0); 355 return; 356 } 357 358 /* Enabling MSI */ 359 360 /* Check if the device supports as many IRQs as requested */ 361 if (ret_intr_type == RTAS_TYPE_MSI) { 362 max_irqs = msi_nr_vectors_allocated(pdev); 363 } else if (ret_intr_type == RTAS_TYPE_MSIX) { 364 max_irqs = pdev->msix_entries_nr; 365 } 366 if (!max_irqs) { 367 error_report("Requested interrupt type %d is not enabled for device %x", 368 ret_intr_type, config_addr); 369 rtas_st(rets, 0, -1); /* Hardware error */ 370 return; 371 } 372 /* Correct the number if the guest asked for too many */ 373 if (req_num > max_irqs) { 374 trace_spapr_pci_msi_retry(config_addr, req_num, max_irqs); 375 req_num = max_irqs; 376 irq = 0; /* to avoid misleading trace */ 377 goto out; 378 } 379 380 /* Allocate MSIs */ 381 if (smc->legacy_irq_allocation) { 382 irq = spapr_irq_find(spapr, req_num, ret_intr_type == RTAS_TYPE_MSI, 383 &err); 384 } else { 385 irq = spapr_irq_msi_alloc(spapr, req_num, 386 ret_intr_type == RTAS_TYPE_MSI, &err); 387 } 388 if (err) { 389 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 390 config_addr); 391 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 392 return; 393 } 394 395 for (i = 0; i < req_num; i++) { 396 spapr_irq_claim(spapr, irq + i, false, &err); 397 if (err) { 398 if (i) { 399 spapr_irq_free(spapr, irq, i); 400 } 401 if (!smc->legacy_irq_allocation) { 402 spapr_irq_msi_free(spapr, irq, req_num); 403 } 404 error_reportf_err(err, "Can't allocate MSIs for device %x: ", 405 config_addr); 406 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 407 return; 408 } 409 } 410 411 /* Release previous MSIs */ 412 if (msi) { 413 if (!smc->legacy_irq_allocation) { 414 spapr_irq_msi_free(spapr, msi->first_irq, msi->num); 415 } 416 spapr_irq_free(spapr, msi->first_irq, msi->num); 417 g_hash_table_remove(phb->msi, &config_addr); 418 } 419 420 /* Setup MSI/MSIX vectors in the device (via cfgspace or MSIX BAR) */ 421 spapr_msi_setmsg(pdev, SPAPR_PCI_MSI_WINDOW, ret_intr_type == RTAS_TYPE_MSIX, 422 irq, req_num); 423 424 /* Add MSI device to cache */ 425 msi = g_new(spapr_pci_msi, 1); 426 msi->first_irq = irq; 427 msi->num = req_num; 428 config_addr_key = g_new(int, 1); 429 *config_addr_key = config_addr; 430 g_hash_table_insert(phb->msi, config_addr_key, msi); 431 432 out: 433 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 434 rtas_st(rets, 1, req_num); 435 rtas_st(rets, 2, ++seq_num); 436 if (nret > 3) { 437 rtas_st(rets, 3, ret_intr_type); 438 } 439 440 trace_spapr_pci_rtas_ibm_change_msi(config_addr, func, req_num, irq); 441 } 442 443 static void rtas_ibm_query_interrupt_source_number(PowerPCCPU *cpu, 444 SpaprMachineState *spapr, 445 uint32_t token, 446 uint32_t nargs, 447 target_ulong args, 448 uint32_t nret, 449 target_ulong rets) 450 { 451 uint32_t config_addr = rtas_ld(args, 0); 452 uint64_t buid = rtas_ldq(args, 1); 453 unsigned int intr_src_num = -1, ioa_intr_num = rtas_ld(args, 3); 454 SpaprPhbState *phb = NULL; 455 PCIDevice *pdev = NULL; 456 spapr_pci_msi *msi; 457 458 /* Find SpaprPhbState */ 459 phb = spapr_pci_find_phb(spapr, buid); 460 if (phb) { 461 pdev = spapr_pci_find_dev(spapr, buid, config_addr); 462 } 463 if (!phb || !pdev) { 464 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 465 return; 466 } 467 468 /* Find device descriptor and start IRQ */ 469 msi = (spapr_pci_msi *) g_hash_table_lookup(phb->msi, &config_addr); 470 if (!msi || !msi->first_irq || !msi->num || (ioa_intr_num >= msi->num)) { 471 trace_spapr_pci_msi("Failed to return vector", config_addr); 472 rtas_st(rets, 0, RTAS_OUT_HW_ERROR); 473 return; 474 } 475 intr_src_num = msi->first_irq + ioa_intr_num; 476 trace_spapr_pci_rtas_ibm_query_interrupt_source_number(ioa_intr_num, 477 intr_src_num); 478 479 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 480 rtas_st(rets, 1, intr_src_num); 481 rtas_st(rets, 2, 1);/* 0 == level; 1 == edge */ 482 } 483 484 static void rtas_ibm_set_eeh_option(PowerPCCPU *cpu, 485 SpaprMachineState *spapr, 486 uint32_t token, uint32_t nargs, 487 target_ulong args, uint32_t nret, 488 target_ulong rets) 489 { 490 SpaprPhbState *sphb; 491 uint32_t addr, option; 492 uint64_t buid; 493 int ret; 494 495 if ((nargs != 4) || (nret != 1)) { 496 goto param_error_exit; 497 } 498 499 buid = rtas_ldq(args, 1); 500 addr = rtas_ld(args, 0); 501 option = rtas_ld(args, 3); 502 503 sphb = spapr_pci_find_phb(spapr, buid); 504 if (!sphb) { 505 goto param_error_exit; 506 } 507 508 if (!spapr_phb_eeh_available(sphb)) { 509 goto param_error_exit; 510 } 511 512 ret = spapr_phb_vfio_eeh_set_option(sphb, addr, option); 513 rtas_st(rets, 0, ret); 514 return; 515 516 param_error_exit: 517 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 518 } 519 520 static void rtas_ibm_get_config_addr_info2(PowerPCCPU *cpu, 521 SpaprMachineState *spapr, 522 uint32_t token, uint32_t nargs, 523 target_ulong args, uint32_t nret, 524 target_ulong rets) 525 { 526 SpaprPhbState *sphb; 527 PCIDevice *pdev; 528 uint32_t addr, option; 529 uint64_t buid; 530 531 if ((nargs != 4) || (nret != 2)) { 532 goto param_error_exit; 533 } 534 535 buid = rtas_ldq(args, 1); 536 sphb = spapr_pci_find_phb(spapr, buid); 537 if (!sphb) { 538 goto param_error_exit; 539 } 540 541 if (!spapr_phb_eeh_available(sphb)) { 542 goto param_error_exit; 543 } 544 545 /* 546 * We always have PE address of form "00BB0001". "BB" 547 * represents the bus number of PE's primary bus. 548 */ 549 option = rtas_ld(args, 3); 550 switch (option) { 551 case RTAS_GET_PE_ADDR: 552 addr = rtas_ld(args, 0); 553 pdev = spapr_pci_find_dev(spapr, buid, addr); 554 if (!pdev) { 555 goto param_error_exit; 556 } 557 558 rtas_st(rets, 1, (pci_bus_num(pci_get_bus(pdev)) << 16) + 1); 559 break; 560 case RTAS_GET_PE_MODE: 561 rtas_st(rets, 1, RTAS_PE_MODE_SHARED); 562 break; 563 default: 564 goto param_error_exit; 565 } 566 567 rtas_st(rets, 0, RTAS_OUT_SUCCESS); 568 return; 569 570 param_error_exit: 571 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 572 } 573 574 static void rtas_ibm_read_slot_reset_state2(PowerPCCPU *cpu, 575 SpaprMachineState *spapr, 576 uint32_t token, uint32_t nargs, 577 target_ulong args, uint32_t nret, 578 target_ulong rets) 579 { 580 SpaprPhbState *sphb; 581 uint64_t buid; 582 int state, ret; 583 584 if ((nargs != 3) || (nret != 4 && nret != 5)) { 585 goto param_error_exit; 586 } 587 588 buid = rtas_ldq(args, 1); 589 sphb = spapr_pci_find_phb(spapr, buid); 590 if (!sphb) { 591 goto param_error_exit; 592 } 593 594 if (!spapr_phb_eeh_available(sphb)) { 595 goto param_error_exit; 596 } 597 598 ret = spapr_phb_vfio_eeh_get_state(sphb, &state); 599 rtas_st(rets, 0, ret); 600 if (ret != RTAS_OUT_SUCCESS) { 601 return; 602 } 603 604 rtas_st(rets, 1, state); 605 rtas_st(rets, 2, RTAS_EEH_SUPPORT); 606 rtas_st(rets, 3, RTAS_EEH_PE_UNAVAIL_INFO); 607 if (nret >= 5) { 608 rtas_st(rets, 4, RTAS_EEH_PE_RECOVER_INFO); 609 } 610 return; 611 612 param_error_exit: 613 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 614 } 615 616 static void rtas_ibm_set_slot_reset(PowerPCCPU *cpu, 617 SpaprMachineState *spapr, 618 uint32_t token, uint32_t nargs, 619 target_ulong args, uint32_t nret, 620 target_ulong rets) 621 { 622 SpaprPhbState *sphb; 623 uint32_t option; 624 uint64_t buid; 625 int ret; 626 627 if ((nargs != 4) || (nret != 1)) { 628 goto param_error_exit; 629 } 630 631 buid = rtas_ldq(args, 1); 632 option = rtas_ld(args, 3); 633 sphb = spapr_pci_find_phb(spapr, buid); 634 if (!sphb) { 635 goto param_error_exit; 636 } 637 638 if (!spapr_phb_eeh_available(sphb)) { 639 goto param_error_exit; 640 } 641 642 ret = spapr_phb_vfio_eeh_reset(sphb, option); 643 rtas_st(rets, 0, ret); 644 return; 645 646 param_error_exit: 647 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 648 } 649 650 static void rtas_ibm_configure_pe(PowerPCCPU *cpu, 651 SpaprMachineState *spapr, 652 uint32_t token, uint32_t nargs, 653 target_ulong args, uint32_t nret, 654 target_ulong rets) 655 { 656 SpaprPhbState *sphb; 657 uint64_t buid; 658 int ret; 659 660 if ((nargs != 3) || (nret != 1)) { 661 goto param_error_exit; 662 } 663 664 buid = rtas_ldq(args, 1); 665 sphb = spapr_pci_find_phb(spapr, buid); 666 if (!sphb) { 667 goto param_error_exit; 668 } 669 670 if (!spapr_phb_eeh_available(sphb)) { 671 goto param_error_exit; 672 } 673 674 ret = spapr_phb_vfio_eeh_configure(sphb); 675 rtas_st(rets, 0, ret); 676 return; 677 678 param_error_exit: 679 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 680 } 681 682 /* To support it later */ 683 static void rtas_ibm_slot_error_detail(PowerPCCPU *cpu, 684 SpaprMachineState *spapr, 685 uint32_t token, uint32_t nargs, 686 target_ulong args, uint32_t nret, 687 target_ulong rets) 688 { 689 SpaprPhbState *sphb; 690 int option; 691 uint64_t buid; 692 693 if ((nargs != 8) || (nret != 1)) { 694 goto param_error_exit; 695 } 696 697 buid = rtas_ldq(args, 1); 698 sphb = spapr_pci_find_phb(spapr, buid); 699 if (!sphb) { 700 goto param_error_exit; 701 } 702 703 if (!spapr_phb_eeh_available(sphb)) { 704 goto param_error_exit; 705 } 706 707 option = rtas_ld(args, 7); 708 switch (option) { 709 case RTAS_SLOT_TEMP_ERR_LOG: 710 case RTAS_SLOT_PERM_ERR_LOG: 711 break; 712 default: 713 goto param_error_exit; 714 } 715 716 /* We don't have error log yet */ 717 rtas_st(rets, 0, RTAS_OUT_NO_ERRORS_FOUND); 718 return; 719 720 param_error_exit: 721 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); 722 } 723 724 static void pci_spapr_set_irq(void *opaque, int irq_num, int level) 725 { 726 /* 727 * Here we use the number returned by pci_swizzle_map_irq_fn to find a 728 * corresponding qemu_irq. 729 */ 730 SpaprPhbState *phb = opaque; 731 732 trace_spapr_pci_lsi_set(phb->dtbusname, irq_num, phb->lsi_table[irq_num].irq); 733 qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); 734 } 735 736 static PCIINTxRoute spapr_route_intx_pin_to_irq(void *opaque, int pin) 737 { 738 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(opaque); 739 PCIINTxRoute route; 740 741 route.mode = PCI_INTX_ENABLED; 742 route.irq = sphb->lsi_table[pin].irq; 743 744 return route; 745 } 746 747 /* 748 * MSI/MSIX memory region implementation. 749 * The handler handles both MSI and MSIX. 750 * The vector number is encoded in least bits in data. 751 */ 752 static void spapr_msi_write(void *opaque, hwaddr addr, 753 uint64_t data, unsigned size) 754 { 755 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 756 uint32_t irq = data; 757 758 trace_spapr_pci_msi_write(addr, data, irq); 759 760 qemu_irq_pulse(spapr_qirq(spapr, irq)); 761 } 762 763 static const MemoryRegionOps spapr_msi_ops = { 764 /* There is no .read as the read result is undefined by PCI spec */ 765 .read = NULL, 766 .write = spapr_msi_write, 767 .endianness = DEVICE_LITTLE_ENDIAN 768 }; 769 770 /* 771 * PHB PCI device 772 */ 773 static AddressSpace *spapr_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) 774 { 775 SpaprPhbState *phb = opaque; 776 777 return &phb->iommu_as; 778 } 779 780 static char *spapr_phb_vfio_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 781 { 782 char *path = NULL, *buf = NULL, *host = NULL; 783 784 /* Get the PCI VFIO host id */ 785 host = object_property_get_str(OBJECT(pdev), "host", NULL); 786 if (!host) { 787 goto err_out; 788 } 789 790 /* Construct the path of the file that will give us the DT location */ 791 path = g_strdup_printf("/sys/bus/pci/devices/%s/devspec", host); 792 g_free(host); 793 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 794 goto err_out; 795 } 796 g_free(path); 797 798 /* Construct and read from host device tree the loc-code */ 799 path = g_strdup_printf("/proc/device-tree%s/ibm,loc-code", buf); 800 g_free(buf); 801 if (!g_file_get_contents(path, &buf, NULL, NULL)) { 802 goto err_out; 803 } 804 return buf; 805 806 err_out: 807 g_free(path); 808 return NULL; 809 } 810 811 static char *spapr_phb_get_loc_code(SpaprPhbState *sphb, PCIDevice *pdev) 812 { 813 char *buf; 814 const char *devtype = "qemu"; 815 uint32_t busnr = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(pdev)))); 816 817 if (object_dynamic_cast(OBJECT(pdev), "vfio-pci")) { 818 buf = spapr_phb_vfio_get_loc_code(sphb, pdev); 819 if (buf) { 820 return buf; 821 } 822 devtype = "vfio"; 823 } 824 /* 825 * For emulated devices and VFIO-failure case, make up 826 * the loc-code. 827 */ 828 buf = g_strdup_printf("%s_%s:%04x:%02x:%02x.%x", 829 devtype, pdev->name, sphb->index, busnr, 830 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); 831 return buf; 832 } 833 834 /* Macros to operate with address in OF binding to PCI */ 835 #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) 836 #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ 837 #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ 838 #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ 839 #define b_ss(x) b_x((x), 24, 2) /* the space code */ 840 #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ 841 #define b_ddddd(x) b_x((x), 11, 5) /* device number */ 842 #define b_fff(x) b_x((x), 8, 3) /* function number */ 843 #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ 844 845 /* for 'reg'/'assigned-addresses' OF properties */ 846 #define RESOURCE_CELLS_SIZE 2 847 #define RESOURCE_CELLS_ADDRESS 3 848 849 typedef struct ResourceFields { 850 uint32_t phys_hi; 851 uint32_t phys_mid; 852 uint32_t phys_lo; 853 uint32_t size_hi; 854 uint32_t size_lo; 855 } QEMU_PACKED ResourceFields; 856 857 typedef struct ResourceProps { 858 ResourceFields reg[8]; 859 ResourceFields assigned[7]; 860 uint32_t reg_len; 861 uint32_t assigned_len; 862 } ResourceProps; 863 864 /* fill in the 'reg'/'assigned-resources' OF properties for 865 * a PCI device. 'reg' describes resource requirements for a 866 * device's IO/MEM regions, 'assigned-addresses' describes the 867 * actual resource assignments. 868 * 869 * the properties are arrays of ('phys-addr', 'size') pairs describing 870 * the addressable regions of the PCI device, where 'phys-addr' is a 871 * RESOURCE_CELLS_ADDRESS-tuple of 32-bit integers corresponding to 872 * (phys.hi, phys.mid, phys.lo), and 'size' is a 873 * RESOURCE_CELLS_SIZE-tuple corresponding to (size.hi, size.lo). 874 * 875 * phys.hi = 0xYYXXXXZZ, where: 876 * 0xYY = npt000ss 877 * ||| | 878 * ||| +-- space code 879 * ||| | 880 * ||| + 00 if configuration space 881 * ||| + 01 if IO region, 882 * ||| + 10 if 32-bit MEM region 883 * ||| + 11 if 64-bit MEM region 884 * ||| 885 * ||+------ for non-relocatable IO: 1 if aliased 886 * || for relocatable IO: 1 if below 64KB 887 * || for MEM: 1 if below 1MB 888 * |+------- 1 if region is prefetchable 889 * +-------- 1 if region is non-relocatable 890 * 0xXXXX = bbbbbbbb dddddfff, encoding bus, slot, and function 891 * bits respectively 892 * 0xZZ = rrrrrrrr, the register number of the BAR corresponding 893 * to the region 894 * 895 * phys.mid and phys.lo correspond respectively to the hi/lo portions 896 * of the actual address of the region. 897 * 898 * how the phys-addr/size values are used differ slightly between 899 * 'reg' and 'assigned-addresses' properties. namely, 'reg' has 900 * an additional description for the config space region of the 901 * device, and in the case of QEMU has n=0 and phys.mid=phys.lo=0 902 * to describe the region as relocatable, with an address-mapping 903 * that corresponds directly to the PHB's address space for the 904 * resource. 'assigned-addresses' always has n=1 set with an absolute 905 * address assigned for the resource. in general, 'assigned-addresses' 906 * won't be populated, since addresses for PCI devices are generally 907 * unmapped initially and left to the guest to assign. 908 * 909 * note also that addresses defined in these properties are, at least 910 * for PAPR guests, relative to the PHBs IO/MEM windows, and 911 * correspond directly to the addresses in the BARs. 912 * 913 * in accordance with PCI Bus Binding to Open Firmware, 914 * IEEE Std 1275-1994, section 4.1.1, as implemented by PAPR+ v2.7, 915 * Appendix C. 916 */ 917 static void populate_resource_props(PCIDevice *d, ResourceProps *rp) 918 { 919 int bus_num = pci_bus_num(PCI_BUS(qdev_get_parent_bus(DEVICE(d)))); 920 uint32_t dev_id = (b_bbbbbbbb(bus_num) | 921 b_ddddd(PCI_SLOT(d->devfn)) | 922 b_fff(PCI_FUNC(d->devfn))); 923 ResourceFields *reg, *assigned; 924 int i, reg_idx = 0, assigned_idx = 0; 925 926 /* config space region */ 927 reg = &rp->reg[reg_idx++]; 928 reg->phys_hi = cpu_to_be32(dev_id); 929 reg->phys_mid = 0; 930 reg->phys_lo = 0; 931 reg->size_hi = 0; 932 reg->size_lo = 0; 933 934 for (i = 0; i < PCI_NUM_REGIONS; i++) { 935 if (!d->io_regions[i].size) { 936 continue; 937 } 938 939 reg = &rp->reg[reg_idx++]; 940 941 reg->phys_hi = cpu_to_be32(dev_id | b_rrrrrrrr(pci_bar(d, i))); 942 if (d->io_regions[i].type & PCI_BASE_ADDRESS_SPACE_IO) { 943 reg->phys_hi |= cpu_to_be32(b_ss(1)); 944 } else if (d->io_regions[i].type & PCI_BASE_ADDRESS_MEM_TYPE_64) { 945 reg->phys_hi |= cpu_to_be32(b_ss(3)); 946 } else { 947 reg->phys_hi |= cpu_to_be32(b_ss(2)); 948 } 949 reg->phys_mid = 0; 950 reg->phys_lo = 0; 951 reg->size_hi = cpu_to_be32(d->io_regions[i].size >> 32); 952 reg->size_lo = cpu_to_be32(d->io_regions[i].size); 953 954 if (d->io_regions[i].addr == PCI_BAR_UNMAPPED) { 955 continue; 956 } 957 958 assigned = &rp->assigned[assigned_idx++]; 959 assigned->phys_hi = cpu_to_be32(be32_to_cpu(reg->phys_hi) | b_n(1)); 960 assigned->phys_mid = cpu_to_be32(d->io_regions[i].addr >> 32); 961 assigned->phys_lo = cpu_to_be32(d->io_regions[i].addr); 962 assigned->size_hi = reg->size_hi; 963 assigned->size_lo = reg->size_lo; 964 } 965 966 rp->reg_len = reg_idx * sizeof(ResourceFields); 967 rp->assigned_len = assigned_idx * sizeof(ResourceFields); 968 } 969 970 typedef struct PCIClass PCIClass; 971 typedef struct PCISubClass PCISubClass; 972 typedef struct PCIIFace PCIIFace; 973 974 struct PCIIFace { 975 int iface; 976 const char *name; 977 }; 978 979 struct PCISubClass { 980 int subclass; 981 const char *name; 982 const PCIIFace *iface; 983 }; 984 985 struct PCIClass { 986 const char *name; 987 const PCISubClass *subc; 988 }; 989 990 static const PCISubClass undef_subclass[] = { 991 { PCI_CLASS_NOT_DEFINED_VGA, "display", NULL }, 992 { 0xFF, NULL, NULL }, 993 }; 994 995 static const PCISubClass mass_subclass[] = { 996 { PCI_CLASS_STORAGE_SCSI, "scsi", NULL }, 997 { PCI_CLASS_STORAGE_IDE, "ide", NULL }, 998 { PCI_CLASS_STORAGE_FLOPPY, "fdc", NULL }, 999 { PCI_CLASS_STORAGE_IPI, "ipi", NULL }, 1000 { PCI_CLASS_STORAGE_RAID, "raid", NULL }, 1001 { PCI_CLASS_STORAGE_ATA, "ata", NULL }, 1002 { PCI_CLASS_STORAGE_SATA, "sata", NULL }, 1003 { PCI_CLASS_STORAGE_SAS, "sas", NULL }, 1004 { 0xFF, NULL, NULL }, 1005 }; 1006 1007 static const PCISubClass net_subclass[] = { 1008 { PCI_CLASS_NETWORK_ETHERNET, "ethernet", NULL }, 1009 { PCI_CLASS_NETWORK_TOKEN_RING, "token-ring", NULL }, 1010 { PCI_CLASS_NETWORK_FDDI, "fddi", NULL }, 1011 { PCI_CLASS_NETWORK_ATM, "atm", NULL }, 1012 { PCI_CLASS_NETWORK_ISDN, "isdn", NULL }, 1013 { PCI_CLASS_NETWORK_WORLDFIP, "worldfip", NULL }, 1014 { PCI_CLASS_NETWORK_PICMG214, "picmg", NULL }, 1015 { 0xFF, NULL, NULL }, 1016 }; 1017 1018 static const PCISubClass displ_subclass[] = { 1019 { PCI_CLASS_DISPLAY_VGA, "vga", NULL }, 1020 { PCI_CLASS_DISPLAY_XGA, "xga", NULL }, 1021 { PCI_CLASS_DISPLAY_3D, "3d-controller", NULL }, 1022 { 0xFF, NULL, NULL }, 1023 }; 1024 1025 static const PCISubClass media_subclass[] = { 1026 { PCI_CLASS_MULTIMEDIA_VIDEO, "video", NULL }, 1027 { PCI_CLASS_MULTIMEDIA_AUDIO, "sound", NULL }, 1028 { PCI_CLASS_MULTIMEDIA_PHONE, "telephony", NULL }, 1029 { 0xFF, NULL, NULL }, 1030 }; 1031 1032 static const PCISubClass mem_subclass[] = { 1033 { PCI_CLASS_MEMORY_RAM, "memory", NULL }, 1034 { PCI_CLASS_MEMORY_FLASH, "flash", NULL }, 1035 { 0xFF, NULL, NULL }, 1036 }; 1037 1038 static const PCISubClass bridg_subclass[] = { 1039 { PCI_CLASS_BRIDGE_HOST, "host", NULL }, 1040 { PCI_CLASS_BRIDGE_ISA, "isa", NULL }, 1041 { PCI_CLASS_BRIDGE_EISA, "eisa", NULL }, 1042 { PCI_CLASS_BRIDGE_MC, "mca", NULL }, 1043 { PCI_CLASS_BRIDGE_PCI, "pci", NULL }, 1044 { PCI_CLASS_BRIDGE_PCMCIA, "pcmcia", NULL }, 1045 { PCI_CLASS_BRIDGE_NUBUS, "nubus", NULL }, 1046 { PCI_CLASS_BRIDGE_CARDBUS, "cardbus", NULL }, 1047 { PCI_CLASS_BRIDGE_RACEWAY, "raceway", NULL }, 1048 { PCI_CLASS_BRIDGE_PCI_SEMITP, "semi-transparent-pci", NULL }, 1049 { PCI_CLASS_BRIDGE_IB_PCI, "infiniband", NULL }, 1050 { 0xFF, NULL, NULL }, 1051 }; 1052 1053 static const PCISubClass comm_subclass[] = { 1054 { PCI_CLASS_COMMUNICATION_SERIAL, "serial", NULL }, 1055 { PCI_CLASS_COMMUNICATION_PARALLEL, "parallel", NULL }, 1056 { PCI_CLASS_COMMUNICATION_MULTISERIAL, "multiport-serial", NULL }, 1057 { PCI_CLASS_COMMUNICATION_MODEM, "modem", NULL }, 1058 { PCI_CLASS_COMMUNICATION_GPIB, "gpib", NULL }, 1059 { PCI_CLASS_COMMUNICATION_SC, "smart-card", NULL }, 1060 { 0xFF, NULL, NULL, }, 1061 }; 1062 1063 static const PCIIFace pic_iface[] = { 1064 { PCI_CLASS_SYSTEM_PIC_IOAPIC, "io-apic" }, 1065 { PCI_CLASS_SYSTEM_PIC_IOXAPIC, "io-xapic" }, 1066 { 0xFF, NULL }, 1067 }; 1068 1069 static const PCISubClass sys_subclass[] = { 1070 { PCI_CLASS_SYSTEM_PIC, "interrupt-controller", pic_iface }, 1071 { PCI_CLASS_SYSTEM_DMA, "dma-controller", NULL }, 1072 { PCI_CLASS_SYSTEM_TIMER, "timer", NULL }, 1073 { PCI_CLASS_SYSTEM_RTC, "rtc", NULL }, 1074 { PCI_CLASS_SYSTEM_PCI_HOTPLUG, "hot-plug-controller", NULL }, 1075 { PCI_CLASS_SYSTEM_SDHCI, "sd-host-controller", NULL }, 1076 { 0xFF, NULL, NULL }, 1077 }; 1078 1079 static const PCISubClass inp_subclass[] = { 1080 { PCI_CLASS_INPUT_KEYBOARD, "keyboard", NULL }, 1081 { PCI_CLASS_INPUT_PEN, "pen", NULL }, 1082 { PCI_CLASS_INPUT_MOUSE, "mouse", NULL }, 1083 { PCI_CLASS_INPUT_SCANNER, "scanner", NULL }, 1084 { PCI_CLASS_INPUT_GAMEPORT, "gameport", NULL }, 1085 { 0xFF, NULL, NULL }, 1086 }; 1087 1088 static const PCISubClass dock_subclass[] = { 1089 { PCI_CLASS_DOCKING_GENERIC, "dock", NULL }, 1090 { 0xFF, NULL, NULL }, 1091 }; 1092 1093 static const PCISubClass cpu_subclass[] = { 1094 { PCI_CLASS_PROCESSOR_PENTIUM, "pentium", NULL }, 1095 { PCI_CLASS_PROCESSOR_POWERPC, "powerpc", NULL }, 1096 { PCI_CLASS_PROCESSOR_MIPS, "mips", NULL }, 1097 { PCI_CLASS_PROCESSOR_CO, "co-processor", NULL }, 1098 { 0xFF, NULL, NULL }, 1099 }; 1100 1101 static const PCIIFace usb_iface[] = { 1102 { PCI_CLASS_SERIAL_USB_UHCI, "usb-uhci" }, 1103 { PCI_CLASS_SERIAL_USB_OHCI, "usb-ohci", }, 1104 { PCI_CLASS_SERIAL_USB_EHCI, "usb-ehci" }, 1105 { PCI_CLASS_SERIAL_USB_XHCI, "usb-xhci" }, 1106 { PCI_CLASS_SERIAL_USB_UNKNOWN, "usb-unknown" }, 1107 { PCI_CLASS_SERIAL_USB_DEVICE, "usb-device" }, 1108 { 0xFF, NULL }, 1109 }; 1110 1111 static const PCISubClass ser_subclass[] = { 1112 { PCI_CLASS_SERIAL_FIREWIRE, "firewire", NULL }, 1113 { PCI_CLASS_SERIAL_ACCESS, "access-bus", NULL }, 1114 { PCI_CLASS_SERIAL_SSA, "ssa", NULL }, 1115 { PCI_CLASS_SERIAL_USB, "usb", usb_iface }, 1116 { PCI_CLASS_SERIAL_FIBER, "fibre-channel", NULL }, 1117 { PCI_CLASS_SERIAL_SMBUS, "smb", NULL }, 1118 { PCI_CLASS_SERIAL_IB, "infiniband", NULL }, 1119 { PCI_CLASS_SERIAL_IPMI, "ipmi", NULL }, 1120 { PCI_CLASS_SERIAL_SERCOS, "sercos", NULL }, 1121 { PCI_CLASS_SERIAL_CANBUS, "canbus", NULL }, 1122 { 0xFF, NULL, NULL }, 1123 }; 1124 1125 static const PCISubClass wrl_subclass[] = { 1126 { PCI_CLASS_WIRELESS_IRDA, "irda", NULL }, 1127 { PCI_CLASS_WIRELESS_CIR, "consumer-ir", NULL }, 1128 { PCI_CLASS_WIRELESS_RF_CONTROLLER, "rf-controller", NULL }, 1129 { PCI_CLASS_WIRELESS_BLUETOOTH, "bluetooth", NULL }, 1130 { PCI_CLASS_WIRELESS_BROADBAND, "broadband", NULL }, 1131 { 0xFF, NULL, NULL }, 1132 }; 1133 1134 static const PCISubClass sat_subclass[] = { 1135 { PCI_CLASS_SATELLITE_TV, "satellite-tv", NULL }, 1136 { PCI_CLASS_SATELLITE_AUDIO, "satellite-audio", NULL }, 1137 { PCI_CLASS_SATELLITE_VOICE, "satellite-voice", NULL }, 1138 { PCI_CLASS_SATELLITE_DATA, "satellite-data", NULL }, 1139 { 0xFF, NULL, NULL }, 1140 }; 1141 1142 static const PCISubClass crypt_subclass[] = { 1143 { PCI_CLASS_CRYPT_NETWORK, "network-encryption", NULL }, 1144 { PCI_CLASS_CRYPT_ENTERTAINMENT, 1145 "entertainment-encryption", NULL }, 1146 { 0xFF, NULL, NULL }, 1147 }; 1148 1149 static const PCISubClass spc_subclass[] = { 1150 { PCI_CLASS_SP_DPIO, "dpio", NULL }, 1151 { PCI_CLASS_SP_PERF, "counter", NULL }, 1152 { PCI_CLASS_SP_SYNCH, "measurement", NULL }, 1153 { PCI_CLASS_SP_MANAGEMENT, "management-card", NULL }, 1154 { 0xFF, NULL, NULL }, 1155 }; 1156 1157 static const PCIClass pci_classes[] = { 1158 { "legacy-device", undef_subclass }, 1159 { "mass-storage", mass_subclass }, 1160 { "network", net_subclass }, 1161 { "display", displ_subclass, }, 1162 { "multimedia-device", media_subclass }, 1163 { "memory-controller", mem_subclass }, 1164 { "unknown-bridge", bridg_subclass }, 1165 { "communication-controller", comm_subclass}, 1166 { "system-peripheral", sys_subclass }, 1167 { "input-controller", inp_subclass }, 1168 { "docking-station", dock_subclass }, 1169 { "cpu", cpu_subclass }, 1170 { "serial-bus", ser_subclass }, 1171 { "wireless-controller", wrl_subclass }, 1172 { "intelligent-io", NULL }, 1173 { "satellite-device", sat_subclass }, 1174 { "encryption", crypt_subclass }, 1175 { "data-processing-controller", spc_subclass }, 1176 }; 1177 1178 static const char *dt_name_from_class(uint8_t class, uint8_t subclass, 1179 uint8_t iface) 1180 { 1181 const PCIClass *pclass; 1182 const PCISubClass *psubclass; 1183 const PCIIFace *piface; 1184 const char *name; 1185 1186 if (class >= ARRAY_SIZE(pci_classes)) { 1187 return "pci"; 1188 } 1189 1190 pclass = pci_classes + class; 1191 name = pclass->name; 1192 1193 if (pclass->subc == NULL) { 1194 return name; 1195 } 1196 1197 psubclass = pclass->subc; 1198 while ((psubclass->subclass & 0xff) != 0xff) { 1199 if ((psubclass->subclass & 0xff) == subclass) { 1200 name = psubclass->name; 1201 break; 1202 } 1203 psubclass++; 1204 } 1205 1206 piface = psubclass->iface; 1207 if (piface == NULL) { 1208 return name; 1209 } 1210 while ((piface->iface & 0xff) != 0xff) { 1211 if ((piface->iface & 0xff) == iface) { 1212 name = piface->name; 1213 break; 1214 } 1215 piface++; 1216 } 1217 1218 return name; 1219 } 1220 1221 /* 1222 * DRC helper functions 1223 */ 1224 1225 static uint32_t drc_id_from_devfn(SpaprPhbState *phb, 1226 uint8_t chassis, int32_t devfn) 1227 { 1228 return (phb->index << 16) | (chassis << 8) | devfn; 1229 } 1230 1231 static SpaprDrc *drc_from_devfn(SpaprPhbState *phb, 1232 uint8_t chassis, int32_t devfn) 1233 { 1234 return spapr_drc_by_id(TYPE_SPAPR_DRC_PCI, 1235 drc_id_from_devfn(phb, chassis, devfn)); 1236 } 1237 1238 static uint8_t chassis_from_bus(PCIBus *bus, Error **errp) 1239 { 1240 if (pci_bus_is_root(bus)) { 1241 return 0; 1242 } else { 1243 PCIDevice *bridge = pci_bridge_get_device(bus); 1244 1245 return object_property_get_uint(OBJECT(bridge), "chassis_nr", errp); 1246 } 1247 } 1248 1249 static SpaprDrc *drc_from_dev(SpaprPhbState *phb, PCIDevice *dev) 1250 { 1251 Error *local_err = NULL; 1252 uint8_t chassis = chassis_from_bus(pci_get_bus(dev), &local_err); 1253 1254 if (local_err) { 1255 error_report_err(local_err); 1256 return NULL; 1257 } 1258 1259 return drc_from_devfn(phb, chassis, dev->devfn); 1260 } 1261 1262 static void add_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) 1263 { 1264 Object *owner; 1265 int i; 1266 uint8_t chassis; 1267 Error *local_err = NULL; 1268 1269 if (!phb->dr_enabled) { 1270 return; 1271 } 1272 1273 chassis = chassis_from_bus(bus, &local_err); 1274 if (local_err) { 1275 error_propagate(errp, local_err); 1276 return; 1277 } 1278 1279 if (pci_bus_is_root(bus)) { 1280 owner = OBJECT(phb); 1281 } else { 1282 owner = OBJECT(pci_bridge_get_device(bus)); 1283 } 1284 1285 for (i = 0; i < PCI_SLOT_MAX * PCI_FUNC_MAX; i++) { 1286 spapr_dr_connector_new(owner, TYPE_SPAPR_DRC_PCI, 1287 drc_id_from_devfn(phb, chassis, i)); 1288 } 1289 } 1290 1291 static void remove_drcs(SpaprPhbState *phb, PCIBus *bus, Error **errp) 1292 { 1293 int i; 1294 uint8_t chassis; 1295 Error *local_err = NULL; 1296 1297 if (!phb->dr_enabled) { 1298 return; 1299 } 1300 1301 chassis = chassis_from_bus(bus, &local_err); 1302 if (local_err) { 1303 error_propagate(errp, local_err); 1304 return; 1305 } 1306 1307 for (i = PCI_SLOT_MAX * PCI_FUNC_MAX - 1; i >= 0; i--) { 1308 SpaprDrc *drc = drc_from_devfn(phb, chassis, i); 1309 1310 if (drc) { 1311 object_unparent(OBJECT(drc)); 1312 } 1313 } 1314 } 1315 1316 typedef struct PciWalkFdt { 1317 void *fdt; 1318 int offset; 1319 SpaprPhbState *sphb; 1320 int err; 1321 } PciWalkFdt; 1322 1323 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1324 void *fdt, int parent_offset); 1325 1326 static void spapr_dt_pci_device_cb(PCIBus *bus, PCIDevice *pdev, 1327 void *opaque) 1328 { 1329 PciWalkFdt *p = opaque; 1330 int err; 1331 1332 if (p->err) { 1333 /* Something's already broken, don't keep going */ 1334 return; 1335 } 1336 1337 err = spapr_dt_pci_device(p->sphb, pdev, p->fdt, p->offset); 1338 if (err < 0) { 1339 p->err = err; 1340 } 1341 } 1342 1343 /* Augment PCI device node with bridge specific information */ 1344 static int spapr_dt_pci_bus(SpaprPhbState *sphb, PCIBus *bus, 1345 void *fdt, int offset) 1346 { 1347 Object *owner; 1348 PciWalkFdt cbinfo = { 1349 .fdt = fdt, 1350 .offset = offset, 1351 .sphb = sphb, 1352 .err = 0, 1353 }; 1354 int ret; 1355 1356 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 1357 RESOURCE_CELLS_ADDRESS)); 1358 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1359 RESOURCE_CELLS_SIZE)); 1360 1361 assert(bus); 1362 pci_for_each_device_reverse(bus, pci_bus_num(bus), 1363 spapr_dt_pci_device_cb, &cbinfo); 1364 if (cbinfo.err) { 1365 return cbinfo.err; 1366 } 1367 1368 if (pci_bus_is_root(bus)) { 1369 owner = OBJECT(sphb); 1370 } else { 1371 owner = OBJECT(pci_bridge_get_device(bus)); 1372 } 1373 1374 ret = spapr_dt_drc(fdt, offset, owner, 1375 SPAPR_DR_CONNECTOR_TYPE_PCI); 1376 if (ret) { 1377 return ret; 1378 } 1379 1380 return offset; 1381 } 1382 1383 /* create OF node for pci device and required OF DT properties */ 1384 static int spapr_dt_pci_device(SpaprPhbState *sphb, PCIDevice *dev, 1385 void *fdt, int parent_offset) 1386 { 1387 int offset; 1388 const gchar *basename; 1389 gchar *nodename; 1390 int slot = PCI_SLOT(dev->devfn); 1391 int func = PCI_FUNC(dev->devfn); 1392 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); 1393 ResourceProps rp; 1394 SpaprDrc *drc = drc_from_dev(sphb, dev); 1395 uint32_t vendor_id = pci_default_read_config(dev, PCI_VENDOR_ID, 2); 1396 uint32_t device_id = pci_default_read_config(dev, PCI_DEVICE_ID, 2); 1397 uint32_t revision_id = pci_default_read_config(dev, PCI_REVISION_ID, 1); 1398 uint32_t ccode = pci_default_read_config(dev, PCI_CLASS_PROG, 3); 1399 uint32_t irq_pin = pci_default_read_config(dev, PCI_INTERRUPT_PIN, 1); 1400 uint32_t subsystem_id = pci_default_read_config(dev, PCI_SUBSYSTEM_ID, 2); 1401 uint32_t subsystem_vendor_id = 1402 pci_default_read_config(dev, PCI_SUBSYSTEM_VENDOR_ID, 2); 1403 uint32_t cache_line_size = 1404 pci_default_read_config(dev, PCI_CACHE_LINE_SIZE, 1); 1405 uint32_t pci_status = pci_default_read_config(dev, PCI_STATUS, 2); 1406 gchar *loc_code; 1407 1408 basename = dt_name_from_class((ccode >> 16) & 0xff, (ccode >> 8) & 0xff, 1409 ccode & 0xff); 1410 1411 if (func != 0) { 1412 nodename = g_strdup_printf("%s@%x,%x", basename, slot, func); 1413 } else { 1414 nodename = g_strdup_printf("%s@%x", basename, slot); 1415 } 1416 1417 _FDT(offset = fdt_add_subnode(fdt, parent_offset, nodename)); 1418 1419 g_free(nodename); 1420 1421 /* in accordance with PAPR+ v2.7 13.6.3, Table 181 */ 1422 _FDT(fdt_setprop_cell(fdt, offset, "vendor-id", vendor_id)); 1423 _FDT(fdt_setprop_cell(fdt, offset, "device-id", device_id)); 1424 _FDT(fdt_setprop_cell(fdt, offset, "revision-id", revision_id)); 1425 1426 _FDT(fdt_setprop_cell(fdt, offset, "class-code", ccode)); 1427 if (irq_pin) { 1428 _FDT(fdt_setprop_cell(fdt, offset, "interrupts", irq_pin)); 1429 } 1430 1431 if (subsystem_id) { 1432 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-id", subsystem_id)); 1433 } 1434 1435 if (subsystem_vendor_id) { 1436 _FDT(fdt_setprop_cell(fdt, offset, "subsystem-vendor-id", 1437 subsystem_vendor_id)); 1438 } 1439 1440 _FDT(fdt_setprop_cell(fdt, offset, "cache-line-size", cache_line_size)); 1441 1442 1443 /* the following fdt cells are masked off the pci status register */ 1444 _FDT(fdt_setprop_cell(fdt, offset, "devsel-speed", 1445 PCI_STATUS_DEVSEL_MASK & pci_status)); 1446 1447 if (pci_status & PCI_STATUS_FAST_BACK) { 1448 _FDT(fdt_setprop(fdt, offset, "fast-back-to-back", NULL, 0)); 1449 } 1450 if (pci_status & PCI_STATUS_66MHZ) { 1451 _FDT(fdt_setprop(fdt, offset, "66mhz-capable", NULL, 0)); 1452 } 1453 if (pci_status & PCI_STATUS_UDF) { 1454 _FDT(fdt_setprop(fdt, offset, "udf-supported", NULL, 0)); 1455 } 1456 1457 loc_code = spapr_phb_get_loc_code(sphb, dev); 1458 _FDT(fdt_setprop_string(fdt, offset, "ibm,loc-code", loc_code)); 1459 g_free(loc_code); 1460 1461 if (drc) { 1462 _FDT(fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", 1463 spapr_drc_index(drc))); 1464 } 1465 1466 if (msi_present(dev)) { 1467 uint32_t max_msi = msi_nr_vectors_allocated(dev); 1468 if (max_msi) { 1469 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi", max_msi)); 1470 } 1471 } 1472 if (msix_present(dev)) { 1473 uint32_t max_msix = dev->msix_entries_nr; 1474 if (max_msix) { 1475 _FDT(fdt_setprop_cell(fdt, offset, "ibm,req#msi-x", max_msix)); 1476 } 1477 } 1478 1479 populate_resource_props(dev, &rp); 1480 _FDT(fdt_setprop(fdt, offset, "reg", (uint8_t *)rp.reg, rp.reg_len)); 1481 _FDT(fdt_setprop(fdt, offset, "assigned-addresses", 1482 (uint8_t *)rp.assigned, rp.assigned_len)); 1483 1484 if (sphb->pcie_ecs && pci_is_express(dev)) { 1485 _FDT(fdt_setprop_cell(fdt, offset, "ibm,pci-config-space-type", 0x1)); 1486 } 1487 1488 spapr_phb_nvgpu_populate_pcidev_dt(dev, fdt, offset, sphb); 1489 1490 if (!pc->is_bridge) { 1491 /* Properties only for non-bridges */ 1492 uint32_t min_grant = pci_default_read_config(dev, PCI_MIN_GNT, 1); 1493 uint32_t max_latency = pci_default_read_config(dev, PCI_MAX_LAT, 1); 1494 _FDT(fdt_setprop_cell(fdt, offset, "min-grant", min_grant)); 1495 _FDT(fdt_setprop_cell(fdt, offset, "max-latency", max_latency)); 1496 return offset; 1497 } else { 1498 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); 1499 1500 return spapr_dt_pci_bus(sphb, sec_bus, fdt, offset); 1501 } 1502 } 1503 1504 /* Callback to be called during DRC release. */ 1505 void spapr_phb_remove_pci_device_cb(DeviceState *dev) 1506 { 1507 HotplugHandler *hotplug_ctrl = qdev_get_hotplug_handler(dev); 1508 1509 hotplug_handler_unplug(hotplug_ctrl, dev, &error_abort); 1510 object_unparent(OBJECT(dev)); 1511 } 1512 1513 int spapr_pci_dt_populate(SpaprDrc *drc, SpaprMachineState *spapr, 1514 void *fdt, int *fdt_start_offset, Error **errp) 1515 { 1516 HotplugHandler *plug_handler = qdev_get_hotplug_handler(drc->dev); 1517 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(plug_handler); 1518 PCIDevice *pdev = PCI_DEVICE(drc->dev); 1519 1520 *fdt_start_offset = spapr_dt_pci_device(sphb, pdev, fdt, 0); 1521 return 0; 1522 } 1523 1524 static void spapr_pci_bridge_plug(SpaprPhbState *phb, 1525 PCIBridge *bridge, 1526 Error **errp) 1527 { 1528 Error *local_err = NULL; 1529 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1530 1531 add_drcs(phb, bus, &local_err); 1532 if (local_err) { 1533 error_propagate(errp, local_err); 1534 return; 1535 } 1536 } 1537 1538 static void spapr_pci_plug(HotplugHandler *plug_handler, 1539 DeviceState *plugged_dev, Error **errp) 1540 { 1541 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1542 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1543 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1544 SpaprDrc *drc = drc_from_dev(phb, pdev); 1545 Error *local_err = NULL; 1546 PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(pdev))); 1547 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1548 1549 /* if DR is disabled we don't need to do anything in the case of 1550 * hotplug or coldplug callbacks 1551 */ 1552 if (!phb->dr_enabled) { 1553 /* if this is a hotplug operation initiated by the user 1554 * we need to let them know it's not enabled 1555 */ 1556 if (plugged_dev->hotplugged) { 1557 error_setg(&local_err, QERR_BUS_NO_HOTPLUG, 1558 object_get_typename(OBJECT(phb))); 1559 } 1560 goto out; 1561 } 1562 1563 g_assert(drc); 1564 1565 if (pc->is_bridge) { 1566 spapr_pci_bridge_plug(phb, PCI_BRIDGE(plugged_dev), &local_err); 1567 if (local_err) { 1568 error_propagate(errp, local_err); 1569 return; 1570 } 1571 } 1572 1573 /* Following the QEMU convention used for PCIe multifunction 1574 * hotplug, we do not allow functions to be hotplugged to a 1575 * slot that already has function 0 present 1576 */ 1577 if (plugged_dev->hotplugged && bus->devices[PCI_DEVFN(slotnr, 0)] && 1578 PCI_FUNC(pdev->devfn) != 0) { 1579 error_setg(&local_err, "PCI: slot %d function 0 already ocuppied by %s," 1580 " additional functions can no longer be exposed to guest.", 1581 slotnr, bus->devices[PCI_DEVFN(slotnr, 0)]->name); 1582 goto out; 1583 } 1584 1585 spapr_drc_attach(drc, DEVICE(pdev), &local_err); 1586 if (local_err) { 1587 goto out; 1588 } 1589 1590 /* If this is function 0, signal hotplug for all the device functions. 1591 * Otherwise defer sending the hotplug event. 1592 */ 1593 if (!spapr_drc_hotplugged(plugged_dev)) { 1594 spapr_drc_reset(drc); 1595 } else if (PCI_FUNC(pdev->devfn) == 0) { 1596 int i; 1597 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); 1598 1599 if (local_err) { 1600 error_propagate(errp, local_err); 1601 return; 1602 } 1603 1604 for (i = 0; i < 8; i++) { 1605 SpaprDrc *func_drc; 1606 SpaprDrcClass *func_drck; 1607 SpaprDREntitySense state; 1608 1609 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1610 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1611 state = func_drck->dr_entity_sense(func_drc); 1612 1613 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1614 spapr_hotplug_req_add_by_index(func_drc); 1615 } 1616 } 1617 } 1618 1619 out: 1620 error_propagate(errp, local_err); 1621 } 1622 1623 static void spapr_pci_bridge_unplug(SpaprPhbState *phb, 1624 PCIBridge *bridge, 1625 Error **errp) 1626 { 1627 Error *local_err = NULL; 1628 PCIBus *bus = pci_bridge_get_sec_bus(bridge); 1629 1630 remove_drcs(phb, bus, &local_err); 1631 if (local_err) { 1632 error_propagate(errp, local_err); 1633 return; 1634 } 1635 } 1636 1637 static void spapr_pci_unplug(HotplugHandler *plug_handler, 1638 DeviceState *plugged_dev, Error **errp) 1639 { 1640 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1641 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1642 1643 /* some version guests do not wait for completion of a device 1644 * cleanup (generally done asynchronously by the kernel) before 1645 * signaling to QEMU that the device is safe, but instead sleep 1646 * for some 'safe' period of time. unfortunately on a busy host 1647 * this sleep isn't guaranteed to be long enough, resulting in 1648 * bad things like IRQ lines being left asserted during final 1649 * device removal. to deal with this we call reset just prior 1650 * to finalizing the device, which will put the device back into 1651 * an 'idle' state, as the device cleanup code expects. 1652 */ 1653 pci_device_reset(PCI_DEVICE(plugged_dev)); 1654 1655 if (pc->is_bridge) { 1656 Error *local_err = NULL; 1657 spapr_pci_bridge_unplug(phb, PCI_BRIDGE(plugged_dev), &local_err); 1658 if (local_err) { 1659 error_propagate(errp, local_err); 1660 } 1661 return; 1662 } 1663 1664 object_property_set_bool(OBJECT(plugged_dev), false, "realized", NULL); 1665 } 1666 1667 static void spapr_pci_unplug_request(HotplugHandler *plug_handler, 1668 DeviceState *plugged_dev, Error **errp) 1669 { 1670 SpaprPhbState *phb = SPAPR_PCI_HOST_BRIDGE(DEVICE(plug_handler)); 1671 PCIDevice *pdev = PCI_DEVICE(plugged_dev); 1672 SpaprDrc *drc = drc_from_dev(phb, pdev); 1673 1674 if (!phb->dr_enabled) { 1675 error_setg(errp, QERR_BUS_NO_HOTPLUG, 1676 object_get_typename(OBJECT(phb))); 1677 return; 1678 } 1679 1680 g_assert(drc); 1681 g_assert(drc->dev == plugged_dev); 1682 1683 if (!spapr_drc_unplug_requested(drc)) { 1684 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(plugged_dev); 1685 uint32_t slotnr = PCI_SLOT(pdev->devfn); 1686 SpaprDrc *func_drc; 1687 SpaprDrcClass *func_drck; 1688 SpaprDREntitySense state; 1689 int i; 1690 Error *local_err = NULL; 1691 uint8_t chassis = chassis_from_bus(pci_get_bus(pdev), &local_err); 1692 1693 if (local_err) { 1694 error_propagate(errp, local_err); 1695 return; 1696 } 1697 1698 if (pc->is_bridge) { 1699 error_setg(errp, "PCI: Hot unplug of PCI bridges not supported"); 1700 } 1701 1702 /* ensure any other present functions are pending unplug */ 1703 if (PCI_FUNC(pdev->devfn) == 0) { 1704 for (i = 1; i < 8; i++) { 1705 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1706 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1707 state = func_drck->dr_entity_sense(func_drc); 1708 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT 1709 && !spapr_drc_unplug_requested(func_drc)) { 1710 error_setg(errp, 1711 "PCI: slot %d, function %d still present. " 1712 "Must unplug all non-0 functions first.", 1713 slotnr, i); 1714 return; 1715 } 1716 } 1717 } 1718 1719 spapr_drc_detach(drc); 1720 1721 /* if this isn't func 0, defer unplug event. otherwise signal removal 1722 * for all present functions 1723 */ 1724 if (PCI_FUNC(pdev->devfn) == 0) { 1725 for (i = 7; i >= 0; i--) { 1726 func_drc = drc_from_devfn(phb, chassis, PCI_DEVFN(slotnr, i)); 1727 func_drck = SPAPR_DR_CONNECTOR_GET_CLASS(func_drc); 1728 state = func_drck->dr_entity_sense(func_drc); 1729 if (state == SPAPR_DR_ENTITY_SENSE_PRESENT) { 1730 spapr_hotplug_req_remove_by_index(func_drc); 1731 } 1732 } 1733 } 1734 } 1735 } 1736 1737 static void spapr_phb_finalizefn(Object *obj) 1738 { 1739 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(obj); 1740 1741 g_free(sphb->dtbusname); 1742 sphb->dtbusname = NULL; 1743 } 1744 1745 static void spapr_phb_unrealize(DeviceState *dev, Error **errp) 1746 { 1747 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 1748 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1749 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1750 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(phb); 1751 SpaprTceTable *tcet; 1752 int i; 1753 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1754 Error *local_err = NULL; 1755 1756 spapr_phb_nvgpu_free(sphb); 1757 1758 if (sphb->msi) { 1759 g_hash_table_unref(sphb->msi); 1760 sphb->msi = NULL; 1761 } 1762 1763 /* 1764 * Remove IO/MMIO subregions and aliases, rest should get cleaned 1765 * via PHB's unrealize->object_finalize 1766 */ 1767 for (i = windows_supported - 1; i >= 0; i--) { 1768 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 1769 if (tcet) { 1770 memory_region_del_subregion(&sphb->iommu_root, 1771 spapr_tce_get_iommu(tcet)); 1772 } 1773 } 1774 1775 remove_drcs(sphb, phb->bus, &local_err); 1776 if (local_err) { 1777 error_propagate(errp, local_err); 1778 return; 1779 } 1780 1781 for (i = PCI_NUM_PINS - 1; i >= 0; i--) { 1782 if (sphb->lsi_table[i].irq) { 1783 spapr_irq_free(spapr, sphb->lsi_table[i].irq, 1); 1784 sphb->lsi_table[i].irq = 0; 1785 } 1786 } 1787 1788 QLIST_REMOVE(sphb, list); 1789 1790 memory_region_del_subregion(&sphb->iommu_root, &sphb->msiwindow); 1791 1792 /* 1793 * An attached PCI device may have memory listeners, eg. VFIO PCI. We have 1794 * unmapped all sections. Remove the listeners now, before destroying the 1795 * address space. 1796 */ 1797 address_space_remove_listeners(&sphb->iommu_as); 1798 address_space_destroy(&sphb->iommu_as); 1799 1800 qbus_set_hotplug_handler(BUS(phb->bus), NULL, &error_abort); 1801 pci_unregister_root_bus(phb->bus); 1802 1803 memory_region_del_subregion(get_system_memory(), &sphb->iowindow); 1804 if (sphb->mem64_win_pciaddr != (hwaddr)-1) { 1805 memory_region_del_subregion(get_system_memory(), &sphb->mem64window); 1806 } 1807 memory_region_del_subregion(get_system_memory(), &sphb->mem32window); 1808 } 1809 1810 static void spapr_phb_realize(DeviceState *dev, Error **errp) 1811 { 1812 /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user 1813 * tries to add a sPAPR PHB to a non-pseries machine. 1814 */ 1815 SpaprMachineState *spapr = 1816 (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(), 1817 TYPE_SPAPR_MACHINE); 1818 SpaprMachineClass *smc = spapr ? SPAPR_MACHINE_GET_CLASS(spapr) : NULL; 1819 SysBusDevice *s = SYS_BUS_DEVICE(dev); 1820 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(s); 1821 PCIHostState *phb = PCI_HOST_BRIDGE(s); 1822 char *namebuf; 1823 int i; 1824 PCIBus *bus; 1825 uint64_t msi_window_size = 4096; 1826 SpaprTceTable *tcet; 1827 const unsigned windows_supported = spapr_phb_windows_supported(sphb); 1828 Error *local_err = NULL; 1829 1830 if (!spapr) { 1831 error_setg(errp, TYPE_SPAPR_PCI_HOST_BRIDGE " needs a pseries machine"); 1832 return; 1833 } 1834 1835 assert(sphb->index != (uint32_t)-1); /* checked in spapr_phb_pre_plug() */ 1836 1837 if (sphb->mem64_win_size != 0) { 1838 if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1839 error_setg(errp, "32-bit memory window of size 0x%"HWADDR_PRIx 1840 " (max 2 GiB)", sphb->mem_win_size); 1841 return; 1842 } 1843 1844 /* 64-bit window defaults to identity mapping */ 1845 sphb->mem64_win_pciaddr = sphb->mem64_win_addr; 1846 } else if (sphb->mem_win_size > SPAPR_PCI_MEM32_WIN_SIZE) { 1847 /* 1848 * For compatibility with old configuration, if no 64-bit MMIO 1849 * window is specified, but the ordinary (32-bit) memory 1850 * window is specified as > 2GiB, we treat it as a 2GiB 32-bit 1851 * window, with a 64-bit MMIO window following on immediately 1852 * afterwards 1853 */ 1854 sphb->mem64_win_size = sphb->mem_win_size - SPAPR_PCI_MEM32_WIN_SIZE; 1855 sphb->mem64_win_addr = sphb->mem_win_addr + SPAPR_PCI_MEM32_WIN_SIZE; 1856 sphb->mem64_win_pciaddr = 1857 SPAPR_PCI_MEM_WIN_BUS_OFFSET + SPAPR_PCI_MEM32_WIN_SIZE; 1858 sphb->mem_win_size = SPAPR_PCI_MEM32_WIN_SIZE; 1859 } 1860 1861 if (spapr_pci_find_phb(spapr, sphb->buid)) { 1862 SpaprPhbState *s; 1863 1864 error_setg(errp, "PCI host bridges must have unique indexes"); 1865 error_append_hint(errp, "The following indexes are already in use:"); 1866 QLIST_FOREACH(s, &spapr->phbs, list) { 1867 error_append_hint(errp, " %d", s->index); 1868 } 1869 error_append_hint(errp, "\nTry another value for the index property\n"); 1870 return; 1871 } 1872 1873 if (sphb->numa_node != -1 && 1874 (sphb->numa_node >= MAX_NODES || !numa_info[sphb->numa_node].present)) { 1875 error_setg(errp, "Invalid NUMA node ID for PCI host bridge"); 1876 return; 1877 } 1878 1879 sphb->dtbusname = g_strdup_printf("pci@%" PRIx64, sphb->buid); 1880 1881 /* Initialize memory regions */ 1882 namebuf = g_strdup_printf("%s.mmio", sphb->dtbusname); 1883 memory_region_init(&sphb->memspace, OBJECT(sphb), namebuf, UINT64_MAX); 1884 g_free(namebuf); 1885 1886 namebuf = g_strdup_printf("%s.mmio32-alias", sphb->dtbusname); 1887 memory_region_init_alias(&sphb->mem32window, OBJECT(sphb), 1888 namebuf, &sphb->memspace, 1889 SPAPR_PCI_MEM_WIN_BUS_OFFSET, sphb->mem_win_size); 1890 g_free(namebuf); 1891 memory_region_add_subregion(get_system_memory(), sphb->mem_win_addr, 1892 &sphb->mem32window); 1893 1894 if (sphb->mem64_win_size != 0) { 1895 namebuf = g_strdup_printf("%s.mmio64-alias", sphb->dtbusname); 1896 memory_region_init_alias(&sphb->mem64window, OBJECT(sphb), 1897 namebuf, &sphb->memspace, 1898 sphb->mem64_win_pciaddr, sphb->mem64_win_size); 1899 g_free(namebuf); 1900 1901 memory_region_add_subregion(get_system_memory(), 1902 sphb->mem64_win_addr, 1903 &sphb->mem64window); 1904 } 1905 1906 /* Initialize IO regions */ 1907 namebuf = g_strdup_printf("%s.io", sphb->dtbusname); 1908 memory_region_init(&sphb->iospace, OBJECT(sphb), 1909 namebuf, SPAPR_PCI_IO_WIN_SIZE); 1910 g_free(namebuf); 1911 1912 namebuf = g_strdup_printf("%s.io-alias", sphb->dtbusname); 1913 memory_region_init_alias(&sphb->iowindow, OBJECT(sphb), namebuf, 1914 &sphb->iospace, 0, SPAPR_PCI_IO_WIN_SIZE); 1915 g_free(namebuf); 1916 memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, 1917 &sphb->iowindow); 1918 1919 bus = pci_register_root_bus(dev, NULL, 1920 pci_spapr_set_irq, pci_swizzle_map_irq_fn, sphb, 1921 &sphb->memspace, &sphb->iospace, 1922 PCI_DEVFN(0, 0), PCI_NUM_PINS, 1923 TYPE_PCI_BUS); 1924 1925 /* 1926 * Despite resembling a vanilla PCI bus in most ways, the PAPR 1927 * para-virtualized PCI bus *does* permit PCI-E extended config 1928 * space access 1929 */ 1930 if (sphb->pcie_ecs) { 1931 bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1932 } 1933 phb->bus = bus; 1934 qbus_set_hotplug_handler(BUS(phb->bus), OBJECT(sphb), NULL); 1935 1936 /* 1937 * Initialize PHB address space. 1938 * By default there will be at least one subregion for default 1939 * 32bit DMA window. 1940 * Later the guest might want to create another DMA window 1941 * which will become another memory subregion. 1942 */ 1943 namebuf = g_strdup_printf("%s.iommu-root", sphb->dtbusname); 1944 memory_region_init(&sphb->iommu_root, OBJECT(sphb), 1945 namebuf, UINT64_MAX); 1946 g_free(namebuf); 1947 address_space_init(&sphb->iommu_as, &sphb->iommu_root, 1948 sphb->dtbusname); 1949 1950 /* 1951 * As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, 1952 * we need to allocate some memory to catch those writes coming 1953 * from msi_notify()/msix_notify(). 1954 * As MSIMessage:addr is going to be the same and MSIMessage:data 1955 * is going to be a VIRQ number, 4 bytes of the MSI MR will only 1956 * be used. 1957 * 1958 * For KVM we want to ensure that this memory is a full page so that 1959 * our memory slot is of page size granularity. 1960 */ 1961 if (kvm_enabled()) { 1962 msi_window_size = getpagesize(); 1963 } 1964 1965 memory_region_init_io(&sphb->msiwindow, OBJECT(sphb), &spapr_msi_ops, spapr, 1966 "msi", msi_window_size); 1967 memory_region_add_subregion(&sphb->iommu_root, SPAPR_PCI_MSI_WINDOW, 1968 &sphb->msiwindow); 1969 1970 pci_setup_iommu(bus, spapr_pci_dma_iommu, sphb); 1971 1972 pci_bus_set_route_irq_fn(bus, spapr_route_intx_pin_to_irq); 1973 1974 QLIST_INSERT_HEAD(&spapr->phbs, sphb, list); 1975 1976 /* Initialize the LSI table */ 1977 for (i = 0; i < PCI_NUM_PINS; i++) { 1978 uint32_t irq = SPAPR_IRQ_PCI_LSI + sphb->index * PCI_NUM_PINS + i; 1979 1980 if (smc->legacy_irq_allocation) { 1981 irq = spapr_irq_findone(spapr, &local_err); 1982 if (local_err) { 1983 error_propagate_prepend(errp, local_err, 1984 "can't allocate LSIs: "); 1985 /* 1986 * Older machines will never support PHB hotplug, ie, this is an 1987 * init only path and QEMU will terminate. No need to rollback. 1988 */ 1989 return; 1990 } 1991 } 1992 1993 spapr_irq_claim(spapr, irq, true, &local_err); 1994 if (local_err) { 1995 error_propagate_prepend(errp, local_err, "can't allocate LSIs: "); 1996 goto unrealize; 1997 } 1998 1999 sphb->lsi_table[i].irq = irq; 2000 } 2001 2002 /* allocate connectors for child PCI devices */ 2003 add_drcs(sphb, phb->bus, &local_err); 2004 if (local_err) { 2005 error_propagate(errp, local_err); 2006 goto unrealize; 2007 } 2008 2009 /* DMA setup */ 2010 for (i = 0; i < windows_supported; ++i) { 2011 tcet = spapr_tce_new_table(DEVICE(sphb), sphb->dma_liobn[i]); 2012 if (!tcet) { 2013 error_setg(errp, "Creating window#%d failed for %s", 2014 i, sphb->dtbusname); 2015 goto unrealize; 2016 } 2017 memory_region_add_subregion(&sphb->iommu_root, 0, 2018 spapr_tce_get_iommu(tcet)); 2019 } 2020 2021 sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); 2022 return; 2023 2024 unrealize: 2025 spapr_phb_unrealize(dev, NULL); 2026 } 2027 2028 static int spapr_phb_children_reset(Object *child, void *opaque) 2029 { 2030 DeviceState *dev = (DeviceState *) object_dynamic_cast(child, TYPE_DEVICE); 2031 2032 if (dev) { 2033 device_reset(dev); 2034 } 2035 2036 return 0; 2037 } 2038 2039 void spapr_phb_dma_reset(SpaprPhbState *sphb) 2040 { 2041 int i; 2042 SpaprTceTable *tcet; 2043 2044 for (i = 0; i < SPAPR_PCI_DMA_MAX_WINDOWS; ++i) { 2045 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[i]); 2046 2047 if (tcet && tcet->nb_table) { 2048 spapr_tce_table_disable(tcet); 2049 } 2050 } 2051 2052 /* Register default 32bit DMA window */ 2053 tcet = spapr_tce_find_by_liobn(sphb->dma_liobn[0]); 2054 spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, 2055 sphb->dma_win_size >> SPAPR_TCE_PAGE_SHIFT); 2056 } 2057 2058 static void spapr_phb_reset(DeviceState *qdev) 2059 { 2060 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(qdev); 2061 Error *errp = NULL; 2062 2063 spapr_phb_dma_reset(sphb); 2064 spapr_phb_nvgpu_free(sphb); 2065 spapr_phb_nvgpu_setup(sphb, &errp); 2066 if (errp) { 2067 error_report_err(errp); 2068 } 2069 2070 /* Reset the IOMMU state */ 2071 object_child_foreach(OBJECT(qdev), spapr_phb_children_reset, NULL); 2072 2073 if (spapr_phb_eeh_available(SPAPR_PCI_HOST_BRIDGE(qdev))) { 2074 spapr_phb_vfio_reset(qdev); 2075 } 2076 } 2077 2078 static Property spapr_phb_properties[] = { 2079 DEFINE_PROP_UINT32("index", SpaprPhbState, index, -1), 2080 DEFINE_PROP_UINT64("mem_win_size", SpaprPhbState, mem_win_size, 2081 SPAPR_PCI_MEM32_WIN_SIZE), 2082 DEFINE_PROP_UINT64("mem64_win_size", SpaprPhbState, mem64_win_size, 2083 SPAPR_PCI_MEM64_WIN_SIZE), 2084 DEFINE_PROP_UINT64("io_win_size", SpaprPhbState, io_win_size, 2085 SPAPR_PCI_IO_WIN_SIZE), 2086 DEFINE_PROP_BOOL("dynamic-reconfiguration", SpaprPhbState, dr_enabled, 2087 true), 2088 /* Default DMA window is 0..1GB */ 2089 DEFINE_PROP_UINT64("dma_win_addr", SpaprPhbState, dma_win_addr, 0), 2090 DEFINE_PROP_UINT64("dma_win_size", SpaprPhbState, dma_win_size, 0x40000000), 2091 DEFINE_PROP_UINT64("dma64_win_addr", SpaprPhbState, dma64_win_addr, 2092 0x800000000000000ULL), 2093 DEFINE_PROP_BOOL("ddw", SpaprPhbState, ddw_enabled, true), 2094 DEFINE_PROP_UINT64("pgsz", SpaprPhbState, page_size_mask, 2095 (1ULL << 12) | (1ULL << 16)), 2096 DEFINE_PROP_UINT32("numa_node", SpaprPhbState, numa_node, -1), 2097 DEFINE_PROP_BOOL("pre-2.8-migration", SpaprPhbState, 2098 pre_2_8_migration, false), 2099 DEFINE_PROP_BOOL("pcie-extended-configuration-space", SpaprPhbState, 2100 pcie_ecs, true), 2101 DEFINE_PROP_UINT64("gpa", SpaprPhbState, nv2_gpa_win_addr, 0), 2102 DEFINE_PROP_UINT64("atsd", SpaprPhbState, nv2_atsd_win_addr, 0), 2103 DEFINE_PROP_END_OF_LIST(), 2104 }; 2105 2106 static const VMStateDescription vmstate_spapr_pci_lsi = { 2107 .name = "spapr_pci/lsi", 2108 .version_id = 1, 2109 .minimum_version_id = 1, 2110 .fields = (VMStateField[]) { 2111 VMSTATE_UINT32_EQUAL(irq, struct spapr_pci_lsi, NULL), 2112 2113 VMSTATE_END_OF_LIST() 2114 }, 2115 }; 2116 2117 static const VMStateDescription vmstate_spapr_pci_msi = { 2118 .name = "spapr_pci/msi", 2119 .version_id = 1, 2120 .minimum_version_id = 1, 2121 .fields = (VMStateField []) { 2122 VMSTATE_UINT32(key, spapr_pci_msi_mig), 2123 VMSTATE_UINT32(value.first_irq, spapr_pci_msi_mig), 2124 VMSTATE_UINT32(value.num, spapr_pci_msi_mig), 2125 VMSTATE_END_OF_LIST() 2126 }, 2127 }; 2128 2129 static int spapr_pci_pre_save(void *opaque) 2130 { 2131 SpaprPhbState *sphb = opaque; 2132 GHashTableIter iter; 2133 gpointer key, value; 2134 int i; 2135 2136 if (sphb->pre_2_8_migration) { 2137 sphb->mig_liobn = sphb->dma_liobn[0]; 2138 sphb->mig_mem_win_addr = sphb->mem_win_addr; 2139 sphb->mig_mem_win_size = sphb->mem_win_size; 2140 sphb->mig_io_win_addr = sphb->io_win_addr; 2141 sphb->mig_io_win_size = sphb->io_win_size; 2142 2143 if ((sphb->mem64_win_size != 0) 2144 && (sphb->mem64_win_addr 2145 == (sphb->mem_win_addr + sphb->mem_win_size))) { 2146 sphb->mig_mem_win_size += sphb->mem64_win_size; 2147 } 2148 } 2149 2150 g_free(sphb->msi_devs); 2151 sphb->msi_devs = NULL; 2152 sphb->msi_devs_num = g_hash_table_size(sphb->msi); 2153 if (!sphb->msi_devs_num) { 2154 return 0; 2155 } 2156 sphb->msi_devs = g_new(spapr_pci_msi_mig, sphb->msi_devs_num); 2157 2158 g_hash_table_iter_init(&iter, sphb->msi); 2159 for (i = 0; g_hash_table_iter_next(&iter, &key, &value); ++i) { 2160 sphb->msi_devs[i].key = *(uint32_t *) key; 2161 sphb->msi_devs[i].value = *(spapr_pci_msi *) value; 2162 } 2163 2164 return 0; 2165 } 2166 2167 static int spapr_pci_post_load(void *opaque, int version_id) 2168 { 2169 SpaprPhbState *sphb = opaque; 2170 gpointer key, value; 2171 int i; 2172 2173 for (i = 0; i < sphb->msi_devs_num; ++i) { 2174 key = g_memdup(&sphb->msi_devs[i].key, 2175 sizeof(sphb->msi_devs[i].key)); 2176 value = g_memdup(&sphb->msi_devs[i].value, 2177 sizeof(sphb->msi_devs[i].value)); 2178 g_hash_table_insert(sphb->msi, key, value); 2179 } 2180 g_free(sphb->msi_devs); 2181 sphb->msi_devs = NULL; 2182 sphb->msi_devs_num = 0; 2183 2184 return 0; 2185 } 2186 2187 static bool pre_2_8_migration(void *opaque, int version_id) 2188 { 2189 SpaprPhbState *sphb = opaque; 2190 2191 return sphb->pre_2_8_migration; 2192 } 2193 2194 static const VMStateDescription vmstate_spapr_pci = { 2195 .name = "spapr_pci", 2196 .version_id = 2, 2197 .minimum_version_id = 2, 2198 .pre_save = spapr_pci_pre_save, 2199 .post_load = spapr_pci_post_load, 2200 .fields = (VMStateField[]) { 2201 VMSTATE_UINT64_EQUAL(buid, SpaprPhbState, NULL), 2202 VMSTATE_UINT32_TEST(mig_liobn, SpaprPhbState, pre_2_8_migration), 2203 VMSTATE_UINT64_TEST(mig_mem_win_addr, SpaprPhbState, pre_2_8_migration), 2204 VMSTATE_UINT64_TEST(mig_mem_win_size, SpaprPhbState, pre_2_8_migration), 2205 VMSTATE_UINT64_TEST(mig_io_win_addr, SpaprPhbState, pre_2_8_migration), 2206 VMSTATE_UINT64_TEST(mig_io_win_size, SpaprPhbState, pre_2_8_migration), 2207 VMSTATE_STRUCT_ARRAY(lsi_table, SpaprPhbState, PCI_NUM_PINS, 0, 2208 vmstate_spapr_pci_lsi, struct spapr_pci_lsi), 2209 VMSTATE_INT32(msi_devs_num, SpaprPhbState), 2210 VMSTATE_STRUCT_VARRAY_ALLOC(msi_devs, SpaprPhbState, msi_devs_num, 0, 2211 vmstate_spapr_pci_msi, spapr_pci_msi_mig), 2212 VMSTATE_END_OF_LIST() 2213 }, 2214 }; 2215 2216 static const char *spapr_phb_root_bus_path(PCIHostState *host_bridge, 2217 PCIBus *rootbus) 2218 { 2219 SpaprPhbState *sphb = SPAPR_PCI_HOST_BRIDGE(host_bridge); 2220 2221 return sphb->dtbusname; 2222 } 2223 2224 static void spapr_phb_class_init(ObjectClass *klass, void *data) 2225 { 2226 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 2227 DeviceClass *dc = DEVICE_CLASS(klass); 2228 HotplugHandlerClass *hp = HOTPLUG_HANDLER_CLASS(klass); 2229 2230 hc->root_bus_path = spapr_phb_root_bus_path; 2231 dc->realize = spapr_phb_realize; 2232 dc->unrealize = spapr_phb_unrealize; 2233 dc->props = spapr_phb_properties; 2234 dc->reset = spapr_phb_reset; 2235 dc->vmsd = &vmstate_spapr_pci; 2236 /* Supported by TYPE_SPAPR_MACHINE */ 2237 dc->user_creatable = true; 2238 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 2239 hp->plug = spapr_pci_plug; 2240 hp->unplug = spapr_pci_unplug; 2241 hp->unplug_request = spapr_pci_unplug_request; 2242 } 2243 2244 static const TypeInfo spapr_phb_info = { 2245 .name = TYPE_SPAPR_PCI_HOST_BRIDGE, 2246 .parent = TYPE_PCI_HOST_BRIDGE, 2247 .instance_size = sizeof(SpaprPhbState), 2248 .instance_finalize = spapr_phb_finalizefn, 2249 .class_init = spapr_phb_class_init, 2250 .interfaces = (InterfaceInfo[]) { 2251 { TYPE_HOTPLUG_HANDLER }, 2252 { } 2253 } 2254 }; 2255 2256 static void spapr_phb_pci_enumerate_bridge(PCIBus *bus, PCIDevice *pdev, 2257 void *opaque) 2258 { 2259 unsigned int *bus_no = opaque; 2260 PCIBus *sec_bus = NULL; 2261 2262 if ((pci_default_read_config(pdev, PCI_HEADER_TYPE, 1) != 2263 PCI_HEADER_TYPE_BRIDGE)) { 2264 return; 2265 } 2266 2267 (*bus_no)++; 2268 pci_default_write_config(pdev, PCI_PRIMARY_BUS, pci_dev_bus_num(pdev), 1); 2269 pci_default_write_config(pdev, PCI_SECONDARY_BUS, *bus_no, 1); 2270 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2271 2272 sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev)); 2273 if (!sec_bus) { 2274 return; 2275 } 2276 2277 pci_for_each_device(sec_bus, pci_bus_num(sec_bus), 2278 spapr_phb_pci_enumerate_bridge, bus_no); 2279 pci_default_write_config(pdev, PCI_SUBORDINATE_BUS, *bus_no, 1); 2280 } 2281 2282 static void spapr_phb_pci_enumerate(SpaprPhbState *phb) 2283 { 2284 PCIBus *bus = PCI_HOST_BRIDGE(phb)->bus; 2285 unsigned int bus_no = 0; 2286 2287 pci_for_each_device(bus, pci_bus_num(bus), 2288 spapr_phb_pci_enumerate_bridge, 2289 &bus_no); 2290 2291 } 2292 2293 int spapr_dt_phb(SpaprPhbState *phb, uint32_t intc_phandle, void *fdt, 2294 uint32_t nr_msis, int *node_offset) 2295 { 2296 int bus_off, i, j, ret; 2297 uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; 2298 struct { 2299 uint32_t hi; 2300 uint64_t child; 2301 uint64_t parent; 2302 uint64_t size; 2303 } QEMU_PACKED ranges[] = { 2304 { 2305 cpu_to_be32(b_ss(1)), cpu_to_be64(0), 2306 cpu_to_be64(phb->io_win_addr), 2307 cpu_to_be64(memory_region_size(&phb->iospace)), 2308 }, 2309 { 2310 cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), 2311 cpu_to_be64(phb->mem_win_addr), 2312 cpu_to_be64(phb->mem_win_size), 2313 }, 2314 { 2315 cpu_to_be32(b_ss(3)), cpu_to_be64(phb->mem64_win_pciaddr), 2316 cpu_to_be64(phb->mem64_win_addr), 2317 cpu_to_be64(phb->mem64_win_size), 2318 }, 2319 }; 2320 const unsigned sizeof_ranges = 2321 (phb->mem64_win_size ? 3 : 2) * sizeof(ranges[0]); 2322 uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; 2323 uint32_t interrupt_map_mask[] = { 2324 cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, cpu_to_be32(-1)}; 2325 uint32_t interrupt_map[PCI_SLOT_MAX * PCI_NUM_PINS][7]; 2326 uint32_t ddw_applicable[] = { 2327 cpu_to_be32(RTAS_IBM_QUERY_PE_DMA_WINDOW), 2328 cpu_to_be32(RTAS_IBM_CREATE_PE_DMA_WINDOW), 2329 cpu_to_be32(RTAS_IBM_REMOVE_PE_DMA_WINDOW) 2330 }; 2331 uint32_t ddw_extensions[] = { 2332 cpu_to_be32(1), 2333 cpu_to_be32(RTAS_IBM_RESET_PE_DMA_WINDOW) 2334 }; 2335 uint32_t associativity[] = {cpu_to_be32(0x4), 2336 cpu_to_be32(0x0), 2337 cpu_to_be32(0x0), 2338 cpu_to_be32(0x0), 2339 cpu_to_be32(phb->numa_node)}; 2340 SpaprTceTable *tcet; 2341 SpaprDrc *drc; 2342 Error *errp = NULL; 2343 2344 /* Start populating the FDT */ 2345 _FDT(bus_off = fdt_add_subnode(fdt, 0, phb->dtbusname)); 2346 if (node_offset) { 2347 *node_offset = bus_off; 2348 } 2349 2350 /* Write PHB properties */ 2351 _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); 2352 _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); 2353 _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); 2354 _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); 2355 _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); 2356 _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges)); 2357 _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); 2358 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); 2359 _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", nr_msis)); 2360 2361 /* Dynamic DMA window */ 2362 if (phb->ddw_enabled) { 2363 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-applicable", &ddw_applicable, 2364 sizeof(ddw_applicable))); 2365 _FDT(fdt_setprop(fdt, bus_off, "ibm,ddw-extensions", 2366 &ddw_extensions, sizeof(ddw_extensions))); 2367 } 2368 2369 /* Advertise NUMA via ibm,associativity */ 2370 if (phb->numa_node != -1) { 2371 _FDT(fdt_setprop(fdt, bus_off, "ibm,associativity", associativity, 2372 sizeof(associativity))); 2373 } 2374 2375 /* Build the interrupt-map, this must matches what is done 2376 * in pci_swizzle_map_irq_fn 2377 */ 2378 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", 2379 &interrupt_map_mask, sizeof(interrupt_map_mask))); 2380 for (i = 0; i < PCI_SLOT_MAX; i++) { 2381 for (j = 0; j < PCI_NUM_PINS; j++) { 2382 uint32_t *irqmap = interrupt_map[i*PCI_NUM_PINS + j]; 2383 int lsi_num = pci_swizzle(i, j); 2384 2385 irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); 2386 irqmap[1] = 0; 2387 irqmap[2] = 0; 2388 irqmap[3] = cpu_to_be32(j+1); 2389 irqmap[4] = cpu_to_be32(intc_phandle); 2390 spapr_dt_irq(&irqmap[5], phb->lsi_table[lsi_num].irq, true); 2391 } 2392 } 2393 /* Write interrupt map */ 2394 _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, 2395 sizeof(interrupt_map))); 2396 2397 tcet = spapr_tce_find_by_liobn(phb->dma_liobn[0]); 2398 if (!tcet) { 2399 return -1; 2400 } 2401 spapr_dma_dt(fdt, bus_off, "ibm,dma-window", 2402 tcet->liobn, tcet->bus_offset, 2403 tcet->nb_table << tcet->page_shift); 2404 2405 drc = spapr_drc_by_id(TYPE_SPAPR_DRC_PHB, phb->index); 2406 if (drc) { 2407 uint32_t drc_index = cpu_to_be32(spapr_drc_index(drc)); 2408 2409 _FDT(fdt_setprop(fdt, bus_off, "ibm,my-drc-index", &drc_index, 2410 sizeof(drc_index))); 2411 } 2412 2413 /* Walk the bridges and program the bus numbers*/ 2414 spapr_phb_pci_enumerate(phb); 2415 _FDT(fdt_setprop_cell(fdt, bus_off, "qemu,phb-enumerated", 0x1)); 2416 2417 /* Walk the bridge and subordinate buses */ 2418 ret = spapr_dt_pci_bus(phb, PCI_HOST_BRIDGE(phb)->bus, fdt, bus_off); 2419 if (ret < 0) { 2420 return ret; 2421 } 2422 2423 spapr_phb_nvgpu_populate_dt(phb, fdt, bus_off, &errp); 2424 if (errp) { 2425 error_report_err(errp); 2426 } 2427 spapr_phb_nvgpu_ram_populate_dt(phb, fdt); 2428 2429 return 0; 2430 } 2431 2432 void spapr_pci_rtas_init(void) 2433 { 2434 spapr_rtas_register(RTAS_READ_PCI_CONFIG, "read-pci-config", 2435 rtas_read_pci_config); 2436 spapr_rtas_register(RTAS_WRITE_PCI_CONFIG, "write-pci-config", 2437 rtas_write_pci_config); 2438 spapr_rtas_register(RTAS_IBM_READ_PCI_CONFIG, "ibm,read-pci-config", 2439 rtas_ibm_read_pci_config); 2440 spapr_rtas_register(RTAS_IBM_WRITE_PCI_CONFIG, "ibm,write-pci-config", 2441 rtas_ibm_write_pci_config); 2442 if (msi_nonbroken) { 2443 spapr_rtas_register(RTAS_IBM_QUERY_INTERRUPT_SOURCE_NUMBER, 2444 "ibm,query-interrupt-source-number", 2445 rtas_ibm_query_interrupt_source_number); 2446 spapr_rtas_register(RTAS_IBM_CHANGE_MSI, "ibm,change-msi", 2447 rtas_ibm_change_msi); 2448 } 2449 2450 spapr_rtas_register(RTAS_IBM_SET_EEH_OPTION, 2451 "ibm,set-eeh-option", 2452 rtas_ibm_set_eeh_option); 2453 spapr_rtas_register(RTAS_IBM_GET_CONFIG_ADDR_INFO2, 2454 "ibm,get-config-addr-info2", 2455 rtas_ibm_get_config_addr_info2); 2456 spapr_rtas_register(RTAS_IBM_READ_SLOT_RESET_STATE2, 2457 "ibm,read-slot-reset-state2", 2458 rtas_ibm_read_slot_reset_state2); 2459 spapr_rtas_register(RTAS_IBM_SET_SLOT_RESET, 2460 "ibm,set-slot-reset", 2461 rtas_ibm_set_slot_reset); 2462 spapr_rtas_register(RTAS_IBM_CONFIGURE_PE, 2463 "ibm,configure-pe", 2464 rtas_ibm_configure_pe); 2465 spapr_rtas_register(RTAS_IBM_SLOT_ERROR_DETAIL, 2466 "ibm,slot-error-detail", 2467 rtas_ibm_slot_error_detail); 2468 } 2469 2470 static void spapr_pci_register_types(void) 2471 { 2472 type_register_static(&spapr_phb_info); 2473 } 2474 2475 type_init(spapr_pci_register_types) 2476 2477 static int spapr_switch_one_vga(DeviceState *dev, void *opaque) 2478 { 2479 bool be = *(bool *)opaque; 2480 2481 if (object_dynamic_cast(OBJECT(dev), "VGA") 2482 || object_dynamic_cast(OBJECT(dev), "secondary-vga")) { 2483 object_property_set_bool(OBJECT(dev), be, "big-endian-framebuffer", 2484 &error_abort); 2485 } 2486 return 0; 2487 } 2488 2489 void spapr_pci_switch_vga(bool big_endian) 2490 { 2491 SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine()); 2492 SpaprPhbState *sphb; 2493 2494 /* 2495 * For backward compatibility with existing guests, we switch 2496 * the endianness of the VGA controller when changing the guest 2497 * interrupt mode 2498 */ 2499 QLIST_FOREACH(sphb, &spapr->phbs, list) { 2500 BusState *bus = &PCI_HOST_BRIDGE(sphb)->bus->qbus; 2501 qbus_walk_children(bus, spapr_switch_one_vga, NULL, NULL, NULL, 2502 &big_endian); 2503 } 2504 } 2505