156f6e31eSBin Meng /*
256f6e31eSBin Meng * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit
356f6e31eSBin Meng *
456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc.
556f6e31eSBin Meng *
656f6e31eSBin Meng * Author:
756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com>
856f6e31eSBin Meng *
956f6e31eSBin Meng * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit
1056f6e31eSBin Meng *
1156f6e31eSBin Meng * 0) CLINT (Core Level Interruptor)
1256f6e31eSBin Meng * 1) PLIC (Platform Level Interrupt Controller)
1356f6e31eSBin Meng * 2) eNVM (Embedded Non-Volatile Memory)
148f2ac39dSBin Meng * 3) MMUARTs (Multi-Mode UART)
15898dc008SBin Meng * 4) Cadence eMMC/SDHC controller and an SD card connected to it
167124e27bSBin Meng * 5) SiFive Platform DMA (Direct Memory Access Controller)
1747374b07SBin Meng * 6) GEM (Gigabit Ethernet MAC Controller)
18933f73f1SBin Meng * 7) DMC (DDR Memory Controller)
19e35d6179SBin Meng * 8) IOSCB modules
2056f6e31eSBin Meng *
2156f6e31eSBin Meng * This board currently generates devicetree dynamically that indicates at least
2256f6e31eSBin Meng * two harts and up to five harts.
2356f6e31eSBin Meng *
2456f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it
2556f6e31eSBin Meng * under the terms and conditions of the GNU General Public License,
2656f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation.
2756f6e31eSBin Meng *
2856f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT
2956f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
3056f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
3156f6e31eSBin Meng * more details.
3256f6e31eSBin Meng *
3356f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with
3456f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>.
3556f6e31eSBin Meng */
3656f6e31eSBin Meng
3756f6e31eSBin Meng #include "qemu/osdep.h"
3856f6e31eSBin Meng #include "qemu/error-report.h"
3956f6e31eSBin Meng #include "qemu/units.h"
4056f6e31eSBin Meng #include "qemu/cutils.h"
4156f6e31eSBin Meng #include "qapi/error.h"
4256f6e31eSBin Meng #include "hw/boards.h"
4356f6e31eSBin Meng #include "hw/loader.h"
4456f6e31eSBin Meng #include "hw/sysbus.h"
458f2ac39dSBin Meng #include "chardev/char.h"
4656f6e31eSBin Meng #include "hw/cpu/cluster.h"
4756f6e31eSBin Meng #include "target/riscv/cpu.h"
4856f6e31eSBin Meng #include "hw/misc/unimp.h"
4956f6e31eSBin Meng #include "hw/riscv/boot.h"
5056f6e31eSBin Meng #include "hw/riscv/riscv_hart.h"
5156f6e31eSBin Meng #include "hw/riscv/microchip_pfsoc.h"
52cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h"
5384fcf3c1SBin Meng #include "hw/intc/sifive_plic.h"
54143897b5SBin Meng #include "sysemu/device_tree.h"
558f2ac39dSBin Meng #include "sysemu/sysemu.h"
5656f6e31eSBin Meng
5756f6e31eSBin Meng /*
5856f6e31eSBin Meng * The BIOS image used by this machine is called Hart Software Services (HSS).
5956f6e31eSBin Meng * See https://github.com/polarfire-soc/hart-software-services
6056f6e31eSBin Meng */
6156f6e31eSBin Meng #define BIOS_FILENAME "hss.bin"
6256f6e31eSBin Meng #define RESET_VECTOR 0x20220000
6356f6e31eSBin Meng
64a47ef6e9SBin Meng /* CLINT timebase frequency */
65a47ef6e9SBin Meng #define CLINT_TIMEBASE_FREQ 1000000
66a47ef6e9SBin Meng
6747374b07SBin Meng /* GEM version */
6847374b07SBin Meng #define GEM_REVISION 0x0107010c
6947374b07SBin Meng
7008b86e3bSBin Meng /*
7108b86e3bSBin Meng * The complete description of the whole PolarFire SoC memory map is scattered
7208b86e3bSBin Meng * in different documents. There are several places to look at for memory maps:
7308b86e3bSBin Meng *
7408b86e3bSBin Meng * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA
7508b86e3bSBin Meng * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from
7608b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/
7708b86e3bSBin Meng * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide,
7808b86e3bSBin Meng * describes the whole picture of the PolarFire SoC memory map.
7908b86e3bSBin Meng *
8008b86e3bSBin Meng * 2 A zip file for PolarFire soC memory map, which can be downloaded from
8108b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/
8208b86e3bSBin Meng * 1244581-polarfire-soc-register-map, contains the following 2 major parts:
8308b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm
8408b86e3bSBin Meng * describes the complete integrated peripherals memory map
8508b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
8608b86e3bSBin Meng * describes the complete IOSCB modules memory maps
8708b86e3bSBin Meng */
8873261285SBin Meng static const MemMapEntry microchip_pfsoc_memmap[] = {
8927c22b2dSBin Meng [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 },
9027c22b2dSBin Meng [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 },
9156f6e31eSBin Meng [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 },
9256f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 },
9356f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 },
9456f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 },
9556f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 },
9656f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 },
9756f6e31eSBin Meng [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 },
9856f6e31eSBin Meng [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 },
997124e27bSBin Meng [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 },
10056f6e31eSBin Meng [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 },
10156f6e31eSBin Meng [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 },
1028f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 },
10325da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 },
10456f6e31eSBin Meng [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 },
10525da6e31SConor Dooley [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 },
10656f6e31eSBin Meng [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 },
10725da6e31SConor Dooley [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 },
108933f73f1SBin Meng [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 },
109898dc008SBin Meng [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 },
110933f73f1SBin Meng [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 },
1118f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 },
1128f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 },
1138f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 },
1148f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 },
11525da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 },
11625da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 },
11725da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 },
11825da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 },
119dfc973ecSVitaly Wool [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 },
120dfc973ecSVitaly Wool [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 },
12125da6e31SConor Dooley [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 },
12290742c54SBin Meng [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 },
12325da6e31SConor Dooley [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 },
12425da6e31SConor Dooley [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 },
12547374b07SBin Meng [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 },
12647374b07SBin Meng [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 },
127ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 },
128ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 },
129ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 },
13025da6e31SConor Dooley [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 },
13156f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 },
13256f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 },
13325da6e31SConor Dooley [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 },
134dfc973ecSVitaly Wool [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 },
135e35d6179SBin Meng [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 },
1368d32e374SConor Dooley [MICROCHIP_PFSOC_FABRIC_FIC0] = { 0x2000000000, 0x1000000000 },
1378d32e374SConor Dooley [MICROCHIP_PFSOC_FABRIC_FIC1] = { 0x3000000000, 0x1000000000 },
13825da6e31SConor Dooley [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 },
139f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 },
140f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 },
141f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 },
142f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 },
1438d32e374SConor Dooley
14456f6e31eSBin Meng };
14556f6e31eSBin Meng
microchip_pfsoc_soc_instance_init(Object * obj)14656f6e31eSBin Meng static void microchip_pfsoc_soc_instance_init(Object *obj)
14756f6e31eSBin Meng {
14856f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine());
14956f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj);
15056f6e31eSBin Meng
15156f6e31eSBin Meng object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER);
15256f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0);
15356f6e31eSBin Meng
15456f6e31eSBin Meng object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus,
15556f6e31eSBin Meng TYPE_RISCV_HART_ARRAY);
15656f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
15756f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
15856f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type",
15956f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_E51);
16056f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR);
16156f6e31eSBin Meng
16256f6e31eSBin Meng object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
16356f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
16456f6e31eSBin Meng
16556f6e31eSBin Meng object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus,
16656f6e31eSBin Meng TYPE_RISCV_HART_ARRAY);
16756f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
16856f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
16956f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type",
17056f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_U54);
17156f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
172898dc008SBin Meng
1737124e27bSBin Meng object_initialize_child(obj, "dma-controller", &s->dma,
1747124e27bSBin Meng TYPE_SIFIVE_PDMA);
1757124e27bSBin Meng
176cdd58c70SBin Meng object_initialize_child(obj, "sysreg", &s->sysreg,
177cdd58c70SBin Meng TYPE_MCHP_PFSOC_SYSREG);
178cdd58c70SBin Meng
179933f73f1SBin Meng object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy,
180933f73f1SBin Meng TYPE_MCHP_PFSOC_DDR_SGMII_PHY);
181933f73f1SBin Meng object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg,
182933f73f1SBin Meng TYPE_MCHP_PFSOC_DDR_CFG);
183933f73f1SBin Meng
18447374b07SBin Meng object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM);
18547374b07SBin Meng object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM);
18647374b07SBin Meng
187898dc008SBin Meng object_initialize_child(obj, "sd-controller", &s->sdhci,
188898dc008SBin Meng TYPE_CADENCE_SDHCI);
189e35d6179SBin Meng
190e35d6179SBin Meng object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB);
19156f6e31eSBin Meng }
19256f6e31eSBin Meng
microchip_pfsoc_soc_realize(DeviceState * dev,Error ** errp)19356f6e31eSBin Meng static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
19456f6e31eSBin Meng {
19556f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine());
19656f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev);
19773261285SBin Meng const MemMapEntry *memmap = microchip_pfsoc_memmap;
19856f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory();
19927c22b2dSBin Meng MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1);
20056f6e31eSBin Meng MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1);
20156f6e31eSBin Meng MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1);
20256f6e31eSBin Meng MemoryRegion *envm_data = g_new(MemoryRegion, 1);
203dfc973ecSVitaly Wool MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1);
20456f6e31eSBin Meng char *plic_hart_config;
20556f6e31eSBin Meng int i;
20656f6e31eSBin Meng
20756f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
20856f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
20956f6e31eSBin Meng /*
21056f6e31eSBin Meng * The cluster must be realized after the RISC-V hart array container,
21156f6e31eSBin Meng * as the container's CPU object is only created on realize, and the
21256f6e31eSBin Meng * CPU must exist and have been parented into the cluster before the
21356f6e31eSBin Meng * cluster is realized.
21456f6e31eSBin Meng */
21556f6e31eSBin Meng qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort);
21656f6e31eSBin Meng qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort);
21756f6e31eSBin Meng
21827c22b2dSBin Meng /* Reserved Memory at address 0 */
21927c22b2dSBin Meng memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem",
22027c22b2dSBin Meng memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal);
22127c22b2dSBin Meng memory_region_add_subregion(system_memory,
22227c22b2dSBin Meng memmap[MICROCHIP_PFSOC_RSVD0].base,
22327c22b2dSBin Meng rsvd0_mem);
22427c22b2dSBin Meng
22556f6e31eSBin Meng /* E51 DTIM */
22656f6e31eSBin Meng memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem",
22756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal);
22856f6e31eSBin Meng memory_region_add_subregion(system_memory,
22956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].base,
23056f6e31eSBin Meng e51_dtim_mem);
23156f6e31eSBin Meng
23256f6e31eSBin Meng /* Bus Error Units */
23356f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem",
23456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base,
23556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size);
23656f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem",
23756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base,
23856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size);
23956f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem",
24056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base,
24156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size);
24256f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem",
24356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base,
24456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size);
24556f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem",
24656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base,
24756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size);
24856f6e31eSBin Meng
24956f6e31eSBin Meng /* CLINT */
250b8fb878aSAnup Patel riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base,
251b8fb878aSAnup Patel 0, ms->smp.cpus, false);
252b8fb878aSAnup Patel riscv_aclint_mtimer_create(
253b8fb878aSAnup Patel memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE,
254b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus,
255b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME,
256a47ef6e9SBin Meng CLINT_TIMEBASE_FREQ, false);
25756f6e31eSBin Meng
25856f6e31eSBin Meng /* L2 cache controller */
25956f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.l2cc",
26056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size);
26156f6e31eSBin Meng
26256f6e31eSBin Meng /*
26356f6e31eSBin Meng * Add L2-LIM at reset size.
26456f6e31eSBin Meng * This should be reduced in size as the L2 Cache Controller WayEnable
26556f6e31eSBin Meng * register is incremented. Unfortunately I don't see a nice (or any) way
26656f6e31eSBin Meng * to handle reducing or blocking out the L2 LIM while still allowing it
26756f6e31eSBin Meng * be re returned to all enabled after a reset. For the time being, just
26856f6e31eSBin Meng * leave it enabled all the time. This won't break anything, but will be
26956f6e31eSBin Meng * too generous to misbehaving guests.
27056f6e31eSBin Meng */
27156f6e31eSBin Meng memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim",
27256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal);
27356f6e31eSBin Meng memory_region_add_subregion(system_memory,
27456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].base,
27556f6e31eSBin Meng l2lim_mem);
27656f6e31eSBin Meng
27756f6e31eSBin Meng /* create PLIC hart topology configuration string */
2788486eb8cSAlistair Francis plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus);
27956f6e31eSBin Meng
28056f6e31eSBin Meng /* PLIC */
28156f6e31eSBin Meng s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base,
282f436ecc3SAlistair Francis plic_hart_config, ms->smp.cpus, 0,
28356f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_SOURCES,
28456f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES,
28556f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PRIORITY_BASE,
28656f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PENDING_BASE,
28756f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_BASE,
28856f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE,
28956f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_BASE,
29056f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE,
29156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_PLIC].size);
29256f6e31eSBin Meng g_free(plic_hart_config);
29356f6e31eSBin Meng
2947124e27bSBin Meng /* DMA */
2957124e27bSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
2967124e27bSBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
2977124e27bSBin Meng memmap[MICROCHIP_PFSOC_DMA].base);
2987124e27bSBin Meng for (i = 0; i < SIFIVE_PDMA_IRQS; i++) {
2997124e27bSBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
3007124e27bSBin Meng qdev_get_gpio_in(DEVICE(s->plic),
3017124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 + i));
3027124e27bSBin Meng }
3037124e27bSBin Meng
30456f6e31eSBin Meng /* SYSREG */
305cdd58c70SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp);
306cdd58c70SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0,
307cdd58c70SBin Meng memmap[MICROCHIP_PFSOC_SYSREG].base);
308592f0a94SConor Dooley sysbus_connect_irq(SYS_BUS_DEVICE(&s->sysreg), 0,
309592f0a94SConor Dooley qdev_get_gpio_in(DEVICE(s->plic),
310592f0a94SConor Dooley MICROCHIP_PFSOC_MAILBOX_IRQ));
31156f6e31eSBin Meng
31225da6e31SConor Dooley /* AXISW */
31325da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.axisw",
31425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_AXISW].base,
31525da6e31SConor Dooley memmap[MICROCHIP_PFSOC_AXISW].size);
31625da6e31SConor Dooley
31756f6e31eSBin Meng /* MPUCFG */
31856f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.mpucfg",
31956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].base,
32056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].size);
32156f6e31eSBin Meng
32225da6e31SConor Dooley /* FMETER */
32325da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.fmeter",
32425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FMETER].base,
32525da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FMETER].size);
32625da6e31SConor Dooley
327933f73f1SBin Meng /* DDR SGMII PHY */
328933f73f1SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp);
329933f73f1SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0,
330933f73f1SBin Meng memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base);
331933f73f1SBin Meng
332933f73f1SBin Meng /* DDR CFG */
333933f73f1SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp);
334933f73f1SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0,
335933f73f1SBin Meng memmap[MICROCHIP_PFSOC_DDR_CFG].base);
336933f73f1SBin Meng
337898dc008SBin Meng /* SDHCI */
338898dc008SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp);
339898dc008SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0,
340898dc008SBin Meng memmap[MICROCHIP_PFSOC_EMMC_SD].base);
341898dc008SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
342898dc008SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ));
343898dc008SBin Meng
3448f2ac39dSBin Meng /* MMUARTs */
3458f2ac39dSBin Meng s->serial0 = mchp_pfsoc_mmuart_create(system_memory,
3468f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART0].base,
3478f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ),
3488f2ac39dSBin Meng serial_hd(0));
3498f2ac39dSBin Meng s->serial1 = mchp_pfsoc_mmuart_create(system_memory,
3508f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART1].base,
3518f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ),
3528f2ac39dSBin Meng serial_hd(1));
3538f2ac39dSBin Meng s->serial2 = mchp_pfsoc_mmuart_create(system_memory,
3548f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART2].base,
3558f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ),
3568f2ac39dSBin Meng serial_hd(2));
3578f2ac39dSBin Meng s->serial3 = mchp_pfsoc_mmuart_create(system_memory,
3588f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART3].base,
3598f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ),
3608f2ac39dSBin Meng serial_hd(3));
3618f2ac39dSBin Meng s->serial4 = mchp_pfsoc_mmuart_create(system_memory,
3628f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART4].base,
3638f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ),
3648f2ac39dSBin Meng serial_hd(4));
3658f2ac39dSBin Meng
36625da6e31SConor Dooley /* Watchdogs */
36725da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog0",
36825da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG0].base,
36925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG0].size);
37025da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog1",
37125da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG1].base,
37225da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG1].size);
37325da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog2",
37425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG2].base,
37525da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG2].size);
37625da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog3",
37725da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG3].base,
37825da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG3].size);
37925da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog4",
38025da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG4].base,
38125da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG4].size);
38225da6e31SConor Dooley
383dfc973ecSVitaly Wool /* SPI */
384dfc973ecSVitaly Wool create_unimplemented_device("microchip.pfsoc.spi0",
385dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI0].base,
386dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI0].size);
387dfc973ecSVitaly Wool create_unimplemented_device("microchip.pfsoc.spi1",
388dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI1].base,
389dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI1].size);
390dfc973ecSVitaly Wool
39125da6e31SConor Dooley /* I2C */
39225da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.i2c0",
39325da6e31SConor Dooley memmap[MICROCHIP_PFSOC_I2C0].base,
39425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_I2C0].size);
39590742c54SBin Meng create_unimplemented_device("microchip.pfsoc.i2c1",
39690742c54SBin Meng memmap[MICROCHIP_PFSOC_I2C1].base,
39790742c54SBin Meng memmap[MICROCHIP_PFSOC_I2C1].size);
39890742c54SBin Meng
39925da6e31SConor Dooley /* CAN */
40025da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.can0",
40125da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN0].base,
40225da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN0].size);
40325da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.can1",
40425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN1].base,
40525da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN1].size);
40625da6e31SConor Dooley
40725da6e31SConor Dooley /* USB */
40825da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.usb",
40925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_USB].base,
41025da6e31SConor Dooley memmap[MICROCHIP_PFSOC_USB].size);
41125da6e31SConor Dooley
41247374b07SBin Meng /* GEMs */
413*0a7549dbSDavid Woodhouse qemu_configure_nic_device(DEVICE(&s->gem0), true, NULL);
414*0a7549dbSDavid Woodhouse qemu_configure_nic_device(DEVICE(&s->gem1), true, NULL);
41547374b07SBin Meng
41647374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp);
41747374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp);
41847374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp);
41947374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0,
42047374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM0].base);
42147374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0,
42247374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ));
42347374b07SBin Meng
42447374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp);
42547374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp);
42647374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp);
42747374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0,
42847374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM1].base);
42947374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0,
43047374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ));
43147374b07SBin Meng
432ce908a2fSBin Meng /* GPIOs */
433ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio0",
434ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].base,
435ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].size);
436ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio1",
437ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].base,
438ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].size);
439ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio2",
440ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].base,
441ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].size);
442ce908a2fSBin Meng
44356f6e31eSBin Meng /* eNVM */
44456f6e31eSBin Meng memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data",
44556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
44656f6e31eSBin Meng &error_fatal);
44756f6e31eSBin Meng memory_region_add_subregion(system_memory,
44856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
44956f6e31eSBin Meng envm_data);
45056f6e31eSBin Meng
451e35d6179SBin Meng /* IOSCB */
452e35d6179SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp);
453e35d6179SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0,
454e35d6179SBin Meng memmap[MICROCHIP_PFSOC_IOSCB].base);
455592f0a94SConor Dooley sysbus_connect_irq(SYS_BUS_DEVICE(&s->ioscb), 0,
456592f0a94SConor Dooley qdev_get_gpio_in(DEVICE(s->plic),
457592f0a94SConor Dooley MICROCHIP_PFSOC_MAILBOX_IRQ));
458dfc973ecSVitaly Wool
45925da6e31SConor Dooley /* FPGA Fabric */
46025da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.fabricfic3",
46125da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base,
46225da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size);
4638d32e374SConor Dooley /* FPGA Fabric */
4648d32e374SConor Dooley create_unimplemented_device("microchip.pfsoc.fabricfic0",
4658d32e374SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC0].base,
4668d32e374SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC0].size);
4678d32e374SConor Dooley /* FPGA Fabric */
4688d32e374SConor Dooley create_unimplemented_device("microchip.pfsoc.fabricfic1",
4698d32e374SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC1].base,
4708d32e374SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC1].size);
471d6150aceSBin Meng
472dfc973ecSVitaly Wool /* QSPI Flash */
473dfc973ecSVitaly Wool memory_region_init_rom(qspi_xip_mem, OBJECT(dev),
474dfc973ecSVitaly Wool "microchip.pfsoc.qspi_xip",
475dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_QSPI_XIP].size,
476dfc973ecSVitaly Wool &error_fatal);
477dfc973ecSVitaly Wool memory_region_add_subregion(system_memory,
478dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_QSPI_XIP].base,
479dfc973ecSVitaly Wool qspi_xip_mem);
48056f6e31eSBin Meng }
48156f6e31eSBin Meng
microchip_pfsoc_soc_class_init(ObjectClass * oc,void * data)48256f6e31eSBin Meng static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data)
48356f6e31eSBin Meng {
48456f6e31eSBin Meng DeviceClass *dc = DEVICE_CLASS(oc);
48556f6e31eSBin Meng
48656f6e31eSBin Meng dc->realize = microchip_pfsoc_soc_realize;
48756f6e31eSBin Meng /* Reason: Uses serial_hds in realize function, thus can't be used twice */
48856f6e31eSBin Meng dc->user_creatable = false;
48956f6e31eSBin Meng }
49056f6e31eSBin Meng
49156f6e31eSBin Meng static const TypeInfo microchip_pfsoc_soc_type_info = {
49256f6e31eSBin Meng .name = TYPE_MICROCHIP_PFSOC,
49356f6e31eSBin Meng .parent = TYPE_DEVICE,
49456f6e31eSBin Meng .instance_size = sizeof(MicrochipPFSoCState),
49556f6e31eSBin Meng .instance_init = microchip_pfsoc_soc_instance_init,
49656f6e31eSBin Meng .class_init = microchip_pfsoc_soc_class_init,
49756f6e31eSBin Meng };
49856f6e31eSBin Meng
microchip_pfsoc_soc_register_types(void)49956f6e31eSBin Meng static void microchip_pfsoc_soc_register_types(void)
50056f6e31eSBin Meng {
50156f6e31eSBin Meng type_register_static(µchip_pfsoc_soc_type_info);
50256f6e31eSBin Meng }
50356f6e31eSBin Meng
type_init(microchip_pfsoc_soc_register_types)50456f6e31eSBin Meng type_init(microchip_pfsoc_soc_register_types)
50556f6e31eSBin Meng
50656f6e31eSBin Meng static void microchip_icicle_kit_machine_init(MachineState *machine)
50756f6e31eSBin Meng {
50856f6e31eSBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine);
50973261285SBin Meng const MemMapEntry *memmap = microchip_pfsoc_memmap;
51056f6e31eSBin Meng MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine);
51156f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory();
512f03100d7SBin Meng MemoryRegion *mem_low = g_new(MemoryRegion, 1);
513f03100d7SBin Meng MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1);
514f03100d7SBin Meng MemoryRegion *mem_high = g_new(MemoryRegion, 1);
515f03100d7SBin Meng MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1);
516d4c624f4SBin Meng uint64_t mem_low_size, mem_high_size;
517143897b5SBin Meng hwaddr firmware_load_addr;
518143897b5SBin Meng const char *firmware_name;
519143897b5SBin Meng bool kernel_as_payload = false;
520143897b5SBin Meng target_ulong firmware_end_addr, kernel_start_addr;
521143897b5SBin Meng uint64_t kernel_entry;
522143897b5SBin Meng uint32_t fdt_load_addr;
52364eaa820SMarkus Armbruster DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
52456f6e31eSBin Meng
52556f6e31eSBin Meng /* Sanity check on RAM size */
52656f6e31eSBin Meng if (machine->ram_size < mc->default_ram_size) {
52756f6e31eSBin Meng char *sz = size_to_str(mc->default_ram_size);
52856f6e31eSBin Meng error_report("Invalid RAM size, should be bigger than %s", sz);
52956f6e31eSBin Meng g_free(sz);
53056f6e31eSBin Meng exit(EXIT_FAILURE);
53156f6e31eSBin Meng }
53256f6e31eSBin Meng
53356f6e31eSBin Meng /* Initialize SoC */
53456f6e31eSBin Meng object_initialize_child(OBJECT(machine), "soc", &s->soc,
53556f6e31eSBin Meng TYPE_MICROCHIP_PFSOC);
5368f972e5bSAlistair Francis qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
53756f6e31eSBin Meng
538d4c624f4SBin Meng /* Split RAM into low and high regions using aliases to machine->ram */
539d4c624f4SBin Meng mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size;
540d4c624f4SBin Meng mem_high_size = machine->ram_size - mem_low_size;
541d4c624f4SBin Meng memory_region_init_alias(mem_low, NULL,
542d4c624f4SBin Meng "microchip.icicle.kit.ram_low", machine->ram,
543d4c624f4SBin Meng 0, mem_low_size);
544d4c624f4SBin Meng memory_region_init_alias(mem_high, NULL,
545d4c624f4SBin Meng "microchip.icicle.kit.ram_high", machine->ram,
546d4c624f4SBin Meng mem_low_size, mem_high_size);
547d4c624f4SBin Meng
54856f6e31eSBin Meng /* Register RAM */
54956f6e31eSBin Meng memory_region_add_subregion(system_memory,
550f03100d7SBin Meng memmap[MICROCHIP_PFSOC_DRAM_LO].base,
551f03100d7SBin Meng mem_low);
552f03100d7SBin Meng memory_region_add_subregion(system_memory,
553d4c624f4SBin Meng memmap[MICROCHIP_PFSOC_DRAM_HI].base,
554d4c624f4SBin Meng mem_high);
555d4c624f4SBin Meng
556d4c624f4SBin Meng /* Create aliases for the low and high RAM regions */
557d4c624f4SBin Meng memory_region_init_alias(mem_low_alias, NULL,
558d4c624f4SBin Meng "microchip.icicle.kit.ram_low.alias",
559d4c624f4SBin Meng mem_low, 0, mem_low_size);
560d4c624f4SBin Meng memory_region_add_subregion(system_memory,
561f03100d7SBin Meng memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base,
562f03100d7SBin Meng mem_low_alias);
563f03100d7SBin Meng memory_region_init_alias(mem_high_alias, NULL,
564f03100d7SBin Meng "microchip.icicle.kit.ram_high.alias",
565f03100d7SBin Meng mem_high, 0, mem_high_size);
566f03100d7SBin Meng memory_region_add_subregion(system_memory,
567f03100d7SBin Meng memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base,
568f03100d7SBin Meng mem_high_alias);
56956f6e31eSBin Meng
570898dc008SBin Meng /* Attach an SD card */
571898dc008SBin Meng if (dinfo) {
572898dc008SBin Meng CadenceSDHCIState *sdhci = &(s->soc.sdhci);
573898dc008SBin Meng DeviceState *card = qdev_new(TYPE_SD_CARD);
574898dc008SBin Meng
575898dc008SBin Meng qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
576898dc008SBin Meng &error_fatal);
577898dc008SBin Meng qdev_realize_and_unref(card, sdhci->bus, &error_fatal);
578898dc008SBin Meng }
579143897b5SBin Meng
580143897b5SBin Meng /*
581143897b5SBin Meng * We follow the following table to select which payload we execute.
582143897b5SBin Meng *
583143897b5SBin Meng * -bios | -kernel | payload
584143897b5SBin Meng * -------+------------+--------
585143897b5SBin Meng * N | N | HSS
586143897b5SBin Meng * Y | don't care | HSS
587143897b5SBin Meng * N | Y | kernel
588143897b5SBin Meng *
589143897b5SBin Meng * This ensures backwards compatibility with how we used to expose -bios
590143897b5SBin Meng * to users but allows them to run through direct kernel booting as well.
591143897b5SBin Meng *
592143897b5SBin Meng * When -kernel is used for direct boot, -dtb must be present to provide
593143897b5SBin Meng * a valid device tree for the board, as we don't generate device tree.
594143897b5SBin Meng */
595143897b5SBin Meng
596143897b5SBin Meng if (machine->kernel_filename && machine->dtb) {
597143897b5SBin Meng int fdt_size;
598143897b5SBin Meng machine->fdt = load_device_tree(machine->dtb, &fdt_size);
599143897b5SBin Meng if (!machine->fdt) {
600143897b5SBin Meng error_report("load_device_tree() failed");
601143897b5SBin Meng exit(1);
602143897b5SBin Meng }
603143897b5SBin Meng
604143897b5SBin Meng firmware_name = RISCV64_BIOS_BIN;
605143897b5SBin Meng firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base;
606143897b5SBin Meng kernel_as_payload = true;
607143897b5SBin Meng }
608143897b5SBin Meng
609143897b5SBin Meng if (!kernel_as_payload) {
610143897b5SBin Meng firmware_name = BIOS_FILENAME;
611143897b5SBin Meng firmware_load_addr = RESET_VECTOR;
612143897b5SBin Meng }
613143897b5SBin Meng
614143897b5SBin Meng /* Load the firmware */
615143897b5SBin Meng firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name,
616143897b5SBin Meng firmware_load_addr, NULL);
617143897b5SBin Meng
618143897b5SBin Meng if (kernel_as_payload) {
619143897b5SBin Meng kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus,
620143897b5SBin Meng firmware_end_addr);
621143897b5SBin Meng
62262c5bc34SDaniel Henrique Barboza kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus,
623487d73fcSDaniel Henrique Barboza kernel_start_addr, true, NULL);
624143897b5SBin Meng
625143897b5SBin Meng /* Compute the fdt load address in dram */
626bc2c0153SDaniel Henrique Barboza fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base,
6274b402886SDaniel Henrique Barboza memmap[MICROCHIP_PFSOC_DRAM_LO].size,
6284b402886SDaniel Henrique Barboza machine);
629bc2c0153SDaniel Henrique Barboza riscv_load_fdt(fdt_load_addr, machine->fdt);
630bc2c0153SDaniel Henrique Barboza
631143897b5SBin Meng /* Load the reset vector */
632143897b5SBin Meng riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr,
633143897b5SBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base,
634143897b5SBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size,
6356934f15bSDaniel Henrique Barboza kernel_entry, fdt_load_addr);
636143897b5SBin Meng }
63756f6e31eSBin Meng }
63856f6e31eSBin Meng
microchip_icicle_kit_machine_class_init(ObjectClass * oc,void * data)63956f6e31eSBin Meng static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data)
64056f6e31eSBin Meng {
64156f6e31eSBin Meng MachineClass *mc = MACHINE_CLASS(oc);
64256f6e31eSBin Meng
64356f6e31eSBin Meng mc->desc = "Microchip PolarFire SoC Icicle Kit";
64456f6e31eSBin Meng mc->init = microchip_icicle_kit_machine_init;
64556f6e31eSBin Meng mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT +
64656f6e31eSBin Meng MICROCHIP_PFSOC_COMPUTE_CPU_COUNT;
64756f6e31eSBin Meng mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1;
64856f6e31eSBin Meng mc->default_cpus = mc->min_cpus;
649d4c624f4SBin Meng mc->default_ram_id = "microchip.icicle.kit.ram";
650f03100d7SBin Meng
651f03100d7SBin Meng /*
65242fe7499SMichael Tokarev * Map 513 MiB high memory, the minimum required high memory size, because
653f03100d7SBin Meng * HSS will do memory test against the high memory address range regardless
654f03100d7SBin Meng * of physical memory installed.
655f03100d7SBin Meng *
656f03100d7SBin Meng * See memory_tests() in mss_ddr.c in the HSS source code.
657f03100d7SBin Meng */
658f03100d7SBin Meng mc->default_ram_size = 1537 * MiB;
65956f6e31eSBin Meng }
66056f6e31eSBin Meng
66156f6e31eSBin Meng static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
66256f6e31eSBin Meng .name = MACHINE_TYPE_NAME("microchip-icicle-kit"),
66356f6e31eSBin Meng .parent = TYPE_MACHINE,
66456f6e31eSBin Meng .class_init = microchip_icicle_kit_machine_class_init,
66556f6e31eSBin Meng .instance_size = sizeof(MicrochipIcicleKitState),
66656f6e31eSBin Meng };
66756f6e31eSBin Meng
microchip_icicle_kit_machine_init_register_types(void)66856f6e31eSBin Meng static void microchip_icicle_kit_machine_init_register_types(void)
66956f6e31eSBin Meng {
67056f6e31eSBin Meng type_register_static(µchip_icicle_kit_machine_typeinfo);
67156f6e31eSBin Meng }
67256f6e31eSBin Meng
67356f6e31eSBin Meng type_init(microchip_icicle_kit_machine_init_register_types)
674