156f6e31eSBin Meng /* 256f6e31eSBin Meng * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 1056f6e31eSBin Meng * 1156f6e31eSBin Meng * 0) CLINT (Core Level Interruptor) 1256f6e31eSBin Meng * 1) PLIC (Platform Level Interrupt Controller) 1356f6e31eSBin Meng * 2) eNVM (Embedded Non-Volatile Memory) 148f2ac39dSBin Meng * 3) MMUARTs (Multi-Mode UART) 15898dc008SBin Meng * 4) Cadence eMMC/SDHC controller and an SD card connected to it 167124e27bSBin Meng * 5) SiFive Platform DMA (Direct Memory Access Controller) 1747374b07SBin Meng * 6) GEM (Gigabit Ethernet MAC Controller) 1856f6e31eSBin Meng * 1956f6e31eSBin Meng * This board currently generates devicetree dynamically that indicates at least 2056f6e31eSBin Meng * two harts and up to five harts. 2156f6e31eSBin Meng * 2256f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 2356f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 2456f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 2556f6e31eSBin Meng * 2656f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 2756f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 2856f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 2956f6e31eSBin Meng * more details. 3056f6e31eSBin Meng * 3156f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 3256f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 3356f6e31eSBin Meng */ 3456f6e31eSBin Meng 3556f6e31eSBin Meng #include "qemu/osdep.h" 3656f6e31eSBin Meng #include "qemu/error-report.h" 3756f6e31eSBin Meng #include "qemu/log.h" 3856f6e31eSBin Meng #include "qemu/units.h" 3956f6e31eSBin Meng #include "qemu/cutils.h" 4056f6e31eSBin Meng #include "qapi/error.h" 4156f6e31eSBin Meng #include "hw/boards.h" 4256f6e31eSBin Meng #include "hw/irq.h" 4356f6e31eSBin Meng #include "hw/loader.h" 4456f6e31eSBin Meng #include "hw/sysbus.h" 458f2ac39dSBin Meng #include "chardev/char.h" 4656f6e31eSBin Meng #include "hw/cpu/cluster.h" 4756f6e31eSBin Meng #include "target/riscv/cpu.h" 4856f6e31eSBin Meng #include "hw/misc/unimp.h" 4956f6e31eSBin Meng #include "hw/riscv/boot.h" 5056f6e31eSBin Meng #include "hw/riscv/riscv_hart.h" 5156f6e31eSBin Meng #include "hw/riscv/microchip_pfsoc.h" 52406fafd5SBin Meng #include "hw/intc/sifive_clint.h" 5384fcf3c1SBin Meng #include "hw/intc/sifive_plic.h" 548f2ac39dSBin Meng #include "sysemu/sysemu.h" 5556f6e31eSBin Meng 5656f6e31eSBin Meng /* 5756f6e31eSBin Meng * The BIOS image used by this machine is called Hart Software Services (HSS). 5856f6e31eSBin Meng * See https://github.com/polarfire-soc/hart-software-services 5956f6e31eSBin Meng */ 6056f6e31eSBin Meng #define BIOS_FILENAME "hss.bin" 6156f6e31eSBin Meng #define RESET_VECTOR 0x20220000 6256f6e31eSBin Meng 63a47ef6e9SBin Meng /* CLINT timebase frequency */ 64a47ef6e9SBin Meng #define CLINT_TIMEBASE_FREQ 1000000 65a47ef6e9SBin Meng 6647374b07SBin Meng /* GEM version */ 6747374b07SBin Meng #define GEM_REVISION 0x0107010c 6847374b07SBin Meng 69*08b86e3bSBin Meng /* 70*08b86e3bSBin Meng * The complete description of the whole PolarFire SoC memory map is scattered 71*08b86e3bSBin Meng * in different documents. There are several places to look at for memory maps: 72*08b86e3bSBin Meng * 73*08b86e3bSBin Meng * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 74*08b86e3bSBin Meng * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 75*08b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/ 76*08b86e3bSBin Meng * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 77*08b86e3bSBin Meng * describes the whole picture of the PolarFire SoC memory map. 78*08b86e3bSBin Meng * 79*08b86e3bSBin Meng * 2 A zip file for PolarFire soC memory map, which can be downloaded from 80*08b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/ 81*08b86e3bSBin Meng * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 82*08b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 83*08b86e3bSBin Meng * describes the complete integrated peripherals memory map 84*08b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 85*08b86e3bSBin Meng * describes the complete IOSCB modules memory maps 86*08b86e3bSBin Meng */ 8756f6e31eSBin Meng static const struct MemmapEntry { 8856f6e31eSBin Meng hwaddr base; 8956f6e31eSBin Meng hwaddr size; 9056f6e31eSBin Meng } microchip_pfsoc_memmap[] = { 9156f6e31eSBin Meng [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, 9256f6e31eSBin Meng [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 9356f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 9456f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 9556f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 9656f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 9756f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 9856f6e31eSBin Meng [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 9956f6e31eSBin Meng [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 1007124e27bSBin Meng [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 10156f6e31eSBin Meng [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 10256f6e31eSBin Meng [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 1038f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 10456f6e31eSBin Meng [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 10556f6e31eSBin Meng [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 106898dc008SBin Meng [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 1078f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 1088f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 1098f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 1108f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 11147374b07SBin Meng [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 11247374b07SBin Meng [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 113ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 114ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 115ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 11656f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 11756f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 11856f6e31eSBin Meng [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, 11956f6e31eSBin Meng [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, 12056f6e31eSBin Meng }; 12156f6e31eSBin Meng 12256f6e31eSBin Meng static void microchip_pfsoc_soc_instance_init(Object *obj) 12356f6e31eSBin Meng { 12456f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 12556f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 12656f6e31eSBin Meng 12756f6e31eSBin Meng object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 12856f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 12956f6e31eSBin Meng 13056f6e31eSBin Meng object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 13156f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 13256f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 13356f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 13456f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 13556f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_E51); 13656f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 13756f6e31eSBin Meng 13856f6e31eSBin Meng object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 13956f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 14056f6e31eSBin Meng 14156f6e31eSBin Meng object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 14256f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 14356f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 14456f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 14556f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 14656f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_U54); 14756f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 148898dc008SBin Meng 1497124e27bSBin Meng object_initialize_child(obj, "dma-controller", &s->dma, 1507124e27bSBin Meng TYPE_SIFIVE_PDMA); 1517124e27bSBin Meng 15247374b07SBin Meng object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 15347374b07SBin Meng object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 15447374b07SBin Meng 155898dc008SBin Meng object_initialize_child(obj, "sd-controller", &s->sdhci, 156898dc008SBin Meng TYPE_CADENCE_SDHCI); 15756f6e31eSBin Meng } 15856f6e31eSBin Meng 15956f6e31eSBin Meng static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 16056f6e31eSBin Meng { 16156f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 16256f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 16356f6e31eSBin Meng const struct MemmapEntry *memmap = microchip_pfsoc_memmap; 16456f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 16556f6e31eSBin Meng MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 16656f6e31eSBin Meng MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 16756f6e31eSBin Meng MemoryRegion *envm_data = g_new(MemoryRegion, 1); 16856f6e31eSBin Meng char *plic_hart_config; 16956f6e31eSBin Meng size_t plic_hart_config_len; 17047374b07SBin Meng NICInfo *nd; 17156f6e31eSBin Meng int i; 17256f6e31eSBin Meng 17356f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 17456f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 17556f6e31eSBin Meng /* 17656f6e31eSBin Meng * The cluster must be realized after the RISC-V hart array container, 17756f6e31eSBin Meng * as the container's CPU object is only created on realize, and the 17856f6e31eSBin Meng * CPU must exist and have been parented into the cluster before the 17956f6e31eSBin Meng * cluster is realized. 18056f6e31eSBin Meng */ 18156f6e31eSBin Meng qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 18256f6e31eSBin Meng qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 18356f6e31eSBin Meng 18456f6e31eSBin Meng /* E51 DTIM */ 18556f6e31eSBin Meng memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 18656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 18756f6e31eSBin Meng memory_region_add_subregion(system_memory, 18856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].base, 18956f6e31eSBin Meng e51_dtim_mem); 19056f6e31eSBin Meng 19156f6e31eSBin Meng /* Bus Error Units */ 19256f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 19356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 19456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 19556f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 19656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 19756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 19856f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 19956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 20056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 20156f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 20256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 20356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 20456f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 20556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 20656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 20756f6e31eSBin Meng 20856f6e31eSBin Meng /* CLINT */ 20956f6e31eSBin Meng sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, 21056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, 211a47ef6e9SBin Meng SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 212a47ef6e9SBin Meng CLINT_TIMEBASE_FREQ, false); 21356f6e31eSBin Meng 21456f6e31eSBin Meng /* L2 cache controller */ 21556f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.l2cc", 21656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 21756f6e31eSBin Meng 21856f6e31eSBin Meng /* 21956f6e31eSBin Meng * Add L2-LIM at reset size. 22056f6e31eSBin Meng * This should be reduced in size as the L2 Cache Controller WayEnable 22156f6e31eSBin Meng * register is incremented. Unfortunately I don't see a nice (or any) way 22256f6e31eSBin Meng * to handle reducing or blocking out the L2 LIM while still allowing it 22356f6e31eSBin Meng * be re returned to all enabled after a reset. For the time being, just 22456f6e31eSBin Meng * leave it enabled all the time. This won't break anything, but will be 22556f6e31eSBin Meng * too generous to misbehaving guests. 22656f6e31eSBin Meng */ 22756f6e31eSBin Meng memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 22856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 22956f6e31eSBin Meng memory_region_add_subregion(system_memory, 23056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].base, 23156f6e31eSBin Meng l2lim_mem); 23256f6e31eSBin Meng 23356f6e31eSBin Meng /* create PLIC hart topology configuration string */ 23456f6e31eSBin Meng plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * 23556f6e31eSBin Meng ms->smp.cpus; 23656f6e31eSBin Meng plic_hart_config = g_malloc0(plic_hart_config_len); 23756f6e31eSBin Meng for (i = 0; i < ms->smp.cpus; i++) { 23856f6e31eSBin Meng if (i != 0) { 23956f6e31eSBin Meng strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, 24056f6e31eSBin Meng plic_hart_config_len); 24156f6e31eSBin Meng } else { 24256f6e31eSBin Meng strncat(plic_hart_config, "M", plic_hart_config_len); 24356f6e31eSBin Meng } 24456f6e31eSBin Meng plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); 24556f6e31eSBin Meng } 24656f6e31eSBin Meng 24756f6e31eSBin Meng /* PLIC */ 24856f6e31eSBin Meng s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 24956f6e31eSBin Meng plic_hart_config, 0, 25056f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 25156f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 25256f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 25356f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PENDING_BASE, 25456f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 25556f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 25656f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 25756f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 25856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_PLIC].size); 25956f6e31eSBin Meng g_free(plic_hart_config); 26056f6e31eSBin Meng 2617124e27bSBin Meng /* DMA */ 2627124e27bSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 2637124e27bSBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 2647124e27bSBin Meng memmap[MICROCHIP_PFSOC_DMA].base); 2657124e27bSBin Meng for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 2667124e27bSBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 2677124e27bSBin Meng qdev_get_gpio_in(DEVICE(s->plic), 2687124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 + i)); 2697124e27bSBin Meng } 2707124e27bSBin Meng 27156f6e31eSBin Meng /* SYSREG */ 27256f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.sysreg", 27356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_SYSREG].base, 27456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_SYSREG].size); 27556f6e31eSBin Meng 27656f6e31eSBin Meng /* MPUCFG */ 27756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.mpucfg", 27856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].base, 27956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].size); 28056f6e31eSBin Meng 281898dc008SBin Meng /* SDHCI */ 282898dc008SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 283898dc008SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 284898dc008SBin Meng memmap[MICROCHIP_PFSOC_EMMC_SD].base); 285898dc008SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 286898dc008SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 287898dc008SBin Meng 2888f2ac39dSBin Meng /* MMUARTs */ 2898f2ac39dSBin Meng s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 2908f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART0].base, 2918f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 2928f2ac39dSBin Meng serial_hd(0)); 2938f2ac39dSBin Meng s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 2948f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART1].base, 2958f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 2968f2ac39dSBin Meng serial_hd(1)); 2978f2ac39dSBin Meng s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 2988f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART2].base, 2998f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 3008f2ac39dSBin Meng serial_hd(2)); 3018f2ac39dSBin Meng s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 3028f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART3].base, 3038f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 3048f2ac39dSBin Meng serial_hd(3)); 3058f2ac39dSBin Meng s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 3068f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART4].base, 3078f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 3088f2ac39dSBin Meng serial_hd(4)); 3098f2ac39dSBin Meng 31047374b07SBin Meng /* GEMs */ 31147374b07SBin Meng 31247374b07SBin Meng nd = &nd_table[0]; 31347374b07SBin Meng if (nd->used) { 31447374b07SBin Meng qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 31547374b07SBin Meng qdev_set_nic_properties(DEVICE(&s->gem0), nd); 31647374b07SBin Meng } 31747374b07SBin Meng nd = &nd_table[1]; 31847374b07SBin Meng if (nd->used) { 31947374b07SBin Meng qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 32047374b07SBin Meng qdev_set_nic_properties(DEVICE(&s->gem1), nd); 32147374b07SBin Meng } 32247374b07SBin Meng 32347374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 32447374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 32547374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 32647374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 32747374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM0].base); 32847374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 32947374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 33047374b07SBin Meng 33147374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 33247374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 33347374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 33447374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 33547374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM1].base); 33647374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 33747374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 33847374b07SBin Meng 339ce908a2fSBin Meng /* GPIOs */ 340ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio0", 341ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].base, 342ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].size); 343ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio1", 344ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].base, 345ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].size); 346ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio2", 347ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].base, 348ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].size); 349ce908a2fSBin Meng 35056f6e31eSBin Meng /* eNVM */ 35156f6e31eSBin Meng memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 35256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 35356f6e31eSBin Meng &error_fatal); 35456f6e31eSBin Meng memory_region_add_subregion(system_memory, 35556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 35656f6e31eSBin Meng envm_data); 35756f6e31eSBin Meng 35856f6e31eSBin Meng /* IOSCBCFG */ 35956f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.ioscb.cfg", 36056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, 36156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); 36256f6e31eSBin Meng } 36356f6e31eSBin Meng 36456f6e31eSBin Meng static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 36556f6e31eSBin Meng { 36656f6e31eSBin Meng DeviceClass *dc = DEVICE_CLASS(oc); 36756f6e31eSBin Meng 36856f6e31eSBin Meng dc->realize = microchip_pfsoc_soc_realize; 36956f6e31eSBin Meng /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 37056f6e31eSBin Meng dc->user_creatable = false; 37156f6e31eSBin Meng } 37256f6e31eSBin Meng 37356f6e31eSBin Meng static const TypeInfo microchip_pfsoc_soc_type_info = { 37456f6e31eSBin Meng .name = TYPE_MICROCHIP_PFSOC, 37556f6e31eSBin Meng .parent = TYPE_DEVICE, 37656f6e31eSBin Meng .instance_size = sizeof(MicrochipPFSoCState), 37756f6e31eSBin Meng .instance_init = microchip_pfsoc_soc_instance_init, 37856f6e31eSBin Meng .class_init = microchip_pfsoc_soc_class_init, 37956f6e31eSBin Meng }; 38056f6e31eSBin Meng 38156f6e31eSBin Meng static void microchip_pfsoc_soc_register_types(void) 38256f6e31eSBin Meng { 38356f6e31eSBin Meng type_register_static(µchip_pfsoc_soc_type_info); 38456f6e31eSBin Meng } 38556f6e31eSBin Meng 38656f6e31eSBin Meng type_init(microchip_pfsoc_soc_register_types) 38756f6e31eSBin Meng 38856f6e31eSBin Meng static void microchip_icicle_kit_machine_init(MachineState *machine) 38956f6e31eSBin Meng { 39056f6e31eSBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine); 39156f6e31eSBin Meng const struct MemmapEntry *memmap = microchip_pfsoc_memmap; 39256f6e31eSBin Meng MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 39356f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 39456f6e31eSBin Meng MemoryRegion *main_mem = g_new(MemoryRegion, 1); 395898dc008SBin Meng DriveInfo *dinfo = drive_get_next(IF_SD); 39656f6e31eSBin Meng 39756f6e31eSBin Meng /* Sanity check on RAM size */ 39856f6e31eSBin Meng if (machine->ram_size < mc->default_ram_size) { 39956f6e31eSBin Meng char *sz = size_to_str(mc->default_ram_size); 40056f6e31eSBin Meng error_report("Invalid RAM size, should be bigger than %s", sz); 40156f6e31eSBin Meng g_free(sz); 40256f6e31eSBin Meng exit(EXIT_FAILURE); 40356f6e31eSBin Meng } 40456f6e31eSBin Meng 40556f6e31eSBin Meng /* Initialize SoC */ 40656f6e31eSBin Meng object_initialize_child(OBJECT(machine), "soc", &s->soc, 40756f6e31eSBin Meng TYPE_MICROCHIP_PFSOC); 40856f6e31eSBin Meng qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 40956f6e31eSBin Meng 41056f6e31eSBin Meng /* Register RAM */ 41156f6e31eSBin Meng memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", 41256f6e31eSBin Meng machine->ram_size, &error_fatal); 41356f6e31eSBin Meng memory_region_add_subregion(system_memory, 41456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_DRAM].base, main_mem); 41556f6e31eSBin Meng 41656f6e31eSBin Meng /* Load the firmware */ 41756f6e31eSBin Meng riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); 418898dc008SBin Meng 419898dc008SBin Meng /* Attach an SD card */ 420898dc008SBin Meng if (dinfo) { 421898dc008SBin Meng CadenceSDHCIState *sdhci = &(s->soc.sdhci); 422898dc008SBin Meng DeviceState *card = qdev_new(TYPE_SD_CARD); 423898dc008SBin Meng 424898dc008SBin Meng qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 425898dc008SBin Meng &error_fatal); 426898dc008SBin Meng qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 427898dc008SBin Meng } 42856f6e31eSBin Meng } 42956f6e31eSBin Meng 43056f6e31eSBin Meng static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 43156f6e31eSBin Meng { 43256f6e31eSBin Meng MachineClass *mc = MACHINE_CLASS(oc); 43356f6e31eSBin Meng 43456f6e31eSBin Meng mc->desc = "Microchip PolarFire SoC Icicle Kit"; 43556f6e31eSBin Meng mc->init = microchip_icicle_kit_machine_init; 43656f6e31eSBin Meng mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 43756f6e31eSBin Meng MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 43856f6e31eSBin Meng mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 43956f6e31eSBin Meng mc->default_cpus = mc->min_cpus; 44056f6e31eSBin Meng mc->default_ram_size = 1 * GiB; 44156f6e31eSBin Meng } 44256f6e31eSBin Meng 44356f6e31eSBin Meng static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 44456f6e31eSBin Meng .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 44556f6e31eSBin Meng .parent = TYPE_MACHINE, 44656f6e31eSBin Meng .class_init = microchip_icicle_kit_machine_class_init, 44756f6e31eSBin Meng .instance_size = sizeof(MicrochipIcicleKitState), 44856f6e31eSBin Meng }; 44956f6e31eSBin Meng 45056f6e31eSBin Meng static void microchip_icicle_kit_machine_init_register_types(void) 45156f6e31eSBin Meng { 45256f6e31eSBin Meng type_register_static(µchip_icicle_kit_machine_typeinfo); 45356f6e31eSBin Meng } 45456f6e31eSBin Meng 45556f6e31eSBin Meng type_init(microchip_icicle_kit_machine_init_register_types) 456