156f6e31eSBin Meng /* 256f6e31eSBin Meng * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 1056f6e31eSBin Meng * 1156f6e31eSBin Meng * 0) CLINT (Core Level Interruptor) 1256f6e31eSBin Meng * 1) PLIC (Platform Level Interrupt Controller) 1356f6e31eSBin Meng * 2) eNVM (Embedded Non-Volatile Memory) 148f2ac39dSBin Meng * 3) MMUARTs (Multi-Mode UART) 15898dc008SBin Meng * 4) Cadence eMMC/SDHC controller and an SD card connected to it 167124e27bSBin Meng * 5) SiFive Platform DMA (Direct Memory Access Controller) 1747374b07SBin Meng * 6) GEM (Gigabit Ethernet MAC Controller) 18933f73f1SBin Meng * 7) DMC (DDR Memory Controller) 19e35d6179SBin Meng * 8) IOSCB modules 2056f6e31eSBin Meng * 2156f6e31eSBin Meng * This board currently generates devicetree dynamically that indicates at least 2256f6e31eSBin Meng * two harts and up to five harts. 2356f6e31eSBin Meng * 2456f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 2556f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 2656f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 2756f6e31eSBin Meng * 2856f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 2956f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 3056f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 3156f6e31eSBin Meng * more details. 3256f6e31eSBin Meng * 3356f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 3456f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 3556f6e31eSBin Meng */ 3656f6e31eSBin Meng 3756f6e31eSBin Meng #include "qemu/osdep.h" 3856f6e31eSBin Meng #include "qemu/error-report.h" 3956f6e31eSBin Meng #include "qemu/units.h" 4056f6e31eSBin Meng #include "qemu/cutils.h" 4156f6e31eSBin Meng #include "qapi/error.h" 4256f6e31eSBin Meng #include "hw/boards.h" 4356f6e31eSBin Meng #include "hw/loader.h" 4456f6e31eSBin Meng #include "hw/sysbus.h" 458f2ac39dSBin Meng #include "chardev/char.h" 4656f6e31eSBin Meng #include "hw/cpu/cluster.h" 4756f6e31eSBin Meng #include "target/riscv/cpu.h" 4856f6e31eSBin Meng #include "hw/misc/unimp.h" 4956f6e31eSBin Meng #include "hw/riscv/boot.h" 5056f6e31eSBin Meng #include "hw/riscv/riscv_hart.h" 5156f6e31eSBin Meng #include "hw/riscv/microchip_pfsoc.h" 52cc63a182SAnup Patel #include "hw/intc/riscv_aclint.h" 5384fcf3c1SBin Meng #include "hw/intc/sifive_plic.h" 54143897b5SBin Meng #include "sysemu/device_tree.h" 558f2ac39dSBin Meng #include "sysemu/sysemu.h" 5656f6e31eSBin Meng 5756f6e31eSBin Meng /* 5856f6e31eSBin Meng * The BIOS image used by this machine is called Hart Software Services (HSS). 5956f6e31eSBin Meng * See https://github.com/polarfire-soc/hart-software-services 6056f6e31eSBin Meng */ 6156f6e31eSBin Meng #define BIOS_FILENAME "hss.bin" 6256f6e31eSBin Meng #define RESET_VECTOR 0x20220000 6356f6e31eSBin Meng 64a47ef6e9SBin Meng /* CLINT timebase frequency */ 65a47ef6e9SBin Meng #define CLINT_TIMEBASE_FREQ 1000000 66a47ef6e9SBin Meng 6747374b07SBin Meng /* GEM version */ 6847374b07SBin Meng #define GEM_REVISION 0x0107010c 6947374b07SBin Meng 7008b86e3bSBin Meng /* 7108b86e3bSBin Meng * The complete description of the whole PolarFire SoC memory map is scattered 7208b86e3bSBin Meng * in different documents. There are several places to look at for memory maps: 7308b86e3bSBin Meng * 7408b86e3bSBin Meng * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 7508b86e3bSBin Meng * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 7608b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/ 7708b86e3bSBin Meng * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 7808b86e3bSBin Meng * describes the whole picture of the PolarFire SoC memory map. 7908b86e3bSBin Meng * 8008b86e3bSBin Meng * 2 A zip file for PolarFire soC memory map, which can be downloaded from 8108b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/ 8208b86e3bSBin Meng * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 8308b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 8408b86e3bSBin Meng * describes the complete integrated peripherals memory map 8508b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 8608b86e3bSBin Meng * describes the complete IOSCB modules memory maps 8708b86e3bSBin Meng */ 8873261285SBin Meng static const MemMapEntry microchip_pfsoc_memmap[] = { 8927c22b2dSBin Meng [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 9027c22b2dSBin Meng [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 9156f6e31eSBin Meng [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 9256f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 9356f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 9456f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 9556f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 9656f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 9756f6e31eSBin Meng [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 9856f6e31eSBin Meng [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 997124e27bSBin Meng [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 10056f6e31eSBin Meng [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 10156f6e31eSBin Meng [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 1028f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 10325da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG0] = { 0x20001000, 0x1000 }, 10456f6e31eSBin Meng [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 10525da6e31SConor Dooley [MICROCHIP_PFSOC_AXISW] = { 0x20004000, 0x1000 }, 10656f6e31eSBin Meng [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 10725da6e31SConor Dooley [MICROCHIP_PFSOC_FMETER] = { 0x20006000, 0x1000 }, 108933f73f1SBin Meng [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 109898dc008SBin Meng [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 110933f73f1SBin Meng [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 1118f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 1128f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 1138f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 1148f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 11525da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG1] = { 0x20101000, 0x1000 }, 11625da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG2] = { 0x20103000, 0x1000 }, 11725da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG3] = { 0x20105000, 0x1000 }, 11825da6e31SConor Dooley [MICROCHIP_PFSOC_WDOG4] = { 0x20106000, 0x1000 }, 119dfc973ecSVitaly Wool [MICROCHIP_PFSOC_SPI0] = { 0x20108000, 0x1000 }, 120dfc973ecSVitaly Wool [MICROCHIP_PFSOC_SPI1] = { 0x20109000, 0x1000 }, 12125da6e31SConor Dooley [MICROCHIP_PFSOC_I2C0] = { 0x2010a000, 0x1000 }, 12290742c54SBin Meng [MICROCHIP_PFSOC_I2C1] = { 0x2010b000, 0x1000 }, 12325da6e31SConor Dooley [MICROCHIP_PFSOC_CAN0] = { 0x2010c000, 0x1000 }, 12425da6e31SConor Dooley [MICROCHIP_PFSOC_CAN1] = { 0x2010d000, 0x1000 }, 12547374b07SBin Meng [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 12647374b07SBin Meng [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 127ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 128ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 129ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 13025da6e31SConor Dooley [MICROCHIP_PFSOC_RTC] = { 0x20124000, 0x1000 }, 13156f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 13256f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 13325da6e31SConor Dooley [MICROCHIP_PFSOC_USB] = { 0x20201000, 0x1000 }, 134dfc973ecSVitaly Wool [MICROCHIP_PFSOC_QSPI_XIP] = { 0x21000000, 0x1000000 }, 135e35d6179SBin Meng [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 13625da6e31SConor Dooley [MICROCHIP_PFSOC_FABRIC_FIC3] = { 0x40000000, 0x20000000 }, 137f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, 138f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_LO_ALIAS] = { 0xc0000000, 0x40000000 }, 139f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, 140f03100d7SBin Meng [MICROCHIP_PFSOC_DRAM_HI_ALIAS] = { 0x1400000000, 0x0 }, 14156f6e31eSBin Meng }; 14256f6e31eSBin Meng 14356f6e31eSBin Meng static void microchip_pfsoc_soc_instance_init(Object *obj) 14456f6e31eSBin Meng { 14556f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 14656f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 14756f6e31eSBin Meng 14856f6e31eSBin Meng object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 14956f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 15056f6e31eSBin Meng 15156f6e31eSBin Meng object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 15256f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 15356f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 15456f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 15556f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 15656f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_E51); 15756f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 15856f6e31eSBin Meng 15956f6e31eSBin Meng object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 16056f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 16156f6e31eSBin Meng 16256f6e31eSBin Meng object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 16356f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 16456f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 16556f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 16656f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 16756f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_U54); 16856f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 169898dc008SBin Meng 1707124e27bSBin Meng object_initialize_child(obj, "dma-controller", &s->dma, 1717124e27bSBin Meng TYPE_SIFIVE_PDMA); 1727124e27bSBin Meng 173cdd58c70SBin Meng object_initialize_child(obj, "sysreg", &s->sysreg, 174cdd58c70SBin Meng TYPE_MCHP_PFSOC_SYSREG); 175cdd58c70SBin Meng 176933f73f1SBin Meng object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 177933f73f1SBin Meng TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 178933f73f1SBin Meng object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 179933f73f1SBin Meng TYPE_MCHP_PFSOC_DDR_CFG); 180933f73f1SBin Meng 18147374b07SBin Meng object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 18247374b07SBin Meng object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 18347374b07SBin Meng 184898dc008SBin Meng object_initialize_child(obj, "sd-controller", &s->sdhci, 185898dc008SBin Meng TYPE_CADENCE_SDHCI); 186e35d6179SBin Meng 187e35d6179SBin Meng object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 18856f6e31eSBin Meng } 18956f6e31eSBin Meng 19056f6e31eSBin Meng static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 19156f6e31eSBin Meng { 19256f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 19356f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 19473261285SBin Meng const MemMapEntry *memmap = microchip_pfsoc_memmap; 19556f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 19627c22b2dSBin Meng MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 19756f6e31eSBin Meng MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 19856f6e31eSBin Meng MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 19956f6e31eSBin Meng MemoryRegion *envm_data = g_new(MemoryRegion, 1); 200dfc973ecSVitaly Wool MemoryRegion *qspi_xip_mem = g_new(MemoryRegion, 1); 20156f6e31eSBin Meng char *plic_hart_config; 20247374b07SBin Meng NICInfo *nd; 20356f6e31eSBin Meng int i; 20456f6e31eSBin Meng 20556f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 20656f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 20756f6e31eSBin Meng /* 20856f6e31eSBin Meng * The cluster must be realized after the RISC-V hart array container, 20956f6e31eSBin Meng * as the container's CPU object is only created on realize, and the 21056f6e31eSBin Meng * CPU must exist and have been parented into the cluster before the 21156f6e31eSBin Meng * cluster is realized. 21256f6e31eSBin Meng */ 21356f6e31eSBin Meng qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 21456f6e31eSBin Meng qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 21556f6e31eSBin Meng 21627c22b2dSBin Meng /* Reserved Memory at address 0 */ 21727c22b2dSBin Meng memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 21827c22b2dSBin Meng memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 21927c22b2dSBin Meng memory_region_add_subregion(system_memory, 22027c22b2dSBin Meng memmap[MICROCHIP_PFSOC_RSVD0].base, 22127c22b2dSBin Meng rsvd0_mem); 22227c22b2dSBin Meng 22356f6e31eSBin Meng /* E51 DTIM */ 22456f6e31eSBin Meng memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 22556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 22656f6e31eSBin Meng memory_region_add_subregion(system_memory, 22756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].base, 22856f6e31eSBin Meng e51_dtim_mem); 22956f6e31eSBin Meng 23056f6e31eSBin Meng /* Bus Error Units */ 23156f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 23256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 23356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 23456f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 23556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 23656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 23756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 23856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 23956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 24056f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 24156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 24256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 24356f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 24456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 24556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 24656f6e31eSBin Meng 24756f6e31eSBin Meng /* CLINT */ 248b8fb878aSAnup Patel riscv_aclint_swi_create(memmap[MICROCHIP_PFSOC_CLINT].base, 249b8fb878aSAnup Patel 0, ms->smp.cpus, false); 250b8fb878aSAnup Patel riscv_aclint_mtimer_create( 251b8fb878aSAnup Patel memmap[MICROCHIP_PFSOC_CLINT].base + RISCV_ACLINT_SWI_SIZE, 252b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 0, ms->smp.cpus, 253b8fb878aSAnup Patel RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 254a47ef6e9SBin Meng CLINT_TIMEBASE_FREQ, false); 25556f6e31eSBin Meng 25656f6e31eSBin Meng /* L2 cache controller */ 25756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.l2cc", 25856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 25956f6e31eSBin Meng 26056f6e31eSBin Meng /* 26156f6e31eSBin Meng * Add L2-LIM at reset size. 26256f6e31eSBin Meng * This should be reduced in size as the L2 Cache Controller WayEnable 26356f6e31eSBin Meng * register is incremented. Unfortunately I don't see a nice (or any) way 26456f6e31eSBin Meng * to handle reducing or blocking out the L2 LIM while still allowing it 26556f6e31eSBin Meng * be re returned to all enabled after a reset. For the time being, just 26656f6e31eSBin Meng * leave it enabled all the time. This won't break anything, but will be 26756f6e31eSBin Meng * too generous to misbehaving guests. 26856f6e31eSBin Meng */ 26956f6e31eSBin Meng memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 27056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 27156f6e31eSBin Meng memory_region_add_subregion(system_memory, 27256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].base, 27356f6e31eSBin Meng l2lim_mem); 27456f6e31eSBin Meng 27556f6e31eSBin Meng /* create PLIC hart topology configuration string */ 2768486eb8cSAlistair Francis plic_hart_config = riscv_plic_hart_config_string(ms->smp.cpus); 27756f6e31eSBin Meng 27856f6e31eSBin Meng /* PLIC */ 27956f6e31eSBin Meng s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 280f436ecc3SAlistair Francis plic_hart_config, ms->smp.cpus, 0, 28156f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 28256f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 28356f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 28456f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PENDING_BASE, 28556f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 28656f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 28756f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 28856f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 28956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_PLIC].size); 29056f6e31eSBin Meng g_free(plic_hart_config); 29156f6e31eSBin Meng 2927124e27bSBin Meng /* DMA */ 2937124e27bSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 2947124e27bSBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 2957124e27bSBin Meng memmap[MICROCHIP_PFSOC_DMA].base); 2967124e27bSBin Meng for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 2977124e27bSBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 2987124e27bSBin Meng qdev_get_gpio_in(DEVICE(s->plic), 2997124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 + i)); 3007124e27bSBin Meng } 3017124e27bSBin Meng 30256f6e31eSBin Meng /* SYSREG */ 303cdd58c70SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 304cdd58c70SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 305cdd58c70SBin Meng memmap[MICROCHIP_PFSOC_SYSREG].base); 30656f6e31eSBin Meng 30725da6e31SConor Dooley /* AXISW */ 30825da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.axisw", 30925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_AXISW].base, 31025da6e31SConor Dooley memmap[MICROCHIP_PFSOC_AXISW].size); 31125da6e31SConor Dooley 31256f6e31eSBin Meng /* MPUCFG */ 31356f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.mpucfg", 31456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].base, 31556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].size); 31656f6e31eSBin Meng 31725da6e31SConor Dooley /* FMETER */ 31825da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.fmeter", 31925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FMETER].base, 32025da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FMETER].size); 32125da6e31SConor Dooley 322933f73f1SBin Meng /* DDR SGMII PHY */ 323933f73f1SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 324933f73f1SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 325933f73f1SBin Meng memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 326933f73f1SBin Meng 327933f73f1SBin Meng /* DDR CFG */ 328933f73f1SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 329933f73f1SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 330933f73f1SBin Meng memmap[MICROCHIP_PFSOC_DDR_CFG].base); 331933f73f1SBin Meng 332898dc008SBin Meng /* SDHCI */ 333898dc008SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 334898dc008SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 335898dc008SBin Meng memmap[MICROCHIP_PFSOC_EMMC_SD].base); 336898dc008SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 337898dc008SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 338898dc008SBin Meng 3398f2ac39dSBin Meng /* MMUARTs */ 3408f2ac39dSBin Meng s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 3418f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART0].base, 3428f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 3438f2ac39dSBin Meng serial_hd(0)); 3448f2ac39dSBin Meng s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 3458f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART1].base, 3468f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 3478f2ac39dSBin Meng serial_hd(1)); 3488f2ac39dSBin Meng s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 3498f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART2].base, 3508f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 3518f2ac39dSBin Meng serial_hd(2)); 3528f2ac39dSBin Meng s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 3538f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART3].base, 3548f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 3558f2ac39dSBin Meng serial_hd(3)); 3568f2ac39dSBin Meng s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 3578f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART4].base, 3588f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 3598f2ac39dSBin Meng serial_hd(4)); 3608f2ac39dSBin Meng 36125da6e31SConor Dooley /* Watchdogs */ 36225da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog0", 36325da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG0].base, 36425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG0].size); 36525da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog1", 36625da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG1].base, 36725da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG1].size); 36825da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog2", 36925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG2].base, 37025da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG2].size); 37125da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog3", 37225da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG3].base, 37325da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG3].size); 37425da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.watchdog4", 37525da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG4].base, 37625da6e31SConor Dooley memmap[MICROCHIP_PFSOC_WDOG4].size); 37725da6e31SConor Dooley 378dfc973ecSVitaly Wool /* SPI */ 379dfc973ecSVitaly Wool create_unimplemented_device("microchip.pfsoc.spi0", 380dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI0].base, 381dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI0].size); 382dfc973ecSVitaly Wool create_unimplemented_device("microchip.pfsoc.spi1", 383dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI1].base, 384dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_SPI1].size); 385dfc973ecSVitaly Wool 38625da6e31SConor Dooley /* I2C */ 38725da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.i2c0", 38825da6e31SConor Dooley memmap[MICROCHIP_PFSOC_I2C0].base, 38925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_I2C0].size); 39090742c54SBin Meng create_unimplemented_device("microchip.pfsoc.i2c1", 39190742c54SBin Meng memmap[MICROCHIP_PFSOC_I2C1].base, 39290742c54SBin Meng memmap[MICROCHIP_PFSOC_I2C1].size); 39390742c54SBin Meng 39425da6e31SConor Dooley /* CAN */ 39525da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.can0", 39625da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN0].base, 39725da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN0].size); 39825da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.can1", 39925da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN1].base, 40025da6e31SConor Dooley memmap[MICROCHIP_PFSOC_CAN1].size); 40125da6e31SConor Dooley 40225da6e31SConor Dooley /* USB */ 40325da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.usb", 40425da6e31SConor Dooley memmap[MICROCHIP_PFSOC_USB].base, 40525da6e31SConor Dooley memmap[MICROCHIP_PFSOC_USB].size); 40625da6e31SConor Dooley 40747374b07SBin Meng /* GEMs */ 40847374b07SBin Meng 40947374b07SBin Meng nd = &nd_table[0]; 41047374b07SBin Meng if (nd->used) { 41147374b07SBin Meng qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 41247374b07SBin Meng qdev_set_nic_properties(DEVICE(&s->gem0), nd); 41347374b07SBin Meng } 41447374b07SBin Meng nd = &nd_table[1]; 41547374b07SBin Meng if (nd->used) { 41647374b07SBin Meng qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 41747374b07SBin Meng qdev_set_nic_properties(DEVICE(&s->gem1), nd); 41847374b07SBin Meng } 41947374b07SBin Meng 42047374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 42147374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 42247374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 42347374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 42447374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM0].base); 42547374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 42647374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 42747374b07SBin Meng 42847374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 42947374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 43047374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 43147374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 43247374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM1].base); 43347374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 43447374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 43547374b07SBin Meng 436ce908a2fSBin Meng /* GPIOs */ 437ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio0", 438ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].base, 439ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].size); 440ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio1", 441ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].base, 442ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].size); 443ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio2", 444ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].base, 445ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].size); 446ce908a2fSBin Meng 44756f6e31eSBin Meng /* eNVM */ 44856f6e31eSBin Meng memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 44956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 45056f6e31eSBin Meng &error_fatal); 45156f6e31eSBin Meng memory_region_add_subregion(system_memory, 45256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 45356f6e31eSBin Meng envm_data); 45456f6e31eSBin Meng 455e35d6179SBin Meng /* IOSCB */ 456e35d6179SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 457e35d6179SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 458e35d6179SBin Meng memmap[MICROCHIP_PFSOC_IOSCB].base); 459dfc973ecSVitaly Wool 46025da6e31SConor Dooley /* FPGA Fabric */ 46125da6e31SConor Dooley create_unimplemented_device("microchip.pfsoc.fabricfic3", 46225da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC3].base, 46325da6e31SConor Dooley memmap[MICROCHIP_PFSOC_FABRIC_FIC3].size); 464d6150aceSBin Meng 465dfc973ecSVitaly Wool /* QSPI Flash */ 466dfc973ecSVitaly Wool memory_region_init_rom(qspi_xip_mem, OBJECT(dev), 467dfc973ecSVitaly Wool "microchip.pfsoc.qspi_xip", 468dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_QSPI_XIP].size, 469dfc973ecSVitaly Wool &error_fatal); 470dfc973ecSVitaly Wool memory_region_add_subregion(system_memory, 471dfc973ecSVitaly Wool memmap[MICROCHIP_PFSOC_QSPI_XIP].base, 472dfc973ecSVitaly Wool qspi_xip_mem); 47356f6e31eSBin Meng } 47456f6e31eSBin Meng 47556f6e31eSBin Meng static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 47656f6e31eSBin Meng { 47756f6e31eSBin Meng DeviceClass *dc = DEVICE_CLASS(oc); 47856f6e31eSBin Meng 47956f6e31eSBin Meng dc->realize = microchip_pfsoc_soc_realize; 48056f6e31eSBin Meng /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 48156f6e31eSBin Meng dc->user_creatable = false; 48256f6e31eSBin Meng } 48356f6e31eSBin Meng 48456f6e31eSBin Meng static const TypeInfo microchip_pfsoc_soc_type_info = { 48556f6e31eSBin Meng .name = TYPE_MICROCHIP_PFSOC, 48656f6e31eSBin Meng .parent = TYPE_DEVICE, 48756f6e31eSBin Meng .instance_size = sizeof(MicrochipPFSoCState), 48856f6e31eSBin Meng .instance_init = microchip_pfsoc_soc_instance_init, 48956f6e31eSBin Meng .class_init = microchip_pfsoc_soc_class_init, 49056f6e31eSBin Meng }; 49156f6e31eSBin Meng 49256f6e31eSBin Meng static void microchip_pfsoc_soc_register_types(void) 49356f6e31eSBin Meng { 49456f6e31eSBin Meng type_register_static(µchip_pfsoc_soc_type_info); 49556f6e31eSBin Meng } 49656f6e31eSBin Meng 49756f6e31eSBin Meng type_init(microchip_pfsoc_soc_register_types) 49856f6e31eSBin Meng 49956f6e31eSBin Meng static void microchip_icicle_kit_machine_init(MachineState *machine) 50056f6e31eSBin Meng { 50156f6e31eSBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine); 50273261285SBin Meng const MemMapEntry *memmap = microchip_pfsoc_memmap; 50356f6e31eSBin Meng MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 50456f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 505f03100d7SBin Meng MemoryRegion *mem_low = g_new(MemoryRegion, 1); 506f03100d7SBin Meng MemoryRegion *mem_low_alias = g_new(MemoryRegion, 1); 507f03100d7SBin Meng MemoryRegion *mem_high = g_new(MemoryRegion, 1); 508f03100d7SBin Meng MemoryRegion *mem_high_alias = g_new(MemoryRegion, 1); 509d4c624f4SBin Meng uint64_t mem_low_size, mem_high_size; 510143897b5SBin Meng hwaddr firmware_load_addr; 511143897b5SBin Meng const char *firmware_name; 512143897b5SBin Meng bool kernel_as_payload = false; 513143897b5SBin Meng target_ulong firmware_end_addr, kernel_start_addr; 514143897b5SBin Meng uint64_t kernel_entry; 515143897b5SBin Meng uint32_t fdt_load_addr; 51664eaa820SMarkus Armbruster DriveInfo *dinfo = drive_get(IF_SD, 0, 0); 51756f6e31eSBin Meng 51856f6e31eSBin Meng /* Sanity check on RAM size */ 51956f6e31eSBin Meng if (machine->ram_size < mc->default_ram_size) { 52056f6e31eSBin Meng char *sz = size_to_str(mc->default_ram_size); 52156f6e31eSBin Meng error_report("Invalid RAM size, should be bigger than %s", sz); 52256f6e31eSBin Meng g_free(sz); 52356f6e31eSBin Meng exit(EXIT_FAILURE); 52456f6e31eSBin Meng } 52556f6e31eSBin Meng 52656f6e31eSBin Meng /* Initialize SoC */ 52756f6e31eSBin Meng object_initialize_child(OBJECT(machine), "soc", &s->soc, 52856f6e31eSBin Meng TYPE_MICROCHIP_PFSOC); 5298f972e5bSAlistair Francis qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); 53056f6e31eSBin Meng 531d4c624f4SBin Meng /* Split RAM into low and high regions using aliases to machine->ram */ 532d4c624f4SBin Meng mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; 533d4c624f4SBin Meng mem_high_size = machine->ram_size - mem_low_size; 534d4c624f4SBin Meng memory_region_init_alias(mem_low, NULL, 535d4c624f4SBin Meng "microchip.icicle.kit.ram_low", machine->ram, 536d4c624f4SBin Meng 0, mem_low_size); 537d4c624f4SBin Meng memory_region_init_alias(mem_high, NULL, 538d4c624f4SBin Meng "microchip.icicle.kit.ram_high", machine->ram, 539d4c624f4SBin Meng mem_low_size, mem_high_size); 540d4c624f4SBin Meng 54156f6e31eSBin Meng /* Register RAM */ 54256f6e31eSBin Meng memory_region_add_subregion(system_memory, 543f03100d7SBin Meng memmap[MICROCHIP_PFSOC_DRAM_LO].base, 544f03100d7SBin Meng mem_low); 545f03100d7SBin Meng memory_region_add_subregion(system_memory, 546d4c624f4SBin Meng memmap[MICROCHIP_PFSOC_DRAM_HI].base, 547d4c624f4SBin Meng mem_high); 548d4c624f4SBin Meng 549d4c624f4SBin Meng /* Create aliases for the low and high RAM regions */ 550d4c624f4SBin Meng memory_region_init_alias(mem_low_alias, NULL, 551d4c624f4SBin Meng "microchip.icicle.kit.ram_low.alias", 552d4c624f4SBin Meng mem_low, 0, mem_low_size); 553d4c624f4SBin Meng memory_region_add_subregion(system_memory, 554f03100d7SBin Meng memmap[MICROCHIP_PFSOC_DRAM_LO_ALIAS].base, 555f03100d7SBin Meng mem_low_alias); 556f03100d7SBin Meng memory_region_init_alias(mem_high_alias, NULL, 557f03100d7SBin Meng "microchip.icicle.kit.ram_high.alias", 558f03100d7SBin Meng mem_high, 0, mem_high_size); 559f03100d7SBin Meng memory_region_add_subregion(system_memory, 560f03100d7SBin Meng memmap[MICROCHIP_PFSOC_DRAM_HI_ALIAS].base, 561f03100d7SBin Meng mem_high_alias); 56256f6e31eSBin Meng 563898dc008SBin Meng /* Attach an SD card */ 564898dc008SBin Meng if (dinfo) { 565898dc008SBin Meng CadenceSDHCIState *sdhci = &(s->soc.sdhci); 566898dc008SBin Meng DeviceState *card = qdev_new(TYPE_SD_CARD); 567898dc008SBin Meng 568898dc008SBin Meng qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 569898dc008SBin Meng &error_fatal); 570898dc008SBin Meng qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 571898dc008SBin Meng } 572143897b5SBin Meng 573143897b5SBin Meng /* 574143897b5SBin Meng * We follow the following table to select which payload we execute. 575143897b5SBin Meng * 576143897b5SBin Meng * -bios | -kernel | payload 577143897b5SBin Meng * -------+------------+-------- 578143897b5SBin Meng * N | N | HSS 579143897b5SBin Meng * Y | don't care | HSS 580143897b5SBin Meng * N | Y | kernel 581143897b5SBin Meng * 582143897b5SBin Meng * This ensures backwards compatibility with how we used to expose -bios 583143897b5SBin Meng * to users but allows them to run through direct kernel booting as well. 584143897b5SBin Meng * 585143897b5SBin Meng * When -kernel is used for direct boot, -dtb must be present to provide 586143897b5SBin Meng * a valid device tree for the board, as we don't generate device tree. 587143897b5SBin Meng */ 588143897b5SBin Meng 589143897b5SBin Meng if (machine->kernel_filename && machine->dtb) { 590143897b5SBin Meng int fdt_size; 591143897b5SBin Meng machine->fdt = load_device_tree(machine->dtb, &fdt_size); 592143897b5SBin Meng if (!machine->fdt) { 593143897b5SBin Meng error_report("load_device_tree() failed"); 594143897b5SBin Meng exit(1); 595143897b5SBin Meng } 596143897b5SBin Meng 597143897b5SBin Meng firmware_name = RISCV64_BIOS_BIN; 598143897b5SBin Meng firmware_load_addr = memmap[MICROCHIP_PFSOC_DRAM_LO].base; 599143897b5SBin Meng kernel_as_payload = true; 600143897b5SBin Meng } 601143897b5SBin Meng 602143897b5SBin Meng if (!kernel_as_payload) { 603143897b5SBin Meng firmware_name = BIOS_FILENAME; 604143897b5SBin Meng firmware_load_addr = RESET_VECTOR; 605143897b5SBin Meng } 606143897b5SBin Meng 607143897b5SBin Meng /* Load the firmware */ 608143897b5SBin Meng firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, 609143897b5SBin Meng firmware_load_addr, NULL); 610143897b5SBin Meng 611143897b5SBin Meng if (kernel_as_payload) { 612143897b5SBin Meng kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, 613143897b5SBin Meng firmware_end_addr); 614143897b5SBin Meng 615143897b5SBin Meng kernel_entry = riscv_load_kernel(machine->kernel_filename, 616143897b5SBin Meng kernel_start_addr, NULL); 617143897b5SBin Meng 618143897b5SBin Meng if (machine->initrd_filename) { 619143897b5SBin Meng hwaddr start; 620143897b5SBin Meng hwaddr end = riscv_load_initrd(machine->initrd_filename, 621143897b5SBin Meng machine->ram_size, kernel_entry, 622143897b5SBin Meng &start); 623143897b5SBin Meng qemu_fdt_setprop_cell(machine->fdt, "/chosen", 624143897b5SBin Meng "linux,initrd-start", start); 625143897b5SBin Meng qemu_fdt_setprop_cell(machine->fdt, "/chosen", 626143897b5SBin Meng "linux,initrd-end", end); 627143897b5SBin Meng } 628143897b5SBin Meng 62958303fc0SBin Meng if (machine->kernel_cmdline && *machine->kernel_cmdline) { 630143897b5SBin Meng qemu_fdt_setprop_string(machine->fdt, "/chosen", 631143897b5SBin Meng "bootargs", machine->kernel_cmdline); 632143897b5SBin Meng } 633143897b5SBin Meng 634143897b5SBin Meng /* Compute the fdt load address in dram */ 635143897b5SBin Meng fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, 636143897b5SBin Meng machine->ram_size, machine->fdt); 637143897b5SBin Meng /* Load the reset vector */ 638143897b5SBin Meng riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, 639143897b5SBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 640143897b5SBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 6416934f15bSDaniel Henrique Barboza kernel_entry, fdt_load_addr); 642143897b5SBin Meng } 64356f6e31eSBin Meng } 64456f6e31eSBin Meng 64556f6e31eSBin Meng static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 64656f6e31eSBin Meng { 64756f6e31eSBin Meng MachineClass *mc = MACHINE_CLASS(oc); 64856f6e31eSBin Meng 64956f6e31eSBin Meng mc->desc = "Microchip PolarFire SoC Icicle Kit"; 65056f6e31eSBin Meng mc->init = microchip_icicle_kit_machine_init; 65156f6e31eSBin Meng mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 65256f6e31eSBin Meng MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 65356f6e31eSBin Meng mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 65456f6e31eSBin Meng mc->default_cpus = mc->min_cpus; 655d4c624f4SBin Meng mc->default_ram_id = "microchip.icicle.kit.ram"; 656f03100d7SBin Meng 657f03100d7SBin Meng /* 658f03100d7SBin Meng * Map 513 MiB high memory, the mimimum required high memory size, because 659f03100d7SBin Meng * HSS will do memory test against the high memory address range regardless 660f03100d7SBin Meng * of physical memory installed. 661f03100d7SBin Meng * 662f03100d7SBin Meng * See memory_tests() in mss_ddr.c in the HSS source code. 663f03100d7SBin Meng */ 664f03100d7SBin Meng mc->default_ram_size = 1537 * MiB; 66556f6e31eSBin Meng } 66656f6e31eSBin Meng 66756f6e31eSBin Meng static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 66856f6e31eSBin Meng .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 66956f6e31eSBin Meng .parent = TYPE_MACHINE, 67056f6e31eSBin Meng .class_init = microchip_icicle_kit_machine_class_init, 67156f6e31eSBin Meng .instance_size = sizeof(MicrochipIcicleKitState), 67256f6e31eSBin Meng }; 67356f6e31eSBin Meng 67456f6e31eSBin Meng static void microchip_icicle_kit_machine_init_register_types(void) 67556f6e31eSBin Meng { 67656f6e31eSBin Meng type_register_static(µchip_icicle_kit_machine_typeinfo); 67756f6e31eSBin Meng } 67856f6e31eSBin Meng 67956f6e31eSBin Meng type_init(microchip_icicle_kit_machine_init_register_types) 680