156f6e31eSBin Meng /* 256f6e31eSBin Meng * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 1056f6e31eSBin Meng * 1156f6e31eSBin Meng * 0) CLINT (Core Level Interruptor) 1256f6e31eSBin Meng * 1) PLIC (Platform Level Interrupt Controller) 1356f6e31eSBin Meng * 2) eNVM (Embedded Non-Volatile Memory) 148f2ac39dSBin Meng * 3) MMUARTs (Multi-Mode UART) 15898dc008SBin Meng * 4) Cadence eMMC/SDHC controller and an SD card connected to it 167124e27bSBin Meng * 5) SiFive Platform DMA (Direct Memory Access Controller) 1747374b07SBin Meng * 6) GEM (Gigabit Ethernet MAC Controller) 18933f73f1SBin Meng * 7) DMC (DDR Memory Controller) 19e35d6179SBin Meng * 8) IOSCB modules 2056f6e31eSBin Meng * 2156f6e31eSBin Meng * This board currently generates devicetree dynamically that indicates at least 2256f6e31eSBin Meng * two harts and up to five harts. 2356f6e31eSBin Meng * 2456f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 2556f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 2656f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 2756f6e31eSBin Meng * 2856f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 2956f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 3056f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 3156f6e31eSBin Meng * more details. 3256f6e31eSBin Meng * 3356f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 3456f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 3556f6e31eSBin Meng */ 3656f6e31eSBin Meng 3756f6e31eSBin Meng #include "qemu/osdep.h" 3856f6e31eSBin Meng #include "qemu/error-report.h" 3956f6e31eSBin Meng #include "qemu/log.h" 4056f6e31eSBin Meng #include "qemu/units.h" 4156f6e31eSBin Meng #include "qemu/cutils.h" 4256f6e31eSBin Meng #include "qapi/error.h" 4356f6e31eSBin Meng #include "hw/boards.h" 4456f6e31eSBin Meng #include "hw/irq.h" 4556f6e31eSBin Meng #include "hw/loader.h" 4656f6e31eSBin Meng #include "hw/sysbus.h" 478f2ac39dSBin Meng #include "chardev/char.h" 4856f6e31eSBin Meng #include "hw/cpu/cluster.h" 4956f6e31eSBin Meng #include "target/riscv/cpu.h" 5056f6e31eSBin Meng #include "hw/misc/unimp.h" 5156f6e31eSBin Meng #include "hw/riscv/boot.h" 5256f6e31eSBin Meng #include "hw/riscv/riscv_hart.h" 5356f6e31eSBin Meng #include "hw/riscv/microchip_pfsoc.h" 54406fafd5SBin Meng #include "hw/intc/sifive_clint.h" 5584fcf3c1SBin Meng #include "hw/intc/sifive_plic.h" 568f2ac39dSBin Meng #include "sysemu/sysemu.h" 5756f6e31eSBin Meng 5856f6e31eSBin Meng /* 5956f6e31eSBin Meng * The BIOS image used by this machine is called Hart Software Services (HSS). 6056f6e31eSBin Meng * See https://github.com/polarfire-soc/hart-software-services 6156f6e31eSBin Meng */ 6256f6e31eSBin Meng #define BIOS_FILENAME "hss.bin" 6356f6e31eSBin Meng #define RESET_VECTOR 0x20220000 6456f6e31eSBin Meng 65a47ef6e9SBin Meng /* CLINT timebase frequency */ 66a47ef6e9SBin Meng #define CLINT_TIMEBASE_FREQ 1000000 67a47ef6e9SBin Meng 6847374b07SBin Meng /* GEM version */ 6947374b07SBin Meng #define GEM_REVISION 0x0107010c 7047374b07SBin Meng 7108b86e3bSBin Meng /* 7208b86e3bSBin Meng * The complete description of the whole PolarFire SoC memory map is scattered 7308b86e3bSBin Meng * in different documents. There are several places to look at for memory maps: 7408b86e3bSBin Meng * 7508b86e3bSBin Meng * 1 Chapter 11 "MSS Memory Map", in the doc "UG0880: PolarFire SoC FPGA 7608b86e3bSBin Meng * Microprocessor Subsystem (MSS) User Guide", which can be downloaded from 7708b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/ 7808b86e3bSBin Meng * 1244570-ug0880-polarfire-soc-fpga-microprocessor-subsystem-mss-user-guide, 7908b86e3bSBin Meng * describes the whole picture of the PolarFire SoC memory map. 8008b86e3bSBin Meng * 8108b86e3bSBin Meng * 2 A zip file for PolarFire soC memory map, which can be downloaded from 8208b86e3bSBin Meng * https://www.microsemi.com/document-portal/doc_download/ 8308b86e3bSBin Meng * 1244581-polarfire-soc-register-map, contains the following 2 major parts: 8408b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/pfsoc_regmap.htm 8508b86e3bSBin Meng * describes the complete integrated peripherals memory map 8608b86e3bSBin Meng * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm 8708b86e3bSBin Meng * describes the complete IOSCB modules memory maps 8808b86e3bSBin Meng */ 8956f6e31eSBin Meng static const struct MemmapEntry { 9056f6e31eSBin Meng hwaddr base; 9156f6e31eSBin Meng hwaddr size; 9256f6e31eSBin Meng } microchip_pfsoc_memmap[] = { 93*27c22b2dSBin Meng [MICROCHIP_PFSOC_RSVD0] = { 0x0, 0x100 }, 94*27c22b2dSBin Meng [MICROCHIP_PFSOC_DEBUG] = { 0x100, 0xf00 }, 9556f6e31eSBin Meng [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 9656f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 9756f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 9856f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 9956f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 10056f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 10156f6e31eSBin Meng [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 10256f6e31eSBin Meng [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 1037124e27bSBin Meng [MICROCHIP_PFSOC_DMA] = { 0x3000000, 0x100000 }, 10456f6e31eSBin Meng [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 10556f6e31eSBin Meng [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 1068f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 10756f6e31eSBin Meng [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 10856f6e31eSBin Meng [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 109933f73f1SBin Meng [MICROCHIP_PFSOC_DDR_SGMII_PHY] = { 0x20007000, 0x1000 }, 110898dc008SBin Meng [MICROCHIP_PFSOC_EMMC_SD] = { 0x20008000, 0x1000 }, 111933f73f1SBin Meng [MICROCHIP_PFSOC_DDR_CFG] = { 0x20080000, 0x40000 }, 1128f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 1138f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 1148f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 1158f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 11647374b07SBin Meng [MICROCHIP_PFSOC_GEM0] = { 0x20110000, 0x2000 }, 11747374b07SBin Meng [MICROCHIP_PFSOC_GEM1] = { 0x20112000, 0x2000 }, 118ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO0] = { 0x20120000, 0x1000 }, 119ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO1] = { 0x20121000, 0x1000 }, 120ce908a2fSBin Meng [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, 12156f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 12256f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 123e35d6179SBin Meng [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, 12456f6e31eSBin Meng [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, 12556f6e31eSBin Meng }; 12656f6e31eSBin Meng 12756f6e31eSBin Meng static void microchip_pfsoc_soc_instance_init(Object *obj) 12856f6e31eSBin Meng { 12956f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 13056f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 13156f6e31eSBin Meng 13256f6e31eSBin Meng object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 13356f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 13456f6e31eSBin Meng 13556f6e31eSBin Meng object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 13656f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 13756f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 13856f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 13956f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 14056f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_E51); 14156f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 14256f6e31eSBin Meng 14356f6e31eSBin Meng object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 14456f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 14556f6e31eSBin Meng 14656f6e31eSBin Meng object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 14756f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 14856f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 14956f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 15056f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 15156f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_U54); 15256f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 153898dc008SBin Meng 1547124e27bSBin Meng object_initialize_child(obj, "dma-controller", &s->dma, 1557124e27bSBin Meng TYPE_SIFIVE_PDMA); 1567124e27bSBin Meng 157cdd58c70SBin Meng object_initialize_child(obj, "sysreg", &s->sysreg, 158cdd58c70SBin Meng TYPE_MCHP_PFSOC_SYSREG); 159cdd58c70SBin Meng 160933f73f1SBin Meng object_initialize_child(obj, "ddr-sgmii-phy", &s->ddr_sgmii_phy, 161933f73f1SBin Meng TYPE_MCHP_PFSOC_DDR_SGMII_PHY); 162933f73f1SBin Meng object_initialize_child(obj, "ddr-cfg", &s->ddr_cfg, 163933f73f1SBin Meng TYPE_MCHP_PFSOC_DDR_CFG); 164933f73f1SBin Meng 16547374b07SBin Meng object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); 16647374b07SBin Meng object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); 16747374b07SBin Meng 168898dc008SBin Meng object_initialize_child(obj, "sd-controller", &s->sdhci, 169898dc008SBin Meng TYPE_CADENCE_SDHCI); 170e35d6179SBin Meng 171e35d6179SBin Meng object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); 17256f6e31eSBin Meng } 17356f6e31eSBin Meng 17456f6e31eSBin Meng static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 17556f6e31eSBin Meng { 17656f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 17756f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 17856f6e31eSBin Meng const struct MemmapEntry *memmap = microchip_pfsoc_memmap; 17956f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 180*27c22b2dSBin Meng MemoryRegion *rsvd0_mem = g_new(MemoryRegion, 1); 18156f6e31eSBin Meng MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 18256f6e31eSBin Meng MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 18356f6e31eSBin Meng MemoryRegion *envm_data = g_new(MemoryRegion, 1); 18456f6e31eSBin Meng char *plic_hart_config; 18556f6e31eSBin Meng size_t plic_hart_config_len; 18647374b07SBin Meng NICInfo *nd; 18756f6e31eSBin Meng int i; 18856f6e31eSBin Meng 18956f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 19056f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 19156f6e31eSBin Meng /* 19256f6e31eSBin Meng * The cluster must be realized after the RISC-V hart array container, 19356f6e31eSBin Meng * as the container's CPU object is only created on realize, and the 19456f6e31eSBin Meng * CPU must exist and have been parented into the cluster before the 19556f6e31eSBin Meng * cluster is realized. 19656f6e31eSBin Meng */ 19756f6e31eSBin Meng qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 19856f6e31eSBin Meng qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 19956f6e31eSBin Meng 200*27c22b2dSBin Meng /* Reserved Memory at address 0 */ 201*27c22b2dSBin Meng memory_region_init_ram(rsvd0_mem, NULL, "microchip.pfsoc.rsvd0_mem", 202*27c22b2dSBin Meng memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); 203*27c22b2dSBin Meng memory_region_add_subregion(system_memory, 204*27c22b2dSBin Meng memmap[MICROCHIP_PFSOC_RSVD0].base, 205*27c22b2dSBin Meng rsvd0_mem); 206*27c22b2dSBin Meng 20756f6e31eSBin Meng /* E51 DTIM */ 20856f6e31eSBin Meng memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 20956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 21056f6e31eSBin Meng memory_region_add_subregion(system_memory, 21156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].base, 21256f6e31eSBin Meng e51_dtim_mem); 21356f6e31eSBin Meng 21456f6e31eSBin Meng /* Bus Error Units */ 21556f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 21656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 21756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 21856f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 21956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 22056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 22156f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 22256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 22356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 22456f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 22556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 22656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 22756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 22856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 22956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 23056f6e31eSBin Meng 23156f6e31eSBin Meng /* CLINT */ 23256f6e31eSBin Meng sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, 23356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, 234a47ef6e9SBin Meng SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 235a47ef6e9SBin Meng CLINT_TIMEBASE_FREQ, false); 23656f6e31eSBin Meng 23756f6e31eSBin Meng /* L2 cache controller */ 23856f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.l2cc", 23956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 24056f6e31eSBin Meng 24156f6e31eSBin Meng /* 24256f6e31eSBin Meng * Add L2-LIM at reset size. 24356f6e31eSBin Meng * This should be reduced in size as the L2 Cache Controller WayEnable 24456f6e31eSBin Meng * register is incremented. Unfortunately I don't see a nice (or any) way 24556f6e31eSBin Meng * to handle reducing or blocking out the L2 LIM while still allowing it 24656f6e31eSBin Meng * be re returned to all enabled after a reset. For the time being, just 24756f6e31eSBin Meng * leave it enabled all the time. This won't break anything, but will be 24856f6e31eSBin Meng * too generous to misbehaving guests. 24956f6e31eSBin Meng */ 25056f6e31eSBin Meng memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 25156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 25256f6e31eSBin Meng memory_region_add_subregion(system_memory, 25356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].base, 25456f6e31eSBin Meng l2lim_mem); 25556f6e31eSBin Meng 25656f6e31eSBin Meng /* create PLIC hart topology configuration string */ 25756f6e31eSBin Meng plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * 25856f6e31eSBin Meng ms->smp.cpus; 25956f6e31eSBin Meng plic_hart_config = g_malloc0(plic_hart_config_len); 26056f6e31eSBin Meng for (i = 0; i < ms->smp.cpus; i++) { 26156f6e31eSBin Meng if (i != 0) { 26256f6e31eSBin Meng strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, 26356f6e31eSBin Meng plic_hart_config_len); 26456f6e31eSBin Meng } else { 26556f6e31eSBin Meng strncat(plic_hart_config, "M", plic_hart_config_len); 26656f6e31eSBin Meng } 26756f6e31eSBin Meng plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); 26856f6e31eSBin Meng } 26956f6e31eSBin Meng 27056f6e31eSBin Meng /* PLIC */ 27156f6e31eSBin Meng s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 27256f6e31eSBin Meng plic_hart_config, 0, 27356f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 27456f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 27556f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 27656f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PENDING_BASE, 27756f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 27856f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 27956f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 28056f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 28156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_PLIC].size); 28256f6e31eSBin Meng g_free(plic_hart_config); 28356f6e31eSBin Meng 2847124e27bSBin Meng /* DMA */ 2857124e27bSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); 2867124e27bSBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, 2877124e27bSBin Meng memmap[MICROCHIP_PFSOC_DMA].base); 2887124e27bSBin Meng for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { 2897124e27bSBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, 2907124e27bSBin Meng qdev_get_gpio_in(DEVICE(s->plic), 2917124e27bSBin Meng MICROCHIP_PFSOC_DMA_IRQ0 + i)); 2927124e27bSBin Meng } 2937124e27bSBin Meng 29456f6e31eSBin Meng /* SYSREG */ 295cdd58c70SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sysreg), errp); 296cdd58c70SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysreg), 0, 297cdd58c70SBin Meng memmap[MICROCHIP_PFSOC_SYSREG].base); 29856f6e31eSBin Meng 29956f6e31eSBin Meng /* MPUCFG */ 30056f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.mpucfg", 30156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].base, 30256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].size); 30356f6e31eSBin Meng 304933f73f1SBin Meng /* DDR SGMII PHY */ 305933f73f1SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), errp); 306933f73f1SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_sgmii_phy), 0, 307933f73f1SBin Meng memmap[MICROCHIP_PFSOC_DDR_SGMII_PHY].base); 308933f73f1SBin Meng 309933f73f1SBin Meng /* DDR CFG */ 310933f73f1SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ddr_cfg), errp); 311933f73f1SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ddr_cfg), 0, 312933f73f1SBin Meng memmap[MICROCHIP_PFSOC_DDR_CFG].base); 313933f73f1SBin Meng 314898dc008SBin Meng /* SDHCI */ 315898dc008SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); 316898dc008SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, 317898dc008SBin Meng memmap[MICROCHIP_PFSOC_EMMC_SD].base); 318898dc008SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, 319898dc008SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); 320898dc008SBin Meng 3218f2ac39dSBin Meng /* MMUARTs */ 3228f2ac39dSBin Meng s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 3238f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART0].base, 3248f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 3258f2ac39dSBin Meng serial_hd(0)); 3268f2ac39dSBin Meng s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 3278f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART1].base, 3288f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 3298f2ac39dSBin Meng serial_hd(1)); 3308f2ac39dSBin Meng s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 3318f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART2].base, 3328f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 3338f2ac39dSBin Meng serial_hd(2)); 3348f2ac39dSBin Meng s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 3358f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART3].base, 3368f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 3378f2ac39dSBin Meng serial_hd(3)); 3388f2ac39dSBin Meng s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 3398f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART4].base, 3408f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 3418f2ac39dSBin Meng serial_hd(4)); 3428f2ac39dSBin Meng 34347374b07SBin Meng /* GEMs */ 34447374b07SBin Meng 34547374b07SBin Meng nd = &nd_table[0]; 34647374b07SBin Meng if (nd->used) { 34747374b07SBin Meng qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 34847374b07SBin Meng qdev_set_nic_properties(DEVICE(&s->gem0), nd); 34947374b07SBin Meng } 35047374b07SBin Meng nd = &nd_table[1]; 35147374b07SBin Meng if (nd->used) { 35247374b07SBin Meng qemu_check_nic_model(nd, TYPE_CADENCE_GEM); 35347374b07SBin Meng qdev_set_nic_properties(DEVICE(&s->gem1), nd); 35447374b07SBin Meng } 35547374b07SBin Meng 35647374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, errp); 35747374b07SBin Meng object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); 35847374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); 35947374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, 36047374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM0].base); 36147374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, 36247374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); 36347374b07SBin Meng 36447374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, errp); 36547374b07SBin Meng object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); 36647374b07SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); 36747374b07SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, 36847374b07SBin Meng memmap[MICROCHIP_PFSOC_GEM1].base); 36947374b07SBin Meng sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, 37047374b07SBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); 37147374b07SBin Meng 372ce908a2fSBin Meng /* GPIOs */ 373ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio0", 374ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].base, 375ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO0].size); 376ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio1", 377ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].base, 378ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO1].size); 379ce908a2fSBin Meng create_unimplemented_device("microchip.pfsoc.gpio2", 380ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].base, 381ce908a2fSBin Meng memmap[MICROCHIP_PFSOC_GPIO2].size); 382ce908a2fSBin Meng 38356f6e31eSBin Meng /* eNVM */ 38456f6e31eSBin Meng memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 38556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 38656f6e31eSBin Meng &error_fatal); 38756f6e31eSBin Meng memory_region_add_subregion(system_memory, 38856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 38956f6e31eSBin Meng envm_data); 39056f6e31eSBin Meng 391e35d6179SBin Meng /* IOSCB */ 392e35d6179SBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); 393e35d6179SBin Meng sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, 394e35d6179SBin Meng memmap[MICROCHIP_PFSOC_IOSCB].base); 39556f6e31eSBin Meng } 39656f6e31eSBin Meng 39756f6e31eSBin Meng static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 39856f6e31eSBin Meng { 39956f6e31eSBin Meng DeviceClass *dc = DEVICE_CLASS(oc); 40056f6e31eSBin Meng 40156f6e31eSBin Meng dc->realize = microchip_pfsoc_soc_realize; 40256f6e31eSBin Meng /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 40356f6e31eSBin Meng dc->user_creatable = false; 40456f6e31eSBin Meng } 40556f6e31eSBin Meng 40656f6e31eSBin Meng static const TypeInfo microchip_pfsoc_soc_type_info = { 40756f6e31eSBin Meng .name = TYPE_MICROCHIP_PFSOC, 40856f6e31eSBin Meng .parent = TYPE_DEVICE, 40956f6e31eSBin Meng .instance_size = sizeof(MicrochipPFSoCState), 41056f6e31eSBin Meng .instance_init = microchip_pfsoc_soc_instance_init, 41156f6e31eSBin Meng .class_init = microchip_pfsoc_soc_class_init, 41256f6e31eSBin Meng }; 41356f6e31eSBin Meng 41456f6e31eSBin Meng static void microchip_pfsoc_soc_register_types(void) 41556f6e31eSBin Meng { 41656f6e31eSBin Meng type_register_static(µchip_pfsoc_soc_type_info); 41756f6e31eSBin Meng } 41856f6e31eSBin Meng 41956f6e31eSBin Meng type_init(microchip_pfsoc_soc_register_types) 42056f6e31eSBin Meng 42156f6e31eSBin Meng static void microchip_icicle_kit_machine_init(MachineState *machine) 42256f6e31eSBin Meng { 42356f6e31eSBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine); 42456f6e31eSBin Meng const struct MemmapEntry *memmap = microchip_pfsoc_memmap; 42556f6e31eSBin Meng MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 42656f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 42756f6e31eSBin Meng MemoryRegion *main_mem = g_new(MemoryRegion, 1); 428898dc008SBin Meng DriveInfo *dinfo = drive_get_next(IF_SD); 42956f6e31eSBin Meng 43056f6e31eSBin Meng /* Sanity check on RAM size */ 43156f6e31eSBin Meng if (machine->ram_size < mc->default_ram_size) { 43256f6e31eSBin Meng char *sz = size_to_str(mc->default_ram_size); 43356f6e31eSBin Meng error_report("Invalid RAM size, should be bigger than %s", sz); 43456f6e31eSBin Meng g_free(sz); 43556f6e31eSBin Meng exit(EXIT_FAILURE); 43656f6e31eSBin Meng } 43756f6e31eSBin Meng 43856f6e31eSBin Meng /* Initialize SoC */ 43956f6e31eSBin Meng object_initialize_child(OBJECT(machine), "soc", &s->soc, 44056f6e31eSBin Meng TYPE_MICROCHIP_PFSOC); 44156f6e31eSBin Meng qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 44256f6e31eSBin Meng 44356f6e31eSBin Meng /* Register RAM */ 44456f6e31eSBin Meng memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", 44556f6e31eSBin Meng machine->ram_size, &error_fatal); 44656f6e31eSBin Meng memory_region_add_subregion(system_memory, 44756f6e31eSBin Meng memmap[MICROCHIP_PFSOC_DRAM].base, main_mem); 44856f6e31eSBin Meng 44956f6e31eSBin Meng /* Load the firmware */ 45056f6e31eSBin Meng riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); 451898dc008SBin Meng 452898dc008SBin Meng /* Attach an SD card */ 453898dc008SBin Meng if (dinfo) { 454898dc008SBin Meng CadenceSDHCIState *sdhci = &(s->soc.sdhci); 455898dc008SBin Meng DeviceState *card = qdev_new(TYPE_SD_CARD); 456898dc008SBin Meng 457898dc008SBin Meng qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), 458898dc008SBin Meng &error_fatal); 459898dc008SBin Meng qdev_realize_and_unref(card, sdhci->bus, &error_fatal); 460898dc008SBin Meng } 46156f6e31eSBin Meng } 46256f6e31eSBin Meng 46356f6e31eSBin Meng static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 46456f6e31eSBin Meng { 46556f6e31eSBin Meng MachineClass *mc = MACHINE_CLASS(oc); 46656f6e31eSBin Meng 46756f6e31eSBin Meng mc->desc = "Microchip PolarFire SoC Icicle Kit"; 46856f6e31eSBin Meng mc->init = microchip_icicle_kit_machine_init; 46956f6e31eSBin Meng mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 47056f6e31eSBin Meng MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 47156f6e31eSBin Meng mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 47256f6e31eSBin Meng mc->default_cpus = mc->min_cpus; 47356f6e31eSBin Meng mc->default_ram_size = 1 * GiB; 47456f6e31eSBin Meng } 47556f6e31eSBin Meng 47656f6e31eSBin Meng static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 47756f6e31eSBin Meng .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 47856f6e31eSBin Meng .parent = TYPE_MACHINE, 47956f6e31eSBin Meng .class_init = microchip_icicle_kit_machine_class_init, 48056f6e31eSBin Meng .instance_size = sizeof(MicrochipIcicleKitState), 48156f6e31eSBin Meng }; 48256f6e31eSBin Meng 48356f6e31eSBin Meng static void microchip_icicle_kit_machine_init_register_types(void) 48456f6e31eSBin Meng { 48556f6e31eSBin Meng type_register_static(µchip_icicle_kit_machine_typeinfo); 48656f6e31eSBin Meng } 48756f6e31eSBin Meng 48856f6e31eSBin Meng type_init(microchip_icicle_kit_machine_init_register_types) 489