156f6e31eSBin Meng /* 256f6e31eSBin Meng * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit 356f6e31eSBin Meng * 456f6e31eSBin Meng * Copyright (c) 2020 Wind River Systems, Inc. 556f6e31eSBin Meng * 656f6e31eSBin Meng * Author: 756f6e31eSBin Meng * Bin Meng <bin.meng@windriver.com> 856f6e31eSBin Meng * 956f6e31eSBin Meng * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit 1056f6e31eSBin Meng * 1156f6e31eSBin Meng * 0) CLINT (Core Level Interruptor) 1256f6e31eSBin Meng * 1) PLIC (Platform Level Interrupt Controller) 1356f6e31eSBin Meng * 2) eNVM (Embedded Non-Volatile Memory) 14*8f2ac39dSBin Meng * 3) MMUARTs (Multi-Mode UART) 1556f6e31eSBin Meng * 1656f6e31eSBin Meng * This board currently generates devicetree dynamically that indicates at least 1756f6e31eSBin Meng * two harts and up to five harts. 1856f6e31eSBin Meng * 1956f6e31eSBin Meng * This program is free software; you can redistribute it and/or modify it 2056f6e31eSBin Meng * under the terms and conditions of the GNU General Public License, 2156f6e31eSBin Meng * version 2 or later, as published by the Free Software Foundation. 2256f6e31eSBin Meng * 2356f6e31eSBin Meng * This program is distributed in the hope it will be useful, but WITHOUT 2456f6e31eSBin Meng * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 2556f6e31eSBin Meng * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 2656f6e31eSBin Meng * more details. 2756f6e31eSBin Meng * 2856f6e31eSBin Meng * You should have received a copy of the GNU General Public License along with 2956f6e31eSBin Meng * this program. If not, see <http://www.gnu.org/licenses/>. 3056f6e31eSBin Meng */ 3156f6e31eSBin Meng 3256f6e31eSBin Meng #include "qemu/osdep.h" 3356f6e31eSBin Meng #include "qemu/error-report.h" 3456f6e31eSBin Meng #include "qemu/log.h" 3556f6e31eSBin Meng #include "qemu/units.h" 3656f6e31eSBin Meng #include "qemu/cutils.h" 3756f6e31eSBin Meng #include "qapi/error.h" 3856f6e31eSBin Meng #include "hw/boards.h" 3956f6e31eSBin Meng #include "hw/irq.h" 4056f6e31eSBin Meng #include "hw/loader.h" 4156f6e31eSBin Meng #include "hw/sysbus.h" 42*8f2ac39dSBin Meng #include "chardev/char.h" 4356f6e31eSBin Meng #include "hw/cpu/cluster.h" 4456f6e31eSBin Meng #include "target/riscv/cpu.h" 4556f6e31eSBin Meng #include "hw/misc/unimp.h" 4656f6e31eSBin Meng #include "hw/riscv/boot.h" 4756f6e31eSBin Meng #include "hw/riscv/riscv_hart.h" 4856f6e31eSBin Meng #include "hw/riscv/sifive_clint.h" 4956f6e31eSBin Meng #include "hw/riscv/sifive_plic.h" 5056f6e31eSBin Meng #include "hw/riscv/microchip_pfsoc.h" 51*8f2ac39dSBin Meng #include "sysemu/sysemu.h" 5256f6e31eSBin Meng 5356f6e31eSBin Meng /* 5456f6e31eSBin Meng * The BIOS image used by this machine is called Hart Software Services (HSS). 5556f6e31eSBin Meng * See https://github.com/polarfire-soc/hart-software-services 5656f6e31eSBin Meng */ 5756f6e31eSBin Meng #define BIOS_FILENAME "hss.bin" 5856f6e31eSBin Meng #define RESET_VECTOR 0x20220000 5956f6e31eSBin Meng 6056f6e31eSBin Meng static const struct MemmapEntry { 6156f6e31eSBin Meng hwaddr base; 6256f6e31eSBin Meng hwaddr size; 6356f6e31eSBin Meng } microchip_pfsoc_memmap[] = { 6456f6e31eSBin Meng [MICROCHIP_PFSOC_DEBUG] = { 0x0, 0x1000 }, 6556f6e31eSBin Meng [MICROCHIP_PFSOC_E51_DTIM] = { 0x1000000, 0x2000 }, 6656f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT0] = { 0x1700000, 0x1000 }, 6756f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT1] = { 0x1701000, 0x1000 }, 6856f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT2] = { 0x1702000, 0x1000 }, 6956f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT3] = { 0x1703000, 0x1000 }, 7056f6e31eSBin Meng [MICROCHIP_PFSOC_BUSERR_UNIT4] = { 0x1704000, 0x1000 }, 7156f6e31eSBin Meng [MICROCHIP_PFSOC_CLINT] = { 0x2000000, 0x10000 }, 7256f6e31eSBin Meng [MICROCHIP_PFSOC_L2CC] = { 0x2010000, 0x1000 }, 7356f6e31eSBin Meng [MICROCHIP_PFSOC_L2LIM] = { 0x8000000, 0x2000000 }, 7456f6e31eSBin Meng [MICROCHIP_PFSOC_PLIC] = { 0xc000000, 0x4000000 }, 75*8f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART0] = { 0x20000000, 0x1000 }, 7656f6e31eSBin Meng [MICROCHIP_PFSOC_SYSREG] = { 0x20002000, 0x2000 }, 7756f6e31eSBin Meng [MICROCHIP_PFSOC_MPUCFG] = { 0x20005000, 0x1000 }, 78*8f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART1] = { 0x20100000, 0x1000 }, 79*8f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART2] = { 0x20102000, 0x1000 }, 80*8f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART3] = { 0x20104000, 0x1000 }, 81*8f2ac39dSBin Meng [MICROCHIP_PFSOC_MMUART4] = { 0x20106000, 0x1000 }, 8256f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, 8356f6e31eSBin Meng [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, 8456f6e31eSBin Meng [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, 8556f6e31eSBin Meng [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, 8656f6e31eSBin Meng }; 8756f6e31eSBin Meng 8856f6e31eSBin Meng static void microchip_pfsoc_soc_instance_init(Object *obj) 8956f6e31eSBin Meng { 9056f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 9156f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(obj); 9256f6e31eSBin Meng 9356f6e31eSBin Meng object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUSTER); 9456f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); 9556f6e31eSBin Meng 9656f6e31eSBin Meng object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, 9756f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 9856f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); 9956f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); 10056f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 10156f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_E51); 10256f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); 10356f6e31eSBin Meng 10456f6e31eSBin Meng object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); 10556f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); 10656f6e31eSBin Meng 10756f6e31eSBin Meng object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, 10856f6e31eSBin Meng TYPE_RISCV_HART_ARRAY); 10956f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); 11056f6e31eSBin Meng qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); 11156f6e31eSBin Meng qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", 11256f6e31eSBin Meng TYPE_RISCV_CPU_SIFIVE_U54); 11356f6e31eSBin Meng qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); 11456f6e31eSBin Meng } 11556f6e31eSBin Meng 11656f6e31eSBin Meng static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) 11756f6e31eSBin Meng { 11856f6e31eSBin Meng MachineState *ms = MACHINE(qdev_get_machine()); 11956f6e31eSBin Meng MicrochipPFSoCState *s = MICROCHIP_PFSOC(dev); 12056f6e31eSBin Meng const struct MemmapEntry *memmap = microchip_pfsoc_memmap; 12156f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 12256f6e31eSBin Meng MemoryRegion *e51_dtim_mem = g_new(MemoryRegion, 1); 12356f6e31eSBin Meng MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); 12456f6e31eSBin Meng MemoryRegion *envm_data = g_new(MemoryRegion, 1); 12556f6e31eSBin Meng char *plic_hart_config; 12656f6e31eSBin Meng size_t plic_hart_config_len; 12756f6e31eSBin Meng int i; 12856f6e31eSBin Meng 12956f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); 13056f6e31eSBin Meng sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); 13156f6e31eSBin Meng /* 13256f6e31eSBin Meng * The cluster must be realized after the RISC-V hart array container, 13356f6e31eSBin Meng * as the container's CPU object is only created on realize, and the 13456f6e31eSBin Meng * CPU must exist and have been parented into the cluster before the 13556f6e31eSBin Meng * cluster is realized. 13656f6e31eSBin Meng */ 13756f6e31eSBin Meng qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); 13856f6e31eSBin Meng qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); 13956f6e31eSBin Meng 14056f6e31eSBin Meng /* E51 DTIM */ 14156f6e31eSBin Meng memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_mem", 14256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); 14356f6e31eSBin Meng memory_region_add_subregion(system_memory, 14456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_E51_DTIM].base, 14556f6e31eSBin Meng e51_dtim_mem); 14656f6e31eSBin Meng 14756f6e31eSBin Meng /* Bus Error Units */ 14856f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", 14956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, 15056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); 15156f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", 15256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, 15356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); 15456f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", 15556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, 15656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); 15756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", 15856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, 15956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); 16056f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", 16156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, 16256f6e31eSBin Meng memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); 16356f6e31eSBin Meng 16456f6e31eSBin Meng /* CLINT */ 16556f6e31eSBin Meng sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, 16656f6e31eSBin Meng memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, 16756f6e31eSBin Meng SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); 16856f6e31eSBin Meng 16956f6e31eSBin Meng /* L2 cache controller */ 17056f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.l2cc", 17156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].size); 17256f6e31eSBin Meng 17356f6e31eSBin Meng /* 17456f6e31eSBin Meng * Add L2-LIM at reset size. 17556f6e31eSBin Meng * This should be reduced in size as the L2 Cache Controller WayEnable 17656f6e31eSBin Meng * register is incremented. Unfortunately I don't see a nice (or any) way 17756f6e31eSBin Meng * to handle reducing or blocking out the L2 LIM while still allowing it 17856f6e31eSBin Meng * be re returned to all enabled after a reset. For the time being, just 17956f6e31eSBin Meng * leave it enabled all the time. This won't break anything, but will be 18056f6e31eSBin Meng * too generous to misbehaving guests. 18156f6e31eSBin Meng */ 18256f6e31eSBin Meng memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", 18356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fatal); 18456f6e31eSBin Meng memory_region_add_subregion(system_memory, 18556f6e31eSBin Meng memmap[MICROCHIP_PFSOC_L2LIM].base, 18656f6e31eSBin Meng l2lim_mem); 18756f6e31eSBin Meng 18856f6e31eSBin Meng /* create PLIC hart topology configuration string */ 18956f6e31eSBin Meng plic_hart_config_len = (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1) * 19056f6e31eSBin Meng ms->smp.cpus; 19156f6e31eSBin Meng plic_hart_config = g_malloc0(plic_hart_config_len); 19256f6e31eSBin Meng for (i = 0; i < ms->smp.cpus; i++) { 19356f6e31eSBin Meng if (i != 0) { 19456f6e31eSBin Meng strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, 19556f6e31eSBin Meng plic_hart_config_len); 19656f6e31eSBin Meng } else { 19756f6e31eSBin Meng strncat(plic_hart_config, "M", plic_hart_config_len); 19856f6e31eSBin Meng } 19956f6e31eSBin Meng plic_hart_config_len -= (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1); 20056f6e31eSBin Meng } 20156f6e31eSBin Meng 20256f6e31eSBin Meng /* PLIC */ 20356f6e31eSBin Meng s->plic = sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, 20456f6e31eSBin Meng plic_hart_config, 0, 20556f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_SOURCES, 20656f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, 20756f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, 20856f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_PENDING_BASE, 20956f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_BASE, 21056f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, 21156f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, 21256f6e31eSBin Meng MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, 21356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_PLIC].size); 21456f6e31eSBin Meng g_free(plic_hart_config); 21556f6e31eSBin Meng 21656f6e31eSBin Meng /* SYSREG */ 21756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.sysreg", 21856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_SYSREG].base, 21956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_SYSREG].size); 22056f6e31eSBin Meng 22156f6e31eSBin Meng /* MPUCFG */ 22256f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.mpucfg", 22356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].base, 22456f6e31eSBin Meng memmap[MICROCHIP_PFSOC_MPUCFG].size); 22556f6e31eSBin Meng 226*8f2ac39dSBin Meng /* MMUARTs */ 227*8f2ac39dSBin Meng s->serial0 = mchp_pfsoc_mmuart_create(system_memory, 228*8f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART0].base, 229*8f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), 230*8f2ac39dSBin Meng serial_hd(0)); 231*8f2ac39dSBin Meng s->serial1 = mchp_pfsoc_mmuart_create(system_memory, 232*8f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART1].base, 233*8f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), 234*8f2ac39dSBin Meng serial_hd(1)); 235*8f2ac39dSBin Meng s->serial2 = mchp_pfsoc_mmuart_create(system_memory, 236*8f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART2].base, 237*8f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), 238*8f2ac39dSBin Meng serial_hd(2)); 239*8f2ac39dSBin Meng s->serial3 = mchp_pfsoc_mmuart_create(system_memory, 240*8f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART3].base, 241*8f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), 242*8f2ac39dSBin Meng serial_hd(3)); 243*8f2ac39dSBin Meng s->serial4 = mchp_pfsoc_mmuart_create(system_memory, 244*8f2ac39dSBin Meng memmap[MICROCHIP_PFSOC_MMUART4].base, 245*8f2ac39dSBin Meng qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), 246*8f2ac39dSBin Meng serial_hd(4)); 247*8f2ac39dSBin Meng 24856f6e31eSBin Meng /* eNVM */ 24956f6e31eSBin Meng memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.data", 25056f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].size, 25156f6e31eSBin Meng &error_fatal); 25256f6e31eSBin Meng memory_region_add_subregion(system_memory, 25356f6e31eSBin Meng memmap[MICROCHIP_PFSOC_ENVM_DATA].base, 25456f6e31eSBin Meng envm_data); 25556f6e31eSBin Meng 25656f6e31eSBin Meng /* IOSCBCFG */ 25756f6e31eSBin Meng create_unimplemented_device("microchip.pfsoc.ioscb.cfg", 25856f6e31eSBin Meng memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, 25956f6e31eSBin Meng memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); 26056f6e31eSBin Meng } 26156f6e31eSBin Meng 26256f6e31eSBin Meng static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) 26356f6e31eSBin Meng { 26456f6e31eSBin Meng DeviceClass *dc = DEVICE_CLASS(oc); 26556f6e31eSBin Meng 26656f6e31eSBin Meng dc->realize = microchip_pfsoc_soc_realize; 26756f6e31eSBin Meng /* Reason: Uses serial_hds in realize function, thus can't be used twice */ 26856f6e31eSBin Meng dc->user_creatable = false; 26956f6e31eSBin Meng } 27056f6e31eSBin Meng 27156f6e31eSBin Meng static const TypeInfo microchip_pfsoc_soc_type_info = { 27256f6e31eSBin Meng .name = TYPE_MICROCHIP_PFSOC, 27356f6e31eSBin Meng .parent = TYPE_DEVICE, 27456f6e31eSBin Meng .instance_size = sizeof(MicrochipPFSoCState), 27556f6e31eSBin Meng .instance_init = microchip_pfsoc_soc_instance_init, 27656f6e31eSBin Meng .class_init = microchip_pfsoc_soc_class_init, 27756f6e31eSBin Meng }; 27856f6e31eSBin Meng 27956f6e31eSBin Meng static void microchip_pfsoc_soc_register_types(void) 28056f6e31eSBin Meng { 28156f6e31eSBin Meng type_register_static(µchip_pfsoc_soc_type_info); 28256f6e31eSBin Meng } 28356f6e31eSBin Meng 28456f6e31eSBin Meng type_init(microchip_pfsoc_soc_register_types) 28556f6e31eSBin Meng 28656f6e31eSBin Meng static void microchip_icicle_kit_machine_init(MachineState *machine) 28756f6e31eSBin Meng { 28856f6e31eSBin Meng MachineClass *mc = MACHINE_GET_CLASS(machine); 28956f6e31eSBin Meng const struct MemmapEntry *memmap = microchip_pfsoc_memmap; 29056f6e31eSBin Meng MicrochipIcicleKitState *s = MICROCHIP_ICICLE_KIT_MACHINE(machine); 29156f6e31eSBin Meng MemoryRegion *system_memory = get_system_memory(); 29256f6e31eSBin Meng MemoryRegion *main_mem = g_new(MemoryRegion, 1); 29356f6e31eSBin Meng 29456f6e31eSBin Meng /* Sanity check on RAM size */ 29556f6e31eSBin Meng if (machine->ram_size < mc->default_ram_size) { 29656f6e31eSBin Meng char *sz = size_to_str(mc->default_ram_size); 29756f6e31eSBin Meng error_report("Invalid RAM size, should be bigger than %s", sz); 29856f6e31eSBin Meng g_free(sz); 29956f6e31eSBin Meng exit(EXIT_FAILURE); 30056f6e31eSBin Meng } 30156f6e31eSBin Meng 30256f6e31eSBin Meng /* Initialize SoC */ 30356f6e31eSBin Meng object_initialize_child(OBJECT(machine), "soc", &s->soc, 30456f6e31eSBin Meng TYPE_MICROCHIP_PFSOC); 30556f6e31eSBin Meng qdev_realize(DEVICE(&s->soc), NULL, &error_abort); 30656f6e31eSBin Meng 30756f6e31eSBin Meng /* Register RAM */ 30856f6e31eSBin Meng memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", 30956f6e31eSBin Meng machine->ram_size, &error_fatal); 31056f6e31eSBin Meng memory_region_add_subregion(system_memory, 31156f6e31eSBin Meng memmap[MICROCHIP_PFSOC_DRAM].base, main_mem); 31256f6e31eSBin Meng 31356f6e31eSBin Meng /* Load the firmware */ 31456f6e31eSBin Meng riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NULL); 31556f6e31eSBin Meng } 31656f6e31eSBin Meng 31756f6e31eSBin Meng static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void *data) 31856f6e31eSBin Meng { 31956f6e31eSBin Meng MachineClass *mc = MACHINE_CLASS(oc); 32056f6e31eSBin Meng 32156f6e31eSBin Meng mc->desc = "Microchip PolarFire SoC Icicle Kit"; 32256f6e31eSBin Meng mc->init = microchip_icicle_kit_machine_init; 32356f6e31eSBin Meng mc->max_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 32456f6e31eSBin Meng MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; 32556f6e31eSBin Meng mc->min_cpus = MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; 32656f6e31eSBin Meng mc->default_cpus = mc->min_cpus; 32756f6e31eSBin Meng mc->default_ram_size = 1 * GiB; 32856f6e31eSBin Meng } 32956f6e31eSBin Meng 33056f6e31eSBin Meng static const TypeInfo microchip_icicle_kit_machine_typeinfo = { 33156f6e31eSBin Meng .name = MACHINE_TYPE_NAME("microchip-icicle-kit"), 33256f6e31eSBin Meng .parent = TYPE_MACHINE, 33356f6e31eSBin Meng .class_init = microchip_icicle_kit_machine_class_init, 33456f6e31eSBin Meng .instance_size = sizeof(MicrochipIcicleKitState), 33556f6e31eSBin Meng }; 33656f6e31eSBin Meng 33756f6e31eSBin Meng static void microchip_icicle_kit_machine_init_register_types(void) 33856f6e31eSBin Meng { 33956f6e31eSBin Meng type_register_static(µchip_icicle_kit_machine_typeinfo); 34056f6e31eSBin Meng } 34156f6e31eSBin Meng 34256f6e31eSBin Meng type_init(microchip_icicle_kit_machine_init_register_types) 343