1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/log.h" 28 #include "qemu/error-report.h" 29 #include "qapi/error.h" 30 #include "hw/boards.h" 31 #include "hw/loader.h" 32 #include "hw/sysbus.h" 33 #include "target/riscv/cpu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/spike.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/char/riscv_htif.h" 39 #include "hw/intc/sifive_clint.h" 40 #include "chardev/char.h" 41 #include "sysemu/arch_init.h" 42 #include "sysemu/device_tree.h" 43 #include "sysemu/qtest.h" 44 #include "sysemu/sysemu.h" 45 46 static const struct MemmapEntry { 47 hwaddr base; 48 hwaddr size; 49 } spike_memmap[] = { 50 [SPIKE_MROM] = { 0x1000, 0xf000 }, 51 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 52 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 53 }; 54 55 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 56 uint64_t mem_size, const char *cmdline, bool is_32_bit) 57 { 58 void *fdt; 59 uint64_t addr, size; 60 unsigned long clint_addr; 61 int cpu, socket; 62 MachineState *mc = MACHINE(s); 63 uint32_t *clint_cells; 64 uint32_t cpu_phandle, intc_phandle, phandle = 1; 65 char *name, *mem_name, *clint_name, *clust_name; 66 char *core_name, *cpu_name, *intc_name; 67 68 fdt = s->fdt = create_device_tree(&s->fdt_size); 69 if (!fdt) { 70 error_report("create_device_tree() failed"); 71 exit(1); 72 } 73 74 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 75 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 76 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 77 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 78 79 qemu_fdt_add_subnode(fdt, "/htif"); 80 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 81 82 qemu_fdt_add_subnode(fdt, "/soc"); 83 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 84 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 85 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 86 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 87 88 qemu_fdt_add_subnode(fdt, "/cpus"); 89 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 90 SIFIVE_CLINT_TIMEBASE_FREQ); 91 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 92 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 93 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 94 95 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 96 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 97 qemu_fdt_add_subnode(fdt, clust_name); 98 99 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 100 101 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 102 cpu_phandle = phandle++; 103 104 cpu_name = g_strdup_printf("/cpus/cpu@%d", 105 s->soc[socket].hartid_base + cpu); 106 qemu_fdt_add_subnode(fdt, cpu_name); 107 if (is_32_bit) { 108 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 109 } else { 110 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 111 } 112 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 113 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 114 g_free(name); 115 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 116 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 117 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 118 s->soc[socket].hartid_base + cpu); 119 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 120 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 121 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 122 123 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 124 qemu_fdt_add_subnode(fdt, intc_name); 125 intc_phandle = phandle++; 126 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 127 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 128 "riscv,cpu-intc"); 129 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 130 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 131 132 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 133 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 134 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 135 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 136 137 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 138 qemu_fdt_add_subnode(fdt, core_name); 139 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 140 141 g_free(core_name); 142 g_free(intc_name); 143 g_free(cpu_name); 144 } 145 146 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); 147 size = riscv_socket_mem_size(mc, socket); 148 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 149 qemu_fdt_add_subnode(fdt, mem_name); 150 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 151 addr >> 32, addr, size >> 32, size); 152 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 153 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 154 g_free(mem_name); 155 156 clint_addr = memmap[SPIKE_CLINT].base + 157 (memmap[SPIKE_CLINT].size * socket); 158 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 159 qemu_fdt_add_subnode(fdt, clint_name); 160 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 161 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 162 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 163 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 164 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 165 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 166 167 g_free(clint_name); 168 g_free(clint_cells); 169 g_free(clust_name); 170 } 171 172 riscv_socket_fdt_write_distance_matrix(mc, fdt); 173 174 if (cmdline) { 175 qemu_fdt_add_subnode(fdt, "/chosen"); 176 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 177 } 178 } 179 180 static void spike_board_init(MachineState *machine) 181 { 182 const struct MemmapEntry *memmap = spike_memmap; 183 SpikeState *s = SPIKE_MACHINE(machine); 184 MemoryRegion *system_memory = get_system_memory(); 185 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 186 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 187 target_ulong firmware_end_addr, kernel_start_addr; 188 uint32_t fdt_load_addr; 189 uint64_t kernel_entry; 190 char *soc_name; 191 int i, base_hartid, hart_count; 192 193 /* Check socket count limit */ 194 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 195 error_report("number of sockets/nodes should be less than %d", 196 SPIKE_SOCKETS_MAX); 197 exit(1); 198 } 199 200 /* Initialize sockets */ 201 for (i = 0; i < riscv_socket_count(machine); i++) { 202 if (!riscv_socket_check_hartids(machine, i)) { 203 error_report("discontinuous hartids in socket%d", i); 204 exit(1); 205 } 206 207 base_hartid = riscv_socket_first_hartid(machine, i); 208 if (base_hartid < 0) { 209 error_report("can't find hartid base for socket%d", i); 210 exit(1); 211 } 212 213 hart_count = riscv_socket_hart_count(machine, i); 214 if (hart_count < 0) { 215 error_report("can't find hart count for socket%d", i); 216 exit(1); 217 } 218 219 soc_name = g_strdup_printf("soc%d", i); 220 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 221 TYPE_RISCV_HART_ARRAY); 222 g_free(soc_name); 223 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 224 machine->cpu_type, &error_abort); 225 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 226 base_hartid, &error_abort); 227 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 228 hart_count, &error_abort); 229 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 230 231 /* Core Local Interruptor (timer and IPI) for each socket */ 232 sifive_clint_create( 233 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 234 memmap[SPIKE_CLINT].size, base_hartid, hart_count, 235 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 236 SIFIVE_CLINT_TIMEBASE_FREQ, false); 237 } 238 239 /* register system main memory (actual RAM) */ 240 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 241 machine->ram_size, &error_fatal); 242 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 243 main_mem); 244 245 /* create device tree */ 246 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 247 riscv_is_32bit(&s->soc[0])); 248 249 /* boot rom */ 250 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 251 memmap[SPIKE_MROM].size, &error_fatal); 252 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 253 mask_rom); 254 255 /* 256 * Not like other RISC-V machines that use plain binary bios images, 257 * keeping ELF files here was intentional because BIN files don't work 258 * for the Spike machine as HTIF emulation depends on ELF parsing. 259 */ 260 if (riscv_is_32bit(&s->soc[0])) { 261 firmware_end_addr = riscv_find_and_load_firmware(machine, 262 "opensbi-riscv32-generic-fw_dynamic.elf", 263 memmap[SPIKE_DRAM].base, 264 htif_symbol_callback); 265 } else { 266 firmware_end_addr = riscv_find_and_load_firmware(machine, 267 "opensbi-riscv64-generic-fw_dynamic.elf", 268 memmap[SPIKE_DRAM].base, 269 htif_symbol_callback); 270 } 271 272 if (machine->kernel_filename) { 273 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 274 firmware_end_addr); 275 276 kernel_entry = riscv_load_kernel(machine->kernel_filename, 277 kernel_start_addr, 278 htif_symbol_callback); 279 280 if (machine->initrd_filename) { 281 hwaddr start; 282 hwaddr end = riscv_load_initrd(machine->initrd_filename, 283 machine->ram_size, kernel_entry, 284 &start); 285 qemu_fdt_setprop_cell(s->fdt, "/chosen", 286 "linux,initrd-start", start); 287 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 288 end); 289 } 290 } else { 291 /* 292 * If dynamic firmware is used, it doesn't know where is the next mode 293 * if kernel argument is not set. 294 */ 295 kernel_entry = 0; 296 } 297 298 /* Compute the fdt load address in dram */ 299 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, 300 machine->ram_size, s->fdt); 301 /* load the reset vector */ 302 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, 303 memmap[SPIKE_MROM].base, 304 memmap[SPIKE_MROM].size, kernel_entry, 305 fdt_load_addr, s->fdt); 306 307 /* initialize HTIF using symbols found in load_kernel */ 308 htif_mm_init(system_memory, mask_rom, 309 &s->soc[0].harts[0].env, serial_hd(0)); 310 } 311 312 static void spike_machine_instance_init(Object *obj) 313 { 314 } 315 316 static void spike_machine_class_init(ObjectClass *oc, void *data) 317 { 318 MachineClass *mc = MACHINE_CLASS(oc); 319 320 mc->desc = "RISC-V Spike board"; 321 mc->init = spike_board_init; 322 mc->max_cpus = SPIKE_CPUS_MAX; 323 mc->is_default = true; 324 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 325 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 326 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 327 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 328 mc->numa_mem_supported = true; 329 } 330 331 static const TypeInfo spike_machine_typeinfo = { 332 .name = MACHINE_TYPE_NAME("spike"), 333 .parent = TYPE_MACHINE, 334 .class_init = spike_machine_class_init, 335 .instance_init = spike_machine_instance_init, 336 .instance_size = sizeof(SpikeState), 337 }; 338 339 static void spike_machine_init_register_types(void) 340 { 341 type_register_static(&spike_machine_typeinfo); 342 } 343 344 type_init(spike_machine_init_register_types) 345