1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/error-report.h" 28 #include "qapi/error.h" 29 #include "hw/boards.h" 30 #include "hw/loader.h" 31 #include "hw/sysbus.h" 32 #include "target/riscv/cpu.h" 33 #include "hw/riscv/riscv_hart.h" 34 #include "hw/riscv/spike.h" 35 #include "hw/riscv/boot.h" 36 #include "hw/riscv/numa.h" 37 #include "hw/char/riscv_htif.h" 38 #include "hw/intc/sifive_clint.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "sysemu/sysemu.h" 43 44 static const MemMapEntry spike_memmap[] = { 45 [SPIKE_MROM] = { 0x1000, 0xf000 }, 46 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 47 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 48 }; 49 50 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 51 uint64_t mem_size, const char *cmdline, bool is_32_bit) 52 { 53 void *fdt; 54 uint64_t addr, size; 55 unsigned long clint_addr; 56 int cpu, socket; 57 MachineState *mc = MACHINE(s); 58 uint32_t *clint_cells; 59 uint32_t cpu_phandle, intc_phandle, phandle = 1; 60 char *name, *mem_name, *clint_name, *clust_name; 61 char *core_name, *cpu_name, *intc_name; 62 63 fdt = s->fdt = create_device_tree(&s->fdt_size); 64 if (!fdt) { 65 error_report("create_device_tree() failed"); 66 exit(1); 67 } 68 69 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 70 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 71 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 72 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 73 74 qemu_fdt_add_subnode(fdt, "/htif"); 75 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 76 77 qemu_fdt_add_subnode(fdt, "/soc"); 78 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 79 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 80 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 81 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 82 83 qemu_fdt_add_subnode(fdt, "/cpus"); 84 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 85 SIFIVE_CLINT_TIMEBASE_FREQ); 86 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 87 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 88 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 89 90 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 91 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 92 qemu_fdt_add_subnode(fdt, clust_name); 93 94 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 95 96 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 97 cpu_phandle = phandle++; 98 99 cpu_name = g_strdup_printf("/cpus/cpu@%d", 100 s->soc[socket].hartid_base + cpu); 101 qemu_fdt_add_subnode(fdt, cpu_name); 102 if (is_32_bit) { 103 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 104 } else { 105 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 106 } 107 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 108 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 109 g_free(name); 110 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 111 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 112 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 113 s->soc[socket].hartid_base + cpu); 114 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 115 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 116 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 117 118 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 119 qemu_fdt_add_subnode(fdt, intc_name); 120 intc_phandle = phandle++; 121 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 122 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 123 "riscv,cpu-intc"); 124 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 125 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 126 127 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 128 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 129 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 130 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 131 132 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 133 qemu_fdt_add_subnode(fdt, core_name); 134 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 135 136 g_free(core_name); 137 g_free(intc_name); 138 g_free(cpu_name); 139 } 140 141 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); 142 size = riscv_socket_mem_size(mc, socket); 143 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 144 qemu_fdt_add_subnode(fdt, mem_name); 145 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 146 addr >> 32, addr, size >> 32, size); 147 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 148 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 149 g_free(mem_name); 150 151 clint_addr = memmap[SPIKE_CLINT].base + 152 (memmap[SPIKE_CLINT].size * socket); 153 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 154 qemu_fdt_add_subnode(fdt, clint_name); 155 qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0"); 156 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 157 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); 158 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 159 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 160 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 161 162 g_free(clint_name); 163 g_free(clint_cells); 164 g_free(clust_name); 165 } 166 167 riscv_socket_fdt_write_distance_matrix(mc, fdt); 168 169 if (cmdline) { 170 qemu_fdt_add_subnode(fdt, "/chosen"); 171 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 172 } 173 } 174 175 static void spike_board_init(MachineState *machine) 176 { 177 const MemMapEntry *memmap = spike_memmap; 178 SpikeState *s = SPIKE_MACHINE(machine); 179 MemoryRegion *system_memory = get_system_memory(); 180 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 181 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 182 target_ulong firmware_end_addr, kernel_start_addr; 183 uint32_t fdt_load_addr; 184 uint64_t kernel_entry; 185 char *soc_name; 186 int i, base_hartid, hart_count; 187 188 /* Check socket count limit */ 189 if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { 190 error_report("number of sockets/nodes should be less than %d", 191 SPIKE_SOCKETS_MAX); 192 exit(1); 193 } 194 195 /* Initialize sockets */ 196 for (i = 0; i < riscv_socket_count(machine); i++) { 197 if (!riscv_socket_check_hartids(machine, i)) { 198 error_report("discontinuous hartids in socket%d", i); 199 exit(1); 200 } 201 202 base_hartid = riscv_socket_first_hartid(machine, i); 203 if (base_hartid < 0) { 204 error_report("can't find hartid base for socket%d", i); 205 exit(1); 206 } 207 208 hart_count = riscv_socket_hart_count(machine, i); 209 if (hart_count < 0) { 210 error_report("can't find hart count for socket%d", i); 211 exit(1); 212 } 213 214 soc_name = g_strdup_printf("soc%d", i); 215 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 216 TYPE_RISCV_HART_ARRAY); 217 g_free(soc_name); 218 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 219 machine->cpu_type, &error_abort); 220 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 221 base_hartid, &error_abort); 222 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 223 hart_count, &error_abort); 224 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 225 226 /* Core Local Interruptor (timer and IPI) for each socket */ 227 sifive_clint_create( 228 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, 229 memmap[SPIKE_CLINT].size, base_hartid, hart_count, 230 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 231 SIFIVE_CLINT_TIMEBASE_FREQ, false); 232 } 233 234 /* register system main memory (actual RAM) */ 235 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 236 machine->ram_size, &error_fatal); 237 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 238 main_mem); 239 240 /* create device tree */ 241 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 242 riscv_is_32bit(&s->soc[0])); 243 244 /* boot rom */ 245 memory_region_init_rom(mask_rom, NULL, "riscv.spike.mrom", 246 memmap[SPIKE_MROM].size, &error_fatal); 247 memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, 248 mask_rom); 249 250 /* 251 * Not like other RISC-V machines that use plain binary bios images, 252 * keeping ELF files here was intentional because BIN files don't work 253 * for the Spike machine as HTIF emulation depends on ELF parsing. 254 */ 255 if (riscv_is_32bit(&s->soc[0])) { 256 firmware_end_addr = riscv_find_and_load_firmware(machine, 257 "opensbi-riscv32-generic-fw_dynamic.elf", 258 memmap[SPIKE_DRAM].base, 259 htif_symbol_callback); 260 } else { 261 firmware_end_addr = riscv_find_and_load_firmware(machine, 262 "opensbi-riscv64-generic-fw_dynamic.elf", 263 memmap[SPIKE_DRAM].base, 264 htif_symbol_callback); 265 } 266 267 if (machine->kernel_filename) { 268 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 269 firmware_end_addr); 270 271 kernel_entry = riscv_load_kernel(machine->kernel_filename, 272 kernel_start_addr, 273 htif_symbol_callback); 274 275 if (machine->initrd_filename) { 276 hwaddr start; 277 hwaddr end = riscv_load_initrd(machine->initrd_filename, 278 machine->ram_size, kernel_entry, 279 &start); 280 qemu_fdt_setprop_cell(s->fdt, "/chosen", 281 "linux,initrd-start", start); 282 qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", 283 end); 284 } 285 } else { 286 /* 287 * If dynamic firmware is used, it doesn't know where is the next mode 288 * if kernel argument is not set. 289 */ 290 kernel_entry = 0; 291 } 292 293 /* Compute the fdt load address in dram */ 294 fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, 295 machine->ram_size, s->fdt); 296 /* load the reset vector */ 297 riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, 298 memmap[SPIKE_MROM].base, 299 memmap[SPIKE_MROM].size, kernel_entry, 300 fdt_load_addr, s->fdt); 301 302 /* initialize HTIF using symbols found in load_kernel */ 303 htif_mm_init(system_memory, mask_rom, 304 &s->soc[0].harts[0].env, serial_hd(0)); 305 } 306 307 static void spike_machine_instance_init(Object *obj) 308 { 309 } 310 311 static void spike_machine_class_init(ObjectClass *oc, void *data) 312 { 313 MachineClass *mc = MACHINE_CLASS(oc); 314 315 mc->desc = "RISC-V Spike board"; 316 mc->init = spike_board_init; 317 mc->max_cpus = SPIKE_CPUS_MAX; 318 mc->is_default = true; 319 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 320 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 321 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 322 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 323 mc->numa_mem_supported = true; 324 } 325 326 static const TypeInfo spike_machine_typeinfo = { 327 .name = MACHINE_TYPE_NAME("spike"), 328 .parent = TYPE_MACHINE, 329 .class_init = spike_machine_class_init, 330 .instance_init = spike_machine_instance_init, 331 .instance_size = sizeof(SpikeState), 332 }; 333 334 static void spike_machine_init_register_types(void) 335 { 336 type_register_static(&spike_machine_typeinfo); 337 } 338 339 type_init(spike_machine_init_register_types) 340