1 /* 2 * QEMU RISC-V Spike Board 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This provides a RISC-V Board with the following devices: 8 * 9 * 0) HTIF Console and Poweroff 10 * 1) CLINT (Timer and IPI) 11 * 2) PLIC (Platform Level Interrupt Controller) 12 * 13 * This program is free software; you can redistribute it and/or modify it 14 * under the terms and conditions of the GNU General Public License, 15 * version 2 or later, as published by the Free Software Foundation. 16 * 17 * This program is distributed in the hope it will be useful, but WITHOUT 18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 20 * more details. 21 * 22 * You should have received a copy of the GNU General Public License along with 23 * this program. If not, see <http://www.gnu.org/licenses/>. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "qemu/log.h" 28 #include "qemu/error-report.h" 29 #include "qapi/error.h" 30 #include "hw/hw.h" 31 #include "hw/boards.h" 32 #include "hw/loader.h" 33 #include "hw/sysbus.h" 34 #include "target/riscv/cpu.h" 35 #include "hw/riscv/riscv_htif.h" 36 #include "hw/riscv/riscv_hart.h" 37 #include "hw/riscv/sifive_clint.h" 38 #include "hw/riscv/spike.h" 39 #include "chardev/char.h" 40 #include "sysemu/arch_init.h" 41 #include "sysemu/device_tree.h" 42 #include "exec/address-spaces.h" 43 #include "elf.h" 44 45 static const struct MemmapEntry { 46 hwaddr base; 47 hwaddr size; 48 } spike_memmap[] = { 49 [SPIKE_MROM] = { 0x1000, 0x2000 }, 50 [SPIKE_CLINT] = { 0x2000000, 0x10000 }, 51 [SPIKE_DRAM] = { 0x80000000, 0x0 }, 52 }; 53 54 static void copy_le32_to_phys(hwaddr pa, uint32_t *rom, size_t len) 55 { 56 int i; 57 for (i = 0; i < (len >> 2); i++) { 58 stl_phys(&address_space_memory, pa + (i << 2), rom[i]); 59 } 60 } 61 62 static uint64_t identity_translate(void *opaque, uint64_t addr) 63 { 64 return addr; 65 } 66 67 static uint64_t load_kernel(const char *kernel_filename) 68 { 69 uint64_t kernel_entry, kernel_high; 70 71 if (load_elf_ram_sym(kernel_filename, identity_translate, NULL, 72 &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0, 73 NULL, true, htif_symbol_callback) < 0) { 74 error_report("qemu: could not load kernel '%s'", kernel_filename); 75 exit(1); 76 } 77 return kernel_entry; 78 } 79 80 static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, 81 uint64_t mem_size, const char *cmdline) 82 { 83 void *fdt; 84 int cpu; 85 uint32_t *cells; 86 char *nodename; 87 88 fdt = s->fdt = create_device_tree(&s->fdt_size); 89 if (!fdt) { 90 error_report("create_device_tree() failed"); 91 exit(1); 92 } 93 94 qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); 95 qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); 96 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 97 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 98 99 qemu_fdt_add_subnode(fdt, "/htif"); 100 qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); 101 102 qemu_fdt_add_subnode(fdt, "/soc"); 103 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 104 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "ucbbar,spike-bare-soc"); 105 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 106 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 107 108 nodename = g_strdup_printf("/memory@%lx", 109 (long)memmap[SPIKE_DRAM].base); 110 qemu_fdt_add_subnode(fdt, nodename); 111 qemu_fdt_setprop_cells(fdt, nodename, "reg", 112 memmap[SPIKE_DRAM].base >> 32, memmap[SPIKE_DRAM].base, 113 mem_size >> 32, mem_size); 114 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 115 g_free(nodename); 116 117 qemu_fdt_add_subnode(fdt, "/cpus"); 118 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 10000000); 119 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 120 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 121 122 for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) { 123 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 124 char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 125 char *isa = riscv_isa_string(&s->soc.harts[cpu]); 126 qemu_fdt_add_subnode(fdt, nodename); 127 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 1000000000); 128 qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); 129 qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); 130 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); 131 qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); 132 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 133 qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); 134 qemu_fdt_add_subnode(fdt, intc); 135 qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); 136 qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); 137 qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); 138 qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); 139 qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); 140 g_free(isa); 141 g_free(intc); 142 g_free(nodename); 143 } 144 145 cells = g_new0(uint32_t, s->soc.num_harts * 4); 146 for (cpu = 0; cpu < s->soc.num_harts; cpu++) { 147 nodename = 148 g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); 149 uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); 150 cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 151 cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 152 cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 153 cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 154 g_free(nodename); 155 } 156 nodename = g_strdup_printf("/soc/clint@%lx", 157 (long)memmap[SPIKE_CLINT].base); 158 qemu_fdt_add_subnode(fdt, nodename); 159 qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); 160 qemu_fdt_setprop_cells(fdt, nodename, "reg", 161 0x0, memmap[SPIKE_CLINT].base, 162 0x0, memmap[SPIKE_CLINT].size); 163 qemu_fdt_setprop(fdt, nodename, "interrupts-extended", 164 cells, s->soc.num_harts * sizeof(uint32_t) * 4); 165 g_free(cells); 166 g_free(nodename); 167 168 qemu_fdt_add_subnode(fdt, "/chosen"); 169 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 170 } 171 172 static void spike_v1_10_0_board_init(MachineState *machine) 173 { 174 const struct MemmapEntry *memmap = spike_memmap; 175 176 SpikeState *s = g_new0(SpikeState, 1); 177 MemoryRegion *system_memory = get_system_memory(); 178 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 179 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 180 181 /* Initialize SOC */ 182 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 183 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 184 &error_abort); 185 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_10_0_CPU, "cpu-type", 186 &error_abort); 187 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 188 &error_abort); 189 object_property_set_bool(OBJECT(&s->soc), true, "realized", 190 &error_abort); 191 192 /* register system main memory (actual RAM) */ 193 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 194 machine->ram_size, &error_fatal); 195 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 196 main_mem); 197 198 /* create device tree */ 199 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); 200 201 /* boot rom */ 202 memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", 203 s->fdt_size + 0x2000, &error_fatal); 204 memory_region_add_subregion(system_memory, 0x0, boot_rom); 205 206 if (machine->kernel_filename) { 207 load_kernel(machine->kernel_filename); 208 } 209 210 /* reset vector */ 211 uint32_t reset_vec[8] = { 212 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ 213 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ 214 0xf1402573, /* csrr a0, mhartid */ 215 #if defined(TARGET_RISCV32) 216 0x0182a283, /* lw t0, 24(t0) */ 217 #elif defined(TARGET_RISCV64) 218 0x0182b283, /* ld t0, 24(t0) */ 219 #endif 220 0x00028067, /* jr t0 */ 221 0x00000000, 222 memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ 223 0x00000000, 224 /* dtb: */ 225 }; 226 227 /* copy in the reset vector */ 228 copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec)); 229 230 /* copy in the device tree */ 231 qemu_fdt_dumpdtb(s->fdt, s->fdt_size); 232 cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), 233 s->fdt, s->fdt_size); 234 235 /* initialize HTIF using symbols found in load_kernel */ 236 htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); 237 238 /* Core Local Interruptor (timer and IPI) */ 239 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 240 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 241 } 242 243 static void spike_v1_09_1_board_init(MachineState *machine) 244 { 245 const struct MemmapEntry *memmap = spike_memmap; 246 247 SpikeState *s = g_new0(SpikeState, 1); 248 MemoryRegion *system_memory = get_system_memory(); 249 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 250 MemoryRegion *boot_rom = g_new(MemoryRegion, 1); 251 252 /* Initialize SOC */ 253 object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); 254 object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), 255 &error_abort); 256 object_property_set_str(OBJECT(&s->soc), SPIKE_V1_09_1_CPU, "cpu-type", 257 &error_abort); 258 object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", 259 &error_abort); 260 object_property_set_bool(OBJECT(&s->soc), true, "realized", 261 &error_abort); 262 263 /* register system main memory (actual RAM) */ 264 memory_region_init_ram(main_mem, NULL, "riscv.spike.ram", 265 machine->ram_size, &error_fatal); 266 memory_region_add_subregion(system_memory, memmap[SPIKE_DRAM].base, 267 main_mem); 268 269 /* boot rom */ 270 memory_region_init_ram(boot_rom, NULL, "riscv.spike.bootrom", 271 0x40000, &error_fatal); 272 memory_region_add_subregion(system_memory, 0x0, boot_rom); 273 274 if (machine->kernel_filename) { 275 load_kernel(machine->kernel_filename); 276 } 277 278 /* reset vector */ 279 uint32_t reset_vec[8] = { 280 0x297 + memmap[SPIKE_DRAM].base - memmap[SPIKE_MROM].base, /* lui */ 281 0x00028067, /* jump to DRAM_BASE */ 282 0x00000000, /* reserved */ 283 memmap[SPIKE_MROM].base + sizeof(reset_vec), /* config string pointer */ 284 0, 0, 0, 0 /* trap vector */ 285 }; 286 287 /* part one of config string - before memory size specified */ 288 const char *config_string_tmpl = 289 "platform {\n" 290 " vendor ucb;\n" 291 " arch spike;\n" 292 "};\n" 293 "rtc {\n" 294 " addr 0x%" PRIx64 "x;\n" 295 "};\n" 296 "ram {\n" 297 " 0 {\n" 298 " addr 0x%" PRIx64 "x;\n" 299 " size 0x%" PRIx64 "x;\n" 300 " };\n" 301 "};\n" 302 "core {\n" 303 " 0" " {\n" 304 " " "0 {\n" 305 " isa %s;\n" 306 " timecmp 0x%" PRIx64 "x;\n" 307 " ipi 0x%" PRIx64 "x;\n" 308 " };\n" 309 " };\n" 310 "};\n"; 311 312 /* build config string with supplied memory size */ 313 char *isa = riscv_isa_string(&s->soc.harts[0]); 314 size_t config_string_size = strlen(config_string_tmpl) + 48; 315 char *config_string = malloc(config_string_size); 316 snprintf(config_string, config_string_size, config_string_tmpl, 317 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIME_BASE, 318 (uint64_t)memmap[SPIKE_DRAM].base, 319 (uint64_t)ram_size, isa, 320 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_TIMECMP_BASE, 321 (uint64_t)memmap[SPIKE_CLINT].base + SIFIVE_SIP_BASE); 322 g_free(isa); 323 size_t config_string_len = strlen(config_string); 324 325 /* copy in the reset vector */ 326 copy_le32_to_phys(memmap[SPIKE_MROM].base, reset_vec, sizeof(reset_vec)); 327 328 /* copy in the config string */ 329 cpu_physical_memory_write(memmap[SPIKE_MROM].base + sizeof(reset_vec), 330 config_string, config_string_len); 331 332 /* initialize HTIF using symbols found in load_kernel */ 333 htif_mm_init(system_memory, boot_rom, &s->soc.harts[0].env, serial_hd(0)); 334 335 /* Core Local Interruptor (timer and IPI) */ 336 sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size, 337 smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); 338 } 339 340 static const TypeInfo spike_v_1_09_1_device = { 341 .name = TYPE_RISCV_SPIKE_V1_09_1_BOARD, 342 .parent = TYPE_SYS_BUS_DEVICE, 343 .instance_size = sizeof(SpikeState), 344 }; 345 346 static const TypeInfo spike_v_1_10_0_device = { 347 .name = TYPE_RISCV_SPIKE_V1_10_0_BOARD, 348 .parent = TYPE_SYS_BUS_DEVICE, 349 .instance_size = sizeof(SpikeState), 350 }; 351 352 static void spike_v1_09_1_machine_init(MachineClass *mc) 353 { 354 mc->desc = "RISC-V Spike Board (Privileged ISA v1.9.1)"; 355 mc->init = spike_v1_09_1_board_init; 356 mc->max_cpus = 1; 357 } 358 359 static void spike_v1_10_0_machine_init(MachineClass *mc) 360 { 361 mc->desc = "RISC-V Spike Board (Privileged ISA v1.10)"; 362 mc->init = spike_v1_10_0_board_init; 363 mc->max_cpus = 1; 364 mc->is_default = 1; 365 } 366 367 DEFINE_MACHINE("spike_v1.9.1", spike_v1_09_1_machine_init) 368 DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) 369 370 static void riscv_spike_board_register_types(void) 371 { 372 type_register_static(&spike_v_1_09_1_device); 373 type_register_static(&spike_v_1_10_0_device); 374 } 375 376 type_init(riscv_spike_board_register_types); 377