1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/core/sysbus-fdt.h" 32 #include "hw/riscv/riscv_hart.h" 33 #include "hw/riscv/virt.h" 34 #include "hw/riscv/boot.h" 35 #include "hw/riscv/numa.h" 36 #include "hw/intc/riscv_aclint.h" 37 #include "hw/intc/riscv_aplic.h" 38 #include "hw/intc/riscv_imsic.h" 39 #include "hw/intc/sifive_plic.h" 40 #include "hw/misc/sifive_test.h" 41 #include "hw/platform-bus.h" 42 #include "chardev/char.h" 43 #include "sysemu/device_tree.h" 44 #include "sysemu/sysemu.h" 45 #include "sysemu/kvm.h" 46 #include "sysemu/tpm.h" 47 #include "hw/pci/pci.h" 48 #include "hw/pci-host/gpex.h" 49 #include "hw/display/ramfb.h" 50 51 /* 52 * The virt machine physical address space used by some of the devices 53 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 54 * number of CPUs, and number of IMSIC guest files. 55 * 56 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 57 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 58 * of virt machine physical address space. 59 */ 60 61 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 62 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 63 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 64 #error "Can't accomodate single IMSIC group in address space" 65 #endif 66 67 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 68 VIRT_IMSIC_GROUP_MAX_SIZE) 69 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 70 #error "Can't accomodate all IMSIC groups in address space" 71 #endif 72 73 static const MemMapEntry virt_memmap[] = { 74 [VIRT_DEBUG] = { 0x0, 0x100 }, 75 [VIRT_MROM] = { 0x1000, 0xf000 }, 76 [VIRT_TEST] = { 0x100000, 0x1000 }, 77 [VIRT_RTC] = { 0x101000, 0x1000 }, 78 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 79 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 80 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 81 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 82 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 83 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 84 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 85 [VIRT_UART0] = { 0x10000000, 0x100 }, 86 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 87 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 88 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 89 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 90 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 91 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 92 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 93 [VIRT_DRAM] = { 0x80000000, 0x0 }, 94 }; 95 96 /* PCIe high mmio is fixed for RV32 */ 97 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 98 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 99 100 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 101 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 102 103 static MemMapEntry virt_high_pcie_memmap; 104 105 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 106 107 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 108 const char *name, 109 const char *alias_prop_name) 110 { 111 /* 112 * Create a single flash device. We use the same parameters as 113 * the flash devices on the ARM virt board. 114 */ 115 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 116 117 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 118 qdev_prop_set_uint8(dev, "width", 4); 119 qdev_prop_set_uint8(dev, "device-width", 2); 120 qdev_prop_set_bit(dev, "big-endian", false); 121 qdev_prop_set_uint16(dev, "id0", 0x89); 122 qdev_prop_set_uint16(dev, "id1", 0x18); 123 qdev_prop_set_uint16(dev, "id2", 0x00); 124 qdev_prop_set_uint16(dev, "id3", 0x00); 125 qdev_prop_set_string(dev, "name", name); 126 127 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 128 object_property_add_alias(OBJECT(s), alias_prop_name, 129 OBJECT(dev), "drive"); 130 131 return PFLASH_CFI01(dev); 132 } 133 134 static void virt_flash_create(RISCVVirtState *s) 135 { 136 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 137 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 138 } 139 140 static void virt_flash_map1(PFlashCFI01 *flash, 141 hwaddr base, hwaddr size, 142 MemoryRegion *sysmem) 143 { 144 DeviceState *dev = DEVICE(flash); 145 146 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 147 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 148 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 149 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 150 151 memory_region_add_subregion(sysmem, base, 152 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 153 0)); 154 } 155 156 static void virt_flash_map(RISCVVirtState *s, 157 MemoryRegion *sysmem) 158 { 159 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 160 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 161 162 virt_flash_map1(s->flash[0], flashbase, flashsize, 163 sysmem); 164 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 165 sysmem); 166 } 167 168 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 169 uint32_t irqchip_phandle) 170 { 171 int pin, dev; 172 uint32_t irq_map_stride = 0; 173 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 174 FDT_MAX_INT_MAP_WIDTH] = {}; 175 uint32_t *irq_map = full_irq_map; 176 177 /* This code creates a standard swizzle of interrupts such that 178 * each device's first interrupt is based on it's PCI_SLOT number. 179 * (See pci_swizzle_map_irq_fn()) 180 * 181 * We only need one entry per interrupt in the table (not one per 182 * possible slot) seeing the interrupt-map-mask will allow the table 183 * to wrap to any number of devices. 184 */ 185 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 186 int devfn = dev * 0x8; 187 188 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 189 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 190 int i = 0; 191 192 /* Fill PCI address cells */ 193 irq_map[i] = cpu_to_be32(devfn << 8); 194 i += FDT_PCI_ADDR_CELLS; 195 196 /* Fill PCI Interrupt cells */ 197 irq_map[i] = cpu_to_be32(pin + 1); 198 i += FDT_PCI_INT_CELLS; 199 200 /* Fill interrupt controller phandle and cells */ 201 irq_map[i++] = cpu_to_be32(irqchip_phandle); 202 irq_map[i++] = cpu_to_be32(irq_nr); 203 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 204 irq_map[i++] = cpu_to_be32(0x4); 205 } 206 207 if (!irq_map_stride) { 208 irq_map_stride = i; 209 } 210 irq_map += irq_map_stride; 211 } 212 } 213 214 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 215 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 216 irq_map_stride * sizeof(uint32_t)); 217 218 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 219 0x1800, 0, 0, 0x7); 220 } 221 222 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 223 char *clust_name, uint32_t *phandle, 224 bool is_32_bit, uint32_t *intc_phandles) 225 { 226 int cpu; 227 uint32_t cpu_phandle; 228 MachineState *mc = MACHINE(s); 229 char *name, *cpu_name, *core_name, *intc_name; 230 231 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 232 cpu_phandle = (*phandle)++; 233 234 cpu_name = g_strdup_printf("/cpus/cpu@%d", 235 s->soc[socket].hartid_base + cpu); 236 qemu_fdt_add_subnode(mc->fdt, cpu_name); 237 if (riscv_feature(&s->soc[socket].harts[cpu].env, 238 RISCV_FEATURE_MMU)) { 239 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 240 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 241 } else { 242 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 243 "riscv,none"); 244 } 245 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 246 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 247 g_free(name); 248 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 249 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 250 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 251 s->soc[socket].hartid_base + cpu); 252 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 253 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 254 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 255 256 intc_phandles[cpu] = (*phandle)++; 257 258 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 259 qemu_fdt_add_subnode(mc->fdt, intc_name); 260 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 261 intc_phandles[cpu]); 262 if (riscv_feature(&s->soc[socket].harts[cpu].env, 263 RISCV_FEATURE_AIA)) { 264 static const char * const compat[2] = { 265 "riscv,cpu-intc-aia", "riscv,cpu-intc" 266 }; 267 qemu_fdt_setprop_string_array(mc->fdt, intc_name, "compatible", 268 (char **)&compat, ARRAY_SIZE(compat)); 269 } else { 270 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 271 "riscv,cpu-intc"); 272 } 273 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 274 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 275 276 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 277 qemu_fdt_add_subnode(mc->fdt, core_name); 278 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 279 280 g_free(core_name); 281 g_free(intc_name); 282 g_free(cpu_name); 283 } 284 } 285 286 static void create_fdt_socket_memory(RISCVVirtState *s, 287 const MemMapEntry *memmap, int socket) 288 { 289 char *mem_name; 290 uint64_t addr, size; 291 MachineState *mc = MACHINE(s); 292 293 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 294 size = riscv_socket_mem_size(mc, socket); 295 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 296 qemu_fdt_add_subnode(mc->fdt, mem_name); 297 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 298 addr >> 32, addr, size >> 32, size); 299 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 300 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 301 g_free(mem_name); 302 } 303 304 static void create_fdt_socket_clint(RISCVVirtState *s, 305 const MemMapEntry *memmap, int socket, 306 uint32_t *intc_phandles) 307 { 308 int cpu; 309 char *clint_name; 310 uint32_t *clint_cells; 311 unsigned long clint_addr; 312 MachineState *mc = MACHINE(s); 313 static const char * const clint_compat[2] = { 314 "sifive,clint0", "riscv,clint0" 315 }; 316 317 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 318 319 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 320 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 321 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 322 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 323 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 324 } 325 326 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 327 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 328 qemu_fdt_add_subnode(mc->fdt, clint_name); 329 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 330 (char **)&clint_compat, 331 ARRAY_SIZE(clint_compat)); 332 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 333 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 334 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 335 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 336 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 337 g_free(clint_name); 338 339 g_free(clint_cells); 340 } 341 342 static void create_fdt_socket_aclint(RISCVVirtState *s, 343 const MemMapEntry *memmap, int socket, 344 uint32_t *intc_phandles) 345 { 346 int cpu; 347 char *name; 348 unsigned long addr, size; 349 uint32_t aclint_cells_size; 350 uint32_t *aclint_mswi_cells; 351 uint32_t *aclint_sswi_cells; 352 uint32_t *aclint_mtimer_cells; 353 MachineState *mc = MACHINE(s); 354 355 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 356 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 357 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 358 359 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 360 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 361 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 362 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 363 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 364 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 365 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 366 } 367 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 368 369 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 370 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 371 name = g_strdup_printf("/soc/mswi@%lx", addr); 372 qemu_fdt_add_subnode(mc->fdt, name); 373 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 374 "riscv,aclint-mswi"); 375 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 376 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 377 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 378 aclint_mswi_cells, aclint_cells_size); 379 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 380 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 381 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 382 g_free(name); 383 } 384 385 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 386 addr = memmap[VIRT_CLINT].base + 387 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 388 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 389 } else { 390 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 391 (memmap[VIRT_CLINT].size * socket); 392 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 393 } 394 name = g_strdup_printf("/soc/mtimer@%lx", addr); 395 qemu_fdt_add_subnode(mc->fdt, name); 396 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 397 "riscv,aclint-mtimer"); 398 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 399 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 400 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 401 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 402 0x0, RISCV_ACLINT_DEFAULT_MTIME); 403 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 404 aclint_mtimer_cells, aclint_cells_size); 405 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 406 g_free(name); 407 408 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 409 addr = memmap[VIRT_ACLINT_SSWI].base + 410 (memmap[VIRT_ACLINT_SSWI].size * socket); 411 name = g_strdup_printf("/soc/sswi@%lx", addr); 412 qemu_fdt_add_subnode(mc->fdt, name); 413 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 414 "riscv,aclint-sswi"); 415 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 416 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 417 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 418 aclint_sswi_cells, aclint_cells_size); 419 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 420 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 421 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 422 g_free(name); 423 } 424 425 g_free(aclint_mswi_cells); 426 g_free(aclint_mtimer_cells); 427 g_free(aclint_sswi_cells); 428 } 429 430 static void create_fdt_socket_plic(RISCVVirtState *s, 431 const MemMapEntry *memmap, int socket, 432 uint32_t *phandle, uint32_t *intc_phandles, 433 uint32_t *plic_phandles) 434 { 435 int cpu; 436 char *plic_name; 437 uint32_t *plic_cells; 438 unsigned long plic_addr; 439 MachineState *mc = MACHINE(s); 440 static const char * const plic_compat[2] = { 441 "sifive,plic-1.0.0", "riscv,plic0" 442 }; 443 444 if (kvm_enabled()) { 445 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 446 } else { 447 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 448 } 449 450 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 451 if (kvm_enabled()) { 452 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 453 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 454 } else { 455 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 456 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 457 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 458 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 459 } 460 } 461 462 plic_phandles[socket] = (*phandle)++; 463 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 464 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 465 qemu_fdt_add_subnode(mc->fdt, plic_name); 466 qemu_fdt_setprop_cell(mc->fdt, plic_name, 467 "#interrupt-cells", FDT_PLIC_INT_CELLS); 468 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 469 (char **)&plic_compat, 470 ARRAY_SIZE(plic_compat)); 471 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 472 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 473 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 474 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 475 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 476 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 477 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 478 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 479 plic_phandles[socket]); 480 481 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 482 memmap[VIRT_PLATFORM_BUS].base, 483 memmap[VIRT_PLATFORM_BUS].size, 484 VIRT_PLATFORM_BUS_IRQ); 485 486 g_free(plic_name); 487 488 g_free(plic_cells); 489 } 490 491 static uint32_t imsic_num_bits(uint32_t count) 492 { 493 uint32_t ret = 0; 494 495 while (BIT(ret) < count) { 496 ret++; 497 } 498 499 return ret; 500 } 501 502 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 503 uint32_t *phandle, uint32_t *intc_phandles, 504 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 505 { 506 int cpu, socket; 507 char *imsic_name; 508 MachineState *mc = MACHINE(s); 509 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 510 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 511 512 *msi_m_phandle = (*phandle)++; 513 *msi_s_phandle = (*phandle)++; 514 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 515 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 516 517 /* M-level IMSIC node */ 518 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 519 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 520 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 521 } 522 imsic_max_hart_per_socket = 0; 523 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 524 imsic_addr = memmap[VIRT_IMSIC_M].base + 525 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 526 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 527 imsic_regs[socket * 4 + 0] = 0; 528 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 529 imsic_regs[socket * 4 + 2] = 0; 530 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 531 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 532 imsic_max_hart_per_socket = s->soc[socket].num_harts; 533 } 534 } 535 imsic_name = g_strdup_printf("/soc/imsics@%lx", 536 (unsigned long)memmap[VIRT_IMSIC_M].base); 537 qemu_fdt_add_subnode(mc->fdt, imsic_name); 538 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 539 "riscv,imsics"); 540 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 541 FDT_IMSIC_INT_CELLS); 542 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 543 NULL, 0); 544 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 545 NULL, 0); 546 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 547 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 548 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 549 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 550 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 551 VIRT_IRQCHIP_NUM_MSIS); 552 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 553 VIRT_IRQCHIP_IPI_MSI); 554 if (riscv_socket_count(mc) > 1) { 555 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 556 imsic_num_bits(imsic_max_hart_per_socket)); 557 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 558 imsic_num_bits(riscv_socket_count(mc))); 559 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 560 IMSIC_MMIO_GROUP_MIN_SHIFT); 561 } 562 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 563 564 platform_bus_add_all_fdt_nodes(mc->fdt, imsic_name, 565 memmap[VIRT_PLATFORM_BUS].base, 566 memmap[VIRT_PLATFORM_BUS].size, 567 VIRT_PLATFORM_BUS_IRQ); 568 569 g_free(imsic_name); 570 571 /* S-level IMSIC node */ 572 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 573 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 574 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 575 } 576 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 577 imsic_max_hart_per_socket = 0; 578 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 579 imsic_addr = memmap[VIRT_IMSIC_S].base + 580 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 581 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 582 s->soc[socket].num_harts; 583 imsic_regs[socket * 4 + 0] = 0; 584 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 585 imsic_regs[socket * 4 + 2] = 0; 586 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 587 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 588 imsic_max_hart_per_socket = s->soc[socket].num_harts; 589 } 590 } 591 imsic_name = g_strdup_printf("/soc/imsics@%lx", 592 (unsigned long)memmap[VIRT_IMSIC_S].base); 593 qemu_fdt_add_subnode(mc->fdt, imsic_name); 594 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 595 "riscv,imsics"); 596 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 597 FDT_IMSIC_INT_CELLS); 598 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 599 NULL, 0); 600 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 601 NULL, 0); 602 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 603 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 604 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 605 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 606 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 607 VIRT_IRQCHIP_NUM_MSIS); 608 qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", 609 VIRT_IRQCHIP_IPI_MSI); 610 if (imsic_guest_bits) { 611 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 612 imsic_guest_bits); 613 } 614 if (riscv_socket_count(mc) > 1) { 615 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 616 imsic_num_bits(imsic_max_hart_per_socket)); 617 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 618 imsic_num_bits(riscv_socket_count(mc))); 619 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 620 IMSIC_MMIO_GROUP_MIN_SHIFT); 621 } 622 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 623 g_free(imsic_name); 624 625 g_free(imsic_regs); 626 g_free(imsic_cells); 627 } 628 629 static void create_fdt_socket_aplic(RISCVVirtState *s, 630 const MemMapEntry *memmap, int socket, 631 uint32_t msi_m_phandle, 632 uint32_t msi_s_phandle, 633 uint32_t *phandle, 634 uint32_t *intc_phandles, 635 uint32_t *aplic_phandles) 636 { 637 int cpu; 638 char *aplic_name; 639 uint32_t *aplic_cells; 640 unsigned long aplic_addr; 641 MachineState *mc = MACHINE(s); 642 uint32_t aplic_m_phandle, aplic_s_phandle; 643 644 aplic_m_phandle = (*phandle)++; 645 aplic_s_phandle = (*phandle)++; 646 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 647 648 /* M-level APLIC node */ 649 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 650 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 651 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 652 } 653 aplic_addr = memmap[VIRT_APLIC_M].base + 654 (memmap[VIRT_APLIC_M].size * socket); 655 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 656 qemu_fdt_add_subnode(mc->fdt, aplic_name); 657 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 658 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 659 "#interrupt-cells", FDT_APLIC_INT_CELLS); 660 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 661 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 662 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 663 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 664 } else { 665 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 666 msi_m_phandle); 667 } 668 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 669 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 670 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 671 VIRT_IRQCHIP_NUM_SOURCES); 672 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 673 aplic_s_phandle); 674 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 675 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 676 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 677 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 678 g_free(aplic_name); 679 680 /* S-level APLIC node */ 681 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 682 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 683 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 684 } 685 aplic_addr = memmap[VIRT_APLIC_S].base + 686 (memmap[VIRT_APLIC_S].size * socket); 687 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 688 qemu_fdt_add_subnode(mc->fdt, aplic_name); 689 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 690 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 691 "#interrupt-cells", FDT_APLIC_INT_CELLS); 692 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 693 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 694 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 695 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 696 } else { 697 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 698 msi_s_phandle); 699 } 700 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 701 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 702 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 703 VIRT_IRQCHIP_NUM_SOURCES); 704 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 705 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 706 707 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 708 memmap[VIRT_PLATFORM_BUS].base, 709 memmap[VIRT_PLATFORM_BUS].size, 710 VIRT_PLATFORM_BUS_IRQ); 711 712 g_free(aplic_name); 713 714 g_free(aplic_cells); 715 aplic_phandles[socket] = aplic_s_phandle; 716 } 717 718 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 719 bool is_32_bit, uint32_t *phandle, 720 uint32_t *irq_mmio_phandle, 721 uint32_t *irq_pcie_phandle, 722 uint32_t *irq_virtio_phandle, 723 uint32_t *msi_pcie_phandle) 724 { 725 char *clust_name; 726 int socket, phandle_pos; 727 MachineState *mc = MACHINE(s); 728 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 729 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 730 731 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 732 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 733 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 734 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 735 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 736 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 737 738 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 739 740 phandle_pos = mc->smp.cpus; 741 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 742 phandle_pos -= s->soc[socket].num_harts; 743 744 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 745 qemu_fdt_add_subnode(mc->fdt, clust_name); 746 747 create_fdt_socket_cpus(s, socket, clust_name, phandle, 748 is_32_bit, &intc_phandles[phandle_pos]); 749 750 create_fdt_socket_memory(s, memmap, socket); 751 752 g_free(clust_name); 753 754 if (!kvm_enabled()) { 755 if (s->have_aclint) { 756 create_fdt_socket_aclint(s, memmap, socket, 757 &intc_phandles[phandle_pos]); 758 } else { 759 create_fdt_socket_clint(s, memmap, socket, 760 &intc_phandles[phandle_pos]); 761 } 762 } 763 } 764 765 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 766 create_fdt_imsic(s, memmap, phandle, intc_phandles, 767 &msi_m_phandle, &msi_s_phandle); 768 *msi_pcie_phandle = msi_s_phandle; 769 } 770 771 phandle_pos = mc->smp.cpus; 772 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 773 phandle_pos -= s->soc[socket].num_harts; 774 775 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 776 create_fdt_socket_plic(s, memmap, socket, phandle, 777 &intc_phandles[phandle_pos], xplic_phandles); 778 } else { 779 create_fdt_socket_aplic(s, memmap, socket, 780 msi_m_phandle, msi_s_phandle, phandle, 781 &intc_phandles[phandle_pos], xplic_phandles); 782 } 783 } 784 785 g_free(intc_phandles); 786 787 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 788 if (socket == 0) { 789 *irq_mmio_phandle = xplic_phandles[socket]; 790 *irq_virtio_phandle = xplic_phandles[socket]; 791 *irq_pcie_phandle = xplic_phandles[socket]; 792 } 793 if (socket == 1) { 794 *irq_virtio_phandle = xplic_phandles[socket]; 795 *irq_pcie_phandle = xplic_phandles[socket]; 796 } 797 if (socket == 2) { 798 *irq_pcie_phandle = xplic_phandles[socket]; 799 } 800 } 801 802 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 803 } 804 805 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 806 uint32_t irq_virtio_phandle) 807 { 808 int i; 809 char *name; 810 MachineState *mc = MACHINE(s); 811 812 for (i = 0; i < VIRTIO_COUNT; i++) { 813 name = g_strdup_printf("/soc/virtio_mmio@%lx", 814 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 815 qemu_fdt_add_subnode(mc->fdt, name); 816 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 817 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 818 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 819 0x0, memmap[VIRT_VIRTIO].size); 820 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 821 irq_virtio_phandle); 822 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 823 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 824 VIRTIO_IRQ + i); 825 } else { 826 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 827 VIRTIO_IRQ + i, 0x4); 828 } 829 g_free(name); 830 } 831 } 832 833 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 834 uint32_t irq_pcie_phandle, 835 uint32_t msi_pcie_phandle) 836 { 837 char *name; 838 MachineState *mc = MACHINE(s); 839 840 name = g_strdup_printf("/soc/pci@%lx", 841 (long) memmap[VIRT_PCIE_ECAM].base); 842 qemu_fdt_add_subnode(mc->fdt, name); 843 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 844 FDT_PCI_ADDR_CELLS); 845 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 846 FDT_PCI_INT_CELLS); 847 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 848 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 849 "pci-host-ecam-generic"); 850 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 851 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 852 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 853 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 854 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 855 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 856 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 857 } 858 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 859 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 860 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 861 1, FDT_PCI_RANGE_IOPORT, 2, 0, 862 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 863 1, FDT_PCI_RANGE_MMIO, 864 2, memmap[VIRT_PCIE_MMIO].base, 865 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 866 1, FDT_PCI_RANGE_MMIO_64BIT, 867 2, virt_high_pcie_memmap.base, 868 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 869 870 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 871 g_free(name); 872 } 873 874 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 875 uint32_t *phandle) 876 { 877 char *name; 878 uint32_t test_phandle; 879 MachineState *mc = MACHINE(s); 880 881 test_phandle = (*phandle)++; 882 name = g_strdup_printf("/soc/test@%lx", 883 (long)memmap[VIRT_TEST].base); 884 qemu_fdt_add_subnode(mc->fdt, name); 885 { 886 static const char * const compat[3] = { 887 "sifive,test1", "sifive,test0", "syscon" 888 }; 889 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 890 (char **)&compat, ARRAY_SIZE(compat)); 891 } 892 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 893 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 894 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 895 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 896 g_free(name); 897 898 name = g_strdup_printf("/soc/reboot"); 899 qemu_fdt_add_subnode(mc->fdt, name); 900 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 901 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 902 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 903 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 904 g_free(name); 905 906 name = g_strdup_printf("/soc/poweroff"); 907 qemu_fdt_add_subnode(mc->fdt, name); 908 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 909 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 910 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 911 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 912 g_free(name); 913 } 914 915 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 916 uint32_t irq_mmio_phandle) 917 { 918 char *name; 919 MachineState *mc = MACHINE(s); 920 921 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 922 qemu_fdt_add_subnode(mc->fdt, name); 923 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 924 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 925 0x0, memmap[VIRT_UART0].base, 926 0x0, memmap[VIRT_UART0].size); 927 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 928 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 929 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 930 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 931 } else { 932 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 933 } 934 935 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 936 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 937 g_free(name); 938 } 939 940 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 941 uint32_t irq_mmio_phandle) 942 { 943 char *name; 944 MachineState *mc = MACHINE(s); 945 946 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 947 qemu_fdt_add_subnode(mc->fdt, name); 948 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 949 "google,goldfish-rtc"); 950 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 951 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 952 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 953 irq_mmio_phandle); 954 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 955 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 956 } else { 957 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 958 } 959 g_free(name); 960 } 961 962 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 963 { 964 char *name; 965 MachineState *mc = MACHINE(s); 966 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 967 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 968 969 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 970 qemu_fdt_add_subnode(mc->fdt, name); 971 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 972 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 973 2, flashbase, 2, flashsize, 974 2, flashbase + flashsize, 2, flashsize); 975 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 976 g_free(name); 977 } 978 979 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 980 uint64_t mem_size, const char *cmdline, bool is_32_bit) 981 { 982 MachineState *mc = MACHINE(s); 983 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 984 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 985 986 if (mc->dtb) { 987 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 988 if (!mc->fdt) { 989 error_report("load_device_tree() failed"); 990 exit(1); 991 } 992 goto update_bootargs; 993 } else { 994 mc->fdt = create_device_tree(&s->fdt_size); 995 if (!mc->fdt) { 996 error_report("create_device_tree() failed"); 997 exit(1); 998 } 999 } 1000 1001 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1002 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1003 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1004 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1005 1006 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1007 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1008 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1009 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1010 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1011 1012 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 1013 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 1014 &msi_pcie_phandle); 1015 1016 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1017 1018 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1019 1020 create_fdt_reset(s, memmap, &phandle); 1021 1022 create_fdt_uart(s, memmap, irq_mmio_phandle); 1023 1024 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1025 1026 create_fdt_flash(s, memmap); 1027 1028 update_bootargs: 1029 if (cmdline && *cmdline) { 1030 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1031 } 1032 } 1033 1034 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1035 hwaddr ecam_base, hwaddr ecam_size, 1036 hwaddr mmio_base, hwaddr mmio_size, 1037 hwaddr high_mmio_base, 1038 hwaddr high_mmio_size, 1039 hwaddr pio_base, 1040 DeviceState *irqchip) 1041 { 1042 DeviceState *dev; 1043 MemoryRegion *ecam_alias, *ecam_reg; 1044 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1045 qemu_irq irq; 1046 int i; 1047 1048 dev = qdev_new(TYPE_GPEX_HOST); 1049 1050 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1051 1052 ecam_alias = g_new0(MemoryRegion, 1); 1053 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1054 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1055 ecam_reg, 0, ecam_size); 1056 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1057 1058 mmio_alias = g_new0(MemoryRegion, 1); 1059 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1060 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1061 mmio_reg, mmio_base, mmio_size); 1062 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1063 1064 /* Map high MMIO space */ 1065 high_mmio_alias = g_new0(MemoryRegion, 1); 1066 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1067 mmio_reg, high_mmio_base, high_mmio_size); 1068 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1069 high_mmio_alias); 1070 1071 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1072 1073 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1074 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1075 1076 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1077 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1078 } 1079 1080 return dev; 1081 } 1082 1083 static FWCfgState *create_fw_cfg(const MachineState *mc) 1084 { 1085 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1086 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 1087 FWCfgState *fw_cfg; 1088 char *nodename; 1089 1090 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1091 &address_space_memory); 1092 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1093 1094 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 1095 qemu_fdt_add_subnode(mc->fdt, nodename); 1096 qemu_fdt_setprop_string(mc->fdt, nodename, 1097 "compatible", "qemu,fw-cfg-mmio"); 1098 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 1099 2, base, 2, size); 1100 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 1101 g_free(nodename); 1102 return fw_cfg; 1103 } 1104 1105 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1106 int base_hartid, int hart_count) 1107 { 1108 DeviceState *ret; 1109 char *plic_hart_config; 1110 1111 /* Per-socket PLIC hart topology configuration string */ 1112 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1113 1114 /* Per-socket PLIC */ 1115 ret = sifive_plic_create( 1116 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1117 plic_hart_config, hart_count, base_hartid, 1118 VIRT_IRQCHIP_NUM_SOURCES, 1119 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1120 VIRT_PLIC_PRIORITY_BASE, 1121 VIRT_PLIC_PENDING_BASE, 1122 VIRT_PLIC_ENABLE_BASE, 1123 VIRT_PLIC_ENABLE_STRIDE, 1124 VIRT_PLIC_CONTEXT_BASE, 1125 VIRT_PLIC_CONTEXT_STRIDE, 1126 memmap[VIRT_PLIC].size); 1127 1128 g_free(plic_hart_config); 1129 1130 return ret; 1131 } 1132 1133 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1134 const MemMapEntry *memmap, int socket, 1135 int base_hartid, int hart_count) 1136 { 1137 int i; 1138 hwaddr addr; 1139 uint32_t guest_bits; 1140 DeviceState *aplic_m; 1141 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1142 1143 if (msimode) { 1144 /* Per-socket M-level IMSICs */ 1145 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1146 for (i = 0; i < hart_count; i++) { 1147 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1148 base_hartid + i, true, 1, 1149 VIRT_IRQCHIP_NUM_MSIS); 1150 } 1151 1152 /* Per-socket S-level IMSICs */ 1153 guest_bits = imsic_num_bits(aia_guests + 1); 1154 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1155 for (i = 0; i < hart_count; i++) { 1156 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1157 base_hartid + i, false, 1 + aia_guests, 1158 VIRT_IRQCHIP_NUM_MSIS); 1159 } 1160 } 1161 1162 /* Per-socket M-level APLIC */ 1163 aplic_m = riscv_aplic_create( 1164 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1165 memmap[VIRT_APLIC_M].size, 1166 (msimode) ? 0 : base_hartid, 1167 (msimode) ? 0 : hart_count, 1168 VIRT_IRQCHIP_NUM_SOURCES, 1169 VIRT_IRQCHIP_NUM_PRIO_BITS, 1170 msimode, true, NULL); 1171 1172 if (aplic_m) { 1173 /* Per-socket S-level APLIC */ 1174 riscv_aplic_create( 1175 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1176 memmap[VIRT_APLIC_S].size, 1177 (msimode) ? 0 : base_hartid, 1178 (msimode) ? 0 : hart_count, 1179 VIRT_IRQCHIP_NUM_SOURCES, 1180 VIRT_IRQCHIP_NUM_PRIO_BITS, 1181 msimode, false, aplic_m); 1182 } 1183 1184 return aplic_m; 1185 } 1186 1187 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1188 { 1189 DeviceState *dev; 1190 SysBusDevice *sysbus; 1191 const MemMapEntry *memmap = virt_memmap; 1192 int i; 1193 MemoryRegion *sysmem = get_system_memory(); 1194 1195 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1196 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1197 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1198 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1199 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1200 s->platform_bus_dev = dev; 1201 1202 sysbus = SYS_BUS_DEVICE(dev); 1203 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1204 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1205 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1206 } 1207 1208 memory_region_add_subregion(sysmem, 1209 memmap[VIRT_PLATFORM_BUS].base, 1210 sysbus_mmio_get_region(sysbus, 0)); 1211 } 1212 1213 static void virt_machine_done(Notifier *notifier, void *data) 1214 { 1215 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1216 machine_done); 1217 const MemMapEntry *memmap = virt_memmap; 1218 MachineState *machine = MACHINE(s); 1219 target_ulong start_addr = memmap[VIRT_DRAM].base; 1220 target_ulong firmware_end_addr, kernel_start_addr; 1221 uint32_t fdt_load_addr; 1222 uint64_t kernel_entry; 1223 1224 /* 1225 * Only direct boot kernel is currently supported for KVM VM, 1226 * so the "-bios" parameter is not supported when KVM is enabled. 1227 */ 1228 if (kvm_enabled()) { 1229 if (machine->firmware) { 1230 if (strcmp(machine->firmware, "none")) { 1231 error_report("Machine mode firmware is not supported in " 1232 "combination with KVM."); 1233 exit(1); 1234 } 1235 } else { 1236 machine->firmware = g_strdup("none"); 1237 } 1238 } 1239 1240 if (riscv_is_32bit(&s->soc[0])) { 1241 firmware_end_addr = riscv_find_and_load_firmware(machine, 1242 RISCV32_BIOS_BIN, start_addr, NULL); 1243 } else { 1244 firmware_end_addr = riscv_find_and_load_firmware(machine, 1245 RISCV64_BIOS_BIN, start_addr, NULL); 1246 } 1247 1248 if (machine->kernel_filename) { 1249 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1250 firmware_end_addr); 1251 1252 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1253 kernel_start_addr, NULL); 1254 1255 if (machine->initrd_filename) { 1256 hwaddr start; 1257 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1258 machine->ram_size, kernel_entry, 1259 &start); 1260 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1261 "linux,initrd-start", start); 1262 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1263 end); 1264 } 1265 } else { 1266 /* 1267 * If dynamic firmware is used, it doesn't know where is the next mode 1268 * if kernel argument is not set. 1269 */ 1270 kernel_entry = 0; 1271 } 1272 1273 if (drive_get(IF_PFLASH, 0, 0)) { 1274 /* 1275 * Pflash was supplied, let's overwrite the address we jump to after 1276 * reset to the base of the flash. 1277 */ 1278 start_addr = virt_memmap[VIRT_FLASH].base; 1279 } 1280 1281 /* 1282 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1283 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1284 */ 1285 s->fw_cfg = create_fw_cfg(machine); 1286 rom_set_fw(s->fw_cfg); 1287 1288 /* Compute the fdt load address in dram */ 1289 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1290 machine->ram_size, machine->fdt); 1291 /* load the reset vector */ 1292 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1293 virt_memmap[VIRT_MROM].base, 1294 virt_memmap[VIRT_MROM].size, kernel_entry, 1295 fdt_load_addr, machine->fdt); 1296 1297 /* 1298 * Only direct boot kernel is currently supported for KVM VM, 1299 * So here setup kernel start address and fdt address. 1300 * TODO:Support firmware loading and integrate to TCG start 1301 */ 1302 if (kvm_enabled()) { 1303 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1304 } 1305 } 1306 1307 static void virt_machine_init(MachineState *machine) 1308 { 1309 const MemMapEntry *memmap = virt_memmap; 1310 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1311 MemoryRegion *system_memory = get_system_memory(); 1312 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1313 char *soc_name; 1314 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1315 int i, base_hartid, hart_count; 1316 1317 /* Check socket count limit */ 1318 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1319 error_report("number of sockets/nodes should be less than %d", 1320 VIRT_SOCKETS_MAX); 1321 exit(1); 1322 } 1323 1324 /* Initialize sockets */ 1325 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1326 for (i = 0; i < riscv_socket_count(machine); i++) { 1327 if (!riscv_socket_check_hartids(machine, i)) { 1328 error_report("discontinuous hartids in socket%d", i); 1329 exit(1); 1330 } 1331 1332 base_hartid = riscv_socket_first_hartid(machine, i); 1333 if (base_hartid < 0) { 1334 error_report("can't find hartid base for socket%d", i); 1335 exit(1); 1336 } 1337 1338 hart_count = riscv_socket_hart_count(machine, i); 1339 if (hart_count < 0) { 1340 error_report("can't find hart count for socket%d", i); 1341 exit(1); 1342 } 1343 1344 soc_name = g_strdup_printf("soc%d", i); 1345 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1346 TYPE_RISCV_HART_ARRAY); 1347 g_free(soc_name); 1348 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1349 machine->cpu_type, &error_abort); 1350 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1351 base_hartid, &error_abort); 1352 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1353 hart_count, &error_abort); 1354 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 1355 1356 if (!kvm_enabled()) { 1357 if (s->have_aclint) { 1358 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1359 /* Per-socket ACLINT MTIMER */ 1360 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1361 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1362 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1363 base_hartid, hart_count, 1364 RISCV_ACLINT_DEFAULT_MTIMECMP, 1365 RISCV_ACLINT_DEFAULT_MTIME, 1366 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1367 } else { 1368 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1369 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1370 i * memmap[VIRT_CLINT].size, 1371 base_hartid, hart_count, false); 1372 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1373 i * memmap[VIRT_CLINT].size + 1374 RISCV_ACLINT_SWI_SIZE, 1375 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1376 base_hartid, hart_count, 1377 RISCV_ACLINT_DEFAULT_MTIMECMP, 1378 RISCV_ACLINT_DEFAULT_MTIME, 1379 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1380 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1381 i * memmap[VIRT_ACLINT_SSWI].size, 1382 base_hartid, hart_count, true); 1383 } 1384 } else { 1385 /* Per-socket SiFive CLINT */ 1386 riscv_aclint_swi_create( 1387 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1388 base_hartid, hart_count, false); 1389 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1390 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1391 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1392 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1393 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1394 } 1395 } 1396 1397 /* Per-socket interrupt controller */ 1398 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1399 s->irqchip[i] = virt_create_plic(memmap, i, 1400 base_hartid, hart_count); 1401 } else { 1402 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1403 memmap, i, base_hartid, 1404 hart_count); 1405 } 1406 1407 /* Try to use different IRQCHIP instance based device type */ 1408 if (i == 0) { 1409 mmio_irqchip = s->irqchip[i]; 1410 virtio_irqchip = s->irqchip[i]; 1411 pcie_irqchip = s->irqchip[i]; 1412 } 1413 if (i == 1) { 1414 virtio_irqchip = s->irqchip[i]; 1415 pcie_irqchip = s->irqchip[i]; 1416 } 1417 if (i == 2) { 1418 pcie_irqchip = s->irqchip[i]; 1419 } 1420 } 1421 1422 if (riscv_is_32bit(&s->soc[0])) { 1423 #if HOST_LONG_BITS == 64 1424 /* limit RAM size in a 32-bit system */ 1425 if (machine->ram_size > 10 * GiB) { 1426 machine->ram_size = 10 * GiB; 1427 error_report("Limiting RAM size to 10 GiB"); 1428 } 1429 #endif 1430 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1431 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1432 } else { 1433 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1434 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1435 virt_high_pcie_memmap.base = 1436 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1437 } 1438 1439 /* register system main memory (actual RAM) */ 1440 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1441 machine->ram); 1442 1443 /* boot rom */ 1444 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1445 memmap[VIRT_MROM].size, &error_fatal); 1446 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1447 mask_rom); 1448 1449 /* SiFive Test MMIO device */ 1450 sifive_test_create(memmap[VIRT_TEST].base); 1451 1452 /* VirtIO MMIO devices */ 1453 for (i = 0; i < VIRTIO_COUNT; i++) { 1454 sysbus_create_simple("virtio-mmio", 1455 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1456 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1457 } 1458 1459 gpex_pcie_init(system_memory, 1460 memmap[VIRT_PCIE_ECAM].base, 1461 memmap[VIRT_PCIE_ECAM].size, 1462 memmap[VIRT_PCIE_MMIO].base, 1463 memmap[VIRT_PCIE_MMIO].size, 1464 virt_high_pcie_memmap.base, 1465 virt_high_pcie_memmap.size, 1466 memmap[VIRT_PCIE_PIO].base, 1467 DEVICE(pcie_irqchip)); 1468 1469 create_platform_bus(s, DEVICE(mmio_irqchip)); 1470 1471 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1472 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1473 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1474 1475 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1476 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1477 1478 virt_flash_create(s); 1479 1480 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1481 /* Map legacy -drive if=pflash to machine properties */ 1482 pflash_cfi01_legacy_drive(s->flash[i], 1483 drive_get(IF_PFLASH, 0, i)); 1484 } 1485 virt_flash_map(s, system_memory); 1486 1487 /* create device tree */ 1488 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1489 riscv_is_32bit(&s->soc[0])); 1490 1491 s->machine_done.notify = virt_machine_done; 1492 qemu_add_machine_init_done_notifier(&s->machine_done); 1493 } 1494 1495 static void virt_machine_instance_init(Object *obj) 1496 { 1497 } 1498 1499 static char *virt_get_aia_guests(Object *obj, Error **errp) 1500 { 1501 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1502 char val[32]; 1503 1504 sprintf(val, "%d", s->aia_guests); 1505 return g_strdup(val); 1506 } 1507 1508 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1509 { 1510 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1511 1512 s->aia_guests = atoi(val); 1513 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1514 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1515 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1516 VIRT_IRQCHIP_MAX_GUESTS); 1517 } 1518 } 1519 1520 static char *virt_get_aia(Object *obj, Error **errp) 1521 { 1522 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1523 const char *val; 1524 1525 switch (s->aia_type) { 1526 case VIRT_AIA_TYPE_APLIC: 1527 val = "aplic"; 1528 break; 1529 case VIRT_AIA_TYPE_APLIC_IMSIC: 1530 val = "aplic-imsic"; 1531 break; 1532 default: 1533 val = "none"; 1534 break; 1535 }; 1536 1537 return g_strdup(val); 1538 } 1539 1540 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1541 { 1542 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1543 1544 if (!strcmp(val, "none")) { 1545 s->aia_type = VIRT_AIA_TYPE_NONE; 1546 } else if (!strcmp(val, "aplic")) { 1547 s->aia_type = VIRT_AIA_TYPE_APLIC; 1548 } else if (!strcmp(val, "aplic-imsic")) { 1549 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1550 } else { 1551 error_setg(errp, "Invalid AIA interrupt controller type"); 1552 error_append_hint(errp, "Valid values are none, aplic, and " 1553 "aplic-imsic.\n"); 1554 } 1555 } 1556 1557 static bool virt_get_aclint(Object *obj, Error **errp) 1558 { 1559 MachineState *ms = MACHINE(obj); 1560 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1561 1562 return s->have_aclint; 1563 } 1564 1565 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1566 { 1567 MachineState *ms = MACHINE(obj); 1568 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1569 1570 s->have_aclint = value; 1571 } 1572 1573 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1574 DeviceState *dev) 1575 { 1576 MachineClass *mc = MACHINE_GET_CLASS(machine); 1577 1578 if (device_is_dynamic_sysbus(mc, dev)) { 1579 return HOTPLUG_HANDLER(machine); 1580 } 1581 return NULL; 1582 } 1583 1584 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1585 DeviceState *dev, Error **errp) 1586 { 1587 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1588 1589 if (s->platform_bus_dev) { 1590 MachineClass *mc = MACHINE_GET_CLASS(s); 1591 1592 if (device_is_dynamic_sysbus(mc, dev)) { 1593 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1594 SYS_BUS_DEVICE(dev)); 1595 } 1596 } 1597 } 1598 1599 static void virt_machine_class_init(ObjectClass *oc, void *data) 1600 { 1601 char str[128]; 1602 MachineClass *mc = MACHINE_CLASS(oc); 1603 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1604 1605 mc->desc = "RISC-V VirtIO board"; 1606 mc->init = virt_machine_init; 1607 mc->max_cpus = VIRT_CPUS_MAX; 1608 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1609 mc->pci_allow_0_address = true; 1610 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1611 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1612 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1613 mc->numa_mem_supported = true; 1614 mc->default_ram_id = "riscv_virt_board.ram"; 1615 assert(!mc->get_hotplug_handler); 1616 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1617 1618 hc->plug = virt_machine_device_plug_cb; 1619 1620 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1621 #ifdef CONFIG_TPM 1622 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1623 #endif 1624 1625 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1626 virt_set_aclint); 1627 object_class_property_set_description(oc, "aclint", 1628 "Set on/off to enable/disable " 1629 "emulating ACLINT devices"); 1630 1631 object_class_property_add_str(oc, "aia", virt_get_aia, 1632 virt_set_aia); 1633 object_class_property_set_description(oc, "aia", 1634 "Set type of AIA interrupt " 1635 "conttoller. Valid values are " 1636 "none, aplic, and aplic-imsic."); 1637 1638 object_class_property_add_str(oc, "aia-guests", 1639 virt_get_aia_guests, 1640 virt_set_aia_guests); 1641 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1642 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1643 object_class_property_set_description(oc, "aia-guests", str); 1644 } 1645 1646 static const TypeInfo virt_machine_typeinfo = { 1647 .name = MACHINE_TYPE_NAME("virt"), 1648 .parent = TYPE_MACHINE, 1649 .class_init = virt_machine_class_init, 1650 .instance_init = virt_machine_instance_init, 1651 .instance_size = sizeof(RISCVVirtState), 1652 .interfaces = (InterfaceInfo[]) { 1653 { TYPE_HOTPLUG_HANDLER }, 1654 { } 1655 }, 1656 }; 1657 1658 static void virt_machine_init_register_types(void) 1659 { 1660 type_register_static(&virt_machine_typeinfo); 1661 } 1662 1663 type_init(virt_machine_init_register_types) 1664