1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qapi/error.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "hw/qdev-properties.h" 29 #include "hw/char/serial.h" 30 #include "target/riscv/cpu.h" 31 #include "hw/riscv/riscv_hart.h" 32 #include "hw/riscv/virt.h" 33 #include "hw/riscv/boot.h" 34 #include "hw/riscv/numa.h" 35 #include "hw/intc/sifive_clint.h" 36 #include "hw/intc/sifive_plic.h" 37 #include "hw/misc/sifive_test.h" 38 #include "chardev/char.h" 39 #include "sysemu/device_tree.h" 40 #include "sysemu/sysemu.h" 41 #include "hw/pci/pci.h" 42 #include "hw/pci-host/gpex.h" 43 #include "hw/display/ramfb.h" 44 45 static const MemMapEntry virt_memmap[] = { 46 [VIRT_DEBUG] = { 0x0, 0x100 }, 47 [VIRT_MROM] = { 0x1000, 0xf000 }, 48 [VIRT_TEST] = { 0x100000, 0x1000 }, 49 [VIRT_RTC] = { 0x101000, 0x1000 }, 50 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 51 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 52 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 53 [VIRT_UART0] = { 0x10000000, 0x100 }, 54 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 55 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 56 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 57 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 58 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 59 [VIRT_DRAM] = { 0x80000000, 0x0 }, 60 }; 61 62 /* PCIe high mmio is fixed for RV32 */ 63 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 64 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 65 66 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 67 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 68 69 static MemMapEntry virt_high_pcie_memmap; 70 71 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 72 73 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 74 const char *name, 75 const char *alias_prop_name) 76 { 77 /* 78 * Create a single flash device. We use the same parameters as 79 * the flash devices on the ARM virt board. 80 */ 81 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 82 83 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 84 qdev_prop_set_uint8(dev, "width", 4); 85 qdev_prop_set_uint8(dev, "device-width", 2); 86 qdev_prop_set_bit(dev, "big-endian", false); 87 qdev_prop_set_uint16(dev, "id0", 0x89); 88 qdev_prop_set_uint16(dev, "id1", 0x18); 89 qdev_prop_set_uint16(dev, "id2", 0x00); 90 qdev_prop_set_uint16(dev, "id3", 0x00); 91 qdev_prop_set_string(dev, "name", name); 92 93 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 94 object_property_add_alias(OBJECT(s), alias_prop_name, 95 OBJECT(dev), "drive"); 96 97 return PFLASH_CFI01(dev); 98 } 99 100 static void virt_flash_create(RISCVVirtState *s) 101 { 102 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 103 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 104 } 105 106 static void virt_flash_map1(PFlashCFI01 *flash, 107 hwaddr base, hwaddr size, 108 MemoryRegion *sysmem) 109 { 110 DeviceState *dev = DEVICE(flash); 111 112 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 113 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 114 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 115 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 116 117 memory_region_add_subregion(sysmem, base, 118 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 119 0)); 120 } 121 122 static void virt_flash_map(RISCVVirtState *s, 123 MemoryRegion *sysmem) 124 { 125 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 126 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 127 128 virt_flash_map1(s->flash[0], flashbase, flashsize, 129 sysmem); 130 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 131 sysmem); 132 } 133 134 static void create_pcie_irq_map(void *fdt, char *nodename, 135 uint32_t plic_phandle) 136 { 137 int pin, dev; 138 uint32_t 139 full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; 140 uint32_t *irq_map = full_irq_map; 141 142 /* This code creates a standard swizzle of interrupts such that 143 * each device's first interrupt is based on it's PCI_SLOT number. 144 * (See pci_swizzle_map_irq_fn()) 145 * 146 * We only need one entry per interrupt in the table (not one per 147 * possible slot) seeing the interrupt-map-mask will allow the table 148 * to wrap to any number of devices. 149 */ 150 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 151 int devfn = dev * 0x8; 152 153 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 154 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 155 int i = 0; 156 157 irq_map[i] = cpu_to_be32(devfn << 8); 158 159 i += FDT_PCI_ADDR_CELLS; 160 irq_map[i] = cpu_to_be32(pin + 1); 161 162 i += FDT_PCI_INT_CELLS; 163 irq_map[i++] = cpu_to_be32(plic_phandle); 164 165 i += FDT_PLIC_ADDR_CELLS; 166 irq_map[i] = cpu_to_be32(irq_nr); 167 168 irq_map += FDT_INT_MAP_WIDTH; 169 } 170 } 171 172 qemu_fdt_setprop(fdt, nodename, "interrupt-map", 173 full_irq_map, sizeof(full_irq_map)); 174 175 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 176 0x1800, 0, 0, 0x7); 177 } 178 179 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 180 uint64_t mem_size, const char *cmdline, bool is_32_bit) 181 { 182 void *fdt; 183 int i, cpu, socket; 184 MachineState *mc = MACHINE(s); 185 uint64_t addr, size; 186 uint32_t *clint_cells, *plic_cells; 187 unsigned long clint_addr, plic_addr; 188 uint32_t plic_phandle[MAX_NODES]; 189 uint32_t cpu_phandle, intc_phandle, test_phandle; 190 uint32_t phandle = 1, plic_mmio_phandle = 1; 191 uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1; 192 char *mem_name, *cpu_name, *core_name, *intc_name; 193 char *name, *clint_name, *plic_name, *clust_name; 194 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 195 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 196 static const char * const clint_compat[2] = { 197 "sifive,clint0", "riscv,clint0" 198 }; 199 static const char * const plic_compat[2] = { 200 "sifive,plic-1.0.0", "riscv,plic0" 201 }; 202 203 if (mc->dtb) { 204 fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 205 if (!fdt) { 206 error_report("load_device_tree() failed"); 207 exit(1); 208 } 209 goto update_bootargs; 210 } else { 211 fdt = mc->fdt = create_device_tree(&s->fdt_size); 212 if (!fdt) { 213 error_report("create_device_tree() failed"); 214 exit(1); 215 } 216 } 217 218 qemu_fdt_setprop_string(fdt, "/", "model", "riscv-virtio,qemu"); 219 qemu_fdt_setprop_string(fdt, "/", "compatible", "riscv-virtio"); 220 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); 221 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); 222 223 qemu_fdt_add_subnode(fdt, "/soc"); 224 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 225 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 226 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); 227 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); 228 229 qemu_fdt_add_subnode(fdt, "/cpus"); 230 qemu_fdt_setprop_cell(fdt, "/cpus", "timebase-frequency", 231 SIFIVE_CLINT_TIMEBASE_FREQ); 232 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 233 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 234 qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); 235 236 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 237 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 238 qemu_fdt_add_subnode(fdt, clust_name); 239 240 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 241 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 242 243 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 244 cpu_phandle = phandle++; 245 246 cpu_name = g_strdup_printf("/cpus/cpu@%d", 247 s->soc[socket].hartid_base + cpu); 248 qemu_fdt_add_subnode(fdt, cpu_name); 249 if (is_32_bit) { 250 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); 251 } else { 252 qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); 253 } 254 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 255 qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); 256 g_free(name); 257 qemu_fdt_setprop_string(fdt, cpu_name, "compatible", "riscv"); 258 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay"); 259 qemu_fdt_setprop_cell(fdt, cpu_name, "reg", 260 s->soc[socket].hartid_base + cpu); 261 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); 262 riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); 263 qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); 264 265 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 266 qemu_fdt_add_subnode(fdt, intc_name); 267 intc_phandle = phandle++; 268 qemu_fdt_setprop_cell(fdt, intc_name, "phandle", intc_phandle); 269 qemu_fdt_setprop_string(fdt, intc_name, "compatible", 270 "riscv,cpu-intc"); 271 qemu_fdt_setprop(fdt, intc_name, "interrupt-controller", NULL, 0); 272 qemu_fdt_setprop_cell(fdt, intc_name, "#interrupt-cells", 1); 273 274 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 275 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 276 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 277 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 278 279 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); 280 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 281 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); 282 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 283 284 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 285 qemu_fdt_add_subnode(fdt, core_name); 286 qemu_fdt_setprop_cell(fdt, core_name, "cpu", cpu_phandle); 287 288 g_free(core_name); 289 g_free(intc_name); 290 g_free(cpu_name); 291 } 292 293 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 294 size = riscv_socket_mem_size(mc, socket); 295 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 296 qemu_fdt_add_subnode(fdt, mem_name); 297 qemu_fdt_setprop_cells(fdt, mem_name, "reg", 298 addr >> 32, addr, size >> 32, size); 299 qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); 300 riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); 301 g_free(mem_name); 302 303 clint_addr = memmap[VIRT_CLINT].base + 304 (memmap[VIRT_CLINT].size * socket); 305 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 306 qemu_fdt_add_subnode(fdt, clint_name); 307 qemu_fdt_setprop_string_array(fdt, clint_name, "compatible", 308 (char **)&clint_compat, ARRAY_SIZE(clint_compat)); 309 qemu_fdt_setprop_cells(fdt, clint_name, "reg", 310 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 311 qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", 312 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 313 riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); 314 g_free(clint_name); 315 316 plic_phandle[socket] = phandle++; 317 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 318 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 319 qemu_fdt_add_subnode(fdt, plic_name); 320 qemu_fdt_setprop_cell(fdt, plic_name, 321 "#address-cells", FDT_PLIC_ADDR_CELLS); 322 qemu_fdt_setprop_cell(fdt, plic_name, 323 "#interrupt-cells", FDT_PLIC_INT_CELLS); 324 qemu_fdt_setprop_string_array(fdt, plic_name, "compatible", 325 (char **)&plic_compat, ARRAY_SIZE(plic_compat)); 326 qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0); 327 qemu_fdt_setprop(fdt, plic_name, "interrupts-extended", 328 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 329 qemu_fdt_setprop_cells(fdt, plic_name, "reg", 330 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 331 qemu_fdt_setprop_cell(fdt, plic_name, "riscv,ndev", VIRTIO_NDEV); 332 riscv_socket_fdt_write_id(mc, fdt, plic_name, socket); 333 qemu_fdt_setprop_cell(fdt, plic_name, "phandle", plic_phandle[socket]); 334 g_free(plic_name); 335 336 g_free(clint_cells); 337 g_free(plic_cells); 338 g_free(clust_name); 339 } 340 341 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 342 if (socket == 0) { 343 plic_mmio_phandle = plic_phandle[socket]; 344 plic_virtio_phandle = plic_phandle[socket]; 345 plic_pcie_phandle = plic_phandle[socket]; 346 } 347 if (socket == 1) { 348 plic_virtio_phandle = plic_phandle[socket]; 349 plic_pcie_phandle = plic_phandle[socket]; 350 } 351 if (socket == 2) { 352 plic_pcie_phandle = plic_phandle[socket]; 353 } 354 } 355 356 riscv_socket_fdt_write_distance_matrix(mc, fdt); 357 358 for (i = 0; i < VIRTIO_COUNT; i++) { 359 name = g_strdup_printf("/soc/virtio_mmio@%lx", 360 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 361 qemu_fdt_add_subnode(fdt, name); 362 qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio"); 363 qemu_fdt_setprop_cells(fdt, name, "reg", 364 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 365 0x0, memmap[VIRT_VIRTIO].size); 366 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", 367 plic_virtio_phandle); 368 qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i); 369 g_free(name); 370 } 371 372 name = g_strdup_printf("/soc/pci@%lx", 373 (long) memmap[VIRT_PCIE_ECAM].base); 374 qemu_fdt_add_subnode(fdt, name); 375 qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); 376 qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); 377 qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2); 378 qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic"); 379 qemu_fdt_setprop_string(fdt, name, "device_type", "pci"); 380 qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0); 381 qemu_fdt_setprop_cells(fdt, name, "bus-range", 0, 382 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 383 qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0); 384 qemu_fdt_setprop_cells(fdt, name, "reg", 0, 385 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 386 qemu_fdt_setprop_sized_cells(fdt, name, "ranges", 387 1, FDT_PCI_RANGE_IOPORT, 2, 0, 388 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 389 1, FDT_PCI_RANGE_MMIO, 390 2, memmap[VIRT_PCIE_MMIO].base, 391 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 392 1, FDT_PCI_RANGE_MMIO_64BIT, 393 2, virt_high_pcie_memmap.base, 394 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 395 396 create_pcie_irq_map(fdt, name, plic_pcie_phandle); 397 g_free(name); 398 399 test_phandle = phandle++; 400 name = g_strdup_printf("/soc/test@%lx", 401 (long)memmap[VIRT_TEST].base); 402 qemu_fdt_add_subnode(fdt, name); 403 { 404 static const char * const compat[3] = { 405 "sifive,test1", "sifive,test0", "syscon" 406 }; 407 qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat, 408 ARRAY_SIZE(compat)); 409 } 410 qemu_fdt_setprop_cells(fdt, name, "reg", 411 0x0, memmap[VIRT_TEST].base, 412 0x0, memmap[VIRT_TEST].size); 413 qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle); 414 test_phandle = qemu_fdt_get_phandle(fdt, name); 415 g_free(name); 416 417 name = g_strdup_printf("/soc/reboot"); 418 qemu_fdt_add_subnode(fdt, name); 419 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot"); 420 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 421 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 422 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET); 423 g_free(name); 424 425 name = g_strdup_printf("/soc/poweroff"); 426 qemu_fdt_add_subnode(fdt, name); 427 qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff"); 428 qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle); 429 qemu_fdt_setprop_cell(fdt, name, "offset", 0x0); 430 qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS); 431 g_free(name); 432 433 name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base); 434 qemu_fdt_add_subnode(fdt, name); 435 qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a"); 436 qemu_fdt_setprop_cells(fdt, name, "reg", 437 0x0, memmap[VIRT_UART0].base, 438 0x0, memmap[VIRT_UART0].size); 439 qemu_fdt_setprop_cell(fdt, name, "clock-frequency", 3686400); 440 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 441 qemu_fdt_setprop_cell(fdt, name, "interrupts", UART0_IRQ); 442 443 qemu_fdt_add_subnode(fdt, "/chosen"); 444 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name); 445 g_free(name); 446 447 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 448 qemu_fdt_add_subnode(fdt, name); 449 qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc"); 450 qemu_fdt_setprop_cells(fdt, name, "reg", 451 0x0, memmap[VIRT_RTC].base, 452 0x0, memmap[VIRT_RTC].size); 453 qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle); 454 qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ); 455 g_free(name); 456 457 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 458 qemu_fdt_add_subnode(mc->fdt, name); 459 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 460 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 461 2, flashbase, 2, flashsize, 462 2, flashbase + flashsize, 2, flashsize); 463 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 464 g_free(name); 465 466 update_bootargs: 467 if (cmdline) { 468 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 469 } 470 } 471 472 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 473 hwaddr ecam_base, hwaddr ecam_size, 474 hwaddr mmio_base, hwaddr mmio_size, 475 hwaddr high_mmio_base, 476 hwaddr high_mmio_size, 477 hwaddr pio_base, 478 DeviceState *plic) 479 { 480 DeviceState *dev; 481 MemoryRegion *ecam_alias, *ecam_reg; 482 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 483 qemu_irq irq; 484 int i; 485 486 dev = qdev_new(TYPE_GPEX_HOST); 487 488 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 489 490 ecam_alias = g_new0(MemoryRegion, 1); 491 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 492 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 493 ecam_reg, 0, ecam_size); 494 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 495 496 mmio_alias = g_new0(MemoryRegion, 1); 497 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 498 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 499 mmio_reg, mmio_base, mmio_size); 500 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 501 502 /* Map high MMIO space */ 503 high_mmio_alias = g_new0(MemoryRegion, 1); 504 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 505 mmio_reg, high_mmio_base, high_mmio_size); 506 memory_region_add_subregion(get_system_memory(), high_mmio_base, 507 high_mmio_alias); 508 509 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 510 511 for (i = 0; i < GPEX_NUM_IRQS; i++) { 512 irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); 513 514 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 515 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 516 } 517 518 return dev; 519 } 520 521 static FWCfgState *create_fw_cfg(const MachineState *mc) 522 { 523 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 524 hwaddr size = virt_memmap[VIRT_FW_CFG].size; 525 FWCfgState *fw_cfg; 526 char *nodename; 527 528 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 529 &address_space_memory); 530 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 531 532 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 533 qemu_fdt_add_subnode(mc->fdt, nodename); 534 qemu_fdt_setprop_string(mc->fdt, nodename, 535 "compatible", "qemu,fw-cfg-mmio"); 536 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 537 2, base, 2, size); 538 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 539 g_free(nodename); 540 return fw_cfg; 541 } 542 543 /* 544 * Return the per-socket PLIC hart topology configuration string 545 * (caller must free with g_free()) 546 */ 547 static char *plic_hart_config_string(int hart_count) 548 { 549 g_autofree const char **vals = g_new(const char *, hart_count + 1); 550 int i; 551 552 for (i = 0; i < hart_count; i++) { 553 vals[i] = VIRT_PLIC_HART_CONFIG; 554 } 555 vals[i] = NULL; 556 557 /* g_strjoinv() obliges us to cast away const here */ 558 return g_strjoinv(",", (char **)vals); 559 } 560 561 static void virt_machine_init(MachineState *machine) 562 { 563 const MemMapEntry *memmap = virt_memmap; 564 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 565 MemoryRegion *system_memory = get_system_memory(); 566 MemoryRegion *main_mem = g_new(MemoryRegion, 1); 567 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 568 char *plic_hart_config, *soc_name; 569 target_ulong start_addr = memmap[VIRT_DRAM].base; 570 target_ulong firmware_end_addr, kernel_start_addr; 571 uint32_t fdt_load_addr; 572 uint64_t kernel_entry; 573 DeviceState *mmio_plic, *virtio_plic, *pcie_plic; 574 int i, base_hartid, hart_count; 575 576 /* Check socket count limit */ 577 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 578 error_report("number of sockets/nodes should be less than %d", 579 VIRT_SOCKETS_MAX); 580 exit(1); 581 } 582 583 /* Initialize sockets */ 584 mmio_plic = virtio_plic = pcie_plic = NULL; 585 for (i = 0; i < riscv_socket_count(machine); i++) { 586 if (!riscv_socket_check_hartids(machine, i)) { 587 error_report("discontinuous hartids in socket%d", i); 588 exit(1); 589 } 590 591 base_hartid = riscv_socket_first_hartid(machine, i); 592 if (base_hartid < 0) { 593 error_report("can't find hartid base for socket%d", i); 594 exit(1); 595 } 596 597 hart_count = riscv_socket_hart_count(machine, i); 598 if (hart_count < 0) { 599 error_report("can't find hart count for socket%d", i); 600 exit(1); 601 } 602 603 soc_name = g_strdup_printf("soc%d", i); 604 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 605 TYPE_RISCV_HART_ARRAY); 606 g_free(soc_name); 607 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 608 machine->cpu_type, &error_abort); 609 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 610 base_hartid, &error_abort); 611 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 612 hart_count, &error_abort); 613 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); 614 615 /* Per-socket CLINT */ 616 sifive_clint_create( 617 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 618 memmap[VIRT_CLINT].size, base_hartid, hart_count, 619 SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, 620 SIFIVE_CLINT_TIMEBASE_FREQ, true); 621 622 /* Per-socket PLIC hart topology configuration string */ 623 plic_hart_config = plic_hart_config_string(hart_count); 624 625 /* Per-socket PLIC */ 626 s->plic[i] = sifive_plic_create( 627 memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, 628 plic_hart_config, base_hartid, 629 VIRT_PLIC_NUM_SOURCES, 630 VIRT_PLIC_NUM_PRIORITIES, 631 VIRT_PLIC_PRIORITY_BASE, 632 VIRT_PLIC_PENDING_BASE, 633 VIRT_PLIC_ENABLE_BASE, 634 VIRT_PLIC_ENABLE_STRIDE, 635 VIRT_PLIC_CONTEXT_BASE, 636 VIRT_PLIC_CONTEXT_STRIDE, 637 memmap[VIRT_PLIC].size); 638 g_free(plic_hart_config); 639 640 /* Try to use different PLIC instance based device type */ 641 if (i == 0) { 642 mmio_plic = s->plic[i]; 643 virtio_plic = s->plic[i]; 644 pcie_plic = s->plic[i]; 645 } 646 if (i == 1) { 647 virtio_plic = s->plic[i]; 648 pcie_plic = s->plic[i]; 649 } 650 if (i == 2) { 651 pcie_plic = s->plic[i]; 652 } 653 } 654 655 if (riscv_is_32bit(&s->soc[0])) { 656 #if HOST_LONG_BITS == 64 657 /* limit RAM size in a 32-bit system */ 658 if (machine->ram_size > 10 * GiB) { 659 machine->ram_size = 10 * GiB; 660 error_report("Limiting RAM size to 10 GiB"); 661 } 662 #endif 663 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 664 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 665 } else { 666 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 667 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 668 virt_high_pcie_memmap.base = 669 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 670 } 671 672 /* register system main memory (actual RAM) */ 673 memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", 674 machine->ram_size, &error_fatal); 675 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 676 main_mem); 677 678 /* create device tree */ 679 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 680 riscv_is_32bit(&s->soc[0])); 681 682 /* boot rom */ 683 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 684 memmap[VIRT_MROM].size, &error_fatal); 685 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 686 mask_rom); 687 688 if (riscv_is_32bit(&s->soc[0])) { 689 firmware_end_addr = riscv_find_and_load_firmware(machine, 690 RISCV32_BIOS_BIN, start_addr, NULL); 691 } else { 692 firmware_end_addr = riscv_find_and_load_firmware(machine, 693 RISCV64_BIOS_BIN, start_addr, NULL); 694 } 695 696 if (machine->kernel_filename) { 697 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 698 firmware_end_addr); 699 700 kernel_entry = riscv_load_kernel(machine->kernel_filename, 701 kernel_start_addr, NULL); 702 703 if (machine->initrd_filename) { 704 hwaddr start; 705 hwaddr end = riscv_load_initrd(machine->initrd_filename, 706 machine->ram_size, kernel_entry, 707 &start); 708 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 709 "linux,initrd-start", start); 710 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 711 end); 712 } 713 } else { 714 /* 715 * If dynamic firmware is used, it doesn't know where is the next mode 716 * if kernel argument is not set. 717 */ 718 kernel_entry = 0; 719 } 720 721 if (drive_get(IF_PFLASH, 0, 0)) { 722 /* 723 * Pflash was supplied, let's overwrite the address we jump to after 724 * reset to the base of the flash. 725 */ 726 start_addr = virt_memmap[VIRT_FLASH].base; 727 } 728 729 /* 730 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 731 * tree cannot be altered and we get FDT_ERR_NOSPACE. 732 */ 733 s->fw_cfg = create_fw_cfg(machine); 734 rom_set_fw(s->fw_cfg); 735 736 /* Compute the fdt load address in dram */ 737 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 738 machine->ram_size, machine->fdt); 739 /* load the reset vector */ 740 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 741 virt_memmap[VIRT_MROM].base, 742 virt_memmap[VIRT_MROM].size, kernel_entry, 743 fdt_load_addr, machine->fdt); 744 745 /* SiFive Test MMIO device */ 746 sifive_test_create(memmap[VIRT_TEST].base); 747 748 /* VirtIO MMIO devices */ 749 for (i = 0; i < VIRTIO_COUNT; i++) { 750 sysbus_create_simple("virtio-mmio", 751 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 752 qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); 753 } 754 755 gpex_pcie_init(system_memory, 756 memmap[VIRT_PCIE_ECAM].base, 757 memmap[VIRT_PCIE_ECAM].size, 758 memmap[VIRT_PCIE_MMIO].base, 759 memmap[VIRT_PCIE_MMIO].size, 760 virt_high_pcie_memmap.base, 761 virt_high_pcie_memmap.size, 762 memmap[VIRT_PCIE_PIO].base, 763 DEVICE(pcie_plic)); 764 765 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 766 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, 767 serial_hd(0), DEVICE_LITTLE_ENDIAN); 768 769 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 770 qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); 771 772 virt_flash_create(s); 773 774 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 775 /* Map legacy -drive if=pflash to machine properties */ 776 pflash_cfi01_legacy_drive(s->flash[i], 777 drive_get(IF_PFLASH, 0, i)); 778 } 779 virt_flash_map(s, system_memory); 780 } 781 782 static void virt_machine_instance_init(Object *obj) 783 { 784 } 785 786 static void virt_machine_class_init(ObjectClass *oc, void *data) 787 { 788 MachineClass *mc = MACHINE_CLASS(oc); 789 790 mc->desc = "RISC-V VirtIO board"; 791 mc->init = virt_machine_init; 792 mc->max_cpus = VIRT_CPUS_MAX; 793 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 794 mc->pci_allow_0_address = true; 795 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 796 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 797 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 798 mc->numa_mem_supported = true; 799 800 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 801 } 802 803 static const TypeInfo virt_machine_typeinfo = { 804 .name = MACHINE_TYPE_NAME("virt"), 805 .parent = TYPE_MACHINE, 806 .class_init = virt_machine_class_init, 807 .instance_init = virt_machine_instance_init, 808 .instance_size = sizeof(RISCVVirtState), 809 }; 810 811 static void virt_machine_init_register_types(void) 812 { 813 type_register_static(&virt_machine_typeinfo); 814 } 815 816 type_init(virt_machine_init_register_types) 817