1 /* 2 * QEMU RISC-V VirtIO Board 3 * 4 * Copyright (c) 2017 SiFive, Inc. 5 * 6 * RISC-V machine with 16550a UART and VirtIO MMIO 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2 or later, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/units.h" 23 #include "qemu/error-report.h" 24 #include "qemu/guest-random.h" 25 #include "qapi/error.h" 26 #include "hw/boards.h" 27 #include "hw/loader.h" 28 #include "hw/sysbus.h" 29 #include "hw/qdev-properties.h" 30 #include "hw/char/serial.h" 31 #include "target/riscv/cpu.h" 32 #include "hw/core/sysbus-fdt.h" 33 #include "target/riscv/pmu.h" 34 #include "hw/riscv/riscv_hart.h" 35 #include "hw/riscv/virt.h" 36 #include "hw/riscv/boot.h" 37 #include "hw/riscv/numa.h" 38 #include "hw/intc/riscv_aclint.h" 39 #include "hw/intc/riscv_aplic.h" 40 #include "hw/intc/riscv_imsic.h" 41 #include "hw/intc/sifive_plic.h" 42 #include "hw/misc/sifive_test.h" 43 #include "hw/platform-bus.h" 44 #include "chardev/char.h" 45 #include "sysemu/device_tree.h" 46 #include "sysemu/sysemu.h" 47 #include "sysemu/kvm.h" 48 #include "sysemu/tpm.h" 49 #include "hw/pci/pci.h" 50 #include "hw/pci-host/gpex.h" 51 #include "hw/display/ramfb.h" 52 53 /* 54 * The virt machine physical address space used by some of the devices 55 * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, 56 * number of CPUs, and number of IMSIC guest files. 57 * 58 * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, 59 * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization 60 * of virt machine physical address space. 61 */ 62 63 #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) 64 #if VIRT_IMSIC_GROUP_MAX_SIZE < \ 65 IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) 66 #error "Can't accomodate single IMSIC group in address space" 67 #endif 68 69 #define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ 70 VIRT_IMSIC_GROUP_MAX_SIZE) 71 #if 0x4000000 < VIRT_IMSIC_MAX_SIZE 72 #error "Can't accomodate all IMSIC groups in address space" 73 #endif 74 75 static const MemMapEntry virt_memmap[] = { 76 [VIRT_DEBUG] = { 0x0, 0x100 }, 77 [VIRT_MROM] = { 0x1000, 0xf000 }, 78 [VIRT_TEST] = { 0x100000, 0x1000 }, 79 [VIRT_RTC] = { 0x101000, 0x1000 }, 80 [VIRT_CLINT] = { 0x2000000, 0x10000 }, 81 [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, 82 [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, 83 [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, 84 [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, 85 [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 86 [VIRT_APLIC_S] = { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, 87 [VIRT_UART0] = { 0x10000000, 0x100 }, 88 [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, 89 [VIRT_FW_CFG] = { 0x10100000, 0x18 }, 90 [VIRT_FLASH] = { 0x20000000, 0x4000000 }, 91 [VIRT_IMSIC_M] = { 0x24000000, VIRT_IMSIC_MAX_SIZE }, 92 [VIRT_IMSIC_S] = { 0x28000000, VIRT_IMSIC_MAX_SIZE }, 93 [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, 94 [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, 95 [VIRT_DRAM] = { 0x80000000, 0x0 }, 96 }; 97 98 /* PCIe high mmio is fixed for RV32 */ 99 #define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL 100 #define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) 101 102 /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ 103 #define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) 104 105 static MemMapEntry virt_high_pcie_memmap; 106 107 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) 108 109 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, 110 const char *name, 111 const char *alias_prop_name) 112 { 113 /* 114 * Create a single flash device. We use the same parameters as 115 * the flash devices on the ARM virt board. 116 */ 117 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 118 119 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 120 qdev_prop_set_uint8(dev, "width", 4); 121 qdev_prop_set_uint8(dev, "device-width", 2); 122 qdev_prop_set_bit(dev, "big-endian", false); 123 qdev_prop_set_uint16(dev, "id0", 0x89); 124 qdev_prop_set_uint16(dev, "id1", 0x18); 125 qdev_prop_set_uint16(dev, "id2", 0x00); 126 qdev_prop_set_uint16(dev, "id3", 0x00); 127 qdev_prop_set_string(dev, "name", name); 128 129 object_property_add_child(OBJECT(s), name, OBJECT(dev)); 130 object_property_add_alias(OBJECT(s), alias_prop_name, 131 OBJECT(dev), "drive"); 132 133 return PFLASH_CFI01(dev); 134 } 135 136 static void virt_flash_create(RISCVVirtState *s) 137 { 138 s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); 139 s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); 140 } 141 142 static void virt_flash_map1(PFlashCFI01 *flash, 143 hwaddr base, hwaddr size, 144 MemoryRegion *sysmem) 145 { 146 DeviceState *dev = DEVICE(flash); 147 148 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 149 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 150 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 151 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 152 153 memory_region_add_subregion(sysmem, base, 154 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 155 0)); 156 } 157 158 static void virt_flash_map(RISCVVirtState *s, 159 MemoryRegion *sysmem) 160 { 161 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 162 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 163 164 virt_flash_map1(s->flash[0], flashbase, flashsize, 165 sysmem); 166 virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, 167 sysmem); 168 } 169 170 static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, 171 uint32_t irqchip_phandle) 172 { 173 int pin, dev; 174 uint32_t irq_map_stride = 0; 175 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 176 FDT_MAX_INT_MAP_WIDTH] = {}; 177 uint32_t *irq_map = full_irq_map; 178 179 /* This code creates a standard swizzle of interrupts such that 180 * each device's first interrupt is based on it's PCI_SLOT number. 181 * (See pci_swizzle_map_irq_fn()) 182 * 183 * We only need one entry per interrupt in the table (not one per 184 * possible slot) seeing the interrupt-map-mask will allow the table 185 * to wrap to any number of devices. 186 */ 187 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 188 int devfn = dev * 0x8; 189 190 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 191 int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 192 int i = 0; 193 194 /* Fill PCI address cells */ 195 irq_map[i] = cpu_to_be32(devfn << 8); 196 i += FDT_PCI_ADDR_CELLS; 197 198 /* Fill PCI Interrupt cells */ 199 irq_map[i] = cpu_to_be32(pin + 1); 200 i += FDT_PCI_INT_CELLS; 201 202 /* Fill interrupt controller phandle and cells */ 203 irq_map[i++] = cpu_to_be32(irqchip_phandle); 204 irq_map[i++] = cpu_to_be32(irq_nr); 205 if (s->aia_type != VIRT_AIA_TYPE_NONE) { 206 irq_map[i++] = cpu_to_be32(0x4); 207 } 208 209 if (!irq_map_stride) { 210 irq_map_stride = i; 211 } 212 irq_map += irq_map_stride; 213 } 214 } 215 216 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 217 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 218 irq_map_stride * sizeof(uint32_t)); 219 220 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 221 0x1800, 0, 0, 0x7); 222 } 223 224 static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, 225 char *clust_name, uint32_t *phandle, 226 bool is_32_bit, uint32_t *intc_phandles) 227 { 228 int cpu; 229 uint32_t cpu_phandle; 230 MachineState *mc = MACHINE(s); 231 char *name, *cpu_name, *core_name, *intc_name; 232 233 for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { 234 cpu_phandle = (*phandle)++; 235 236 cpu_name = g_strdup_printf("/cpus/cpu@%d", 237 s->soc[socket].hartid_base + cpu); 238 qemu_fdt_add_subnode(mc->fdt, cpu_name); 239 if (riscv_feature(&s->soc[socket].harts[cpu].env, 240 RISCV_FEATURE_MMU)) { 241 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 242 (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); 243 } else { 244 qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", 245 "riscv,none"); 246 } 247 name = riscv_isa_string(&s->soc[socket].harts[cpu]); 248 qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); 249 g_free(name); 250 qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); 251 qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); 252 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", 253 s->soc[socket].hartid_base + cpu); 254 qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); 255 riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); 256 qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); 257 258 intc_phandles[cpu] = (*phandle)++; 259 260 intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); 261 qemu_fdt_add_subnode(mc->fdt, intc_name); 262 qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", 263 intc_phandles[cpu]); 264 qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", 265 "riscv,cpu-intc"); 266 qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); 267 qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); 268 269 core_name = g_strdup_printf("%s/core%d", clust_name, cpu); 270 qemu_fdt_add_subnode(mc->fdt, core_name); 271 qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); 272 273 g_free(core_name); 274 g_free(intc_name); 275 g_free(cpu_name); 276 } 277 } 278 279 static void create_fdt_socket_memory(RISCVVirtState *s, 280 const MemMapEntry *memmap, int socket) 281 { 282 char *mem_name; 283 uint64_t addr, size; 284 MachineState *mc = MACHINE(s); 285 286 addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); 287 size = riscv_socket_mem_size(mc, socket); 288 mem_name = g_strdup_printf("/memory@%lx", (long)addr); 289 qemu_fdt_add_subnode(mc->fdt, mem_name); 290 qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", 291 addr >> 32, addr, size >> 32, size); 292 qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); 293 riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); 294 g_free(mem_name); 295 } 296 297 static void create_fdt_socket_clint(RISCVVirtState *s, 298 const MemMapEntry *memmap, int socket, 299 uint32_t *intc_phandles) 300 { 301 int cpu; 302 char *clint_name; 303 uint32_t *clint_cells; 304 unsigned long clint_addr; 305 MachineState *mc = MACHINE(s); 306 static const char * const clint_compat[2] = { 307 "sifive,clint0", "riscv,clint0" 308 }; 309 310 clint_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 311 312 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 313 clint_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 314 clint_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_SOFT); 315 clint_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 316 clint_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_M_TIMER); 317 } 318 319 clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 320 clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); 321 qemu_fdt_add_subnode(mc->fdt, clint_name); 322 qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", 323 (char **)&clint_compat, 324 ARRAY_SIZE(clint_compat)); 325 qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", 326 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); 327 qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", 328 clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 329 riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); 330 g_free(clint_name); 331 332 g_free(clint_cells); 333 } 334 335 static void create_fdt_socket_aclint(RISCVVirtState *s, 336 const MemMapEntry *memmap, int socket, 337 uint32_t *intc_phandles) 338 { 339 int cpu; 340 char *name; 341 unsigned long addr, size; 342 uint32_t aclint_cells_size; 343 uint32_t *aclint_mswi_cells; 344 uint32_t *aclint_sswi_cells; 345 uint32_t *aclint_mtimer_cells; 346 MachineState *mc = MACHINE(s); 347 348 aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 349 aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 350 aclint_sswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 351 352 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 353 aclint_mswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 354 aclint_mswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_SOFT); 355 aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 356 aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); 357 aclint_sswi_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 358 aclint_sswi_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_SOFT); 359 } 360 aclint_cells_size = s->soc[socket].num_harts * sizeof(uint32_t) * 2; 361 362 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 363 addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); 364 name = g_strdup_printf("/soc/mswi@%lx", addr); 365 qemu_fdt_add_subnode(mc->fdt, name); 366 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 367 "riscv,aclint-mswi"); 368 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 369 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); 370 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 371 aclint_mswi_cells, aclint_cells_size); 372 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 373 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 374 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 375 g_free(name); 376 } 377 378 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 379 addr = memmap[VIRT_CLINT].base + 380 (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); 381 size = RISCV_ACLINT_DEFAULT_MTIMER_SIZE; 382 } else { 383 addr = memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + 384 (memmap[VIRT_CLINT].size * socket); 385 size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; 386 } 387 name = g_strdup_printf("/soc/mtimer@%lx", addr); 388 qemu_fdt_add_subnode(mc->fdt, name); 389 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 390 "riscv,aclint-mtimer"); 391 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 392 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 393 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 394 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 395 0x0, RISCV_ACLINT_DEFAULT_MTIME); 396 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 397 aclint_mtimer_cells, aclint_cells_size); 398 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 399 g_free(name); 400 401 if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { 402 addr = memmap[VIRT_ACLINT_SSWI].base + 403 (memmap[VIRT_ACLINT_SSWI].size * socket); 404 name = g_strdup_printf("/soc/sswi@%lx", addr); 405 qemu_fdt_add_subnode(mc->fdt, name); 406 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 407 "riscv,aclint-sswi"); 408 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 409 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); 410 qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", 411 aclint_sswi_cells, aclint_cells_size); 412 qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); 413 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); 414 riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); 415 g_free(name); 416 } 417 418 g_free(aclint_mswi_cells); 419 g_free(aclint_mtimer_cells); 420 g_free(aclint_sswi_cells); 421 } 422 423 static void create_fdt_socket_plic(RISCVVirtState *s, 424 const MemMapEntry *memmap, int socket, 425 uint32_t *phandle, uint32_t *intc_phandles, 426 uint32_t *plic_phandles) 427 { 428 int cpu; 429 char *plic_name; 430 uint32_t *plic_cells; 431 unsigned long plic_addr; 432 MachineState *mc = MACHINE(s); 433 static const char * const plic_compat[2] = { 434 "sifive,plic-1.0.0", "riscv,plic0" 435 }; 436 437 if (kvm_enabled()) { 438 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 439 } else { 440 plic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 4); 441 } 442 443 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 444 if (kvm_enabled()) { 445 plic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 446 plic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 447 } else { 448 plic_cells[cpu * 4 + 0] = cpu_to_be32(intc_phandles[cpu]); 449 plic_cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); 450 plic_cells[cpu * 4 + 2] = cpu_to_be32(intc_phandles[cpu]); 451 plic_cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); 452 } 453 } 454 455 plic_phandles[socket] = (*phandle)++; 456 plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); 457 plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); 458 qemu_fdt_add_subnode(mc->fdt, plic_name); 459 qemu_fdt_setprop_cell(mc->fdt, plic_name, 460 "#interrupt-cells", FDT_PLIC_INT_CELLS); 461 qemu_fdt_setprop_cell(mc->fdt, plic_name, 462 "#address-cells", FDT_PLIC_ADDR_CELLS); 463 qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", 464 (char **)&plic_compat, 465 ARRAY_SIZE(plic_compat)); 466 qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); 467 qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", 468 plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); 469 qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", 470 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); 471 qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", 472 VIRT_IRQCHIP_NUM_SOURCES - 1); 473 riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); 474 qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", 475 plic_phandles[socket]); 476 477 if (!socket) { 478 platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, 479 memmap[VIRT_PLATFORM_BUS].base, 480 memmap[VIRT_PLATFORM_BUS].size, 481 VIRT_PLATFORM_BUS_IRQ); 482 } 483 484 g_free(plic_name); 485 486 g_free(plic_cells); 487 } 488 489 static uint32_t imsic_num_bits(uint32_t count) 490 { 491 uint32_t ret = 0; 492 493 while (BIT(ret) < count) { 494 ret++; 495 } 496 497 return ret; 498 } 499 500 static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, 501 uint32_t *phandle, uint32_t *intc_phandles, 502 uint32_t *msi_m_phandle, uint32_t *msi_s_phandle) 503 { 504 int cpu, socket; 505 char *imsic_name; 506 MachineState *mc = MACHINE(s); 507 uint32_t imsic_max_hart_per_socket, imsic_guest_bits; 508 uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; 509 510 *msi_m_phandle = (*phandle)++; 511 *msi_s_phandle = (*phandle)++; 512 imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); 513 imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); 514 515 /* M-level IMSIC node */ 516 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 517 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 518 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 519 } 520 imsic_max_hart_per_socket = 0; 521 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 522 imsic_addr = memmap[VIRT_IMSIC_M].base + 523 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 524 imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; 525 imsic_regs[socket * 4 + 0] = 0; 526 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 527 imsic_regs[socket * 4 + 2] = 0; 528 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 529 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 530 imsic_max_hart_per_socket = s->soc[socket].num_harts; 531 } 532 } 533 imsic_name = g_strdup_printf("/soc/imsics@%lx", 534 (unsigned long)memmap[VIRT_IMSIC_M].base); 535 qemu_fdt_add_subnode(mc->fdt, imsic_name); 536 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 537 "riscv,imsics"); 538 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 539 FDT_IMSIC_INT_CELLS); 540 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 541 NULL, 0); 542 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 543 NULL, 0); 544 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 545 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 546 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 547 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 548 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 549 VIRT_IRQCHIP_NUM_MSIS); 550 if (riscv_socket_count(mc) > 1) { 551 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 552 imsic_num_bits(imsic_max_hart_per_socket)); 553 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 554 imsic_num_bits(riscv_socket_count(mc))); 555 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 556 IMSIC_MMIO_GROUP_MIN_SHIFT); 557 } 558 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); 559 560 g_free(imsic_name); 561 562 /* S-level IMSIC node */ 563 for (cpu = 0; cpu < mc->smp.cpus; cpu++) { 564 imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 565 imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 566 } 567 imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); 568 imsic_max_hart_per_socket = 0; 569 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 570 imsic_addr = memmap[VIRT_IMSIC_S].base + 571 socket * VIRT_IMSIC_GROUP_MAX_SIZE; 572 imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * 573 s->soc[socket].num_harts; 574 imsic_regs[socket * 4 + 0] = 0; 575 imsic_regs[socket * 4 + 1] = cpu_to_be32(imsic_addr); 576 imsic_regs[socket * 4 + 2] = 0; 577 imsic_regs[socket * 4 + 3] = cpu_to_be32(imsic_size); 578 if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { 579 imsic_max_hart_per_socket = s->soc[socket].num_harts; 580 } 581 } 582 imsic_name = g_strdup_printf("/soc/imsics@%lx", 583 (unsigned long)memmap[VIRT_IMSIC_S].base); 584 qemu_fdt_add_subnode(mc->fdt, imsic_name); 585 qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", 586 "riscv,imsics"); 587 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", 588 FDT_IMSIC_INT_CELLS); 589 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", 590 NULL, 0); 591 qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", 592 NULL, 0); 593 qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", 594 imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); 595 qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, 596 riscv_socket_count(mc) * sizeof(uint32_t) * 4); 597 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", 598 VIRT_IRQCHIP_NUM_MSIS); 599 if (imsic_guest_bits) { 600 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", 601 imsic_guest_bits); 602 } 603 if (riscv_socket_count(mc) > 1) { 604 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", 605 imsic_num_bits(imsic_max_hart_per_socket)); 606 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", 607 imsic_num_bits(riscv_socket_count(mc))); 608 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", 609 IMSIC_MMIO_GROUP_MIN_SHIFT); 610 } 611 qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); 612 g_free(imsic_name); 613 614 g_free(imsic_regs); 615 g_free(imsic_cells); 616 } 617 618 static void create_fdt_socket_aplic(RISCVVirtState *s, 619 const MemMapEntry *memmap, int socket, 620 uint32_t msi_m_phandle, 621 uint32_t msi_s_phandle, 622 uint32_t *phandle, 623 uint32_t *intc_phandles, 624 uint32_t *aplic_phandles) 625 { 626 int cpu; 627 char *aplic_name; 628 uint32_t *aplic_cells; 629 unsigned long aplic_addr; 630 MachineState *mc = MACHINE(s); 631 uint32_t aplic_m_phandle, aplic_s_phandle; 632 633 aplic_m_phandle = (*phandle)++; 634 aplic_s_phandle = (*phandle)++; 635 aplic_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); 636 637 /* M-level APLIC node */ 638 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 639 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 640 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); 641 } 642 aplic_addr = memmap[VIRT_APLIC_M].base + 643 (memmap[VIRT_APLIC_M].size * socket); 644 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 645 qemu_fdt_add_subnode(mc->fdt, aplic_name); 646 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 647 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 648 "#interrupt-cells", FDT_APLIC_INT_CELLS); 649 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 650 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 651 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 652 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 653 } else { 654 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 655 msi_m_phandle); 656 } 657 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 658 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); 659 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 660 VIRT_IRQCHIP_NUM_SOURCES); 661 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", 662 aplic_s_phandle); 663 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", 664 aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); 665 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 666 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); 667 g_free(aplic_name); 668 669 /* S-level APLIC node */ 670 for (cpu = 0; cpu < s->soc[socket].num_harts; cpu++) { 671 aplic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); 672 aplic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); 673 } 674 aplic_addr = memmap[VIRT_APLIC_S].base + 675 (memmap[VIRT_APLIC_S].size * socket); 676 aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); 677 qemu_fdt_add_subnode(mc->fdt, aplic_name); 678 qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); 679 qemu_fdt_setprop_cell(mc->fdt, aplic_name, 680 "#interrupt-cells", FDT_APLIC_INT_CELLS); 681 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); 682 if (s->aia_type == VIRT_AIA_TYPE_APLIC) { 683 qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", 684 aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); 685 } else { 686 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", 687 msi_s_phandle); 688 } 689 qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 690 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); 691 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", 692 VIRT_IRQCHIP_NUM_SOURCES); 693 riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); 694 qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); 695 696 if (!socket) { 697 platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, 698 memmap[VIRT_PLATFORM_BUS].base, 699 memmap[VIRT_PLATFORM_BUS].size, 700 VIRT_PLATFORM_BUS_IRQ); 701 } 702 703 g_free(aplic_name); 704 705 g_free(aplic_cells); 706 aplic_phandles[socket] = aplic_s_phandle; 707 } 708 709 static void create_fdt_pmu(RISCVVirtState *s) 710 { 711 char *pmu_name; 712 MachineState *mc = MACHINE(s); 713 RISCVCPU hart = s->soc[0].harts[0]; 714 715 pmu_name = g_strdup_printf("/soc/pmu"); 716 qemu_fdt_add_subnode(mc->fdt, pmu_name); 717 qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); 718 riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); 719 720 g_free(pmu_name); 721 } 722 723 static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, 724 bool is_32_bit, uint32_t *phandle, 725 uint32_t *irq_mmio_phandle, 726 uint32_t *irq_pcie_phandle, 727 uint32_t *irq_virtio_phandle, 728 uint32_t *msi_pcie_phandle) 729 { 730 char *clust_name; 731 int socket, phandle_pos; 732 MachineState *mc = MACHINE(s); 733 uint32_t msi_m_phandle = 0, msi_s_phandle = 0; 734 uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; 735 736 qemu_fdt_add_subnode(mc->fdt, "/cpus"); 737 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", 738 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); 739 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); 740 qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); 741 qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); 742 743 intc_phandles = g_new0(uint32_t, mc->smp.cpus); 744 745 phandle_pos = mc->smp.cpus; 746 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 747 phandle_pos -= s->soc[socket].num_harts; 748 749 clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); 750 qemu_fdt_add_subnode(mc->fdt, clust_name); 751 752 create_fdt_socket_cpus(s, socket, clust_name, phandle, 753 is_32_bit, &intc_phandles[phandle_pos]); 754 755 create_fdt_socket_memory(s, memmap, socket); 756 757 g_free(clust_name); 758 759 if (!kvm_enabled()) { 760 if (s->have_aclint) { 761 create_fdt_socket_aclint(s, memmap, socket, 762 &intc_phandles[phandle_pos]); 763 } else { 764 create_fdt_socket_clint(s, memmap, socket, 765 &intc_phandles[phandle_pos]); 766 } 767 } 768 } 769 770 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 771 create_fdt_imsic(s, memmap, phandle, intc_phandles, 772 &msi_m_phandle, &msi_s_phandle); 773 *msi_pcie_phandle = msi_s_phandle; 774 } 775 776 phandle_pos = mc->smp.cpus; 777 for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { 778 phandle_pos -= s->soc[socket].num_harts; 779 780 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 781 create_fdt_socket_plic(s, memmap, socket, phandle, 782 &intc_phandles[phandle_pos], xplic_phandles); 783 } else { 784 create_fdt_socket_aplic(s, memmap, socket, 785 msi_m_phandle, msi_s_phandle, phandle, 786 &intc_phandles[phandle_pos], xplic_phandles); 787 } 788 } 789 790 g_free(intc_phandles); 791 792 for (socket = 0; socket < riscv_socket_count(mc); socket++) { 793 if (socket == 0) { 794 *irq_mmio_phandle = xplic_phandles[socket]; 795 *irq_virtio_phandle = xplic_phandles[socket]; 796 *irq_pcie_phandle = xplic_phandles[socket]; 797 } 798 if (socket == 1) { 799 *irq_virtio_phandle = xplic_phandles[socket]; 800 *irq_pcie_phandle = xplic_phandles[socket]; 801 } 802 if (socket == 2) { 803 *irq_pcie_phandle = xplic_phandles[socket]; 804 } 805 } 806 807 riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); 808 } 809 810 static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, 811 uint32_t irq_virtio_phandle) 812 { 813 int i; 814 char *name; 815 MachineState *mc = MACHINE(s); 816 817 for (i = 0; i < VIRTIO_COUNT; i++) { 818 name = g_strdup_printf("/soc/virtio_mmio@%lx", 819 (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); 820 qemu_fdt_add_subnode(mc->fdt, name); 821 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); 822 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 823 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 824 0x0, memmap[VIRT_VIRTIO].size); 825 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 826 irq_virtio_phandle); 827 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 828 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", 829 VIRTIO_IRQ + i); 830 } else { 831 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", 832 VIRTIO_IRQ + i, 0x4); 833 } 834 g_free(name); 835 } 836 } 837 838 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 839 uint32_t irq_pcie_phandle, 840 uint32_t msi_pcie_phandle) 841 { 842 char *name; 843 MachineState *mc = MACHINE(s); 844 845 name = g_strdup_printf("/soc/pci@%lx", 846 (long) memmap[VIRT_PCIE_ECAM].base); 847 qemu_fdt_add_subnode(mc->fdt, name); 848 qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", 849 FDT_PCI_ADDR_CELLS); 850 qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 851 FDT_PCI_INT_CELLS); 852 qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); 853 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 854 "pci-host-ecam-generic"); 855 qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); 856 qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); 857 qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, 858 memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); 859 qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); 860 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 861 qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); 862 } 863 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, 864 memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); 865 qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", 866 1, FDT_PCI_RANGE_IOPORT, 2, 0, 867 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 868 1, FDT_PCI_RANGE_MMIO, 869 2, memmap[VIRT_PCIE_MMIO].base, 870 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, 871 1, FDT_PCI_RANGE_MMIO_64BIT, 872 2, virt_high_pcie_memmap.base, 873 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); 874 875 create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); 876 g_free(name); 877 } 878 879 static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, 880 uint32_t *phandle) 881 { 882 char *name; 883 uint32_t test_phandle; 884 MachineState *mc = MACHINE(s); 885 886 test_phandle = (*phandle)++; 887 name = g_strdup_printf("/soc/test@%lx", 888 (long)memmap[VIRT_TEST].base); 889 qemu_fdt_add_subnode(mc->fdt, name); 890 { 891 static const char * const compat[3] = { 892 "sifive,test1", "sifive,test0", "syscon" 893 }; 894 qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", 895 (char **)&compat, ARRAY_SIZE(compat)); 896 } 897 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 898 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); 899 qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); 900 test_phandle = qemu_fdt_get_phandle(mc->fdt, name); 901 g_free(name); 902 903 name = g_strdup_printf("/reboot"); 904 qemu_fdt_add_subnode(mc->fdt, name); 905 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); 906 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 907 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 908 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); 909 g_free(name); 910 911 name = g_strdup_printf("/poweroff"); 912 qemu_fdt_add_subnode(mc->fdt, name); 913 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); 914 qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); 915 qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); 916 qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); 917 g_free(name); 918 } 919 920 static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, 921 uint32_t irq_mmio_phandle) 922 { 923 char *name; 924 MachineState *mc = MACHINE(s); 925 926 name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); 927 qemu_fdt_add_subnode(mc->fdt, name); 928 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); 929 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 930 0x0, memmap[VIRT_UART0].base, 931 0x0, memmap[VIRT_UART0].size); 932 qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); 933 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); 934 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 935 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); 936 } else { 937 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); 938 } 939 940 qemu_fdt_add_subnode(mc->fdt, "/chosen"); 941 qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); 942 g_free(name); 943 } 944 945 static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, 946 uint32_t irq_mmio_phandle) 947 { 948 char *name; 949 MachineState *mc = MACHINE(s); 950 951 name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); 952 qemu_fdt_add_subnode(mc->fdt, name); 953 qemu_fdt_setprop_string(mc->fdt, name, "compatible", 954 "google,goldfish-rtc"); 955 qemu_fdt_setprop_cells(mc->fdt, name, "reg", 956 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); 957 qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", 958 irq_mmio_phandle); 959 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 960 qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); 961 } else { 962 qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); 963 } 964 g_free(name); 965 } 966 967 static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) 968 { 969 char *name; 970 MachineState *mc = MACHINE(s); 971 hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; 972 hwaddr flashbase = virt_memmap[VIRT_FLASH].base; 973 974 name = g_strdup_printf("/flash@%" PRIx64, flashbase); 975 qemu_fdt_add_subnode(mc->fdt, name); 976 qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); 977 qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", 978 2, flashbase, 2, flashsize, 979 2, flashbase + flashsize, 2, flashsize); 980 qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); 981 g_free(name); 982 } 983 984 static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) 985 { 986 char *nodename; 987 MachineState *mc = MACHINE(s); 988 hwaddr base = memmap[VIRT_FW_CFG].base; 989 hwaddr size = memmap[VIRT_FW_CFG].size; 990 991 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); 992 qemu_fdt_add_subnode(mc->fdt, nodename); 993 qemu_fdt_setprop_string(mc->fdt, nodename, 994 "compatible", "qemu,fw-cfg-mmio"); 995 qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", 996 2, base, 2, size); 997 qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); 998 g_free(nodename); 999 } 1000 1001 static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, 1002 uint64_t mem_size, const char *cmdline, bool is_32_bit) 1003 { 1004 MachineState *mc = MACHINE(s); 1005 uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; 1006 uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; 1007 uint8_t rng_seed[32]; 1008 1009 if (mc->dtb) { 1010 mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); 1011 if (!mc->fdt) { 1012 error_report("load_device_tree() failed"); 1013 exit(1); 1014 } 1015 goto update_bootargs; 1016 } else { 1017 mc->fdt = create_device_tree(&s->fdt_size); 1018 if (!mc->fdt) { 1019 error_report("create_device_tree() failed"); 1020 exit(1); 1021 } 1022 } 1023 1024 qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); 1025 qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); 1026 qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); 1027 qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); 1028 1029 qemu_fdt_add_subnode(mc->fdt, "/soc"); 1030 qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); 1031 qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); 1032 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); 1033 qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); 1034 1035 create_fdt_sockets(s, memmap, is_32_bit, &phandle, 1036 &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, 1037 &msi_pcie_phandle); 1038 1039 create_fdt_virtio(s, memmap, irq_virtio_phandle); 1040 1041 create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); 1042 1043 create_fdt_reset(s, memmap, &phandle); 1044 1045 create_fdt_uart(s, memmap, irq_mmio_phandle); 1046 1047 create_fdt_rtc(s, memmap, irq_mmio_phandle); 1048 1049 create_fdt_flash(s, memmap); 1050 create_fdt_fw_cfg(s, memmap); 1051 create_fdt_pmu(s); 1052 1053 update_bootargs: 1054 if (cmdline && *cmdline) { 1055 qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); 1056 } 1057 1058 /* Pass seed to RNG */ 1059 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 1060 qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); 1061 } 1062 1063 static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, 1064 hwaddr ecam_base, hwaddr ecam_size, 1065 hwaddr mmio_base, hwaddr mmio_size, 1066 hwaddr high_mmio_base, 1067 hwaddr high_mmio_size, 1068 hwaddr pio_base, 1069 DeviceState *irqchip) 1070 { 1071 DeviceState *dev; 1072 MemoryRegion *ecam_alias, *ecam_reg; 1073 MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; 1074 qemu_irq irq; 1075 int i; 1076 1077 dev = qdev_new(TYPE_GPEX_HOST); 1078 1079 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1080 1081 ecam_alias = g_new0(MemoryRegion, 1); 1082 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 1083 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", 1084 ecam_reg, 0, ecam_size); 1085 memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); 1086 1087 mmio_alias = g_new0(MemoryRegion, 1); 1088 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 1089 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", 1090 mmio_reg, mmio_base, mmio_size); 1091 memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); 1092 1093 /* Map high MMIO space */ 1094 high_mmio_alias = g_new0(MemoryRegion, 1); 1095 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high", 1096 mmio_reg, high_mmio_base, high_mmio_size); 1097 memory_region_add_subregion(get_system_memory(), high_mmio_base, 1098 high_mmio_alias); 1099 1100 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); 1101 1102 for (i = 0; i < GPEX_NUM_IRQS; i++) { 1103 irq = qdev_get_gpio_in(irqchip, PCIE_IRQ + i); 1104 1105 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); 1106 gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); 1107 } 1108 1109 return dev; 1110 } 1111 1112 static FWCfgState *create_fw_cfg(const MachineState *mc) 1113 { 1114 hwaddr base = virt_memmap[VIRT_FW_CFG].base; 1115 FWCfgState *fw_cfg; 1116 1117 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, 1118 &address_space_memory); 1119 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); 1120 1121 return fw_cfg; 1122 } 1123 1124 static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, 1125 int base_hartid, int hart_count) 1126 { 1127 DeviceState *ret; 1128 char *plic_hart_config; 1129 1130 /* Per-socket PLIC hart topology configuration string */ 1131 plic_hart_config = riscv_plic_hart_config_string(hart_count); 1132 1133 /* Per-socket PLIC */ 1134 ret = sifive_plic_create( 1135 memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, 1136 plic_hart_config, hart_count, base_hartid, 1137 VIRT_IRQCHIP_NUM_SOURCES, 1138 ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), 1139 VIRT_PLIC_PRIORITY_BASE, 1140 VIRT_PLIC_PENDING_BASE, 1141 VIRT_PLIC_ENABLE_BASE, 1142 VIRT_PLIC_ENABLE_STRIDE, 1143 VIRT_PLIC_CONTEXT_BASE, 1144 VIRT_PLIC_CONTEXT_STRIDE, 1145 memmap[VIRT_PLIC].size); 1146 1147 g_free(plic_hart_config); 1148 1149 return ret; 1150 } 1151 1152 static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, 1153 const MemMapEntry *memmap, int socket, 1154 int base_hartid, int hart_count) 1155 { 1156 int i; 1157 hwaddr addr; 1158 uint32_t guest_bits; 1159 DeviceState *aplic_m; 1160 bool msimode = (aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) ? true : false; 1161 1162 if (msimode) { 1163 /* Per-socket M-level IMSICs */ 1164 addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1165 for (i = 0; i < hart_count; i++) { 1166 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), 1167 base_hartid + i, true, 1, 1168 VIRT_IRQCHIP_NUM_MSIS); 1169 } 1170 1171 /* Per-socket S-level IMSICs */ 1172 guest_bits = imsic_num_bits(aia_guests + 1); 1173 addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; 1174 for (i = 0; i < hart_count; i++) { 1175 riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), 1176 base_hartid + i, false, 1 + aia_guests, 1177 VIRT_IRQCHIP_NUM_MSIS); 1178 } 1179 } 1180 1181 /* Per-socket M-level APLIC */ 1182 aplic_m = riscv_aplic_create( 1183 memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, 1184 memmap[VIRT_APLIC_M].size, 1185 (msimode) ? 0 : base_hartid, 1186 (msimode) ? 0 : hart_count, 1187 VIRT_IRQCHIP_NUM_SOURCES, 1188 VIRT_IRQCHIP_NUM_PRIO_BITS, 1189 msimode, true, NULL); 1190 1191 if (aplic_m) { 1192 /* Per-socket S-level APLIC */ 1193 riscv_aplic_create( 1194 memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, 1195 memmap[VIRT_APLIC_S].size, 1196 (msimode) ? 0 : base_hartid, 1197 (msimode) ? 0 : hart_count, 1198 VIRT_IRQCHIP_NUM_SOURCES, 1199 VIRT_IRQCHIP_NUM_PRIO_BITS, 1200 msimode, false, aplic_m); 1201 } 1202 1203 return aplic_m; 1204 } 1205 1206 static void create_platform_bus(RISCVVirtState *s, DeviceState *irqchip) 1207 { 1208 DeviceState *dev; 1209 SysBusDevice *sysbus; 1210 const MemMapEntry *memmap = virt_memmap; 1211 int i; 1212 MemoryRegion *sysmem = get_system_memory(); 1213 1214 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 1215 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 1216 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 1217 qdev_prop_set_uint32(dev, "mmio_size", memmap[VIRT_PLATFORM_BUS].size); 1218 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 1219 s->platform_bus_dev = dev; 1220 1221 sysbus = SYS_BUS_DEVICE(dev); 1222 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 1223 int irq = VIRT_PLATFORM_BUS_IRQ + i; 1224 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(irqchip, irq)); 1225 } 1226 1227 memory_region_add_subregion(sysmem, 1228 memmap[VIRT_PLATFORM_BUS].base, 1229 sysbus_mmio_get_region(sysbus, 0)); 1230 } 1231 1232 static void virt_machine_done(Notifier *notifier, void *data) 1233 { 1234 RISCVVirtState *s = container_of(notifier, RISCVVirtState, 1235 machine_done); 1236 const MemMapEntry *memmap = virt_memmap; 1237 MachineState *machine = MACHINE(s); 1238 target_ulong start_addr = memmap[VIRT_DRAM].base; 1239 target_ulong firmware_end_addr, kernel_start_addr; 1240 uint32_t fdt_load_addr; 1241 uint64_t kernel_entry; 1242 1243 /* 1244 * Only direct boot kernel is currently supported for KVM VM, 1245 * so the "-bios" parameter is not supported when KVM is enabled. 1246 */ 1247 if (kvm_enabled()) { 1248 if (machine->firmware) { 1249 if (strcmp(machine->firmware, "none")) { 1250 error_report("Machine mode firmware is not supported in " 1251 "combination with KVM."); 1252 exit(1); 1253 } 1254 } else { 1255 machine->firmware = g_strdup("none"); 1256 } 1257 } 1258 1259 if (riscv_is_32bit(&s->soc[0])) { 1260 firmware_end_addr = riscv_find_and_load_firmware(machine, 1261 RISCV32_BIOS_BIN, start_addr, NULL); 1262 } else { 1263 firmware_end_addr = riscv_find_and_load_firmware(machine, 1264 RISCV64_BIOS_BIN, start_addr, NULL); 1265 } 1266 1267 /* 1268 * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device 1269 * tree cannot be altered and we get FDT_ERR_NOSPACE. 1270 */ 1271 s->fw_cfg = create_fw_cfg(machine); 1272 rom_set_fw(s->fw_cfg); 1273 1274 if (drive_get(IF_PFLASH, 0, 1)) { 1275 /* 1276 * S-mode FW like EDK2 will be kept in second plash (unit 1). 1277 * When both kernel, initrd and pflash options are provided in the 1278 * command line, the kernel and initrd will be copied to the fw_cfg 1279 * table and opensbi will jump to the flash address which is the 1280 * entry point of S-mode FW. It is the job of the S-mode FW to load 1281 * the kernel and initrd using fw_cfg table. 1282 * 1283 * If only pflash is given but not -kernel, then it is the job of 1284 * of the S-mode firmware to locate and load the kernel. 1285 * In either case, the next_addr for opensbi will be the flash address. 1286 */ 1287 riscv_setup_firmware_boot(machine); 1288 kernel_entry = virt_memmap[VIRT_FLASH].base + 1289 virt_memmap[VIRT_FLASH].size / 2; 1290 } else if (machine->kernel_filename) { 1291 kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], 1292 firmware_end_addr); 1293 1294 kernel_entry = riscv_load_kernel(machine->kernel_filename, 1295 kernel_start_addr, NULL); 1296 1297 if (machine->initrd_filename) { 1298 hwaddr start; 1299 hwaddr end = riscv_load_initrd(machine->initrd_filename, 1300 machine->ram_size, kernel_entry, 1301 &start); 1302 qemu_fdt_setprop_cell(machine->fdt, "/chosen", 1303 "linux,initrd-start", start); 1304 qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", 1305 end); 1306 } 1307 } else { 1308 /* 1309 * If dynamic firmware is used, it doesn't know where is the next mode 1310 * if kernel argument is not set. 1311 */ 1312 kernel_entry = 0; 1313 } 1314 1315 if (drive_get(IF_PFLASH, 0, 0)) { 1316 /* 1317 * Pflash was supplied, let's overwrite the address we jump to after 1318 * reset to the base of the flash. 1319 */ 1320 start_addr = virt_memmap[VIRT_FLASH].base; 1321 } 1322 1323 /* Compute the fdt load address in dram */ 1324 fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, 1325 machine->ram_size, machine->fdt); 1326 /* load the reset vector */ 1327 riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, 1328 virt_memmap[VIRT_MROM].base, 1329 virt_memmap[VIRT_MROM].size, kernel_entry, 1330 fdt_load_addr); 1331 1332 /* 1333 * Only direct boot kernel is currently supported for KVM VM, 1334 * So here setup kernel start address and fdt address. 1335 * TODO:Support firmware loading and integrate to TCG start 1336 */ 1337 if (kvm_enabled()) { 1338 riscv_setup_direct_kernel(kernel_entry, fdt_load_addr); 1339 } 1340 } 1341 1342 static void virt_machine_init(MachineState *machine) 1343 { 1344 const MemMapEntry *memmap = virt_memmap; 1345 RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); 1346 MemoryRegion *system_memory = get_system_memory(); 1347 MemoryRegion *mask_rom = g_new(MemoryRegion, 1); 1348 char *soc_name; 1349 DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; 1350 int i, base_hartid, hart_count; 1351 1352 /* Check socket count limit */ 1353 if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { 1354 error_report("number of sockets/nodes should be less than %d", 1355 VIRT_SOCKETS_MAX); 1356 exit(1); 1357 } 1358 1359 /* Initialize sockets */ 1360 mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; 1361 for (i = 0; i < riscv_socket_count(machine); i++) { 1362 if (!riscv_socket_check_hartids(machine, i)) { 1363 error_report("discontinuous hartids in socket%d", i); 1364 exit(1); 1365 } 1366 1367 base_hartid = riscv_socket_first_hartid(machine, i); 1368 if (base_hartid < 0) { 1369 error_report("can't find hartid base for socket%d", i); 1370 exit(1); 1371 } 1372 1373 hart_count = riscv_socket_hart_count(machine, i); 1374 if (hart_count < 0) { 1375 error_report("can't find hart count for socket%d", i); 1376 exit(1); 1377 } 1378 1379 soc_name = g_strdup_printf("soc%d", i); 1380 object_initialize_child(OBJECT(machine), soc_name, &s->soc[i], 1381 TYPE_RISCV_HART_ARRAY); 1382 g_free(soc_name); 1383 object_property_set_str(OBJECT(&s->soc[i]), "cpu-type", 1384 machine->cpu_type, &error_abort); 1385 object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", 1386 base_hartid, &error_abort); 1387 object_property_set_int(OBJECT(&s->soc[i]), "num-harts", 1388 hart_count, &error_abort); 1389 sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); 1390 1391 if (!kvm_enabled()) { 1392 if (s->have_aclint) { 1393 if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { 1394 /* Per-socket ACLINT MTIMER */ 1395 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1396 i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1397 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1398 base_hartid, hart_count, 1399 RISCV_ACLINT_DEFAULT_MTIMECMP, 1400 RISCV_ACLINT_DEFAULT_MTIME, 1401 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1402 } else { 1403 /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ 1404 riscv_aclint_swi_create(memmap[VIRT_CLINT].base + 1405 i * memmap[VIRT_CLINT].size, 1406 base_hartid, hart_count, false); 1407 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1408 i * memmap[VIRT_CLINT].size + 1409 RISCV_ACLINT_SWI_SIZE, 1410 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, 1411 base_hartid, hart_count, 1412 RISCV_ACLINT_DEFAULT_MTIMECMP, 1413 RISCV_ACLINT_DEFAULT_MTIME, 1414 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1415 riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + 1416 i * memmap[VIRT_ACLINT_SSWI].size, 1417 base_hartid, hart_count, true); 1418 } 1419 } else { 1420 /* Per-socket SiFive CLINT */ 1421 riscv_aclint_swi_create( 1422 memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, 1423 base_hartid, hart_count, false); 1424 riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + 1425 i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZE, 1426 RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, 1427 RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, 1428 RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); 1429 } 1430 } 1431 1432 /* Per-socket interrupt controller */ 1433 if (s->aia_type == VIRT_AIA_TYPE_NONE) { 1434 s->irqchip[i] = virt_create_plic(memmap, i, 1435 base_hartid, hart_count); 1436 } else { 1437 s->irqchip[i] = virt_create_aia(s->aia_type, s->aia_guests, 1438 memmap, i, base_hartid, 1439 hart_count); 1440 } 1441 1442 /* Try to use different IRQCHIP instance based device type */ 1443 if (i == 0) { 1444 mmio_irqchip = s->irqchip[i]; 1445 virtio_irqchip = s->irqchip[i]; 1446 pcie_irqchip = s->irqchip[i]; 1447 } 1448 if (i == 1) { 1449 virtio_irqchip = s->irqchip[i]; 1450 pcie_irqchip = s->irqchip[i]; 1451 } 1452 if (i == 2) { 1453 pcie_irqchip = s->irqchip[i]; 1454 } 1455 } 1456 1457 if (riscv_is_32bit(&s->soc[0])) { 1458 #if HOST_LONG_BITS == 64 1459 /* limit RAM size in a 32-bit system */ 1460 if (machine->ram_size > 10 * GiB) { 1461 machine->ram_size = 10 * GiB; 1462 error_report("Limiting RAM size to 10 GiB"); 1463 } 1464 #endif 1465 virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE; 1466 virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE; 1467 } else { 1468 virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE; 1469 virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size; 1470 virt_high_pcie_memmap.base = 1471 ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size); 1472 } 1473 1474 /* register system main memory (actual RAM) */ 1475 memory_region_add_subregion(system_memory, memmap[VIRT_DRAM].base, 1476 machine->ram); 1477 1478 /* boot rom */ 1479 memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", 1480 memmap[VIRT_MROM].size, &error_fatal); 1481 memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, 1482 mask_rom); 1483 1484 /* SiFive Test MMIO device */ 1485 sifive_test_create(memmap[VIRT_TEST].base); 1486 1487 /* VirtIO MMIO devices */ 1488 for (i = 0; i < VIRTIO_COUNT; i++) { 1489 sysbus_create_simple("virtio-mmio", 1490 memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 1491 qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); 1492 } 1493 1494 gpex_pcie_init(system_memory, 1495 memmap[VIRT_PCIE_ECAM].base, 1496 memmap[VIRT_PCIE_ECAM].size, 1497 memmap[VIRT_PCIE_MMIO].base, 1498 memmap[VIRT_PCIE_MMIO].size, 1499 virt_high_pcie_memmap.base, 1500 virt_high_pcie_memmap.size, 1501 memmap[VIRT_PCIE_PIO].base, 1502 DEVICE(pcie_irqchip)); 1503 1504 create_platform_bus(s, DEVICE(mmio_irqchip)); 1505 1506 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 1507 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, 1508 serial_hd(0), DEVICE_LITTLE_ENDIAN); 1509 1510 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, 1511 qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); 1512 1513 virt_flash_create(s); 1514 1515 for (i = 0; i < ARRAY_SIZE(s->flash); i++) { 1516 /* Map legacy -drive if=pflash to machine properties */ 1517 pflash_cfi01_legacy_drive(s->flash[i], 1518 drive_get(IF_PFLASH, 0, i)); 1519 } 1520 virt_flash_map(s, system_memory); 1521 1522 /* create device tree */ 1523 create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, 1524 riscv_is_32bit(&s->soc[0])); 1525 1526 s->machine_done.notify = virt_machine_done; 1527 qemu_add_machine_init_done_notifier(&s->machine_done); 1528 } 1529 1530 static void virt_machine_instance_init(Object *obj) 1531 { 1532 } 1533 1534 static char *virt_get_aia_guests(Object *obj, Error **errp) 1535 { 1536 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1537 char val[32]; 1538 1539 sprintf(val, "%d", s->aia_guests); 1540 return g_strdup(val); 1541 } 1542 1543 static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) 1544 { 1545 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1546 1547 s->aia_guests = atoi(val); 1548 if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { 1549 error_setg(errp, "Invalid number of AIA IMSIC guests"); 1550 error_append_hint(errp, "Valid values be between 0 and %d.\n", 1551 VIRT_IRQCHIP_MAX_GUESTS); 1552 } 1553 } 1554 1555 static char *virt_get_aia(Object *obj, Error **errp) 1556 { 1557 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1558 const char *val; 1559 1560 switch (s->aia_type) { 1561 case VIRT_AIA_TYPE_APLIC: 1562 val = "aplic"; 1563 break; 1564 case VIRT_AIA_TYPE_APLIC_IMSIC: 1565 val = "aplic-imsic"; 1566 break; 1567 default: 1568 val = "none"; 1569 break; 1570 }; 1571 1572 return g_strdup(val); 1573 } 1574 1575 static void virt_set_aia(Object *obj, const char *val, Error **errp) 1576 { 1577 RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); 1578 1579 if (!strcmp(val, "none")) { 1580 s->aia_type = VIRT_AIA_TYPE_NONE; 1581 } else if (!strcmp(val, "aplic")) { 1582 s->aia_type = VIRT_AIA_TYPE_APLIC; 1583 } else if (!strcmp(val, "aplic-imsic")) { 1584 s->aia_type = VIRT_AIA_TYPE_APLIC_IMSIC; 1585 } else { 1586 error_setg(errp, "Invalid AIA interrupt controller type"); 1587 error_append_hint(errp, "Valid values are none, aplic, and " 1588 "aplic-imsic.\n"); 1589 } 1590 } 1591 1592 static bool virt_get_aclint(Object *obj, Error **errp) 1593 { 1594 MachineState *ms = MACHINE(obj); 1595 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1596 1597 return s->have_aclint; 1598 } 1599 1600 static void virt_set_aclint(Object *obj, bool value, Error **errp) 1601 { 1602 MachineState *ms = MACHINE(obj); 1603 RISCVVirtState *s = RISCV_VIRT_MACHINE(ms); 1604 1605 s->have_aclint = value; 1606 } 1607 1608 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1609 DeviceState *dev) 1610 { 1611 MachineClass *mc = MACHINE_GET_CLASS(machine); 1612 1613 if (device_is_dynamic_sysbus(mc, dev)) { 1614 return HOTPLUG_HANDLER(machine); 1615 } 1616 return NULL; 1617 } 1618 1619 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1620 DeviceState *dev, Error **errp) 1621 { 1622 RISCVVirtState *s = RISCV_VIRT_MACHINE(hotplug_dev); 1623 1624 if (s->platform_bus_dev) { 1625 MachineClass *mc = MACHINE_GET_CLASS(s); 1626 1627 if (device_is_dynamic_sysbus(mc, dev)) { 1628 platform_bus_link_device(PLATFORM_BUS_DEVICE(s->platform_bus_dev), 1629 SYS_BUS_DEVICE(dev)); 1630 } 1631 } 1632 } 1633 1634 static void virt_machine_class_init(ObjectClass *oc, void *data) 1635 { 1636 char str[128]; 1637 MachineClass *mc = MACHINE_CLASS(oc); 1638 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1639 1640 mc->desc = "RISC-V VirtIO board"; 1641 mc->init = virt_machine_init; 1642 mc->max_cpus = VIRT_CPUS_MAX; 1643 mc->default_cpu_type = TYPE_RISCV_CPU_BASE; 1644 mc->pci_allow_0_address = true; 1645 mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids; 1646 mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props; 1647 mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id; 1648 mc->numa_mem_supported = true; 1649 mc->default_ram_id = "riscv_virt_board.ram"; 1650 assert(!mc->get_hotplug_handler); 1651 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1652 1653 hc->plug = virt_machine_device_plug_cb; 1654 1655 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1656 #ifdef CONFIG_TPM 1657 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1658 #endif 1659 1660 object_class_property_add_bool(oc, "aclint", virt_get_aclint, 1661 virt_set_aclint); 1662 object_class_property_set_description(oc, "aclint", 1663 "Set on/off to enable/disable " 1664 "emulating ACLINT devices"); 1665 1666 object_class_property_add_str(oc, "aia", virt_get_aia, 1667 virt_set_aia); 1668 object_class_property_set_description(oc, "aia", 1669 "Set type of AIA interrupt " 1670 "conttoller. Valid values are " 1671 "none, aplic, and aplic-imsic."); 1672 1673 object_class_property_add_str(oc, "aia-guests", 1674 virt_get_aia_guests, 1675 virt_set_aia_guests); 1676 sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid value " 1677 "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); 1678 object_class_property_set_description(oc, "aia-guests", str); 1679 } 1680 1681 static const TypeInfo virt_machine_typeinfo = { 1682 .name = MACHINE_TYPE_NAME("virt"), 1683 .parent = TYPE_MACHINE, 1684 .class_init = virt_machine_class_init, 1685 .instance_init = virt_machine_instance_init, 1686 .instance_size = sizeof(RISCVVirtState), 1687 .interfaces = (InterfaceInfo[]) { 1688 { TYPE_HOTPLUG_HANDLER }, 1689 { } 1690 }, 1691 }; 1692 1693 static void virt_machine_init_register_types(void) 1694 { 1695 type_register_static(&virt_machine_typeinfo); 1696 } 1697 1698 type_init(virt_machine_init_register_types) 1699