1819ce6b2SPhilippe Mathieu-Daudé /* 2819ce6b2SPhilippe Mathieu-Daudé * QEMU M48T59 and M48T08 NVRAM emulation (ISA bus interface) 3819ce6b2SPhilippe Mathieu-Daudé * 4819ce6b2SPhilippe Mathieu-Daudé * Copyright (c) 2003-2005, 2007 Jocelyn Mayer 5819ce6b2SPhilippe Mathieu-Daudé * Copyright (c) 2013 Hervé Poussineau 6819ce6b2SPhilippe Mathieu-Daudé * 7819ce6b2SPhilippe Mathieu-Daudé * Permission is hereby granted, free of charge, to any person obtaining a copy 8819ce6b2SPhilippe Mathieu-Daudé * of this software and associated documentation files (the "Software"), to deal 9819ce6b2SPhilippe Mathieu-Daudé * in the Software without restriction, including without limitation the rights 10819ce6b2SPhilippe Mathieu-Daudé * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11819ce6b2SPhilippe Mathieu-Daudé * copies of the Software, and to permit persons to whom the Software is 12819ce6b2SPhilippe Mathieu-Daudé * furnished to do so, subject to the following conditions: 13819ce6b2SPhilippe Mathieu-Daudé * 14819ce6b2SPhilippe Mathieu-Daudé * The above copyright notice and this permission notice shall be included in 15819ce6b2SPhilippe Mathieu-Daudé * all copies or substantial portions of the Software. 16819ce6b2SPhilippe Mathieu-Daudé * 17819ce6b2SPhilippe Mathieu-Daudé * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18819ce6b2SPhilippe Mathieu-Daudé * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19819ce6b2SPhilippe Mathieu-Daudé * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20819ce6b2SPhilippe Mathieu-Daudé * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21819ce6b2SPhilippe Mathieu-Daudé * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22819ce6b2SPhilippe Mathieu-Daudé * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23819ce6b2SPhilippe Mathieu-Daudé * THE SOFTWARE. 24819ce6b2SPhilippe Mathieu-Daudé */ 25819ce6b2SPhilippe Mathieu-Daudé 26819ce6b2SPhilippe Mathieu-Daudé #include "qemu/osdep.h" 27819ce6b2SPhilippe Mathieu-Daudé #include "hw/isa/isa.h" 28819ce6b2SPhilippe Mathieu-Daudé #include "hw/qdev-properties.h" 29819ce6b2SPhilippe Mathieu-Daudé #include "hw/rtc/m48t59.h" 30819ce6b2SPhilippe Mathieu-Daudé #include "m48t59-internal.h" 3196927c74SMarkus Armbruster #include "qapi/error.h" 32819ce6b2SPhilippe Mathieu-Daudé #include "qemu/module.h" 33*db1015e9SEduardo Habkost #include "qom/object.h" 34819ce6b2SPhilippe Mathieu-Daudé 35819ce6b2SPhilippe Mathieu-Daudé #define TYPE_M48TXX_ISA "isa-m48txx" 36*db1015e9SEduardo Habkost typedef struct M48txxISADeviceClass M48txxISADeviceClass; 37*db1015e9SEduardo Habkost typedef struct M48txxISAState M48txxISAState; 38819ce6b2SPhilippe Mathieu-Daudé #define M48TXX_ISA_GET_CLASS(obj) \ 39819ce6b2SPhilippe Mathieu-Daudé OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA) 40819ce6b2SPhilippe Mathieu-Daudé #define M48TXX_ISA_CLASS(klass) \ 41819ce6b2SPhilippe Mathieu-Daudé OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA) 42819ce6b2SPhilippe Mathieu-Daudé #define M48TXX_ISA(obj) \ 43819ce6b2SPhilippe Mathieu-Daudé OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA) 44819ce6b2SPhilippe Mathieu-Daudé 45*db1015e9SEduardo Habkost struct M48txxISAState { 46819ce6b2SPhilippe Mathieu-Daudé ISADevice parent_obj; 47819ce6b2SPhilippe Mathieu-Daudé M48t59State state; 48819ce6b2SPhilippe Mathieu-Daudé uint32_t io_base; 49819ce6b2SPhilippe Mathieu-Daudé MemoryRegion io; 50*db1015e9SEduardo Habkost }; 51819ce6b2SPhilippe Mathieu-Daudé 52*db1015e9SEduardo Habkost struct M48txxISADeviceClass { 53819ce6b2SPhilippe Mathieu-Daudé ISADeviceClass parent_class; 54819ce6b2SPhilippe Mathieu-Daudé M48txxInfo info; 55*db1015e9SEduardo Habkost }; 56819ce6b2SPhilippe Mathieu-Daudé 57819ce6b2SPhilippe Mathieu-Daudé static M48txxInfo m48txx_isa_info[] = { 58819ce6b2SPhilippe Mathieu-Daudé { 59819ce6b2SPhilippe Mathieu-Daudé .bus_name = "isa-m48t59", 60819ce6b2SPhilippe Mathieu-Daudé .model = 59, 61819ce6b2SPhilippe Mathieu-Daudé .size = 0x2000, 62819ce6b2SPhilippe Mathieu-Daudé } 63819ce6b2SPhilippe Mathieu-Daudé }; 64819ce6b2SPhilippe Mathieu-Daudé 65819ce6b2SPhilippe Mathieu-Daudé Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, 66819ce6b2SPhilippe Mathieu-Daudé int base_year, int model) 67819ce6b2SPhilippe Mathieu-Daudé { 6896927c74SMarkus Armbruster ISADevice *isa_dev; 69819ce6b2SPhilippe Mathieu-Daudé DeviceState *dev; 70819ce6b2SPhilippe Mathieu-Daudé int i; 71819ce6b2SPhilippe Mathieu-Daudé 72819ce6b2SPhilippe Mathieu-Daudé for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 73819ce6b2SPhilippe Mathieu-Daudé if (m48txx_isa_info[i].size != size || 74819ce6b2SPhilippe Mathieu-Daudé m48txx_isa_info[i].model != model) { 75819ce6b2SPhilippe Mathieu-Daudé continue; 76819ce6b2SPhilippe Mathieu-Daudé } 77819ce6b2SPhilippe Mathieu-Daudé 7896927c74SMarkus Armbruster isa_dev = isa_new(m48txx_isa_info[i].bus_name); 7996927c74SMarkus Armbruster dev = DEVICE(isa_dev); 80819ce6b2SPhilippe Mathieu-Daudé qdev_prop_set_uint32(dev, "iobase", io_base); 81819ce6b2SPhilippe Mathieu-Daudé qdev_prop_set_int32(dev, "base-year", base_year); 8296927c74SMarkus Armbruster isa_realize_and_unref(isa_dev, bus, &error_fatal); 83819ce6b2SPhilippe Mathieu-Daudé return NVRAM(dev); 84819ce6b2SPhilippe Mathieu-Daudé } 85819ce6b2SPhilippe Mathieu-Daudé 86819ce6b2SPhilippe Mathieu-Daudé assert(false); 87819ce6b2SPhilippe Mathieu-Daudé return NULL; 88819ce6b2SPhilippe Mathieu-Daudé } 89819ce6b2SPhilippe Mathieu-Daudé 90819ce6b2SPhilippe Mathieu-Daudé static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr) 91819ce6b2SPhilippe Mathieu-Daudé { 92819ce6b2SPhilippe Mathieu-Daudé M48txxISAState *d = M48TXX_ISA(obj); 93819ce6b2SPhilippe Mathieu-Daudé return m48t59_read(&d->state, addr); 94819ce6b2SPhilippe Mathieu-Daudé } 95819ce6b2SPhilippe Mathieu-Daudé 96819ce6b2SPhilippe Mathieu-Daudé static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val) 97819ce6b2SPhilippe Mathieu-Daudé { 98819ce6b2SPhilippe Mathieu-Daudé M48txxISAState *d = M48TXX_ISA(obj); 99819ce6b2SPhilippe Mathieu-Daudé m48t59_write(&d->state, addr, val); 100819ce6b2SPhilippe Mathieu-Daudé } 101819ce6b2SPhilippe Mathieu-Daudé 102819ce6b2SPhilippe Mathieu-Daudé static void m48txx_isa_toggle_lock(Nvram *obj, int lock) 103819ce6b2SPhilippe Mathieu-Daudé { 104819ce6b2SPhilippe Mathieu-Daudé M48txxISAState *d = M48TXX_ISA(obj); 105819ce6b2SPhilippe Mathieu-Daudé m48t59_toggle_lock(&d->state, lock); 106819ce6b2SPhilippe Mathieu-Daudé } 107819ce6b2SPhilippe Mathieu-Daudé 108819ce6b2SPhilippe Mathieu-Daudé static Property m48t59_isa_properties[] = { 109819ce6b2SPhilippe Mathieu-Daudé DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), 110819ce6b2SPhilippe Mathieu-Daudé DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), 111819ce6b2SPhilippe Mathieu-Daudé DEFINE_PROP_END_OF_LIST(), 112819ce6b2SPhilippe Mathieu-Daudé }; 113819ce6b2SPhilippe Mathieu-Daudé 114819ce6b2SPhilippe Mathieu-Daudé static void m48t59_reset_isa(DeviceState *d) 115819ce6b2SPhilippe Mathieu-Daudé { 116819ce6b2SPhilippe Mathieu-Daudé M48txxISAState *isa = M48TXX_ISA(d); 117819ce6b2SPhilippe Mathieu-Daudé M48t59State *NVRAM = &isa->state; 118819ce6b2SPhilippe Mathieu-Daudé 119819ce6b2SPhilippe Mathieu-Daudé m48t59_reset_common(NVRAM); 120819ce6b2SPhilippe Mathieu-Daudé } 121819ce6b2SPhilippe Mathieu-Daudé 122819ce6b2SPhilippe Mathieu-Daudé static void m48t59_isa_realize(DeviceState *dev, Error **errp) 123819ce6b2SPhilippe Mathieu-Daudé { 124819ce6b2SPhilippe Mathieu-Daudé M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev); 125819ce6b2SPhilippe Mathieu-Daudé ISADevice *isadev = ISA_DEVICE(dev); 126819ce6b2SPhilippe Mathieu-Daudé M48txxISAState *d = M48TXX_ISA(dev); 127819ce6b2SPhilippe Mathieu-Daudé M48t59State *s = &d->state; 128819ce6b2SPhilippe Mathieu-Daudé 129819ce6b2SPhilippe Mathieu-Daudé s->model = u->info.model; 130819ce6b2SPhilippe Mathieu-Daudé s->size = u->info.size; 131819ce6b2SPhilippe Mathieu-Daudé isa_init_irq(isadev, &s->IRQ, 8); 132819ce6b2SPhilippe Mathieu-Daudé m48t59_realize_common(s, errp); 133819ce6b2SPhilippe Mathieu-Daudé memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4); 134819ce6b2SPhilippe Mathieu-Daudé if (d->io_base != 0) { 135819ce6b2SPhilippe Mathieu-Daudé isa_register_ioport(isadev, &d->io, d->io_base); 136819ce6b2SPhilippe Mathieu-Daudé } 137819ce6b2SPhilippe Mathieu-Daudé } 138819ce6b2SPhilippe Mathieu-Daudé 139819ce6b2SPhilippe Mathieu-Daudé static void m48txx_isa_class_init(ObjectClass *klass, void *data) 140819ce6b2SPhilippe Mathieu-Daudé { 141819ce6b2SPhilippe Mathieu-Daudé DeviceClass *dc = DEVICE_CLASS(klass); 142819ce6b2SPhilippe Mathieu-Daudé NvramClass *nc = NVRAM_CLASS(klass); 143819ce6b2SPhilippe Mathieu-Daudé 144819ce6b2SPhilippe Mathieu-Daudé dc->realize = m48t59_isa_realize; 145819ce6b2SPhilippe Mathieu-Daudé dc->reset = m48t59_reset_isa; 1464f67d30bSMarc-André Lureau device_class_set_props(dc, m48t59_isa_properties); 147819ce6b2SPhilippe Mathieu-Daudé nc->read = m48txx_isa_read; 148819ce6b2SPhilippe Mathieu-Daudé nc->write = m48txx_isa_write; 149819ce6b2SPhilippe Mathieu-Daudé nc->toggle_lock = m48txx_isa_toggle_lock; 150819ce6b2SPhilippe Mathieu-Daudé } 151819ce6b2SPhilippe Mathieu-Daudé 152819ce6b2SPhilippe Mathieu-Daudé static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data) 153819ce6b2SPhilippe Mathieu-Daudé { 154819ce6b2SPhilippe Mathieu-Daudé M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass); 155819ce6b2SPhilippe Mathieu-Daudé M48txxInfo *info = data; 156819ce6b2SPhilippe Mathieu-Daudé 157819ce6b2SPhilippe Mathieu-Daudé u->info = *info; 158819ce6b2SPhilippe Mathieu-Daudé } 159819ce6b2SPhilippe Mathieu-Daudé 160819ce6b2SPhilippe Mathieu-Daudé static const TypeInfo m48txx_isa_type_info = { 161819ce6b2SPhilippe Mathieu-Daudé .name = TYPE_M48TXX_ISA, 162819ce6b2SPhilippe Mathieu-Daudé .parent = TYPE_ISA_DEVICE, 163819ce6b2SPhilippe Mathieu-Daudé .instance_size = sizeof(M48txxISAState), 164819ce6b2SPhilippe Mathieu-Daudé .abstract = true, 165819ce6b2SPhilippe Mathieu-Daudé .class_init = m48txx_isa_class_init, 166819ce6b2SPhilippe Mathieu-Daudé .interfaces = (InterfaceInfo[]) { 167819ce6b2SPhilippe Mathieu-Daudé { TYPE_NVRAM }, 168819ce6b2SPhilippe Mathieu-Daudé { } 169819ce6b2SPhilippe Mathieu-Daudé } 170819ce6b2SPhilippe Mathieu-Daudé }; 171819ce6b2SPhilippe Mathieu-Daudé 172819ce6b2SPhilippe Mathieu-Daudé static void m48t59_isa_register_types(void) 173819ce6b2SPhilippe Mathieu-Daudé { 174819ce6b2SPhilippe Mathieu-Daudé TypeInfo isa_type_info = { 175819ce6b2SPhilippe Mathieu-Daudé .parent = TYPE_M48TXX_ISA, 176819ce6b2SPhilippe Mathieu-Daudé .class_size = sizeof(M48txxISADeviceClass), 177819ce6b2SPhilippe Mathieu-Daudé .class_init = m48txx_isa_concrete_class_init, 178819ce6b2SPhilippe Mathieu-Daudé }; 179819ce6b2SPhilippe Mathieu-Daudé int i; 180819ce6b2SPhilippe Mathieu-Daudé 181819ce6b2SPhilippe Mathieu-Daudé type_register_static(&m48txx_isa_type_info); 182819ce6b2SPhilippe Mathieu-Daudé 183819ce6b2SPhilippe Mathieu-Daudé for (i = 0; i < ARRAY_SIZE(m48txx_isa_info); i++) { 184819ce6b2SPhilippe Mathieu-Daudé isa_type_info.name = m48txx_isa_info[i].bus_name; 185819ce6b2SPhilippe Mathieu-Daudé isa_type_info.class_data = &m48txx_isa_info[i]; 186819ce6b2SPhilippe Mathieu-Daudé type_register(&isa_type_info); 187819ce6b2SPhilippe Mathieu-Daudé } 188819ce6b2SPhilippe Mathieu-Daudé } 189819ce6b2SPhilippe Mathieu-Daudé 190819ce6b2SPhilippe Mathieu-Daudé type_init(m48t59_isa_register_types) 191