1 /* 2 * Channel subsystem base support. 3 * 4 * Copyright 2012 IBM Corp. 5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com> 6 * 7 * This work is licensed under the terms of the GNU GPL, version 2 or (at 8 * your option) any later version. See the COPYING file in the top-level 9 * directory. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "qapi/error.h" 14 #include "qapi/visitor.h" 15 #include "qemu/bitops.h" 16 #include "qemu/error-report.h" 17 #include "exec/address-spaces.h" 18 #include "hw/s390x/ioinst.h" 19 #include "hw/qdev-properties.h" 20 #include "hw/s390x/css.h" 21 #include "trace.h" 22 #include "hw/s390x/s390_flic.h" 23 #include "hw/s390x/s390-virtio-ccw.h" 24 #include "hw/s390x/s390-ccw.h" 25 26 typedef struct CrwContainer { 27 CRW crw; 28 QTAILQ_ENTRY(CrwContainer) sibling; 29 } CrwContainer; 30 31 static const VMStateDescription vmstate_crw = { 32 .name = "s390_crw", 33 .version_id = 1, 34 .minimum_version_id = 1, 35 .fields = (VMStateField[]) { 36 VMSTATE_UINT16(flags, CRW), 37 VMSTATE_UINT16(rsid, CRW), 38 VMSTATE_END_OF_LIST() 39 }, 40 }; 41 42 static const VMStateDescription vmstate_crw_container = { 43 .name = "s390_crw_container", 44 .version_id = 1, 45 .minimum_version_id = 1, 46 .fields = (VMStateField[]) { 47 VMSTATE_STRUCT(crw, CrwContainer, 0, vmstate_crw, CRW), 48 VMSTATE_END_OF_LIST() 49 }, 50 }; 51 52 typedef struct ChpInfo { 53 uint8_t in_use; 54 uint8_t type; 55 uint8_t is_virtual; 56 } ChpInfo; 57 58 static const VMStateDescription vmstate_chp_info = { 59 .name = "s390_chp_info", 60 .version_id = 1, 61 .minimum_version_id = 1, 62 .fields = (VMStateField[]) { 63 VMSTATE_UINT8(in_use, ChpInfo), 64 VMSTATE_UINT8(type, ChpInfo), 65 VMSTATE_UINT8(is_virtual, ChpInfo), 66 VMSTATE_END_OF_LIST() 67 } 68 }; 69 70 typedef struct SubchSet { 71 SubchDev *sch[MAX_SCHID + 1]; 72 unsigned long schids_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 73 unsigned long devnos_used[BITS_TO_LONGS(MAX_SCHID + 1)]; 74 } SubchSet; 75 76 static const VMStateDescription vmstate_scsw = { 77 .name = "s390_scsw", 78 .version_id = 1, 79 .minimum_version_id = 1, 80 .fields = (VMStateField[]) { 81 VMSTATE_UINT16(flags, SCSW), 82 VMSTATE_UINT16(ctrl, SCSW), 83 VMSTATE_UINT32(cpa, SCSW), 84 VMSTATE_UINT8(dstat, SCSW), 85 VMSTATE_UINT8(cstat, SCSW), 86 VMSTATE_UINT16(count, SCSW), 87 VMSTATE_END_OF_LIST() 88 } 89 }; 90 91 static const VMStateDescription vmstate_pmcw = { 92 .name = "s390_pmcw", 93 .version_id = 1, 94 .minimum_version_id = 1, 95 .fields = (VMStateField[]) { 96 VMSTATE_UINT32(intparm, PMCW), 97 VMSTATE_UINT16(flags, PMCW), 98 VMSTATE_UINT16(devno, PMCW), 99 VMSTATE_UINT8(lpm, PMCW), 100 VMSTATE_UINT8(pnom, PMCW), 101 VMSTATE_UINT8(lpum, PMCW), 102 VMSTATE_UINT8(pim, PMCW), 103 VMSTATE_UINT16(mbi, PMCW), 104 VMSTATE_UINT8(pom, PMCW), 105 VMSTATE_UINT8(pam, PMCW), 106 VMSTATE_UINT8_ARRAY(chpid, PMCW, 8), 107 VMSTATE_UINT32(chars, PMCW), 108 VMSTATE_END_OF_LIST() 109 } 110 }; 111 112 static const VMStateDescription vmstate_schib = { 113 .name = "s390_schib", 114 .version_id = 1, 115 .minimum_version_id = 1, 116 .fields = (VMStateField[]) { 117 VMSTATE_STRUCT(pmcw, SCHIB, 0, vmstate_pmcw, PMCW), 118 VMSTATE_STRUCT(scsw, SCHIB, 0, vmstate_scsw, SCSW), 119 VMSTATE_UINT64(mba, SCHIB), 120 VMSTATE_UINT8_ARRAY(mda, SCHIB, 4), 121 VMSTATE_END_OF_LIST() 122 } 123 }; 124 125 126 static const VMStateDescription vmstate_ccw1 = { 127 .name = "s390_ccw1", 128 .version_id = 1, 129 .minimum_version_id = 1, 130 .fields = (VMStateField[]) { 131 VMSTATE_UINT8(cmd_code, CCW1), 132 VMSTATE_UINT8(flags, CCW1), 133 VMSTATE_UINT16(count, CCW1), 134 VMSTATE_UINT32(cda, CCW1), 135 VMSTATE_END_OF_LIST() 136 } 137 }; 138 139 static const VMStateDescription vmstate_ciw = { 140 .name = "s390_ciw", 141 .version_id = 1, 142 .minimum_version_id = 1, 143 .fields = (VMStateField[]) { 144 VMSTATE_UINT8(type, CIW), 145 VMSTATE_UINT8(command, CIW), 146 VMSTATE_UINT16(count, CIW), 147 VMSTATE_END_OF_LIST() 148 } 149 }; 150 151 static const VMStateDescription vmstate_sense_id = { 152 .name = "s390_sense_id", 153 .version_id = 1, 154 .minimum_version_id = 1, 155 .fields = (VMStateField[]) { 156 VMSTATE_UINT8(reserved, SenseId), 157 VMSTATE_UINT16(cu_type, SenseId), 158 VMSTATE_UINT8(cu_model, SenseId), 159 VMSTATE_UINT16(dev_type, SenseId), 160 VMSTATE_UINT8(dev_model, SenseId), 161 VMSTATE_UINT8(unused, SenseId), 162 VMSTATE_STRUCT_ARRAY(ciw, SenseId, MAX_CIWS, 0, vmstate_ciw, CIW), 163 VMSTATE_END_OF_LIST() 164 } 165 }; 166 167 static const VMStateDescription vmstate_orb = { 168 .name = "s390_orb", 169 .version_id = 1, 170 .minimum_version_id = 1, 171 .fields = (VMStateField[]) { 172 VMSTATE_UINT32(intparm, ORB), 173 VMSTATE_UINT16(ctrl0, ORB), 174 VMSTATE_UINT8(lpm, ORB), 175 VMSTATE_UINT8(ctrl1, ORB), 176 VMSTATE_UINT32(cpa, ORB), 177 VMSTATE_END_OF_LIST() 178 } 179 }; 180 181 static bool vmstate_schdev_orb_needed(void *opaque) 182 { 183 return css_migration_enabled(); 184 } 185 186 static const VMStateDescription vmstate_schdev_orb = { 187 .name = "s390_subch_dev/orb", 188 .version_id = 1, 189 .minimum_version_id = 1, 190 .needed = vmstate_schdev_orb_needed, 191 .fields = (VMStateField[]) { 192 VMSTATE_STRUCT(orb, SubchDev, 1, vmstate_orb, ORB), 193 VMSTATE_END_OF_LIST() 194 } 195 }; 196 197 static int subch_dev_post_load(void *opaque, int version_id); 198 static int subch_dev_pre_save(void *opaque); 199 200 const char err_hint_devno[] = "Devno mismatch, tried to load wrong section!" 201 " Likely reason: some sequences of plug and unplug can break" 202 " migration for machine versions prior to 2.7 (known design flaw)."; 203 204 const VMStateDescription vmstate_subch_dev = { 205 .name = "s390_subch_dev", 206 .version_id = 1, 207 .minimum_version_id = 1, 208 .post_load = subch_dev_post_load, 209 .pre_save = subch_dev_pre_save, 210 .fields = (VMStateField[]) { 211 VMSTATE_UINT8_EQUAL(cssid, SubchDev, "Bug!"), 212 VMSTATE_UINT8_EQUAL(ssid, SubchDev, "Bug!"), 213 VMSTATE_UINT16(migrated_schid, SubchDev), 214 VMSTATE_UINT16_EQUAL(devno, SubchDev, err_hint_devno), 215 VMSTATE_BOOL(thinint_active, SubchDev), 216 VMSTATE_STRUCT(curr_status, SubchDev, 0, vmstate_schib, SCHIB), 217 VMSTATE_UINT8_ARRAY(sense_data, SubchDev, 32), 218 VMSTATE_UINT64(channel_prog, SubchDev), 219 VMSTATE_STRUCT(last_cmd, SubchDev, 0, vmstate_ccw1, CCW1), 220 VMSTATE_BOOL(last_cmd_valid, SubchDev), 221 VMSTATE_STRUCT(id, SubchDev, 0, vmstate_sense_id, SenseId), 222 VMSTATE_BOOL(ccw_fmt_1, SubchDev), 223 VMSTATE_UINT8(ccw_no_data_cnt, SubchDev), 224 VMSTATE_END_OF_LIST() 225 }, 226 .subsections = (const VMStateDescription * []) { 227 &vmstate_schdev_orb, 228 NULL 229 } 230 }; 231 232 typedef struct IndAddrPtrTmp { 233 IndAddr **parent; 234 uint64_t addr; 235 int32_t len; 236 } IndAddrPtrTmp; 237 238 static int post_load_ind_addr(void *opaque, int version_id) 239 { 240 IndAddrPtrTmp *ptmp = opaque; 241 IndAddr **ind_addr = ptmp->parent; 242 243 if (ptmp->len != 0) { 244 *ind_addr = get_indicator(ptmp->addr, ptmp->len); 245 } else { 246 *ind_addr = NULL; 247 } 248 return 0; 249 } 250 251 static int pre_save_ind_addr(void *opaque) 252 { 253 IndAddrPtrTmp *ptmp = opaque; 254 IndAddr *ind_addr = *(ptmp->parent); 255 256 if (ind_addr != NULL) { 257 ptmp->len = ind_addr->len; 258 ptmp->addr = ind_addr->addr; 259 } else { 260 ptmp->len = 0; 261 ptmp->addr = 0L; 262 } 263 264 return 0; 265 } 266 267 const VMStateDescription vmstate_ind_addr_tmp = { 268 .name = "s390_ind_addr_tmp", 269 .pre_save = pre_save_ind_addr, 270 .post_load = post_load_ind_addr, 271 272 .fields = (VMStateField[]) { 273 VMSTATE_INT32(len, IndAddrPtrTmp), 274 VMSTATE_UINT64(addr, IndAddrPtrTmp), 275 VMSTATE_END_OF_LIST() 276 } 277 }; 278 279 const VMStateDescription vmstate_ind_addr = { 280 .name = "s390_ind_addr_tmp", 281 .fields = (VMStateField[]) { 282 VMSTATE_WITH_TMP(IndAddr*, IndAddrPtrTmp, vmstate_ind_addr_tmp), 283 VMSTATE_END_OF_LIST() 284 } 285 }; 286 287 typedef struct CssImage { 288 SubchSet *sch_set[MAX_SSID + 1]; 289 ChpInfo chpids[MAX_CHPID + 1]; 290 } CssImage; 291 292 static const VMStateDescription vmstate_css_img = { 293 .name = "s390_css_img", 294 .version_id = 1, 295 .minimum_version_id = 1, 296 .fields = (VMStateField[]) { 297 /* Subchannel sets have no relevant state. */ 298 VMSTATE_STRUCT_ARRAY(chpids, CssImage, MAX_CHPID + 1, 0, 299 vmstate_chp_info, ChpInfo), 300 VMSTATE_END_OF_LIST() 301 } 302 303 }; 304 305 typedef struct IoAdapter { 306 uint32_t id; 307 uint8_t type; 308 uint8_t isc; 309 uint8_t flags; 310 } IoAdapter; 311 312 typedef struct ChannelSubSys { 313 QTAILQ_HEAD(, CrwContainer) pending_crws; 314 bool sei_pending; 315 bool do_crw_mchk; 316 bool crws_lost; 317 uint8_t max_cssid; 318 uint8_t max_ssid; 319 bool chnmon_active; 320 uint64_t chnmon_area; 321 CssImage *css[MAX_CSSID + 1]; 322 uint8_t default_cssid; 323 /* don't migrate, see css_register_io_adapters */ 324 IoAdapter *io_adapters[CSS_IO_ADAPTER_TYPE_NUMS][MAX_ISC + 1]; 325 /* don't migrate, see get_indicator and IndAddrPtrTmp */ 326 QTAILQ_HEAD(, IndAddr) indicator_addresses; 327 } ChannelSubSys; 328 329 static const VMStateDescription vmstate_css = { 330 .name = "s390_css", 331 .version_id = 1, 332 .minimum_version_id = 1, 333 .fields = (VMStateField[]) { 334 VMSTATE_QTAILQ_V(pending_crws, ChannelSubSys, 1, vmstate_crw_container, 335 CrwContainer, sibling), 336 VMSTATE_BOOL(sei_pending, ChannelSubSys), 337 VMSTATE_BOOL(do_crw_mchk, ChannelSubSys), 338 VMSTATE_BOOL(crws_lost, ChannelSubSys), 339 /* These were kind of migrated by virtio */ 340 VMSTATE_UINT8(max_cssid, ChannelSubSys), 341 VMSTATE_UINT8(max_ssid, ChannelSubSys), 342 VMSTATE_BOOL(chnmon_active, ChannelSubSys), 343 VMSTATE_UINT64(chnmon_area, ChannelSubSys), 344 VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(css, ChannelSubSys, MAX_CSSID + 1, 345 0, vmstate_css_img, CssImage), 346 VMSTATE_UINT8(default_cssid, ChannelSubSys), 347 VMSTATE_END_OF_LIST() 348 } 349 }; 350 351 static ChannelSubSys channel_subsys = { 352 .pending_crws = QTAILQ_HEAD_INITIALIZER(channel_subsys.pending_crws), 353 .do_crw_mchk = true, 354 .sei_pending = false, 355 .crws_lost = false, 356 .chnmon_active = false, 357 .indicator_addresses = 358 QTAILQ_HEAD_INITIALIZER(channel_subsys.indicator_addresses), 359 }; 360 361 static int subch_dev_pre_save(void *opaque) 362 { 363 SubchDev *s = opaque; 364 365 /* Prepare remote_schid for save */ 366 s->migrated_schid = s->schid; 367 368 return 0; 369 } 370 371 static int subch_dev_post_load(void *opaque, int version_id) 372 { 373 374 SubchDev *s = opaque; 375 376 /* Re-assign the subchannel to remote_schid if necessary */ 377 if (s->migrated_schid != s->schid) { 378 if (css_find_subch(true, s->cssid, s->ssid, s->schid) == s) { 379 /* 380 * Cleanup the slot before moving to s->migrated_schid provided 381 * it still belongs to us, i.e. it was not changed by previous 382 * invocation of this function. 383 */ 384 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, NULL); 385 } 386 /* It's OK to re-assign without a prior de-assign. */ 387 s->schid = s->migrated_schid; 388 css_subch_assign(s->cssid, s->ssid, s->schid, s->devno, s); 389 } 390 391 if (css_migration_enabled()) { 392 /* No compat voodoo to do ;) */ 393 return 0; 394 } 395 /* 396 * Hack alert. If we don't migrate the channel subsystem status 397 * we still need to find out if the guest enabled mss/mcss-e. 398 * If the subchannel is enabled, it certainly was able to access it, 399 * so adjust the max_ssid/max_cssid values for relevant ssid/cssid 400 * values. This is not watertight, but better than nothing. 401 */ 402 if (s->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA) { 403 if (s->ssid) { 404 channel_subsys.max_ssid = MAX_SSID; 405 } 406 if (s->cssid != channel_subsys.default_cssid) { 407 channel_subsys.max_cssid = MAX_CSSID; 408 } 409 } 410 return 0; 411 } 412 413 void css_register_vmstate(void) 414 { 415 vmstate_register(NULL, 0, &vmstate_css, &channel_subsys); 416 } 417 418 IndAddr *get_indicator(hwaddr ind_addr, int len) 419 { 420 IndAddr *indicator; 421 422 QTAILQ_FOREACH(indicator, &channel_subsys.indicator_addresses, sibling) { 423 if (indicator->addr == ind_addr) { 424 indicator->refcnt++; 425 return indicator; 426 } 427 } 428 indicator = g_new0(IndAddr, 1); 429 indicator->addr = ind_addr; 430 indicator->len = len; 431 indicator->refcnt = 1; 432 QTAILQ_INSERT_TAIL(&channel_subsys.indicator_addresses, 433 indicator, sibling); 434 return indicator; 435 } 436 437 static int s390_io_adapter_map(AdapterInfo *adapter, uint64_t map_addr, 438 bool do_map) 439 { 440 S390FLICState *fs = s390_get_flic(); 441 S390FLICStateClass *fsc = s390_get_flic_class(fs); 442 443 return fsc->io_adapter_map(fs, adapter->adapter_id, map_addr, do_map); 444 } 445 446 void release_indicator(AdapterInfo *adapter, IndAddr *indicator) 447 { 448 assert(indicator->refcnt > 0); 449 indicator->refcnt--; 450 if (indicator->refcnt > 0) { 451 return; 452 } 453 QTAILQ_REMOVE(&channel_subsys.indicator_addresses, indicator, sibling); 454 if (indicator->map) { 455 s390_io_adapter_map(adapter, indicator->map, false); 456 } 457 g_free(indicator); 458 } 459 460 int map_indicator(AdapterInfo *adapter, IndAddr *indicator) 461 { 462 int ret; 463 464 if (indicator->map) { 465 return 0; /* already mapped is not an error */ 466 } 467 indicator->map = indicator->addr; 468 ret = s390_io_adapter_map(adapter, indicator->map, true); 469 if ((ret != 0) && (ret != -ENOSYS)) { 470 goto out_err; 471 } 472 return 0; 473 474 out_err: 475 indicator->map = 0; 476 return ret; 477 } 478 479 int css_create_css_image(uint8_t cssid, bool default_image) 480 { 481 trace_css_new_image(cssid, default_image ? "(default)" : ""); 482 /* 255 is reserved */ 483 if (cssid == 255) { 484 return -EINVAL; 485 } 486 if (channel_subsys.css[cssid]) { 487 return -EBUSY; 488 } 489 channel_subsys.css[cssid] = g_new0(CssImage, 1); 490 if (default_image) { 491 channel_subsys.default_cssid = cssid; 492 } 493 return 0; 494 } 495 496 uint32_t css_get_adapter_id(CssIoAdapterType type, uint8_t isc) 497 { 498 if (type >= CSS_IO_ADAPTER_TYPE_NUMS || isc > MAX_ISC || 499 !channel_subsys.io_adapters[type][isc]) { 500 return -1; 501 } 502 503 return channel_subsys.io_adapters[type][isc]->id; 504 } 505 506 /** 507 * css_register_io_adapters: Register I/O adapters per ISC during init 508 * 509 * @swap: an indication if byte swap is needed. 510 * @maskable: an indication if the adapter is subject to the mask operation. 511 * @flags: further characteristics of the adapter. 512 * e.g. suppressible, an indication if the adapter is subject to AIS. 513 * @errp: location to store error information. 514 */ 515 void css_register_io_adapters(CssIoAdapterType type, bool swap, bool maskable, 516 uint8_t flags, Error **errp) 517 { 518 uint32_t id; 519 int ret, isc; 520 IoAdapter *adapter; 521 S390FLICState *fs = s390_get_flic(); 522 S390FLICStateClass *fsc = s390_get_flic_class(fs); 523 524 /* 525 * Disallow multiple registrations for the same device type. 526 * Report an error if registering for an already registered type. 527 */ 528 if (channel_subsys.io_adapters[type][0]) { 529 error_setg(errp, "Adapters for type %d already registered", type); 530 } 531 532 for (isc = 0; isc <= MAX_ISC; isc++) { 533 id = (type << 3) | isc; 534 ret = fsc->register_io_adapter(fs, id, isc, swap, maskable, flags); 535 if (ret == 0) { 536 adapter = g_new0(IoAdapter, 1); 537 adapter->id = id; 538 adapter->isc = isc; 539 adapter->type = type; 540 adapter->flags = flags; 541 channel_subsys.io_adapters[type][isc] = adapter; 542 } else { 543 error_setg_errno(errp, -ret, "Unexpected error %d when " 544 "registering adapter %d", ret, id); 545 break; 546 } 547 } 548 549 /* 550 * No need to free registered adapters in kvm: kvm will clean up 551 * when the machine goes away. 552 */ 553 if (ret) { 554 for (isc--; isc >= 0; isc--) { 555 g_free(channel_subsys.io_adapters[type][isc]); 556 channel_subsys.io_adapters[type][isc] = NULL; 557 } 558 } 559 560 } 561 562 static void css_clear_io_interrupt(uint16_t subchannel_id, 563 uint16_t subchannel_nr) 564 { 565 Error *err = NULL; 566 static bool no_clear_irq; 567 S390FLICState *fs = s390_get_flic(); 568 S390FLICStateClass *fsc = s390_get_flic_class(fs); 569 int r; 570 571 if (unlikely(no_clear_irq)) { 572 return; 573 } 574 r = fsc->clear_io_irq(fs, subchannel_id, subchannel_nr); 575 switch (r) { 576 case 0: 577 break; 578 case -ENOSYS: 579 no_clear_irq = true; 580 /* 581 * Ignore unavailability, as the user can't do anything 582 * about it anyway. 583 */ 584 break; 585 default: 586 error_setg_errno(&err, -r, "unexpected error condition"); 587 error_propagate(&error_abort, err); 588 } 589 } 590 591 static inline uint16_t css_do_build_subchannel_id(uint8_t cssid, uint8_t ssid) 592 { 593 if (channel_subsys.max_cssid > 0) { 594 return (cssid << 8) | (1 << 3) | (ssid << 1) | 1; 595 } 596 return (ssid << 1) | 1; 597 } 598 599 uint16_t css_build_subchannel_id(SubchDev *sch) 600 { 601 return css_do_build_subchannel_id(sch->cssid, sch->ssid); 602 } 603 604 void css_inject_io_interrupt(SubchDev *sch) 605 { 606 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 607 608 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 609 sch->curr_status.pmcw.intparm, isc, ""); 610 s390_io_interrupt(css_build_subchannel_id(sch), 611 sch->schid, 612 sch->curr_status.pmcw.intparm, 613 isc << 27); 614 } 615 616 void css_conditional_io_interrupt(SubchDev *sch) 617 { 618 /* 619 * If the subchannel is not enabled, it is not made status pending 620 * (see PoP p. 16-17, "Status Control"). 621 */ 622 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ENA)) { 623 return; 624 } 625 626 /* 627 * If the subchannel is not currently status pending, make it pending 628 * with alert status. 629 */ 630 if (!(sch->curr_status.scsw.ctrl & SCSW_STCTL_STATUS_PEND)) { 631 uint8_t isc = (sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_ISC) >> 11; 632 633 trace_css_io_interrupt(sch->cssid, sch->ssid, sch->schid, 634 sch->curr_status.pmcw.intparm, isc, 635 "(unsolicited)"); 636 sch->curr_status.scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 637 sch->curr_status.scsw.ctrl |= 638 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 639 /* Inject an I/O interrupt. */ 640 s390_io_interrupt(css_build_subchannel_id(sch), 641 sch->schid, 642 sch->curr_status.pmcw.intparm, 643 isc << 27); 644 } 645 } 646 647 int css_do_sic(CPUS390XState *env, uint8_t isc, uint16_t mode) 648 { 649 S390FLICState *fs = s390_get_flic(); 650 S390FLICStateClass *fsc = s390_get_flic_class(fs); 651 int r; 652 653 if (env->psw.mask & PSW_MASK_PSTATE) { 654 r = -PGM_PRIVILEGED; 655 goto out; 656 } 657 658 trace_css_do_sic(mode, isc); 659 switch (mode) { 660 case SIC_IRQ_MODE_ALL: 661 case SIC_IRQ_MODE_SINGLE: 662 break; 663 default: 664 r = -PGM_OPERAND; 665 goto out; 666 } 667 668 r = fsc->modify_ais_mode(fs, isc, mode) ? -PGM_OPERATION : 0; 669 out: 670 return r; 671 } 672 673 void css_adapter_interrupt(CssIoAdapterType type, uint8_t isc) 674 { 675 S390FLICState *fs = s390_get_flic(); 676 S390FLICStateClass *fsc = s390_get_flic_class(fs); 677 uint32_t io_int_word = (isc << 27) | IO_INT_WORD_AI; 678 IoAdapter *adapter = channel_subsys.io_adapters[type][isc]; 679 680 if (!adapter) { 681 return; 682 } 683 684 trace_css_adapter_interrupt(isc); 685 if (fs->ais_supported) { 686 if (fsc->inject_airq(fs, type, isc, adapter->flags)) { 687 error_report("Failed to inject airq with AIS supported"); 688 exit(1); 689 } 690 } else { 691 s390_io_interrupt(0, 0, 0, io_int_word); 692 } 693 } 694 695 static void sch_handle_clear_func(SubchDev *sch) 696 { 697 SCHIB *schib = &sch->curr_status; 698 int path; 699 700 /* Path management: In our simple css, we always choose the only path. */ 701 path = 0x80; 702 703 /* Reset values prior to 'issuing the clear signal'. */ 704 schib->pmcw.lpum = 0; 705 schib->pmcw.pom = 0xff; 706 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 707 708 /* We always 'attempt to issue the clear signal', and we always succeed. */ 709 sch->channel_prog = 0x0; 710 sch->last_cmd_valid = false; 711 schib->scsw.ctrl &= ~SCSW_ACTL_CLEAR_PEND; 712 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND; 713 714 schib->scsw.dstat = 0; 715 schib->scsw.cstat = 0; 716 schib->pmcw.lpum = path; 717 718 } 719 720 static void sch_handle_halt_func(SubchDev *sch) 721 { 722 SCHIB *schib = &sch->curr_status; 723 hwaddr curr_ccw = sch->channel_prog; 724 int path; 725 726 /* Path management: In our simple css, we always choose the only path. */ 727 path = 0x80; 728 729 /* We always 'attempt to issue the halt signal', and we always succeed. */ 730 sch->channel_prog = 0x0; 731 sch->last_cmd_valid = false; 732 schib->scsw.ctrl &= ~SCSW_ACTL_HALT_PEND; 733 schib->scsw.ctrl |= SCSW_STCTL_STATUS_PEND; 734 735 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE | 736 SCSW_ACTL_DEVICE_ACTIVE)) || 737 !((schib->scsw.ctrl & SCSW_ACTL_START_PEND) || 738 (schib->scsw.ctrl & SCSW_ACTL_SUSP))) { 739 schib->scsw.dstat = SCSW_DSTAT_DEVICE_END; 740 } 741 if ((schib->scsw.ctrl & (SCSW_ACTL_SUBCH_ACTIVE | 742 SCSW_ACTL_DEVICE_ACTIVE)) || 743 (schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 744 schib->scsw.cpa = curr_ccw + 8; 745 } 746 schib->scsw.cstat = 0; 747 schib->pmcw.lpum = path; 748 749 } 750 751 /* 752 * As the SenseId struct cannot be packed (would cause unaligned accesses), we 753 * have to copy the individual fields to an unstructured area using the correct 754 * layout (see SA22-7204-01 "Common I/O-Device Commands"). 755 */ 756 static void copy_sense_id_to_guest(uint8_t *dest, SenseId *src) 757 { 758 int i; 759 760 dest[0] = src->reserved; 761 stw_be_p(dest + 1, src->cu_type); 762 dest[3] = src->cu_model; 763 stw_be_p(dest + 4, src->dev_type); 764 dest[6] = src->dev_model; 765 dest[7] = src->unused; 766 for (i = 0; i < ARRAY_SIZE(src->ciw); i++) { 767 dest[8 + i * 4] = src->ciw[i].type; 768 dest[9 + i * 4] = src->ciw[i].command; 769 stw_be_p(dest + 10 + i * 4, src->ciw[i].count); 770 } 771 } 772 773 static CCW1 copy_ccw_from_guest(hwaddr addr, bool fmt1) 774 { 775 CCW0 tmp0; 776 CCW1 tmp1; 777 CCW1 ret; 778 779 if (fmt1) { 780 cpu_physical_memory_read(addr, &tmp1, sizeof(tmp1)); 781 ret.cmd_code = tmp1.cmd_code; 782 ret.flags = tmp1.flags; 783 ret.count = be16_to_cpu(tmp1.count); 784 ret.cda = be32_to_cpu(tmp1.cda); 785 } else { 786 cpu_physical_memory_read(addr, &tmp0, sizeof(tmp0)); 787 if ((tmp0.cmd_code & 0x0f) == CCW_CMD_TIC) { 788 ret.cmd_code = CCW_CMD_TIC; 789 ret.flags = 0; 790 ret.count = 0; 791 } else { 792 ret.cmd_code = tmp0.cmd_code; 793 ret.flags = tmp0.flags; 794 ret.count = be16_to_cpu(tmp0.count); 795 } 796 ret.cda = be16_to_cpu(tmp0.cda1) | (tmp0.cda0 << 16); 797 } 798 return ret; 799 } 800 /** 801 * If out of bounds marks the stream broken. If broken returns -EINVAL, 802 * otherwise the requested length (may be zero) 803 */ 804 static inline int cds_check_len(CcwDataStream *cds, int len) 805 { 806 if (cds->at_byte + len > cds->count) { 807 cds->flags |= CDS_F_STREAM_BROKEN; 808 } 809 return cds->flags & CDS_F_STREAM_BROKEN ? -EINVAL : len; 810 } 811 812 static inline bool cds_ccw_addrs_ok(hwaddr addr, int len, bool ccw_fmt1) 813 { 814 return (addr + len) < (ccw_fmt1 ? (1UL << 31) : (1UL << 24)); 815 } 816 817 static int ccw_dstream_rw_noflags(CcwDataStream *cds, void *buff, int len, 818 CcwDataStreamOp op) 819 { 820 int ret; 821 822 ret = cds_check_len(cds, len); 823 if (ret <= 0) { 824 return ret; 825 } 826 if (!cds_ccw_addrs_ok(cds->cda, len, cds->flags & CDS_F_FMT)) { 827 return -EINVAL; /* channel program check */ 828 } 829 if (op == CDS_OP_A) { 830 goto incr; 831 } 832 if (!cds->do_skip) { 833 ret = address_space_rw(&address_space_memory, cds->cda, 834 MEMTXATTRS_UNSPECIFIED, buff, len, op); 835 } else { 836 ret = MEMTX_OK; 837 } 838 if (ret != MEMTX_OK) { 839 cds->flags |= CDS_F_STREAM_BROKEN; 840 return -EINVAL; 841 } 842 incr: 843 cds->at_byte += len; 844 cds->cda += len; 845 return 0; 846 } 847 848 /* returns values between 1 and bsz, where bsz is a power of 2 */ 849 static inline uint16_t ida_continuous_left(hwaddr cda, uint64_t bsz) 850 { 851 return bsz - (cda & (bsz - 1)); 852 } 853 854 static inline uint64_t ccw_ida_block_size(uint8_t flags) 855 { 856 if ((flags & CDS_F_C64) && !(flags & CDS_F_I2K)) { 857 return 1ULL << 12; 858 } 859 return 1ULL << 11; 860 } 861 862 static inline int ida_read_next_idaw(CcwDataStream *cds) 863 { 864 union {uint64_t fmt2; uint32_t fmt1; } idaw; 865 int ret; 866 hwaddr idaw_addr; 867 bool idaw_fmt2 = cds->flags & CDS_F_C64; 868 bool ccw_fmt1 = cds->flags & CDS_F_FMT; 869 870 if (idaw_fmt2) { 871 idaw_addr = cds->cda_orig + sizeof(idaw.fmt2) * cds->at_idaw; 872 if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 873 return -EINVAL; /* channel program check */ 874 } 875 ret = address_space_read(&address_space_memory, idaw_addr, 876 MEMTXATTRS_UNSPECIFIED, &idaw.fmt2, 877 sizeof(idaw.fmt2)); 878 cds->cda = be64_to_cpu(idaw.fmt2); 879 } else { 880 idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; 881 if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { 882 return -EINVAL; /* channel program check */ 883 } 884 ret = address_space_read(&address_space_memory, idaw_addr, 885 MEMTXATTRS_UNSPECIFIED, &idaw.fmt1, 886 sizeof(idaw.fmt1)); 887 cds->cda = be64_to_cpu(idaw.fmt1); 888 if (cds->cda & 0x80000000) { 889 return -EINVAL; /* channel program check */ 890 } 891 } 892 ++(cds->at_idaw); 893 if (ret != MEMTX_OK) { 894 /* assume inaccessible address */ 895 return -EINVAL; /* channel program check */ 896 } 897 return 0; 898 } 899 900 static int ccw_dstream_rw_ida(CcwDataStream *cds, void *buff, int len, 901 CcwDataStreamOp op) 902 { 903 uint64_t bsz = ccw_ida_block_size(cds->flags); 904 int ret = 0; 905 uint16_t cont_left, iter_len; 906 907 ret = cds_check_len(cds, len); 908 if (ret <= 0) { 909 return ret; 910 } 911 if (!cds->at_idaw) { 912 /* read first idaw */ 913 ret = ida_read_next_idaw(cds); 914 if (ret) { 915 goto err; 916 } 917 cont_left = ida_continuous_left(cds->cda, bsz); 918 } else { 919 cont_left = ida_continuous_left(cds->cda, bsz); 920 if (cont_left == bsz) { 921 ret = ida_read_next_idaw(cds); 922 if (ret) { 923 goto err; 924 } 925 if (cds->cda & (bsz - 1)) { 926 ret = -EINVAL; /* channel program check */ 927 goto err; 928 } 929 } 930 } 931 do { 932 iter_len = MIN(len, cont_left); 933 if (op != CDS_OP_A) { 934 if (!cds->do_skip) { 935 ret = address_space_rw(&address_space_memory, cds->cda, 936 MEMTXATTRS_UNSPECIFIED, buff, iter_len, 937 op); 938 } else { 939 ret = MEMTX_OK; 940 } 941 if (ret != MEMTX_OK) { 942 /* assume inaccessible address */ 943 ret = -EINVAL; /* channel program check */ 944 goto err; 945 } 946 } 947 cds->at_byte += iter_len; 948 cds->cda += iter_len; 949 len -= iter_len; 950 if (!len) { 951 break; 952 } 953 ret = ida_read_next_idaw(cds); 954 if (ret) { 955 goto err; 956 } 957 cont_left = bsz; 958 } while (true); 959 return ret; 960 err: 961 cds->flags |= CDS_F_STREAM_BROKEN; 962 return ret; 963 } 964 965 void ccw_dstream_init(CcwDataStream *cds, CCW1 const *ccw, ORB const *orb) 966 { 967 /* 968 * We don't support MIDA (an optional facility) yet and we 969 * catch this earlier. Just for expressing the precondition. 970 */ 971 g_assert(!(orb->ctrl1 & ORB_CTRL1_MASK_MIDAW)); 972 cds->flags = (orb->ctrl0 & ORB_CTRL0_MASK_I2K ? CDS_F_I2K : 0) | 973 (orb->ctrl0 & ORB_CTRL0_MASK_C64 ? CDS_F_C64 : 0) | 974 (orb->ctrl0 & ORB_CTRL0_MASK_FMT ? CDS_F_FMT : 0) | 975 (ccw->flags & CCW_FLAG_IDA ? CDS_F_IDA : 0); 976 977 cds->count = ccw->count; 978 cds->cda_orig = ccw->cda; 979 /* skip is only effective for read, read backwards, or sense commands */ 980 cds->do_skip = (ccw->flags & CCW_FLAG_SKIP) && 981 ((ccw->cmd_code & 0x0f) == CCW_CMD_BASIC_SENSE || 982 (ccw->cmd_code & 0x03) == 0x02 /* read */ || 983 (ccw->cmd_code & 0x0f) == 0x0c /* read backwards */); 984 ccw_dstream_rewind(cds); 985 if (!(cds->flags & CDS_F_IDA)) { 986 cds->op_handler = ccw_dstream_rw_noflags; 987 } else { 988 cds->op_handler = ccw_dstream_rw_ida; 989 } 990 } 991 992 static int css_interpret_ccw(SubchDev *sch, hwaddr ccw_addr, 993 bool suspend_allowed) 994 { 995 int ret; 996 bool check_len; 997 int len; 998 CCW1 ccw; 999 1000 if (!ccw_addr) { 1001 return -EINVAL; /* channel-program check */ 1002 } 1003 /* Check doubleword aligned and 31 or 24 (fmt 0) bit addressable. */ 1004 if (ccw_addr & (sch->ccw_fmt_1 ? 0x80000007 : 0xff000007)) { 1005 return -EINVAL; 1006 } 1007 1008 /* Translate everything to format-1 ccws - the information is the same. */ 1009 ccw = copy_ccw_from_guest(ccw_addr, sch->ccw_fmt_1); 1010 1011 /* Check for invalid command codes. */ 1012 if ((ccw.cmd_code & 0x0f) == 0) { 1013 return -EINVAL; 1014 } 1015 if (((ccw.cmd_code & 0x0f) == CCW_CMD_TIC) && 1016 ((ccw.cmd_code & 0xf0) != 0)) { 1017 return -EINVAL; 1018 } 1019 if (!sch->ccw_fmt_1 && (ccw.count == 0) && 1020 (ccw.cmd_code != CCW_CMD_TIC)) { 1021 return -EINVAL; 1022 } 1023 1024 /* We don't support MIDA. */ 1025 if (ccw.flags & CCW_FLAG_MIDA) { 1026 return -EINVAL; 1027 } 1028 1029 if (ccw.flags & CCW_FLAG_SUSPEND) { 1030 return suspend_allowed ? -EINPROGRESS : -EINVAL; 1031 } 1032 1033 check_len = !((ccw.flags & CCW_FLAG_SLI) && !(ccw.flags & CCW_FLAG_DC)); 1034 1035 if (!ccw.cda) { 1036 if (sch->ccw_no_data_cnt == 255) { 1037 return -EINVAL; 1038 } 1039 sch->ccw_no_data_cnt++; 1040 } 1041 1042 /* Look at the command. */ 1043 ccw_dstream_init(&sch->cds, &ccw, &(sch->orb)); 1044 switch (ccw.cmd_code) { 1045 case CCW_CMD_NOOP: 1046 /* Nothing to do. */ 1047 ret = 0; 1048 break; 1049 case CCW_CMD_BASIC_SENSE: 1050 if (check_len) { 1051 if (ccw.count != sizeof(sch->sense_data)) { 1052 ret = -EINVAL; 1053 break; 1054 } 1055 } 1056 len = MIN(ccw.count, sizeof(sch->sense_data)); 1057 ret = ccw_dstream_write_buf(&sch->cds, sch->sense_data, len); 1058 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1059 if (!ret) { 1060 memset(sch->sense_data, 0, sizeof(sch->sense_data)); 1061 } 1062 break; 1063 case CCW_CMD_SENSE_ID: 1064 { 1065 /* According to SA22-7204-01, Sense-ID can store up to 256 bytes */ 1066 uint8_t sense_id[256]; 1067 1068 copy_sense_id_to_guest(sense_id, &sch->id); 1069 /* Sense ID information is device specific. */ 1070 if (check_len) { 1071 if (ccw.count != sizeof(sense_id)) { 1072 ret = -EINVAL; 1073 break; 1074 } 1075 } 1076 len = MIN(ccw.count, sizeof(sense_id)); 1077 /* 1078 * Only indicate 0xff in the first sense byte if we actually 1079 * have enough place to store at least bytes 0-3. 1080 */ 1081 if (len >= 4) { 1082 sense_id[0] = 0xff; 1083 } else { 1084 sense_id[0] = 0; 1085 } 1086 ret = ccw_dstream_write_buf(&sch->cds, sense_id, len); 1087 if (!ret) { 1088 sch->curr_status.scsw.count = ccw_dstream_residual_count(&sch->cds); 1089 } 1090 break; 1091 } 1092 case CCW_CMD_TIC: 1093 if (sch->last_cmd_valid && (sch->last_cmd.cmd_code == CCW_CMD_TIC)) { 1094 ret = -EINVAL; 1095 break; 1096 } 1097 if (ccw.flags || ccw.count) { 1098 /* We have already sanitized these if converted from fmt 0. */ 1099 ret = -EINVAL; 1100 break; 1101 } 1102 sch->channel_prog = ccw.cda; 1103 ret = -EAGAIN; 1104 break; 1105 default: 1106 if (sch->ccw_cb) { 1107 /* Handle device specific commands. */ 1108 ret = sch->ccw_cb(sch, ccw); 1109 } else { 1110 ret = -ENOSYS; 1111 } 1112 break; 1113 } 1114 sch->last_cmd = ccw; 1115 sch->last_cmd_valid = true; 1116 if (ret == 0) { 1117 if (ccw.flags & CCW_FLAG_CC) { 1118 sch->channel_prog += 8; 1119 ret = -EAGAIN; 1120 } 1121 } 1122 1123 return ret; 1124 } 1125 1126 static void sch_handle_start_func_virtual(SubchDev *sch) 1127 { 1128 SCHIB *schib = &sch->curr_status; 1129 int path; 1130 int ret; 1131 bool suspend_allowed; 1132 1133 /* Path management: In our simple css, we always choose the only path. */ 1134 path = 0x80; 1135 1136 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 1137 /* Start Function triggered via ssch, i.e. we have an ORB */ 1138 ORB *orb = &sch->orb; 1139 schib->scsw.cstat = 0; 1140 schib->scsw.dstat = 0; 1141 /* Look at the orb and try to execute the channel program. */ 1142 schib->pmcw.intparm = orb->intparm; 1143 if (!(orb->lpm & path)) { 1144 /* Generate a deferred cc 3 condition. */ 1145 schib->scsw.flags |= SCSW_FLAGS_MASK_CC; 1146 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1147 schib->scsw.ctrl |= (SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND); 1148 return; 1149 } 1150 sch->ccw_fmt_1 = !!(orb->ctrl0 & ORB_CTRL0_MASK_FMT); 1151 schib->scsw.flags |= (sch->ccw_fmt_1) ? SCSW_FLAGS_MASK_FMT : 0; 1152 sch->ccw_no_data_cnt = 0; 1153 suspend_allowed = !!(orb->ctrl0 & ORB_CTRL0_MASK_SPND); 1154 } else { 1155 /* Start Function resumed via rsch */ 1156 schib->scsw.ctrl &= ~(SCSW_ACTL_SUSP | SCSW_ACTL_RESUME_PEND); 1157 /* The channel program had been suspended before. */ 1158 suspend_allowed = true; 1159 } 1160 sch->last_cmd_valid = false; 1161 do { 1162 ret = css_interpret_ccw(sch, sch->channel_prog, suspend_allowed); 1163 switch (ret) { 1164 case -EAGAIN: 1165 /* ccw chain, continue processing */ 1166 break; 1167 case 0: 1168 /* success */ 1169 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1170 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1171 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1172 SCSW_STCTL_STATUS_PEND; 1173 schib->scsw.dstat = SCSW_DSTAT_CHANNEL_END | SCSW_DSTAT_DEVICE_END; 1174 schib->scsw.cpa = sch->channel_prog + 8; 1175 break; 1176 case -EIO: 1177 /* I/O errors, status depends on specific devices */ 1178 break; 1179 case -ENOSYS: 1180 /* unsupported command, generate unit check (command reject) */ 1181 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1182 schib->scsw.dstat = SCSW_DSTAT_UNIT_CHECK; 1183 /* Set sense bit 0 in ecw0. */ 1184 sch->sense_data[0] = 0x80; 1185 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1186 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1187 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1188 schib->scsw.cpa = sch->channel_prog + 8; 1189 break; 1190 case -EINPROGRESS: 1191 /* channel program has been suspended */ 1192 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1193 schib->scsw.ctrl |= SCSW_ACTL_SUSP; 1194 break; 1195 default: 1196 /* error, generate channel program check */ 1197 schib->scsw.ctrl &= ~SCSW_ACTL_START_PEND; 1198 schib->scsw.cstat = SCSW_CSTAT_PROG_CHECK; 1199 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1200 schib->scsw.ctrl |= SCSW_STCTL_PRIMARY | SCSW_STCTL_SECONDARY | 1201 SCSW_STCTL_ALERT | SCSW_STCTL_STATUS_PEND; 1202 schib->scsw.cpa = sch->channel_prog + 8; 1203 break; 1204 } 1205 } while (ret == -EAGAIN); 1206 1207 } 1208 1209 static void sch_handle_halt_func_passthrough(SubchDev *sch) 1210 { 1211 int ret; 1212 1213 ret = s390_ccw_halt(sch); 1214 if (ret == -ENOSYS) { 1215 sch_handle_halt_func(sch); 1216 } 1217 } 1218 1219 static void sch_handle_clear_func_passthrough(SubchDev *sch) 1220 { 1221 int ret; 1222 1223 ret = s390_ccw_clear(sch); 1224 if (ret == -ENOSYS) { 1225 sch_handle_clear_func(sch); 1226 } 1227 } 1228 1229 static IOInstEnding sch_handle_start_func_passthrough(SubchDev *sch) 1230 { 1231 SCHIB *schib = &sch->curr_status; 1232 ORB *orb = &sch->orb; 1233 if (!(schib->scsw.ctrl & SCSW_ACTL_SUSP)) { 1234 assert(orb != NULL); 1235 schib->pmcw.intparm = orb->intparm; 1236 } 1237 return s390_ccw_cmd_request(sch); 1238 } 1239 1240 /* 1241 * On real machines, this would run asynchronously to the main vcpus. 1242 * We might want to make some parts of the ssch handling (interpreting 1243 * read/writes) asynchronous later on if we start supporting more than 1244 * our current very simple devices. 1245 */ 1246 IOInstEnding do_subchannel_work_virtual(SubchDev *sch) 1247 { 1248 SCHIB *schib = &sch->curr_status; 1249 1250 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { 1251 sch_handle_clear_func(sch); 1252 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { 1253 sch_handle_halt_func(sch); 1254 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) { 1255 /* Triggered by both ssch and rsch. */ 1256 sch_handle_start_func_virtual(sch); 1257 } 1258 css_inject_io_interrupt(sch); 1259 /* inst must succeed if this func is called */ 1260 return IOINST_CC_EXPECTED; 1261 } 1262 1263 IOInstEnding do_subchannel_work_passthrough(SubchDev *sch) 1264 { 1265 SCHIB *schib = &sch->curr_status; 1266 1267 if (schib->scsw.ctrl & SCSW_FCTL_CLEAR_FUNC) { 1268 sch_handle_clear_func_passthrough(sch); 1269 } else if (schib->scsw.ctrl & SCSW_FCTL_HALT_FUNC) { 1270 sch_handle_halt_func_passthrough(sch); 1271 } else if (schib->scsw.ctrl & SCSW_FCTL_START_FUNC) { 1272 return sch_handle_start_func_passthrough(sch); 1273 } 1274 return IOINST_CC_EXPECTED; 1275 } 1276 1277 static IOInstEnding do_subchannel_work(SubchDev *sch) 1278 { 1279 if (!sch->do_subchannel_work) { 1280 return IOINST_CC_STATUS_PRESENT; 1281 } 1282 g_assert(sch->curr_status.scsw.ctrl & SCSW_CTRL_MASK_FCTL); 1283 return sch->do_subchannel_work(sch); 1284 } 1285 1286 static void copy_pmcw_to_guest(PMCW *dest, const PMCW *src) 1287 { 1288 int i; 1289 1290 dest->intparm = cpu_to_be32(src->intparm); 1291 dest->flags = cpu_to_be16(src->flags); 1292 dest->devno = cpu_to_be16(src->devno); 1293 dest->lpm = src->lpm; 1294 dest->pnom = src->pnom; 1295 dest->lpum = src->lpum; 1296 dest->pim = src->pim; 1297 dest->mbi = cpu_to_be16(src->mbi); 1298 dest->pom = src->pom; 1299 dest->pam = src->pam; 1300 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1301 dest->chpid[i] = src->chpid[i]; 1302 } 1303 dest->chars = cpu_to_be32(src->chars); 1304 } 1305 1306 void copy_scsw_to_guest(SCSW *dest, const SCSW *src) 1307 { 1308 dest->flags = cpu_to_be16(src->flags); 1309 dest->ctrl = cpu_to_be16(src->ctrl); 1310 dest->cpa = cpu_to_be32(src->cpa); 1311 dest->dstat = src->dstat; 1312 dest->cstat = src->cstat; 1313 dest->count = cpu_to_be16(src->count); 1314 } 1315 1316 static void copy_schib_to_guest(SCHIB *dest, const SCHIB *src) 1317 { 1318 int i; 1319 /* 1320 * We copy the PMCW and SCSW in and out of local variables to 1321 * avoid taking the address of members of a packed struct. 1322 */ 1323 PMCW src_pmcw, dest_pmcw; 1324 SCSW src_scsw, dest_scsw; 1325 1326 src_pmcw = src->pmcw; 1327 copy_pmcw_to_guest(&dest_pmcw, &src_pmcw); 1328 dest->pmcw = dest_pmcw; 1329 src_scsw = src->scsw; 1330 copy_scsw_to_guest(&dest_scsw, &src_scsw); 1331 dest->scsw = dest_scsw; 1332 dest->mba = cpu_to_be64(src->mba); 1333 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1334 dest->mda[i] = src->mda[i]; 1335 } 1336 } 1337 1338 void copy_esw_to_guest(ESW *dest, const ESW *src) 1339 { 1340 dest->word0 = cpu_to_be32(src->word0); 1341 dest->erw = cpu_to_be32(src->erw); 1342 dest->word2 = cpu_to_be64(src->word2); 1343 dest->word4 = cpu_to_be32(src->word4); 1344 } 1345 1346 IOInstEnding css_do_stsch(SubchDev *sch, SCHIB *schib) 1347 { 1348 int ret; 1349 1350 /* 1351 * For some subchannels, we may want to update parts of 1352 * the schib (e.g., update path masks from the host device 1353 * for passthrough subchannels). 1354 */ 1355 ret = s390_ccw_store(sch); 1356 1357 /* Use current status. */ 1358 copy_schib_to_guest(schib, &sch->curr_status); 1359 return ret; 1360 } 1361 1362 static void copy_pmcw_from_guest(PMCW *dest, const PMCW *src) 1363 { 1364 int i; 1365 1366 dest->intparm = be32_to_cpu(src->intparm); 1367 dest->flags = be16_to_cpu(src->flags); 1368 dest->devno = be16_to_cpu(src->devno); 1369 dest->lpm = src->lpm; 1370 dest->pnom = src->pnom; 1371 dest->lpum = src->lpum; 1372 dest->pim = src->pim; 1373 dest->mbi = be16_to_cpu(src->mbi); 1374 dest->pom = src->pom; 1375 dest->pam = src->pam; 1376 for (i = 0; i < ARRAY_SIZE(dest->chpid); i++) { 1377 dest->chpid[i] = src->chpid[i]; 1378 } 1379 dest->chars = be32_to_cpu(src->chars); 1380 } 1381 1382 static void copy_scsw_from_guest(SCSW *dest, const SCSW *src) 1383 { 1384 dest->flags = be16_to_cpu(src->flags); 1385 dest->ctrl = be16_to_cpu(src->ctrl); 1386 dest->cpa = be32_to_cpu(src->cpa); 1387 dest->dstat = src->dstat; 1388 dest->cstat = src->cstat; 1389 dest->count = be16_to_cpu(src->count); 1390 } 1391 1392 static void copy_schib_from_guest(SCHIB *dest, const SCHIB *src) 1393 { 1394 int i; 1395 /* 1396 * We copy the PMCW and SCSW in and out of local variables to 1397 * avoid taking the address of members of a packed struct. 1398 */ 1399 PMCW src_pmcw, dest_pmcw; 1400 SCSW src_scsw, dest_scsw; 1401 1402 src_pmcw = src->pmcw; 1403 copy_pmcw_from_guest(&dest_pmcw, &src_pmcw); 1404 dest->pmcw = dest_pmcw; 1405 src_scsw = src->scsw; 1406 copy_scsw_from_guest(&dest_scsw, &src_scsw); 1407 dest->scsw = dest_scsw; 1408 dest->mba = be64_to_cpu(src->mba); 1409 for (i = 0; i < ARRAY_SIZE(dest->mda); i++) { 1410 dest->mda[i] = src->mda[i]; 1411 } 1412 } 1413 1414 IOInstEnding css_do_msch(SubchDev *sch, const SCHIB *orig_schib) 1415 { 1416 SCHIB *schib = &sch->curr_status; 1417 uint16_t oldflags; 1418 SCHIB schib_copy; 1419 1420 if (!(schib->pmcw.flags & PMCW_FLAGS_MASK_DNV)) { 1421 return IOINST_CC_EXPECTED; 1422 } 1423 1424 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1425 return IOINST_CC_STATUS_PRESENT; 1426 } 1427 1428 if (schib->scsw.ctrl & 1429 (SCSW_FCTL_START_FUNC|SCSW_FCTL_HALT_FUNC|SCSW_FCTL_CLEAR_FUNC)) { 1430 return IOINST_CC_BUSY; 1431 } 1432 1433 copy_schib_from_guest(&schib_copy, orig_schib); 1434 /* Only update the program-modifiable fields. */ 1435 schib->pmcw.intparm = schib_copy.pmcw.intparm; 1436 oldflags = schib->pmcw.flags; 1437 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1438 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1439 PMCW_FLAGS_MASK_MP); 1440 schib->pmcw.flags |= schib_copy.pmcw.flags & 1441 (PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 1442 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 1443 PMCW_FLAGS_MASK_MP); 1444 schib->pmcw.lpm = schib_copy.pmcw.lpm; 1445 schib->pmcw.mbi = schib_copy.pmcw.mbi; 1446 schib->pmcw.pom = schib_copy.pmcw.pom; 1447 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1448 schib->pmcw.chars |= schib_copy.pmcw.chars & 1449 (PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_CSENSE); 1450 schib->mba = schib_copy.mba; 1451 1452 /* Has the channel been disabled? */ 1453 if (sch->disable_cb && (oldflags & PMCW_FLAGS_MASK_ENA) != 0 1454 && (schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) == 0) { 1455 sch->disable_cb(sch); 1456 } 1457 return IOINST_CC_EXPECTED; 1458 } 1459 1460 IOInstEnding css_do_xsch(SubchDev *sch) 1461 { 1462 SCHIB *schib = &sch->curr_status; 1463 1464 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1465 return IOINST_CC_NOT_OPERATIONAL; 1466 } 1467 1468 if (schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) { 1469 return IOINST_CC_STATUS_PRESENT; 1470 } 1471 1472 if (!(schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) || 1473 ((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1474 (!(schib->scsw.ctrl & 1475 (SCSW_ACTL_RESUME_PEND | SCSW_ACTL_START_PEND | SCSW_ACTL_SUSP))) || 1476 (schib->scsw.ctrl & SCSW_ACTL_SUBCH_ACTIVE)) { 1477 return IOINST_CC_BUSY; 1478 } 1479 1480 /* Cancel the current operation. */ 1481 schib->scsw.ctrl &= ~(SCSW_FCTL_START_FUNC | 1482 SCSW_ACTL_RESUME_PEND | 1483 SCSW_ACTL_START_PEND | 1484 SCSW_ACTL_SUSP); 1485 sch->channel_prog = 0x0; 1486 sch->last_cmd_valid = false; 1487 schib->scsw.dstat = 0; 1488 schib->scsw.cstat = 0; 1489 return IOINST_CC_EXPECTED; 1490 } 1491 1492 IOInstEnding css_do_csch(SubchDev *sch) 1493 { 1494 SCHIB *schib = &sch->curr_status; 1495 1496 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1497 return IOINST_CC_NOT_OPERATIONAL; 1498 } 1499 1500 /* Trigger the clear function. */ 1501 schib->scsw.ctrl &= ~(SCSW_CTRL_MASK_FCTL | SCSW_CTRL_MASK_ACTL); 1502 schib->scsw.ctrl |= SCSW_FCTL_CLEAR_FUNC | SCSW_ACTL_CLEAR_PEND; 1503 1504 return do_subchannel_work(sch); 1505 } 1506 1507 IOInstEnding css_do_hsch(SubchDev *sch) 1508 { 1509 SCHIB *schib = &sch->curr_status; 1510 1511 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1512 return IOINST_CC_NOT_OPERATIONAL; 1513 } 1514 1515 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == SCSW_STCTL_STATUS_PEND) || 1516 (schib->scsw.ctrl & (SCSW_STCTL_PRIMARY | 1517 SCSW_STCTL_SECONDARY | 1518 SCSW_STCTL_ALERT))) { 1519 return IOINST_CC_STATUS_PRESENT; 1520 } 1521 1522 if (schib->scsw.ctrl & (SCSW_FCTL_HALT_FUNC | SCSW_FCTL_CLEAR_FUNC)) { 1523 return IOINST_CC_BUSY; 1524 } 1525 1526 /* Trigger the halt function. */ 1527 schib->scsw.ctrl |= SCSW_FCTL_HALT_FUNC; 1528 schib->scsw.ctrl &= ~SCSW_FCTL_START_FUNC; 1529 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL) == 1530 (SCSW_ACTL_SUBCH_ACTIVE | SCSW_ACTL_DEVICE_ACTIVE)) && 1531 ((schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL) == 1532 SCSW_STCTL_INTERMEDIATE)) { 1533 schib->scsw.ctrl &= ~SCSW_STCTL_STATUS_PEND; 1534 } 1535 schib->scsw.ctrl |= SCSW_ACTL_HALT_PEND; 1536 1537 return do_subchannel_work(sch); 1538 } 1539 1540 static void css_update_chnmon(SubchDev *sch) 1541 { 1542 if (!(sch->curr_status.pmcw.flags & PMCW_FLAGS_MASK_MME)) { 1543 /* Not active. */ 1544 return; 1545 } 1546 /* The counter is conveniently located at the beginning of the struct. */ 1547 if (sch->curr_status.pmcw.chars & PMCW_CHARS_MASK_MBFC) { 1548 /* Format 1, per-subchannel area. */ 1549 uint32_t count; 1550 1551 count = address_space_ldl(&address_space_memory, 1552 sch->curr_status.mba, 1553 MEMTXATTRS_UNSPECIFIED, 1554 NULL); 1555 count++; 1556 address_space_stl(&address_space_memory, sch->curr_status.mba, count, 1557 MEMTXATTRS_UNSPECIFIED, NULL); 1558 } else { 1559 /* Format 0, global area. */ 1560 uint32_t offset; 1561 uint16_t count; 1562 1563 offset = sch->curr_status.pmcw.mbi << 5; 1564 count = address_space_lduw(&address_space_memory, 1565 channel_subsys.chnmon_area + offset, 1566 MEMTXATTRS_UNSPECIFIED, 1567 NULL); 1568 count++; 1569 address_space_stw(&address_space_memory, 1570 channel_subsys.chnmon_area + offset, count, 1571 MEMTXATTRS_UNSPECIFIED, NULL); 1572 } 1573 } 1574 1575 IOInstEnding css_do_ssch(SubchDev *sch, ORB *orb) 1576 { 1577 SCHIB *schib = &sch->curr_status; 1578 1579 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1580 return IOINST_CC_NOT_OPERATIONAL; 1581 } 1582 1583 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1584 return IOINST_CC_STATUS_PRESENT; 1585 } 1586 1587 if (schib->scsw.ctrl & (SCSW_FCTL_START_FUNC | 1588 SCSW_FCTL_HALT_FUNC | 1589 SCSW_FCTL_CLEAR_FUNC)) { 1590 return IOINST_CC_BUSY; 1591 } 1592 1593 /* If monitoring is active, update counter. */ 1594 if (channel_subsys.chnmon_active) { 1595 css_update_chnmon(sch); 1596 } 1597 sch->orb = *orb; 1598 sch->channel_prog = orb->cpa; 1599 /* Trigger the start function. */ 1600 schib->scsw.ctrl |= (SCSW_FCTL_START_FUNC | SCSW_ACTL_START_PEND); 1601 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1602 1603 return do_subchannel_work(sch); 1604 } 1605 1606 static void copy_irb_to_guest(IRB *dest, const IRB *src, const PMCW *pmcw, 1607 int *irb_len) 1608 { 1609 int i; 1610 uint16_t stctl = src->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1611 uint16_t actl = src->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1612 1613 copy_scsw_to_guest(&dest->scsw, &src->scsw); 1614 1615 copy_esw_to_guest(&dest->esw, &src->esw); 1616 1617 for (i = 0; i < ARRAY_SIZE(dest->ecw); i++) { 1618 dest->ecw[i] = cpu_to_be32(src->ecw[i]); 1619 } 1620 *irb_len = sizeof(*dest) - sizeof(dest->emw); 1621 1622 /* extended measurements enabled? */ 1623 if ((src->scsw.flags & SCSW_FLAGS_MASK_ESWF) || 1624 !(pmcw->flags & PMCW_FLAGS_MASK_TF) || 1625 !(pmcw->chars & PMCW_CHARS_MASK_XMWME)) { 1626 return; 1627 } 1628 /* extended measurements pending? */ 1629 if (!(stctl & SCSW_STCTL_STATUS_PEND)) { 1630 return; 1631 } 1632 if ((stctl & SCSW_STCTL_PRIMARY) || 1633 (stctl == SCSW_STCTL_SECONDARY) || 1634 ((stctl & SCSW_STCTL_INTERMEDIATE) && (actl & SCSW_ACTL_SUSP))) { 1635 for (i = 0; i < ARRAY_SIZE(dest->emw); i++) { 1636 dest->emw[i] = cpu_to_be32(src->emw[i]); 1637 } 1638 } 1639 *irb_len = sizeof(*dest); 1640 } 1641 1642 static void build_irb_sense_data(SubchDev *sch, IRB *irb) 1643 { 1644 int i; 1645 1646 /* Attention: sense_data is already BE! */ 1647 memcpy(irb->ecw, sch->sense_data, sizeof(sch->sense_data)); 1648 for (i = 0; i < ARRAY_SIZE(irb->ecw); i++) { 1649 irb->ecw[i] = be32_to_cpu(irb->ecw[i]); 1650 } 1651 } 1652 1653 void build_irb_passthrough(SubchDev *sch, IRB *irb) 1654 { 1655 /* Copy ESW from hardware */ 1656 irb->esw = sch->esw; 1657 1658 /* 1659 * If (irb->esw.erw & ESW_ERW_SENSE) is true, then the contents 1660 * of the ECW is sense data. If false, then it is model-dependent 1661 * information. Either way, copy it into the IRB for the guest to 1662 * read/decide what to do with. 1663 */ 1664 build_irb_sense_data(sch, irb); 1665 } 1666 1667 void build_irb_virtual(SubchDev *sch, IRB *irb) 1668 { 1669 SCHIB *schib = &sch->curr_status; 1670 uint16_t stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1671 1672 if (stctl & SCSW_STCTL_STATUS_PEND) { 1673 if (schib->scsw.cstat & (SCSW_CSTAT_DATA_CHECK | 1674 SCSW_CSTAT_CHN_CTRL_CHK | 1675 SCSW_CSTAT_INTF_CTRL_CHK)) { 1676 irb->scsw.flags |= SCSW_FLAGS_MASK_ESWF; 1677 irb->esw.word0 = 0x04804000; 1678 } else { 1679 irb->esw.word0 = 0x00800000; 1680 } 1681 /* If a unit check is pending, copy sense data. */ 1682 if ((schib->scsw.dstat & SCSW_DSTAT_UNIT_CHECK) && 1683 (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE)) { 1684 irb->scsw.flags |= SCSW_FLAGS_MASK_ESWF | SCSW_FLAGS_MASK_ECTL; 1685 build_irb_sense_data(sch, irb); 1686 irb->esw.erw = ESW_ERW_SENSE | (sizeof(sch->sense_data) << 8); 1687 } 1688 } 1689 } 1690 1691 int css_do_tsch_get_irb(SubchDev *sch, IRB *target_irb, int *irb_len) 1692 { 1693 SCHIB *schib = &sch->curr_status; 1694 PMCW p; 1695 uint16_t stctl; 1696 IRB irb; 1697 1698 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1699 return 3; 1700 } 1701 1702 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1703 1704 /* Prepare the irb for the guest. */ 1705 memset(&irb, 0, sizeof(IRB)); 1706 1707 /* Copy scsw from current status. */ 1708 irb.scsw = schib->scsw; 1709 1710 /* Build other IRB data, if necessary */ 1711 if (sch->irb_cb) { 1712 sch->irb_cb(sch, &irb); 1713 } 1714 1715 /* Store the irb to the guest. */ 1716 p = schib->pmcw; 1717 copy_irb_to_guest(target_irb, &irb, &p, irb_len); 1718 1719 return ((stctl & SCSW_STCTL_STATUS_PEND) == 0); 1720 } 1721 1722 void css_do_tsch_update_subch(SubchDev *sch) 1723 { 1724 SCHIB *schib = &sch->curr_status; 1725 uint16_t stctl; 1726 uint16_t fctl; 1727 uint16_t actl; 1728 1729 stctl = schib->scsw.ctrl & SCSW_CTRL_MASK_STCTL; 1730 fctl = schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL; 1731 actl = schib->scsw.ctrl & SCSW_CTRL_MASK_ACTL; 1732 1733 /* Clear conditions on subchannel, if applicable. */ 1734 if (stctl & SCSW_STCTL_STATUS_PEND) { 1735 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_STCTL; 1736 if ((stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) || 1737 ((fctl & SCSW_FCTL_HALT_FUNC) && 1738 (actl & SCSW_ACTL_SUSP))) { 1739 schib->scsw.ctrl &= ~SCSW_CTRL_MASK_FCTL; 1740 } 1741 if (stctl != (SCSW_STCTL_INTERMEDIATE | SCSW_STCTL_STATUS_PEND)) { 1742 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1743 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1744 SCSW_ACTL_START_PEND | 1745 SCSW_ACTL_HALT_PEND | 1746 SCSW_ACTL_CLEAR_PEND | 1747 SCSW_ACTL_SUSP); 1748 } else { 1749 if ((actl & SCSW_ACTL_SUSP) && 1750 (fctl & SCSW_FCTL_START_FUNC)) { 1751 schib->scsw.flags &= ~SCSW_FLAGS_MASK_PNO; 1752 if (fctl & SCSW_FCTL_HALT_FUNC) { 1753 schib->scsw.ctrl &= ~(SCSW_ACTL_RESUME_PEND | 1754 SCSW_ACTL_START_PEND | 1755 SCSW_ACTL_HALT_PEND | 1756 SCSW_ACTL_CLEAR_PEND | 1757 SCSW_ACTL_SUSP); 1758 } else { 1759 schib->scsw.ctrl &= ~SCSW_ACTL_RESUME_PEND; 1760 } 1761 } 1762 } 1763 /* Clear pending sense data. */ 1764 if (schib->pmcw.chars & PMCW_CHARS_MASK_CSENSE) { 1765 memset(sch->sense_data, 0 , sizeof(sch->sense_data)); 1766 } 1767 } 1768 } 1769 1770 static void copy_crw_to_guest(CRW *dest, const CRW *src) 1771 { 1772 dest->flags = cpu_to_be16(src->flags); 1773 dest->rsid = cpu_to_be16(src->rsid); 1774 } 1775 1776 int css_do_stcrw(CRW *crw) 1777 { 1778 CrwContainer *crw_cont; 1779 int ret; 1780 1781 crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws); 1782 if (crw_cont) { 1783 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 1784 copy_crw_to_guest(crw, &crw_cont->crw); 1785 g_free(crw_cont); 1786 ret = 0; 1787 } else { 1788 /* List was empty, turn crw machine checks on again. */ 1789 memset(crw, 0, sizeof(*crw)); 1790 channel_subsys.do_crw_mchk = true; 1791 ret = 1; 1792 } 1793 1794 return ret; 1795 } 1796 1797 static void copy_crw_from_guest(CRW *dest, const CRW *src) 1798 { 1799 dest->flags = be16_to_cpu(src->flags); 1800 dest->rsid = be16_to_cpu(src->rsid); 1801 } 1802 1803 void css_undo_stcrw(CRW *crw) 1804 { 1805 CrwContainer *crw_cont; 1806 1807 crw_cont = g_try_new0(CrwContainer, 1); 1808 if (!crw_cont) { 1809 channel_subsys.crws_lost = true; 1810 return; 1811 } 1812 copy_crw_from_guest(&crw_cont->crw, crw); 1813 1814 QTAILQ_INSERT_HEAD(&channel_subsys.pending_crws, crw_cont, sibling); 1815 } 1816 1817 int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid, 1818 int rfmt, void *buf) 1819 { 1820 int i, desc_size; 1821 uint32_t words[8]; 1822 uint32_t chpid_type_word; 1823 CssImage *css; 1824 1825 if (!m && !cssid) { 1826 css = channel_subsys.css[channel_subsys.default_cssid]; 1827 } else { 1828 css = channel_subsys.css[cssid]; 1829 } 1830 if (!css) { 1831 return 0; 1832 } 1833 desc_size = 0; 1834 for (i = f_chpid; i <= l_chpid; i++) { 1835 if (css->chpids[i].in_use) { 1836 chpid_type_word = 0x80000000 | (css->chpids[i].type << 8) | i; 1837 if (rfmt == 0) { 1838 words[0] = cpu_to_be32(chpid_type_word); 1839 words[1] = 0; 1840 memcpy(buf + desc_size, words, 8); 1841 desc_size += 8; 1842 } else if (rfmt == 1) { 1843 words[0] = cpu_to_be32(chpid_type_word); 1844 words[1] = 0; 1845 words[2] = 0; 1846 words[3] = 0; 1847 words[4] = 0; 1848 words[5] = 0; 1849 words[6] = 0; 1850 words[7] = 0; 1851 memcpy(buf + desc_size, words, 32); 1852 desc_size += 32; 1853 } 1854 } 1855 } 1856 return desc_size; 1857 } 1858 1859 void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo) 1860 { 1861 /* dct is currently ignored (not really meaningful for our devices) */ 1862 /* TODO: Don't ignore mbk. */ 1863 if (update && !channel_subsys.chnmon_active) { 1864 /* Enable measuring. */ 1865 channel_subsys.chnmon_area = mbo; 1866 channel_subsys.chnmon_active = true; 1867 } 1868 if (!update && channel_subsys.chnmon_active) { 1869 /* Disable measuring. */ 1870 channel_subsys.chnmon_area = 0; 1871 channel_subsys.chnmon_active = false; 1872 } 1873 } 1874 1875 IOInstEnding css_do_rsch(SubchDev *sch) 1876 { 1877 SCHIB *schib = &sch->curr_status; 1878 1879 if (~(schib->pmcw.flags) & (PMCW_FLAGS_MASK_DNV | PMCW_FLAGS_MASK_ENA)) { 1880 return IOINST_CC_NOT_OPERATIONAL; 1881 } 1882 1883 if (schib->scsw.ctrl & SCSW_STCTL_STATUS_PEND) { 1884 return IOINST_CC_STATUS_PRESENT; 1885 } 1886 1887 if (((schib->scsw.ctrl & SCSW_CTRL_MASK_FCTL) != SCSW_FCTL_START_FUNC) || 1888 (schib->scsw.ctrl & SCSW_ACTL_RESUME_PEND) || 1889 (!(schib->scsw.ctrl & SCSW_ACTL_SUSP))) { 1890 return IOINST_CC_BUSY; 1891 } 1892 1893 /* If monitoring is active, update counter. */ 1894 if (channel_subsys.chnmon_active) { 1895 css_update_chnmon(sch); 1896 } 1897 1898 schib->scsw.ctrl |= SCSW_ACTL_RESUME_PEND; 1899 return do_subchannel_work(sch); 1900 } 1901 1902 int css_do_rchp(uint8_t cssid, uint8_t chpid) 1903 { 1904 uint8_t real_cssid; 1905 1906 if (cssid > channel_subsys.max_cssid) { 1907 return -EINVAL; 1908 } 1909 if (channel_subsys.max_cssid == 0) { 1910 real_cssid = channel_subsys.default_cssid; 1911 } else { 1912 real_cssid = cssid; 1913 } 1914 if (!channel_subsys.css[real_cssid]) { 1915 return -EINVAL; 1916 } 1917 1918 if (!channel_subsys.css[real_cssid]->chpids[chpid].in_use) { 1919 return -ENODEV; 1920 } 1921 1922 if (!channel_subsys.css[real_cssid]->chpids[chpid].is_virtual) { 1923 fprintf(stderr, 1924 "rchp unsupported for non-virtual chpid %x.%02x!\n", 1925 real_cssid, chpid); 1926 return -ENODEV; 1927 } 1928 1929 /* We don't really use a channel path, so we're done here. */ 1930 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 1931 channel_subsys.max_cssid > 0 ? 1 : 0, chpid); 1932 if (channel_subsys.max_cssid > 0) { 1933 css_queue_crw(CRW_RSC_CHP, CRW_ERC_INIT, 1, 0, real_cssid << 8); 1934 } 1935 return 0; 1936 } 1937 1938 bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid) 1939 { 1940 SubchSet *set; 1941 uint8_t real_cssid; 1942 1943 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 1944 if (ssid > MAX_SSID || 1945 !channel_subsys.css[real_cssid] || 1946 !channel_subsys.css[real_cssid]->sch_set[ssid]) { 1947 return true; 1948 } 1949 set = channel_subsys.css[real_cssid]->sch_set[ssid]; 1950 return schid > find_last_bit(set->schids_used, 1951 (MAX_SCHID + 1) / sizeof(unsigned long)); 1952 } 1953 1954 unsigned int css_find_free_chpid(uint8_t cssid) 1955 { 1956 CssImage *css = channel_subsys.css[cssid]; 1957 unsigned int chpid; 1958 1959 if (!css) { 1960 return MAX_CHPID + 1; 1961 } 1962 1963 for (chpid = 0; chpid <= MAX_CHPID; chpid++) { 1964 /* skip reserved chpid */ 1965 if (chpid == VIRTIO_CCW_CHPID) { 1966 continue; 1967 } 1968 if (!css->chpids[chpid].in_use) { 1969 return chpid; 1970 } 1971 } 1972 return MAX_CHPID + 1; 1973 } 1974 1975 static int css_add_chpid(uint8_t cssid, uint8_t chpid, uint8_t type, 1976 bool is_virt) 1977 { 1978 CssImage *css; 1979 1980 trace_css_chpid_add(cssid, chpid, type); 1981 css = channel_subsys.css[cssid]; 1982 if (!css) { 1983 return -EINVAL; 1984 } 1985 if (css->chpids[chpid].in_use) { 1986 return -EEXIST; 1987 } 1988 css->chpids[chpid].in_use = 1; 1989 css->chpids[chpid].type = type; 1990 css->chpids[chpid].is_virtual = is_virt; 1991 1992 css_generate_chp_crws(cssid, chpid); 1993 1994 return 0; 1995 } 1996 1997 void css_sch_build_virtual_schib(SubchDev *sch, uint8_t chpid, uint8_t type) 1998 { 1999 SCHIB *schib = &sch->curr_status; 2000 int i; 2001 CssImage *css = channel_subsys.css[sch->cssid]; 2002 2003 assert(css != NULL); 2004 memset(&schib->pmcw, 0, sizeof(PMCW)); 2005 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2006 schib->pmcw.devno = sch->devno; 2007 /* single path */ 2008 schib->pmcw.pim = 0x80; 2009 schib->pmcw.pom = 0xff; 2010 schib->pmcw.pam = 0x80; 2011 schib->pmcw.chpid[0] = chpid; 2012 if (!css->chpids[chpid].in_use) { 2013 css_add_chpid(sch->cssid, chpid, type, true); 2014 } 2015 2016 memset(&schib->scsw, 0, sizeof(SCSW)); 2017 schib->mba = 0; 2018 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) { 2019 schib->mda[i] = 0; 2020 } 2021 } 2022 2023 SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid, uint16_t schid) 2024 { 2025 uint8_t real_cssid; 2026 2027 real_cssid = (!m && (cssid == 0)) ? channel_subsys.default_cssid : cssid; 2028 2029 if (!channel_subsys.css[real_cssid]) { 2030 return NULL; 2031 } 2032 2033 if (!channel_subsys.css[real_cssid]->sch_set[ssid]) { 2034 return NULL; 2035 } 2036 2037 return channel_subsys.css[real_cssid]->sch_set[ssid]->sch[schid]; 2038 } 2039 2040 /** 2041 * Return free device number in subchannel set. 2042 * 2043 * Return index of the first free device number in the subchannel set 2044 * identified by @p cssid and @p ssid, beginning the search at @p 2045 * start and wrapping around at MAX_DEVNO. Return a value exceeding 2046 * MAX_SCHID if there are no free device numbers in the subchannel 2047 * set. 2048 */ 2049 static uint32_t css_find_free_devno(uint8_t cssid, uint8_t ssid, 2050 uint16_t start) 2051 { 2052 uint32_t round; 2053 2054 for (round = 0; round <= MAX_DEVNO; round++) { 2055 uint16_t devno = (start + round) % MAX_DEVNO; 2056 2057 if (!css_devno_used(cssid, ssid, devno)) { 2058 return devno; 2059 } 2060 } 2061 return MAX_DEVNO + 1; 2062 } 2063 2064 /** 2065 * Return first free subchannel (id) in subchannel set. 2066 * 2067 * Return index of the first free subchannel in the subchannel set 2068 * identified by @p cssid and @p ssid, if there is any. Return a value 2069 * exceeding MAX_SCHID if there are no free subchannels in the 2070 * subchannel set. 2071 */ 2072 static uint32_t css_find_free_subch(uint8_t cssid, uint8_t ssid) 2073 { 2074 uint32_t schid; 2075 2076 for (schid = 0; schid <= MAX_SCHID; schid++) { 2077 if (!css_find_subch(1, cssid, ssid, schid)) { 2078 return schid; 2079 } 2080 } 2081 return MAX_SCHID + 1; 2082 } 2083 2084 /** 2085 * Return first free subchannel (id) in subchannel set for a device number 2086 * 2087 * Verify the device number @p devno is not used yet in the subchannel 2088 * set identified by @p cssid and @p ssid. Set @p schid to the index 2089 * of the first free subchannel in the subchannel set, if there is 2090 * any. Return true if everything succeeded and false otherwise. 2091 */ 2092 static bool css_find_free_subch_for_devno(uint8_t cssid, uint8_t ssid, 2093 uint16_t devno, uint16_t *schid, 2094 Error **errp) 2095 { 2096 uint32_t free_schid; 2097 2098 assert(schid); 2099 if (css_devno_used(cssid, ssid, devno)) { 2100 error_setg(errp, "Device %x.%x.%04x already exists", 2101 cssid, ssid, devno); 2102 return false; 2103 } 2104 free_schid = css_find_free_subch(cssid, ssid); 2105 if (free_schid > MAX_SCHID) { 2106 error_setg(errp, "No free subchannel found for %x.%x.%04x", 2107 cssid, ssid, devno); 2108 return false; 2109 } 2110 *schid = free_schid; 2111 return true; 2112 } 2113 2114 /** 2115 * Return first free subchannel (id) and device number 2116 * 2117 * Locate the first free subchannel and first free device number in 2118 * any of the subchannel sets of the channel subsystem identified by 2119 * @p cssid. Return false if no free subchannel / device number could 2120 * be found. Otherwise set @p ssid, @p devno and @p schid to identify 2121 * the available subchannel and device number and return true. 2122 * 2123 * May modify @p ssid, @p devno and / or @p schid even if no free 2124 * subchannel / device number could be found. 2125 */ 2126 static bool css_find_free_subch_and_devno(uint8_t cssid, uint8_t *ssid, 2127 uint16_t *devno, uint16_t *schid, 2128 Error **errp) 2129 { 2130 uint32_t free_schid, free_devno; 2131 2132 assert(ssid && devno && schid); 2133 for (*ssid = 0; *ssid <= MAX_SSID; (*ssid)++) { 2134 free_schid = css_find_free_subch(cssid, *ssid); 2135 if (free_schid > MAX_SCHID) { 2136 continue; 2137 } 2138 free_devno = css_find_free_devno(cssid, *ssid, free_schid); 2139 if (free_devno > MAX_DEVNO) { 2140 continue; 2141 } 2142 *schid = free_schid; 2143 *devno = free_devno; 2144 return true; 2145 } 2146 error_setg(errp, "Virtual channel subsystem is full!"); 2147 return false; 2148 } 2149 2150 bool css_subch_visible(SubchDev *sch) 2151 { 2152 if (sch->ssid > channel_subsys.max_ssid) { 2153 return false; 2154 } 2155 2156 if (sch->cssid != channel_subsys.default_cssid) { 2157 return (channel_subsys.max_cssid > 0); 2158 } 2159 2160 return true; 2161 } 2162 2163 bool css_present(uint8_t cssid) 2164 { 2165 return (channel_subsys.css[cssid] != NULL); 2166 } 2167 2168 bool css_devno_used(uint8_t cssid, uint8_t ssid, uint16_t devno) 2169 { 2170 if (!channel_subsys.css[cssid]) { 2171 return false; 2172 } 2173 if (!channel_subsys.css[cssid]->sch_set[ssid]) { 2174 return false; 2175 } 2176 2177 return !!test_bit(devno, 2178 channel_subsys.css[cssid]->sch_set[ssid]->devnos_used); 2179 } 2180 2181 void css_subch_assign(uint8_t cssid, uint8_t ssid, uint16_t schid, 2182 uint16_t devno, SubchDev *sch) 2183 { 2184 CssImage *css; 2185 SubchSet *s_set; 2186 2187 trace_css_assign_subch(sch ? "assign" : "deassign", cssid, ssid, schid, 2188 devno); 2189 if (!channel_subsys.css[cssid]) { 2190 fprintf(stderr, 2191 "Suspicious call to %s (%x.%x.%04x) for non-existing css!\n", 2192 __func__, cssid, ssid, schid); 2193 return; 2194 } 2195 css = channel_subsys.css[cssid]; 2196 2197 if (!css->sch_set[ssid]) { 2198 css->sch_set[ssid] = g_new0(SubchSet, 1); 2199 } 2200 s_set = css->sch_set[ssid]; 2201 2202 s_set->sch[schid] = sch; 2203 if (sch) { 2204 set_bit(schid, s_set->schids_used); 2205 set_bit(devno, s_set->devnos_used); 2206 } else { 2207 clear_bit(schid, s_set->schids_used); 2208 clear_bit(devno, s_set->devnos_used); 2209 } 2210 } 2211 2212 void css_crw_add_to_queue(CRW crw) 2213 { 2214 CrwContainer *crw_cont; 2215 2216 trace_css_crw((crw.flags & CRW_FLAGS_MASK_RSC) >> 8, 2217 crw.flags & CRW_FLAGS_MASK_ERC, 2218 crw.rsid, 2219 (crw.flags & CRW_FLAGS_MASK_C) ? "(chained)" : ""); 2220 2221 /* TODO: Maybe use a static crw pool? */ 2222 crw_cont = g_try_new0(CrwContainer, 1); 2223 if (!crw_cont) { 2224 channel_subsys.crws_lost = true; 2225 return; 2226 } 2227 2228 crw_cont->crw = crw; 2229 2230 QTAILQ_INSERT_TAIL(&channel_subsys.pending_crws, crw_cont, sibling); 2231 2232 if (channel_subsys.do_crw_mchk) { 2233 channel_subsys.do_crw_mchk = false; 2234 /* Inject crw pending machine check. */ 2235 s390_crw_mchk(); 2236 } 2237 } 2238 2239 void css_queue_crw(uint8_t rsc, uint8_t erc, int solicited, 2240 int chain, uint16_t rsid) 2241 { 2242 CRW crw; 2243 2244 crw.flags = (rsc << 8) | erc; 2245 if (solicited) { 2246 crw.flags |= CRW_FLAGS_MASK_S; 2247 } 2248 if (chain) { 2249 crw.flags |= CRW_FLAGS_MASK_C; 2250 } 2251 crw.rsid = rsid; 2252 if (channel_subsys.crws_lost) { 2253 crw.flags |= CRW_FLAGS_MASK_R; 2254 channel_subsys.crws_lost = false; 2255 } 2256 2257 css_crw_add_to_queue(crw); 2258 } 2259 2260 void css_generate_sch_crws(uint8_t cssid, uint8_t ssid, uint16_t schid, 2261 int hotplugged, int add) 2262 { 2263 uint8_t guest_cssid; 2264 bool chain_crw; 2265 2266 if (add && !hotplugged) { 2267 return; 2268 } 2269 if (channel_subsys.max_cssid == 0) { 2270 /* Default cssid shows up as 0. */ 2271 guest_cssid = (cssid == channel_subsys.default_cssid) ? 0 : cssid; 2272 } else { 2273 /* Show real cssid to the guest. */ 2274 guest_cssid = cssid; 2275 } 2276 /* 2277 * Only notify for higher subchannel sets/channel subsystems if the 2278 * guest has enabled it. 2279 */ 2280 if ((ssid > channel_subsys.max_ssid) || 2281 (guest_cssid > channel_subsys.max_cssid) || 2282 ((channel_subsys.max_cssid == 0) && 2283 (cssid != channel_subsys.default_cssid))) { 2284 return; 2285 } 2286 chain_crw = (channel_subsys.max_ssid > 0) || 2287 (channel_subsys.max_cssid > 0); 2288 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, chain_crw ? 1 : 0, schid); 2289 if (chain_crw) { 2290 css_queue_crw(CRW_RSC_SUBCH, CRW_ERC_IPI, 0, 0, 2291 (guest_cssid << 8) | (ssid << 4)); 2292 } 2293 /* RW_ERC_IPI --> clear pending interrupts */ 2294 css_clear_io_interrupt(css_do_build_subchannel_id(cssid, ssid), schid); 2295 } 2296 2297 void css_generate_chp_crws(uint8_t cssid, uint8_t chpid) 2298 { 2299 /* TODO */ 2300 } 2301 2302 void css_generate_css_crws(uint8_t cssid) 2303 { 2304 if (!channel_subsys.sei_pending) { 2305 css_queue_crw(CRW_RSC_CSS, CRW_ERC_EVENT, 0, 0, cssid); 2306 } 2307 channel_subsys.sei_pending = true; 2308 } 2309 2310 void css_clear_sei_pending(void) 2311 { 2312 channel_subsys.sei_pending = false; 2313 } 2314 2315 int css_enable_mcsse(void) 2316 { 2317 trace_css_enable_facility("mcsse"); 2318 channel_subsys.max_cssid = MAX_CSSID; 2319 return 0; 2320 } 2321 2322 int css_enable_mss(void) 2323 { 2324 trace_css_enable_facility("mss"); 2325 channel_subsys.max_ssid = MAX_SSID; 2326 return 0; 2327 } 2328 2329 void css_reset_sch(SubchDev *sch) 2330 { 2331 SCHIB *schib = &sch->curr_status; 2332 2333 if ((schib->pmcw.flags & PMCW_FLAGS_MASK_ENA) != 0 && sch->disable_cb) { 2334 sch->disable_cb(sch); 2335 } 2336 2337 schib->pmcw.intparm = 0; 2338 schib->pmcw.flags &= ~(PMCW_FLAGS_MASK_ISC | PMCW_FLAGS_MASK_ENA | 2339 PMCW_FLAGS_MASK_LM | PMCW_FLAGS_MASK_MME | 2340 PMCW_FLAGS_MASK_MP | PMCW_FLAGS_MASK_TF); 2341 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2342 schib->pmcw.devno = sch->devno; 2343 schib->pmcw.pim = 0x80; 2344 schib->pmcw.lpm = schib->pmcw.pim; 2345 schib->pmcw.pnom = 0; 2346 schib->pmcw.lpum = 0; 2347 schib->pmcw.mbi = 0; 2348 schib->pmcw.pom = 0xff; 2349 schib->pmcw.pam = 0x80; 2350 schib->pmcw.chars &= ~(PMCW_CHARS_MASK_MBFC | PMCW_CHARS_MASK_XMWME | 2351 PMCW_CHARS_MASK_CSENSE); 2352 2353 memset(&schib->scsw, 0, sizeof(schib->scsw)); 2354 schib->mba = 0; 2355 2356 sch->channel_prog = 0x0; 2357 sch->last_cmd_valid = false; 2358 sch->thinint_active = false; 2359 } 2360 2361 void css_reset(void) 2362 { 2363 CrwContainer *crw_cont; 2364 2365 /* Clean up monitoring. */ 2366 channel_subsys.chnmon_active = false; 2367 channel_subsys.chnmon_area = 0; 2368 2369 /* Clear pending CRWs. */ 2370 while ((crw_cont = QTAILQ_FIRST(&channel_subsys.pending_crws))) { 2371 QTAILQ_REMOVE(&channel_subsys.pending_crws, crw_cont, sibling); 2372 g_free(crw_cont); 2373 } 2374 channel_subsys.sei_pending = false; 2375 channel_subsys.do_crw_mchk = true; 2376 channel_subsys.crws_lost = false; 2377 2378 /* Reset maximum ids. */ 2379 channel_subsys.max_cssid = 0; 2380 channel_subsys.max_ssid = 0; 2381 } 2382 2383 static void get_css_devid(Object *obj, Visitor *v, const char *name, 2384 void *opaque, Error **errp) 2385 { 2386 Property *prop = opaque; 2387 CssDevId *dev_id = object_field_prop_ptr(obj, prop); 2388 char buffer[] = "xx.x.xxxx"; 2389 char *p = buffer; 2390 int r; 2391 2392 if (dev_id->valid) { 2393 2394 r = snprintf(buffer, sizeof(buffer), "%02x.%1x.%04x", dev_id->cssid, 2395 dev_id->ssid, dev_id->devid); 2396 assert(r == sizeof(buffer) - 1); 2397 2398 /* drop leading zero */ 2399 if (dev_id->cssid <= 0xf) { 2400 p++; 2401 } 2402 } else { 2403 snprintf(buffer, sizeof(buffer), "<unset>"); 2404 } 2405 2406 visit_type_str(v, name, &p, errp); 2407 } 2408 2409 /* 2410 * parse <cssid>.<ssid>.<devid> and assert valid range for cssid/ssid 2411 */ 2412 static void set_css_devid(Object *obj, Visitor *v, const char *name, 2413 void *opaque, Error **errp) 2414 { 2415 Property *prop = opaque; 2416 CssDevId *dev_id = object_field_prop_ptr(obj, prop); 2417 char *str; 2418 int num, n1, n2; 2419 unsigned int cssid, ssid, devid; 2420 2421 if (!visit_type_str(v, name, &str, errp)) { 2422 return; 2423 } 2424 2425 num = sscanf(str, "%2x.%1x%n.%4x%n", &cssid, &ssid, &n1, &devid, &n2); 2426 if (num != 3 || (n2 - n1) != 5 || strlen(str) != n2) { 2427 error_set_from_qdev_prop_error(errp, EINVAL, obj, name, str); 2428 goto out; 2429 } 2430 if ((cssid > MAX_CSSID) || (ssid > MAX_SSID)) { 2431 error_setg(errp, "Invalid cssid or ssid: cssid %x, ssid %x", 2432 cssid, ssid); 2433 goto out; 2434 } 2435 2436 dev_id->cssid = cssid; 2437 dev_id->ssid = ssid; 2438 dev_id->devid = devid; 2439 dev_id->valid = true; 2440 2441 out: 2442 g_free(str); 2443 } 2444 2445 const PropertyInfo css_devid_propinfo = { 2446 .name = "str", 2447 .description = "Identifier of an I/O device in the channel " 2448 "subsystem, example: fe.1.23ab", 2449 .get = get_css_devid, 2450 .set = set_css_devid, 2451 }; 2452 2453 const PropertyInfo css_devid_ro_propinfo = { 2454 .name = "str", 2455 .description = "Read-only identifier of an I/O device in the channel " 2456 "subsystem, example: fe.1.23ab", 2457 .get = get_css_devid, 2458 }; 2459 2460 SubchDev *css_create_sch(CssDevId bus_id, Error **errp) 2461 { 2462 uint16_t schid = 0; 2463 SubchDev *sch; 2464 2465 if (bus_id.valid) { 2466 if (!channel_subsys.css[bus_id.cssid]) { 2467 css_create_css_image(bus_id.cssid, false); 2468 } 2469 2470 if (!css_find_free_subch_for_devno(bus_id.cssid, bus_id.ssid, 2471 bus_id.devid, &schid, errp)) { 2472 return NULL; 2473 } 2474 } else { 2475 for (bus_id.cssid = channel_subsys.default_cssid;;) { 2476 if (!channel_subsys.css[bus_id.cssid]) { 2477 css_create_css_image(bus_id.cssid, false); 2478 } 2479 2480 if (css_find_free_subch_and_devno(bus_id.cssid, &bus_id.ssid, 2481 &bus_id.devid, &schid, 2482 NULL)) { 2483 break; 2484 } 2485 bus_id.cssid = (bus_id.cssid + 1) % MAX_CSSID; 2486 if (bus_id.cssid == channel_subsys.default_cssid) { 2487 error_setg(errp, "Virtual channel subsystem is full!"); 2488 return NULL; 2489 } 2490 } 2491 } 2492 2493 sch = g_new0(SubchDev, 1); 2494 sch->cssid = bus_id.cssid; 2495 sch->ssid = bus_id.ssid; 2496 sch->devno = bus_id.devid; 2497 sch->schid = schid; 2498 css_subch_assign(sch->cssid, sch->ssid, schid, sch->devno, sch); 2499 return sch; 2500 } 2501 2502 static int css_sch_get_chpids(SubchDev *sch, CssDevId *dev_id) 2503 { 2504 char *fid_path; 2505 FILE *fd; 2506 uint32_t chpid[8]; 2507 int i; 2508 SCHIB *schib = &sch->curr_status; 2509 2510 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/chpids", 2511 dev_id->cssid, dev_id->ssid, dev_id->devid); 2512 fd = fopen(fid_path, "r"); 2513 if (fd == NULL) { 2514 error_report("%s: open %s failed", __func__, fid_path); 2515 g_free(fid_path); 2516 return -EINVAL; 2517 } 2518 2519 if (fscanf(fd, "%x %x %x %x %x %x %x %x", 2520 &chpid[0], &chpid[1], &chpid[2], &chpid[3], 2521 &chpid[4], &chpid[5], &chpid[6], &chpid[7]) != 8) { 2522 fclose(fd); 2523 g_free(fid_path); 2524 return -EINVAL; 2525 } 2526 2527 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) { 2528 schib->pmcw.chpid[i] = chpid[i]; 2529 } 2530 2531 fclose(fd); 2532 g_free(fid_path); 2533 2534 return 0; 2535 } 2536 2537 static int css_sch_get_path_masks(SubchDev *sch, CssDevId *dev_id) 2538 { 2539 char *fid_path; 2540 FILE *fd; 2541 uint32_t pim, pam, pom; 2542 SCHIB *schib = &sch->curr_status; 2543 2544 fid_path = g_strdup_printf("/sys/bus/css/devices/%x.%x.%04x/pimpampom", 2545 dev_id->cssid, dev_id->ssid, dev_id->devid); 2546 fd = fopen(fid_path, "r"); 2547 if (fd == NULL) { 2548 error_report("%s: open %s failed", __func__, fid_path); 2549 g_free(fid_path); 2550 return -EINVAL; 2551 } 2552 2553 if (fscanf(fd, "%x %x %x", &pim, &pam, &pom) != 3) { 2554 fclose(fd); 2555 g_free(fid_path); 2556 return -EINVAL; 2557 } 2558 2559 schib->pmcw.pim = pim; 2560 schib->pmcw.pam = pam; 2561 schib->pmcw.pom = pom; 2562 fclose(fd); 2563 g_free(fid_path); 2564 2565 return 0; 2566 } 2567 2568 static int css_sch_get_chpid_type(uint8_t chpid, uint32_t *type, 2569 CssDevId *dev_id) 2570 { 2571 char *fid_path; 2572 FILE *fd; 2573 2574 fid_path = g_strdup_printf("/sys/devices/css%x/chp0.%02x/type", 2575 dev_id->cssid, chpid); 2576 fd = fopen(fid_path, "r"); 2577 if (fd == NULL) { 2578 error_report("%s: open %s failed", __func__, fid_path); 2579 g_free(fid_path); 2580 return -EINVAL; 2581 } 2582 2583 if (fscanf(fd, "%x", type) != 1) { 2584 fclose(fd); 2585 g_free(fid_path); 2586 return -EINVAL; 2587 } 2588 2589 fclose(fd); 2590 g_free(fid_path); 2591 2592 return 0; 2593 } 2594 2595 /* 2596 * We currently retrieve the real device information from sysfs to build the 2597 * guest subchannel information block without considering the migration feature. 2598 * We need to revisit this problem when we want to add migration support. 2599 */ 2600 int css_sch_build_schib(SubchDev *sch, CssDevId *dev_id) 2601 { 2602 CssImage *css = channel_subsys.css[sch->cssid]; 2603 SCHIB *schib = &sch->curr_status; 2604 uint32_t type; 2605 int i, ret; 2606 2607 assert(css != NULL); 2608 memset(&schib->pmcw, 0, sizeof(PMCW)); 2609 schib->pmcw.flags |= PMCW_FLAGS_MASK_DNV; 2610 /* We are dealing with I/O subchannels only. */ 2611 schib->pmcw.devno = sch->devno; 2612 2613 /* Grab path mask from sysfs. */ 2614 ret = css_sch_get_path_masks(sch, dev_id); 2615 if (ret) { 2616 return ret; 2617 } 2618 2619 /* Grab chpids from sysfs. */ 2620 ret = css_sch_get_chpids(sch, dev_id); 2621 if (ret) { 2622 return ret; 2623 } 2624 2625 /* Build chpid type. */ 2626 for (i = 0; i < ARRAY_SIZE(schib->pmcw.chpid); i++) { 2627 if (schib->pmcw.chpid[i] && !css->chpids[schib->pmcw.chpid[i]].in_use) { 2628 ret = css_sch_get_chpid_type(schib->pmcw.chpid[i], &type, dev_id); 2629 if (ret) { 2630 return ret; 2631 } 2632 css_add_chpid(sch->cssid, schib->pmcw.chpid[i], type, false); 2633 } 2634 } 2635 2636 memset(&schib->scsw, 0, sizeof(SCSW)); 2637 schib->mba = 0; 2638 for (i = 0; i < ARRAY_SIZE(schib->mda); i++) { 2639 schib->mda[i] = 0; 2640 } 2641 2642 return 0; 2643 } 2644