1 /* 2 * s390 PCI instructions 3 * 4 * Copyright 2014 IBM Corp. 5 * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> 6 * Hong Bo Li <lihbbj@cn.ibm.com> 7 * Yi Min Zhao <zyimin@cn.ibm.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or (at 10 * your option) any later version. See the COPYING file in the top-level 11 * directory. 12 */ 13 14 #include "qemu/osdep.h" 15 #include "qemu-common.h" 16 #include "cpu.h" 17 #include "s390-pci-inst.h" 18 #include "s390-pci-bus.h" 19 #include "exec/memory-internal.h" 20 #include "qemu/error-report.h" 21 #include "sysemu/hw_accel.h" 22 23 #ifndef DEBUG_S390PCI_INST 24 #define DEBUG_S390PCI_INST 0 25 #endif 26 27 #define DPRINTF(fmt, ...) \ 28 do { \ 29 if (DEBUG_S390PCI_INST) { \ 30 fprintf(stderr, "s390pci-inst: " fmt, ## __VA_ARGS__); \ 31 } \ 32 } while (0) 33 34 static void s390_set_status_code(CPUS390XState *env, 35 uint8_t r, uint64_t status_code) 36 { 37 env->regs[r] &= ~0xff000000ULL; 38 env->regs[r] |= (status_code & 0xff) << 24; 39 } 40 41 static int list_pci(ClpReqRspListPci *rrb, uint8_t *cc) 42 { 43 S390PCIBusDevice *pbdev = NULL; 44 S390pciState *s = s390_get_phb(); 45 uint32_t res_code, initial_l2, g_l2; 46 int rc, i; 47 uint64_t resume_token; 48 49 rc = 0; 50 if (lduw_p(&rrb->request.hdr.len) != 32) { 51 res_code = CLP_RC_LEN; 52 rc = -EINVAL; 53 goto out; 54 } 55 56 if ((ldl_p(&rrb->request.fmt) & CLP_MASK_FMT) != 0) { 57 res_code = CLP_RC_FMT; 58 rc = -EINVAL; 59 goto out; 60 } 61 62 if ((ldl_p(&rrb->request.fmt) & ~CLP_MASK_FMT) != 0 || 63 ldq_p(&rrb->request.reserved1) != 0) { 64 res_code = CLP_RC_RESNOT0; 65 rc = -EINVAL; 66 goto out; 67 } 68 69 resume_token = ldq_p(&rrb->request.resume_token); 70 71 if (resume_token) { 72 pbdev = s390_pci_find_dev_by_idx(s, resume_token); 73 if (!pbdev) { 74 res_code = CLP_RC_LISTPCI_BADRT; 75 rc = -EINVAL; 76 goto out; 77 } 78 } else { 79 pbdev = s390_pci_find_next_avail_dev(s, NULL); 80 } 81 82 if (lduw_p(&rrb->response.hdr.len) < 48) { 83 res_code = CLP_RC_8K; 84 rc = -EINVAL; 85 goto out; 86 } 87 88 initial_l2 = lduw_p(&rrb->response.hdr.len); 89 if ((initial_l2 - LIST_PCI_HDR_LEN) % sizeof(ClpFhListEntry) 90 != 0) { 91 res_code = CLP_RC_LEN; 92 rc = -EINVAL; 93 *cc = 3; 94 goto out; 95 } 96 97 stl_p(&rrb->response.fmt, 0); 98 stq_p(&rrb->response.reserved1, 0); 99 stl_p(&rrb->response.mdd, FH_MASK_SHM); 100 stw_p(&rrb->response.max_fn, PCI_MAX_FUNCTIONS); 101 rrb->response.flags = UID_CHECKING_ENABLED; 102 rrb->response.entry_size = sizeof(ClpFhListEntry); 103 104 i = 0; 105 g_l2 = LIST_PCI_HDR_LEN; 106 while (g_l2 < initial_l2 && pbdev) { 107 stw_p(&rrb->response.fh_list[i].device_id, 108 pci_get_word(pbdev->pdev->config + PCI_DEVICE_ID)); 109 stw_p(&rrb->response.fh_list[i].vendor_id, 110 pci_get_word(pbdev->pdev->config + PCI_VENDOR_ID)); 111 /* Ignore RESERVED devices. */ 112 stl_p(&rrb->response.fh_list[i].config, 113 pbdev->state == ZPCI_FS_STANDBY ? 0 : 1 << 31); 114 stl_p(&rrb->response.fh_list[i].fid, pbdev->fid); 115 stl_p(&rrb->response.fh_list[i].fh, pbdev->fh); 116 117 g_l2 += sizeof(ClpFhListEntry); 118 /* Add endian check for DPRINTF? */ 119 DPRINTF("g_l2 %d vendor id 0x%x device id 0x%x fid 0x%x fh 0x%x\n", 120 g_l2, 121 lduw_p(&rrb->response.fh_list[i].vendor_id), 122 lduw_p(&rrb->response.fh_list[i].device_id), 123 ldl_p(&rrb->response.fh_list[i].fid), 124 ldl_p(&rrb->response.fh_list[i].fh)); 125 pbdev = s390_pci_find_next_avail_dev(s, pbdev); 126 i++; 127 } 128 129 if (!pbdev) { 130 resume_token = 0; 131 } else { 132 resume_token = pbdev->fh & FH_MASK_INDEX; 133 } 134 stq_p(&rrb->response.resume_token, resume_token); 135 stw_p(&rrb->response.hdr.len, g_l2); 136 stw_p(&rrb->response.hdr.rsp, CLP_RC_OK); 137 out: 138 if (rc) { 139 DPRINTF("list pci failed rc 0x%x\n", rc); 140 stw_p(&rrb->response.hdr.rsp, res_code); 141 } 142 return rc; 143 } 144 145 int clp_service_call(S390CPU *cpu, uint8_t r2, uintptr_t ra) 146 { 147 ClpReqHdr *reqh; 148 ClpRspHdr *resh; 149 S390PCIBusDevice *pbdev; 150 uint32_t req_len; 151 uint32_t res_len; 152 uint8_t buffer[4096 * 2]; 153 uint8_t cc = 0; 154 CPUS390XState *env = &cpu->env; 155 S390pciState *s = s390_get_phb(); 156 int i; 157 158 if (env->psw.mask & PSW_MASK_PSTATE) { 159 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 160 return 0; 161 } 162 163 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, sizeof(*reqh))) { 164 s390_cpu_virt_mem_handle_exc(cpu, ra); 165 return 0; 166 } 167 reqh = (ClpReqHdr *)buffer; 168 req_len = lduw_p(&reqh->len); 169 if (req_len < 16 || req_len > 8184 || (req_len % 8 != 0)) { 170 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 171 return 0; 172 } 173 174 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 175 req_len + sizeof(*resh))) { 176 s390_cpu_virt_mem_handle_exc(cpu, ra); 177 return 0; 178 } 179 resh = (ClpRspHdr *)(buffer + req_len); 180 res_len = lduw_p(&resh->len); 181 if (res_len < 8 || res_len > 8176 || (res_len % 8 != 0)) { 182 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 183 return 0; 184 } 185 if ((req_len + res_len) > 8192) { 186 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 187 return 0; 188 } 189 190 if (s390_cpu_virt_mem_read(cpu, env->regs[r2], r2, buffer, 191 req_len + res_len)) { 192 s390_cpu_virt_mem_handle_exc(cpu, ra); 193 return 0; 194 } 195 196 if (req_len != 32) { 197 stw_p(&resh->rsp, CLP_RC_LEN); 198 goto out; 199 } 200 201 switch (lduw_p(&reqh->cmd)) { 202 case CLP_LIST_PCI: { 203 ClpReqRspListPci *rrb = (ClpReqRspListPci *)buffer; 204 list_pci(rrb, &cc); 205 break; 206 } 207 case CLP_SET_PCI_FN: { 208 ClpReqSetPci *reqsetpci = (ClpReqSetPci *)reqh; 209 ClpRspSetPci *ressetpci = (ClpRspSetPci *)resh; 210 211 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqsetpci->fh)); 212 if (!pbdev) { 213 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FH); 214 goto out; 215 } 216 217 switch (reqsetpci->oc) { 218 case CLP_SET_ENABLE_PCI_FN: 219 switch (reqsetpci->ndas) { 220 case 0: 221 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_DMAAS); 222 goto out; 223 case 1: 224 break; 225 default: 226 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_RES); 227 goto out; 228 } 229 230 if (pbdev->fh & FH_MASK_ENABLE) { 231 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 232 goto out; 233 } 234 235 pbdev->fh |= FH_MASK_ENABLE; 236 pbdev->state = ZPCI_FS_ENABLED; 237 stl_p(&ressetpci->fh, pbdev->fh); 238 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 239 break; 240 case CLP_SET_DISABLE_PCI_FN: 241 if (!(pbdev->fh & FH_MASK_ENABLE)) { 242 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 243 goto out; 244 } 245 device_reset(DEVICE(pbdev)); 246 pbdev->fh &= ~FH_MASK_ENABLE; 247 pbdev->state = ZPCI_FS_DISABLED; 248 stl_p(&ressetpci->fh, pbdev->fh); 249 stw_p(&ressetpci->hdr.rsp, CLP_RC_OK); 250 break; 251 default: 252 DPRINTF("unknown set pci command\n"); 253 stw_p(&ressetpci->hdr.rsp, CLP_RC_SETPCIFN_FHOP); 254 break; 255 } 256 break; 257 } 258 case CLP_QUERY_PCI_FN: { 259 ClpReqQueryPci *reqquery = (ClpReqQueryPci *)reqh; 260 ClpRspQueryPci *resquery = (ClpRspQueryPci *)resh; 261 262 pbdev = s390_pci_find_dev_by_fh(s, ldl_p(&reqquery->fh)); 263 if (!pbdev) { 264 DPRINTF("query pci no pci dev\n"); 265 stw_p(&resquery->hdr.rsp, CLP_RC_SETPCIFN_FH); 266 goto out; 267 } 268 269 for (i = 0; i < PCI_BAR_COUNT; i++) { 270 uint32_t data = pci_get_long(pbdev->pdev->config + 271 PCI_BASE_ADDRESS_0 + (i * 4)); 272 273 stl_p(&resquery->bar[i], data); 274 resquery->bar_size[i] = pbdev->pdev->io_regions[i].size ? 275 ctz64(pbdev->pdev->io_regions[i].size) : 0; 276 DPRINTF("bar %d addr 0x%x size 0x%" PRIx64 "barsize 0x%x\n", i, 277 ldl_p(&resquery->bar[i]), 278 pbdev->pdev->io_regions[i].size, 279 resquery->bar_size[i]); 280 } 281 282 stq_p(&resquery->sdma, ZPCI_SDMA_ADDR); 283 stq_p(&resquery->edma, ZPCI_EDMA_ADDR); 284 stl_p(&resquery->fid, pbdev->fid); 285 stw_p(&resquery->pchid, 0); 286 stw_p(&resquery->ug, 1); 287 stl_p(&resquery->uid, pbdev->uid); 288 stw_p(&resquery->hdr.rsp, CLP_RC_OK); 289 break; 290 } 291 case CLP_QUERY_PCI_FNGRP: { 292 ClpRspQueryPciGrp *resgrp = (ClpRspQueryPciGrp *)resh; 293 resgrp->fr = 1; 294 stq_p(&resgrp->dasm, 0); 295 stq_p(&resgrp->msia, ZPCI_MSI_ADDR); 296 stw_p(&resgrp->mui, 0); 297 stw_p(&resgrp->i, 128); 298 stw_p(&resgrp->maxstbl, 128); 299 resgrp->version = 0; 300 301 stw_p(&resgrp->hdr.rsp, CLP_RC_OK); 302 break; 303 } 304 default: 305 DPRINTF("unknown clp command\n"); 306 stw_p(&resh->rsp, CLP_RC_CMD); 307 break; 308 } 309 310 out: 311 if (s390_cpu_virt_mem_write(cpu, env->regs[r2], r2, buffer, 312 req_len + res_len)) { 313 s390_cpu_virt_mem_handle_exc(cpu, ra); 314 return 0; 315 } 316 setcc(cpu, cc); 317 return 0; 318 } 319 320 /** 321 * Swap data contained in s390x big endian registers to little endian 322 * PCI bars. 323 * 324 * @ptr: a pointer to a uint64_t data field 325 * @len: the length of the valid data, must be 1,2,4 or 8 326 */ 327 static int zpci_endian_swap(uint64_t *ptr, uint8_t len) 328 { 329 uint64_t data = *ptr; 330 331 switch (len) { 332 case 1: 333 break; 334 case 2: 335 data = bswap16(data); 336 break; 337 case 4: 338 data = bswap32(data); 339 break; 340 case 8: 341 data = bswap64(data); 342 break; 343 default: 344 return -EINVAL; 345 } 346 *ptr = data; 347 return 0; 348 } 349 350 static MemoryRegion *s390_get_subregion(MemoryRegion *mr, uint64_t offset, 351 uint8_t len) 352 { 353 MemoryRegion *subregion; 354 uint64_t subregion_size; 355 356 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) { 357 subregion_size = int128_get64(subregion->size); 358 if ((offset >= subregion->addr) && 359 (offset + len) <= (subregion->addr + subregion_size)) { 360 mr = subregion; 361 break; 362 } 363 } 364 return mr; 365 } 366 367 static MemTxResult zpci_read_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 368 uint64_t offset, uint64_t *data, uint8_t len) 369 { 370 MemoryRegion *mr; 371 372 mr = pbdev->pdev->io_regions[pcias].memory; 373 mr = s390_get_subregion(mr, offset, len); 374 offset -= mr->addr; 375 return memory_region_dispatch_read(mr, offset, data, len, 376 MEMTXATTRS_UNSPECIFIED); 377 } 378 379 int pcilg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 380 { 381 CPUS390XState *env = &cpu->env; 382 S390PCIBusDevice *pbdev; 383 uint64_t offset; 384 uint64_t data; 385 MemTxResult result; 386 uint8_t len; 387 uint32_t fh; 388 uint8_t pcias; 389 390 if (env->psw.mask & PSW_MASK_PSTATE) { 391 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 392 return 0; 393 } 394 395 if (r2 & 0x1) { 396 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 397 return 0; 398 } 399 400 fh = env->regs[r2] >> 32; 401 pcias = (env->regs[r2] >> 16) & 0xf; 402 len = env->regs[r2] & 0xf; 403 offset = env->regs[r2 + 1]; 404 405 if (!(fh & FH_MASK_ENABLE)) { 406 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 407 return 0; 408 } 409 410 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 411 if (!pbdev) { 412 DPRINTF("pcilg no pci dev\n"); 413 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 414 return 0; 415 } 416 417 switch (pbdev->state) { 418 case ZPCI_FS_PERMANENT_ERROR: 419 case ZPCI_FS_ERROR: 420 setcc(cpu, ZPCI_PCI_LS_ERR); 421 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 422 return 0; 423 default: 424 break; 425 } 426 427 switch (pcias) { 428 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 429 if (!len || (len > (8 - (offset & 0x7)))) { 430 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 431 return 0; 432 } 433 result = zpci_read_bar(pbdev, pcias, offset, &data, len); 434 if (result != MEMTX_OK) { 435 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 436 return 0; 437 } 438 break; 439 case ZPCI_CONFIG_BAR: 440 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 441 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 442 return 0; 443 } 444 data = pci_host_config_read_common( 445 pbdev->pdev, offset, pci_config_size(pbdev->pdev), len); 446 447 if (zpci_endian_swap(&data, len)) { 448 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 449 return 0; 450 } 451 break; 452 default: 453 DPRINTF("pcilg invalid space\n"); 454 setcc(cpu, ZPCI_PCI_LS_ERR); 455 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 456 return 0; 457 } 458 459 env->regs[r1] = data; 460 setcc(cpu, ZPCI_PCI_LS_OK); 461 return 0; 462 } 463 464 static MemTxResult zpci_write_bar(S390PCIBusDevice *pbdev, uint8_t pcias, 465 uint64_t offset, uint64_t data, uint8_t len) 466 { 467 MemoryRegion *mr; 468 469 mr = pbdev->pdev->io_regions[pcias].memory; 470 mr = s390_get_subregion(mr, offset, len); 471 offset -= mr->addr; 472 return memory_region_dispatch_write(mr, offset, data, len, 473 MEMTXATTRS_UNSPECIFIED); 474 } 475 476 int pcistg_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 477 { 478 CPUS390XState *env = &cpu->env; 479 uint64_t offset, data; 480 S390PCIBusDevice *pbdev; 481 MemTxResult result; 482 uint8_t len; 483 uint32_t fh; 484 uint8_t pcias; 485 486 if (env->psw.mask & PSW_MASK_PSTATE) { 487 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 488 return 0; 489 } 490 491 if (r2 & 0x1) { 492 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 493 return 0; 494 } 495 496 fh = env->regs[r2] >> 32; 497 pcias = (env->regs[r2] >> 16) & 0xf; 498 len = env->regs[r2] & 0xf; 499 offset = env->regs[r2 + 1]; 500 data = env->regs[r1]; 501 502 if (!(fh & FH_MASK_ENABLE)) { 503 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 504 return 0; 505 } 506 507 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 508 if (!pbdev) { 509 DPRINTF("pcistg no pci dev\n"); 510 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 511 return 0; 512 } 513 514 switch (pbdev->state) { 515 /* ZPCI_FS_RESERVED, ZPCI_FS_STANDBY and ZPCI_FS_DISABLED 516 * are already covered by the FH_MASK_ENABLE check above 517 */ 518 case ZPCI_FS_PERMANENT_ERROR: 519 case ZPCI_FS_ERROR: 520 setcc(cpu, ZPCI_PCI_LS_ERR); 521 s390_set_status_code(env, r2, ZPCI_PCI_ST_BLOCKED); 522 return 0; 523 default: 524 break; 525 } 526 527 switch (pcias) { 528 /* A ZPCI PCI card may use any BAR from BAR 0 to BAR 5 */ 529 case ZPCI_IO_BAR_MIN...ZPCI_IO_BAR_MAX: 530 /* Check length: 531 * A length of 0 is invalid and length should not cross a double word 532 */ 533 if (!len || (len > (8 - (offset & 0x7)))) { 534 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 535 return 0; 536 } 537 538 result = zpci_write_bar(pbdev, pcias, offset, data, len); 539 if (result != MEMTX_OK) { 540 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 541 return 0; 542 } 543 break; 544 case ZPCI_CONFIG_BAR: 545 /* ZPCI uses the pseudo BAR number 15 as configuration space */ 546 /* possible access lengths are 1,2,4 and must not cross a word */ 547 if (!len || (len > (4 - (offset & 0x3))) || len == 3) { 548 s390_program_interrupt(env, PGM_OPERAND, 4, ra); 549 return 0; 550 } 551 /* len = 1,2,4 so we do not need to test */ 552 zpci_endian_swap(&data, len); 553 pci_host_config_write_common(pbdev->pdev, offset, 554 pci_config_size(pbdev->pdev), 555 data, len); 556 break; 557 default: 558 DPRINTF("pcistg invalid space\n"); 559 setcc(cpu, ZPCI_PCI_LS_ERR); 560 s390_set_status_code(env, r2, ZPCI_PCI_ST_INVAL_AS); 561 return 0; 562 } 563 564 setcc(cpu, ZPCI_PCI_LS_OK); 565 return 0; 566 } 567 568 static void s390_pci_update_iotlb(S390PCIIOMMU *iommu, S390IOTLBEntry *entry) 569 { 570 S390IOTLBEntry *cache = g_hash_table_lookup(iommu->iotlb, &entry->iova); 571 IOMMUTLBEntry notify = { 572 .target_as = &address_space_memory, 573 .iova = entry->iova, 574 .translated_addr = entry->translated_addr, 575 .perm = entry->perm, 576 .addr_mask = ~PAGE_MASK, 577 }; 578 579 if (entry->perm == IOMMU_NONE) { 580 if (!cache) { 581 return; 582 } 583 g_hash_table_remove(iommu->iotlb, &entry->iova); 584 } else { 585 if (cache) { 586 if (cache->perm == entry->perm && 587 cache->translated_addr == entry->translated_addr) { 588 return; 589 } 590 591 notify.perm = IOMMU_NONE; 592 memory_region_notify_iommu(&iommu->iommu_mr, notify); 593 notify.perm = entry->perm; 594 } 595 596 cache = g_new(S390IOTLBEntry, 1); 597 cache->iova = entry->iova; 598 cache->translated_addr = entry->translated_addr; 599 cache->len = PAGE_SIZE; 600 cache->perm = entry->perm; 601 g_hash_table_replace(iommu->iotlb, &cache->iova, cache); 602 } 603 604 memory_region_notify_iommu(&iommu->iommu_mr, notify); 605 } 606 607 int rpcit_service_call(S390CPU *cpu, uint8_t r1, uint8_t r2, uintptr_t ra) 608 { 609 CPUS390XState *env = &cpu->env; 610 uint32_t fh; 611 uint16_t error = 0; 612 S390PCIBusDevice *pbdev; 613 S390PCIIOMMU *iommu; 614 S390IOTLBEntry entry; 615 hwaddr start, end; 616 617 if (env->psw.mask & PSW_MASK_PSTATE) { 618 s390_program_interrupt(env, PGM_PRIVILEGED, 4, ra); 619 return 0; 620 } 621 622 if (r2 & 0x1) { 623 s390_program_interrupt(env, PGM_SPECIFICATION, 4, ra); 624 return 0; 625 } 626 627 fh = env->regs[r1] >> 32; 628 start = env->regs[r2]; 629 end = start + env->regs[r2 + 1]; 630 631 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 632 if (!pbdev) { 633 DPRINTF("rpcit no pci dev\n"); 634 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 635 return 0; 636 } 637 638 switch (pbdev->state) { 639 case ZPCI_FS_RESERVED: 640 case ZPCI_FS_STANDBY: 641 case ZPCI_FS_DISABLED: 642 case ZPCI_FS_PERMANENT_ERROR: 643 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 644 return 0; 645 case ZPCI_FS_ERROR: 646 setcc(cpu, ZPCI_PCI_LS_ERR); 647 s390_set_status_code(env, r1, ZPCI_MOD_ST_ERROR_RECOVER); 648 return 0; 649 default: 650 break; 651 } 652 653 iommu = pbdev->iommu; 654 if (!iommu->g_iota) { 655 error = ERR_EVENT_INVALAS; 656 goto err; 657 } 658 659 if (end < iommu->pba || start > iommu->pal) { 660 error = ERR_EVENT_OORANGE; 661 goto err; 662 } 663 664 while (start < end) { 665 error = s390_guest_io_table_walk(iommu->g_iota, start, &entry); 666 if (error) { 667 break; 668 } 669 670 start += entry.len; 671 while (entry.iova < start && entry.iova < end) { 672 s390_pci_update_iotlb(iommu, &entry); 673 entry.iova += PAGE_SIZE; 674 entry.translated_addr += PAGE_SIZE; 675 } 676 } 677 err: 678 if (error) { 679 pbdev->state = ZPCI_FS_ERROR; 680 setcc(cpu, ZPCI_PCI_LS_ERR); 681 s390_set_status_code(env, r1, ZPCI_PCI_ST_FUNC_IN_ERR); 682 s390_pci_generate_error_event(error, pbdev->fh, pbdev->fid, start, 0); 683 } else { 684 setcc(cpu, ZPCI_PCI_LS_OK); 685 } 686 return 0; 687 } 688 689 int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr, 690 uint8_t ar, uintptr_t ra) 691 { 692 CPUS390XState *env = &cpu->env; 693 S390PCIBusDevice *pbdev; 694 MemoryRegion *mr; 695 MemTxResult result; 696 uint64_t offset; 697 int i; 698 uint32_t fh; 699 uint8_t pcias; 700 uint8_t len; 701 uint8_t buffer[128]; 702 703 if (env->psw.mask & PSW_MASK_PSTATE) { 704 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 705 return 0; 706 } 707 708 fh = env->regs[r1] >> 32; 709 pcias = (env->regs[r1] >> 16) & 0xf; 710 len = env->regs[r1] & 0xff; 711 offset = env->regs[r3]; 712 713 if (!(fh & FH_MASK_ENABLE)) { 714 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 715 return 0; 716 } 717 718 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 719 if (!pbdev) { 720 DPRINTF("pcistb no pci dev fh 0x%x\n", fh); 721 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 722 return 0; 723 } 724 725 switch (pbdev->state) { 726 case ZPCI_FS_PERMANENT_ERROR: 727 case ZPCI_FS_ERROR: 728 setcc(cpu, ZPCI_PCI_LS_ERR); 729 s390_set_status_code(env, r1, ZPCI_PCI_ST_BLOCKED); 730 return 0; 731 default: 732 break; 733 } 734 735 if (pcias > ZPCI_IO_BAR_MAX) { 736 DPRINTF("pcistb invalid space\n"); 737 setcc(cpu, ZPCI_PCI_LS_ERR); 738 s390_set_status_code(env, r1, ZPCI_PCI_ST_INVAL_AS); 739 return 0; 740 } 741 742 /* Verify the address, offset and length */ 743 /* offset must be a multiple of 8 */ 744 if (offset % 8) { 745 goto specification_error; 746 } 747 /* Length must be greater than 8, a multiple of 8 */ 748 /* and not greater than maxstbl */ 749 if ((len <= 8) || (len % 8) || (len > pbdev->maxstbl)) { 750 goto specification_error; 751 } 752 /* Do not cross a 4K-byte boundary */ 753 if (((offset & 0xfff) + len) > 0x1000) { 754 goto specification_error; 755 } 756 /* Guest address must be double word aligned */ 757 if (gaddr & 0x07UL) { 758 goto specification_error; 759 } 760 761 mr = pbdev->pdev->io_regions[pcias].memory; 762 mr = s390_get_subregion(mr, offset, len); 763 offset -= mr->addr; 764 765 if (!memory_region_access_valid(mr, offset, len, true)) { 766 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 767 return 0; 768 } 769 770 if (s390_cpu_virt_mem_read(cpu, gaddr, ar, buffer, len)) { 771 s390_cpu_virt_mem_handle_exc(cpu, ra); 772 return 0; 773 } 774 775 for (i = 0; i < len / 8; i++) { 776 result = memory_region_dispatch_write(mr, offset + i * 8, 777 ldq_p(buffer + i * 8), 8, 778 MEMTXATTRS_UNSPECIFIED); 779 if (result != MEMTX_OK) { 780 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 781 return 0; 782 } 783 } 784 785 setcc(cpu, ZPCI_PCI_LS_OK); 786 return 0; 787 788 specification_error: 789 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 790 return 0; 791 } 792 793 static int reg_irqs(CPUS390XState *env, S390PCIBusDevice *pbdev, ZpciFib fib) 794 { 795 int ret, len; 796 uint8_t isc = FIB_DATA_ISC(ldl_p(&fib.data)); 797 798 pbdev->routes.adapter.adapter_id = css_get_adapter_id( 799 CSS_IO_ADAPTER_PCI, isc); 800 pbdev->summary_ind = get_indicator(ldq_p(&fib.aisb), sizeof(uint64_t)); 801 len = BITS_TO_LONGS(FIB_DATA_NOI(ldl_p(&fib.data))) * sizeof(unsigned long); 802 pbdev->indicator = get_indicator(ldq_p(&fib.aibv), len); 803 804 ret = map_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 805 if (ret) { 806 goto out; 807 } 808 809 ret = map_indicator(&pbdev->routes.adapter, pbdev->indicator); 810 if (ret) { 811 goto out; 812 } 813 814 pbdev->routes.adapter.summary_addr = ldq_p(&fib.aisb); 815 pbdev->routes.adapter.summary_offset = FIB_DATA_AISBO(ldl_p(&fib.data)); 816 pbdev->routes.adapter.ind_addr = ldq_p(&fib.aibv); 817 pbdev->routes.adapter.ind_offset = FIB_DATA_AIBVO(ldl_p(&fib.data)); 818 pbdev->isc = isc; 819 pbdev->noi = FIB_DATA_NOI(ldl_p(&fib.data)); 820 pbdev->sum = FIB_DATA_SUM(ldl_p(&fib.data)); 821 822 DPRINTF("reg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 823 return 0; 824 out: 825 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 826 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 827 pbdev->summary_ind = NULL; 828 pbdev->indicator = NULL; 829 return ret; 830 } 831 832 int pci_dereg_irqs(S390PCIBusDevice *pbdev) 833 { 834 release_indicator(&pbdev->routes.adapter, pbdev->summary_ind); 835 release_indicator(&pbdev->routes.adapter, pbdev->indicator); 836 837 pbdev->summary_ind = NULL; 838 pbdev->indicator = NULL; 839 pbdev->routes.adapter.summary_addr = 0; 840 pbdev->routes.adapter.summary_offset = 0; 841 pbdev->routes.adapter.ind_addr = 0; 842 pbdev->routes.adapter.ind_offset = 0; 843 pbdev->isc = 0; 844 pbdev->noi = 0; 845 pbdev->sum = 0; 846 847 DPRINTF("dereg_irqs adapter id %d\n", pbdev->routes.adapter.adapter_id); 848 return 0; 849 } 850 851 static int reg_ioat(CPUS390XState *env, S390PCIIOMMU *iommu, ZpciFib fib, 852 uintptr_t ra) 853 { 854 uint64_t pba = ldq_p(&fib.pba); 855 uint64_t pal = ldq_p(&fib.pal); 856 uint64_t g_iota = ldq_p(&fib.iota); 857 uint8_t dt = (g_iota >> 2) & 0x7; 858 uint8_t t = (g_iota >> 11) & 0x1; 859 860 pba &= ~0xfff; 861 pal |= 0xfff; 862 if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) { 863 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 864 return -EINVAL; 865 } 866 867 /* currently we only support designation type 1 with translation */ 868 if (!(dt == ZPCI_IOTA_RTTO && t)) { 869 error_report("unsupported ioat dt %d t %d", dt, t); 870 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 871 return -EINVAL; 872 } 873 874 iommu->pba = pba; 875 iommu->pal = pal; 876 iommu->g_iota = g_iota; 877 878 s390_pci_iommu_enable(iommu); 879 880 return 0; 881 } 882 883 void pci_dereg_ioat(S390PCIIOMMU *iommu) 884 { 885 s390_pci_iommu_disable(iommu); 886 iommu->pba = 0; 887 iommu->pal = 0; 888 iommu->g_iota = 0; 889 } 890 891 int mpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 892 uintptr_t ra) 893 { 894 CPUS390XState *env = &cpu->env; 895 uint8_t oc, dmaas; 896 uint32_t fh; 897 ZpciFib fib; 898 S390PCIBusDevice *pbdev; 899 uint64_t cc = ZPCI_PCI_LS_OK; 900 901 if (env->psw.mask & PSW_MASK_PSTATE) { 902 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 903 return 0; 904 } 905 906 oc = env->regs[r1] & 0xff; 907 dmaas = (env->regs[r1] >> 16) & 0xff; 908 fh = env->regs[r1] >> 32; 909 910 if (fiba & 0x7) { 911 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 912 return 0; 913 } 914 915 pbdev = s390_pci_find_dev_by_fh(s390_get_phb(), fh); 916 if (!pbdev) { 917 DPRINTF("mpcifc no pci dev fh 0x%x\n", fh); 918 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 919 return 0; 920 } 921 922 switch (pbdev->state) { 923 case ZPCI_FS_RESERVED: 924 case ZPCI_FS_STANDBY: 925 case ZPCI_FS_DISABLED: 926 case ZPCI_FS_PERMANENT_ERROR: 927 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 928 return 0; 929 default: 930 break; 931 } 932 933 if (s390_cpu_virt_mem_read(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 934 s390_cpu_virt_mem_handle_exc(cpu, ra); 935 return 0; 936 } 937 938 if (fib.fmt != 0) { 939 s390_program_interrupt(env, PGM_OPERAND, 6, ra); 940 return 0; 941 } 942 943 switch (oc) { 944 case ZPCI_MOD_FC_REG_INT: 945 if (pbdev->summary_ind) { 946 cc = ZPCI_PCI_LS_ERR; 947 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 948 } else if (reg_irqs(env, pbdev, fib)) { 949 cc = ZPCI_PCI_LS_ERR; 950 s390_set_status_code(env, r1, ZPCI_MOD_ST_RES_NOT_AVAIL); 951 } 952 break; 953 case ZPCI_MOD_FC_DEREG_INT: 954 if (!pbdev->summary_ind) { 955 cc = ZPCI_PCI_LS_ERR; 956 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 957 } else { 958 pci_dereg_irqs(pbdev); 959 } 960 break; 961 case ZPCI_MOD_FC_REG_IOAT: 962 if (dmaas != 0) { 963 cc = ZPCI_PCI_LS_ERR; 964 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 965 } else if (pbdev->iommu->enabled) { 966 cc = ZPCI_PCI_LS_ERR; 967 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 968 } else if (reg_ioat(env, pbdev->iommu, fib, ra)) { 969 cc = ZPCI_PCI_LS_ERR; 970 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 971 } 972 break; 973 case ZPCI_MOD_FC_DEREG_IOAT: 974 if (dmaas != 0) { 975 cc = ZPCI_PCI_LS_ERR; 976 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 977 } else if (!pbdev->iommu->enabled) { 978 cc = ZPCI_PCI_LS_ERR; 979 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 980 } else { 981 pci_dereg_ioat(pbdev->iommu); 982 } 983 break; 984 case ZPCI_MOD_FC_REREG_IOAT: 985 if (dmaas != 0) { 986 cc = ZPCI_PCI_LS_ERR; 987 s390_set_status_code(env, r1, ZPCI_MOD_ST_DMAAS_INVAL); 988 } else if (!pbdev->iommu->enabled) { 989 cc = ZPCI_PCI_LS_ERR; 990 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 991 } else { 992 pci_dereg_ioat(pbdev->iommu); 993 if (reg_ioat(env, pbdev->iommu, fib, ra)) { 994 cc = ZPCI_PCI_LS_ERR; 995 s390_set_status_code(env, r1, ZPCI_MOD_ST_INSUF_RES); 996 } 997 } 998 break; 999 case ZPCI_MOD_FC_RESET_ERROR: 1000 switch (pbdev->state) { 1001 case ZPCI_FS_BLOCKED: 1002 case ZPCI_FS_ERROR: 1003 pbdev->state = ZPCI_FS_ENABLED; 1004 break; 1005 default: 1006 cc = ZPCI_PCI_LS_ERR; 1007 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1008 } 1009 break; 1010 case ZPCI_MOD_FC_RESET_BLOCK: 1011 switch (pbdev->state) { 1012 case ZPCI_FS_ERROR: 1013 pbdev->state = ZPCI_FS_BLOCKED; 1014 break; 1015 default: 1016 cc = ZPCI_PCI_LS_ERR; 1017 s390_set_status_code(env, r1, ZPCI_MOD_ST_SEQUENCE); 1018 } 1019 break; 1020 case ZPCI_MOD_FC_SET_MEASURE: 1021 pbdev->fmb_addr = ldq_p(&fib.fmb_addr); 1022 break; 1023 default: 1024 s390_program_interrupt(&cpu->env, PGM_OPERAND, 6, ra); 1025 cc = ZPCI_PCI_LS_ERR; 1026 } 1027 1028 setcc(cpu, cc); 1029 return 0; 1030 } 1031 1032 int stpcifc_service_call(S390CPU *cpu, uint8_t r1, uint64_t fiba, uint8_t ar, 1033 uintptr_t ra) 1034 { 1035 CPUS390XState *env = &cpu->env; 1036 uint8_t dmaas; 1037 uint32_t fh; 1038 ZpciFib fib; 1039 S390PCIBusDevice *pbdev; 1040 uint32_t data; 1041 uint64_t cc = ZPCI_PCI_LS_OK; 1042 1043 if (env->psw.mask & PSW_MASK_PSTATE) { 1044 s390_program_interrupt(env, PGM_PRIVILEGED, 6, ra); 1045 return 0; 1046 } 1047 1048 fh = env->regs[r1] >> 32; 1049 dmaas = (env->regs[r1] >> 16) & 0xff; 1050 1051 if (dmaas) { 1052 setcc(cpu, ZPCI_PCI_LS_ERR); 1053 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_INVAL_DMAAS); 1054 return 0; 1055 } 1056 1057 if (fiba & 0x7) { 1058 s390_program_interrupt(env, PGM_SPECIFICATION, 6, ra); 1059 return 0; 1060 } 1061 1062 pbdev = s390_pci_find_dev_by_idx(s390_get_phb(), fh & FH_MASK_INDEX); 1063 if (!pbdev) { 1064 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1065 return 0; 1066 } 1067 1068 memset(&fib, 0, sizeof(fib)); 1069 1070 switch (pbdev->state) { 1071 case ZPCI_FS_RESERVED: 1072 case ZPCI_FS_STANDBY: 1073 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1074 return 0; 1075 case ZPCI_FS_DISABLED: 1076 if (fh & FH_MASK_ENABLE) { 1077 setcc(cpu, ZPCI_PCI_LS_INVAL_HANDLE); 1078 return 0; 1079 } 1080 goto out; 1081 /* BLOCKED bit is set to one coincident with the setting of ERROR bit. 1082 * FH Enabled bit is set to one in states of ENABLED, BLOCKED or ERROR. */ 1083 case ZPCI_FS_ERROR: 1084 fib.fc |= 0x20; 1085 case ZPCI_FS_BLOCKED: 1086 fib.fc |= 0x40; 1087 case ZPCI_FS_ENABLED: 1088 fib.fc |= 0x80; 1089 if (pbdev->iommu->enabled) { 1090 fib.fc |= 0x10; 1091 } 1092 if (!(fh & FH_MASK_ENABLE)) { 1093 env->regs[r1] |= 1ULL << 63; 1094 } 1095 break; 1096 case ZPCI_FS_PERMANENT_ERROR: 1097 setcc(cpu, ZPCI_PCI_LS_ERR); 1098 s390_set_status_code(env, r1, ZPCI_STPCIFC_ST_PERM_ERROR); 1099 return 0; 1100 } 1101 1102 stq_p(&fib.pba, pbdev->iommu->pba); 1103 stq_p(&fib.pal, pbdev->iommu->pal); 1104 stq_p(&fib.iota, pbdev->iommu->g_iota); 1105 stq_p(&fib.aibv, pbdev->routes.adapter.ind_addr); 1106 stq_p(&fib.aisb, pbdev->routes.adapter.summary_addr); 1107 stq_p(&fib.fmb_addr, pbdev->fmb_addr); 1108 1109 data = ((uint32_t)pbdev->isc << 28) | ((uint32_t)pbdev->noi << 16) | 1110 ((uint32_t)pbdev->routes.adapter.ind_offset << 8) | 1111 ((uint32_t)pbdev->sum << 7) | pbdev->routes.adapter.summary_offset; 1112 stl_p(&fib.data, data); 1113 1114 out: 1115 if (s390_cpu_virt_mem_write(cpu, fiba, ar, (uint8_t *)&fib, sizeof(fib))) { 1116 s390_cpu_virt_mem_handle_exc(cpu, ra); 1117 return 0; 1118 } 1119 1120 setcc(cpu, cc); 1121 return 0; 1122 } 1123