1 #ifndef MPTSAS_H 2 #define MPTSAS_H 3 4 #include "mpi.h" 5 6 #define MPTSAS_NUM_PORTS 8 7 #define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ 8 9 #define MPTSAS_REQUEST_QUEUE_DEPTH 128 10 #define MPTSAS_REPLY_QUEUE_DEPTH 128 11 12 #define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22 13 14 typedef struct MPTSASRequest MPTSASRequest; 15 16 #define TYPE_MPTSAS1068 "mptsas1068" 17 typedef struct MPTSASState MPTSASState; 18 #define MPT_SAS(obj) \ 19 OBJECT_CHECK(MPTSASState, (obj), TYPE_MPTSAS1068) 20 21 enum { 22 DOORBELL_NONE, 23 DOORBELL_WRITE, 24 DOORBELL_READ 25 }; 26 27 struct MPTSASState { 28 PCIDevice dev; 29 MemoryRegion mmio_io; 30 MemoryRegion port_io; 31 MemoryRegion diag_io; 32 QEMUBH *request_bh; 33 34 /* properties */ 35 OnOffAuto msi; 36 uint64_t sas_addr; 37 38 bool msi_in_use; 39 40 /* Doorbell register */ 41 uint32_t state; 42 uint8_t who_init; 43 uint8_t doorbell_state; 44 45 /* Buffer for requests that are sent through the doorbell register. */ 46 uint32_t doorbell_msg[256]; 47 int doorbell_idx; 48 int doorbell_cnt; 49 50 uint16_t doorbell_reply[256]; 51 int doorbell_reply_idx; 52 int doorbell_reply_size; 53 54 /* Other registers */ 55 uint8_t diagnostic_idx; 56 uint32_t diagnostic; 57 uint32_t intr_mask; 58 uint32_t intr_status; 59 60 /* Request queues */ 61 uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1]; 62 uint16_t request_post_head; 63 uint16_t request_post_tail; 64 65 uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 66 uint16_t reply_post_head; 67 uint16_t reply_post_tail; 68 69 uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1]; 70 uint16_t reply_free_head; 71 uint16_t reply_free_tail; 72 73 /* IOC Facts */ 74 hwaddr host_mfa_high_addr; 75 hwaddr sense_buffer_high_addr; 76 uint16_t max_devices; 77 uint16_t max_buses; 78 uint16_t reply_frame_size; 79 80 SCSIBus bus; 81 QTAILQ_HEAD(, MPTSASRequest) pending; 82 }; 83 84 void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req); 85 void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply); 86 void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req); 87 void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply); 88 void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req); 89 void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply); 90 void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req); 91 void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply); 92 void mptsas_fix_config_endianness(MPIMsgConfig *req); 93 void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply); 94 void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req); 95 void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply); 96 void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req); 97 void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply); 98 void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req); 99 void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply); 100 101 void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply); 102 103 void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req); 104 105 #endif /* MPTSAS_H */ 106