149ab747fSPaolo Bonzini /* 249ab747fSPaolo Bonzini * SD Association Host Standard Specification v2.0 controller emulation 349ab747fSPaolo Bonzini * 449ab747fSPaolo Bonzini * Copyright (c) 2011 Samsung Electronics Co., Ltd. 549ab747fSPaolo Bonzini * Mitsyanko Igor <i.mitsyanko@samsung.com> 649ab747fSPaolo Bonzini * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 749ab747fSPaolo Bonzini * 849ab747fSPaolo Bonzini * Based on MMC controller for Samsung S5PC1xx-based board emulation 949ab747fSPaolo Bonzini * by Alexey Merkulov and Vladimir Monakhov. 1049ab747fSPaolo Bonzini * 1149ab747fSPaolo Bonzini * This program is free software; you can redistribute it and/or modify it 1249ab747fSPaolo Bonzini * under the terms of the GNU General Public License as published by the 1349ab747fSPaolo Bonzini * Free Software Foundation; either version 2 of the License, or (at your 1449ab747fSPaolo Bonzini * option) any later version. 1549ab747fSPaolo Bonzini * 1649ab747fSPaolo Bonzini * This program is distributed in the hope that it will be useful, 1749ab747fSPaolo Bonzini * but WITHOUT ANY WARRANTY; without even the implied warranty of 1849ab747fSPaolo Bonzini * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 1949ab747fSPaolo Bonzini * See the GNU General Public License for more details. 2049ab747fSPaolo Bonzini * 2149ab747fSPaolo Bonzini * You should have received a copy of the GNU General Public License along 2249ab747fSPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 2349ab747fSPaolo Bonzini */ 2449ab747fSPaolo Bonzini 250430891cSPeter Maydell #include "qemu/osdep.h" 264c8f9735SPhilippe Mathieu-Daudé #include "qemu/units.h" 276ff37c3dSPhilippe Mathieu-Daudé #include "qemu/error-report.h" 28b635d98cSPhilippe Mathieu-Daudé #include "qapi/error.h" 2964552b6bSMarkus Armbruster #include "hw/irq.h" 30a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 3149ab747fSPaolo Bonzini #include "sysemu/dma.h" 3249ab747fSPaolo Bonzini #include "qemu/timer.h" 3349ab747fSPaolo Bonzini #include "qemu/bitops.h" 34f82a0f44SPhilippe Mathieu-Daudé #include "hw/sd/sdhci.h" 35d6454270SMarkus Armbruster #include "migration/vmstate.h" 36637d23beSSai Pavan Boddu #include "sdhci-internal.h" 3703dd024fSPaolo Bonzini #include "qemu/log.h" 380b8fa32fSMarkus Armbruster #include "qemu/module.h" 398be487d8SPhilippe Mathieu-Daudé #include "trace.h" 4049ab747fSPaolo Bonzini 4140bbc194SPeter Maydell #define TYPE_SDHCI_BUS "sdhci-bus" 4240bbc194SPeter Maydell #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 4340bbc194SPeter Maydell 44aa164fbfSPhilippe Mathieu-Daudé #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 45aa164fbfSPhilippe Mathieu-Daudé 4609b738ffSPhilippe Mathieu-Daudé static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 4709b738ffSPhilippe Mathieu-Daudé { 4809b738ffSPhilippe Mathieu-Daudé return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); 4909b738ffSPhilippe Mathieu-Daudé } 5009b738ffSPhilippe Mathieu-Daudé 516ff37c3dSPhilippe Mathieu-Daudé /* return true on error */ 526ff37c3dSPhilippe Mathieu-Daudé static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, 536ff37c3dSPhilippe Mathieu-Daudé uint8_t freq, Error **errp) 546ff37c3dSPhilippe Mathieu-Daudé { 554d67852dSPhilippe Mathieu-Daudé if (s->sd_spec_version >= 3) { 564d67852dSPhilippe Mathieu-Daudé return false; 574d67852dSPhilippe Mathieu-Daudé } 586ff37c3dSPhilippe Mathieu-Daudé switch (freq) { 596ff37c3dSPhilippe Mathieu-Daudé case 0: 606ff37c3dSPhilippe Mathieu-Daudé case 10 ... 63: 616ff37c3dSPhilippe Mathieu-Daudé break; 626ff37c3dSPhilippe Mathieu-Daudé default: 636ff37c3dSPhilippe Mathieu-Daudé error_setg(errp, "SD %s clock frequency can have value" 646ff37c3dSPhilippe Mathieu-Daudé "in range 0-63 only", desc); 656ff37c3dSPhilippe Mathieu-Daudé return true; 666ff37c3dSPhilippe Mathieu-Daudé } 676ff37c3dSPhilippe Mathieu-Daudé return false; 686ff37c3dSPhilippe Mathieu-Daudé } 696ff37c3dSPhilippe Mathieu-Daudé 706ff37c3dSPhilippe Mathieu-Daudé static void sdhci_check_capareg(SDHCIState *s, Error **errp) 716ff37c3dSPhilippe Mathieu-Daudé { 726ff37c3dSPhilippe Mathieu-Daudé uint64_t msk = s->capareg; 736ff37c3dSPhilippe Mathieu-Daudé uint32_t val; 746ff37c3dSPhilippe Mathieu-Daudé bool y; 756ff37c3dSPhilippe Mathieu-Daudé 766ff37c3dSPhilippe Mathieu-Daudé switch (s->sd_spec_version) { 771e23b63fSPhilippe Mathieu-Daudé case 4: 781e23b63fSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); 791e23b63fSPhilippe Mathieu-Daudé trace_sdhci_capareg("64-bit system bus (v4)", val); 801e23b63fSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); 811e23b63fSPhilippe Mathieu-Daudé 821e23b63fSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); 831e23b63fSPhilippe Mathieu-Daudé trace_sdhci_capareg("UHS-II", val); 841e23b63fSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); 851e23b63fSPhilippe Mathieu-Daudé 861e23b63fSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); 871e23b63fSPhilippe Mathieu-Daudé trace_sdhci_capareg("ADMA3", val); 881e23b63fSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); 891e23b63fSPhilippe Mathieu-Daudé 901e23b63fSPhilippe Mathieu-Daudé /* fallthrough */ 914d67852dSPhilippe Mathieu-Daudé case 3: 924d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); 934d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("async interrupt", val); 944d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); 954d67852dSPhilippe Mathieu-Daudé 964d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); 974d67852dSPhilippe Mathieu-Daudé if (val) { 984d67852dSPhilippe Mathieu-Daudé error_setg(errp, "slot-type not supported"); 994d67852dSPhilippe Mathieu-Daudé return; 1004d67852dSPhilippe Mathieu-Daudé } 1014d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("slot type", val); 1024d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); 1034d67852dSPhilippe Mathieu-Daudé 1044d67852dSPhilippe Mathieu-Daudé if (val != 2) { 1054d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); 1064d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("8-bit bus", val); 1074d67852dSPhilippe Mathieu-Daudé } 1084d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); 1094d67852dSPhilippe Mathieu-Daudé 1104d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); 1114d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("bus speed mask", val); 1124d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); 1134d67852dSPhilippe Mathieu-Daudé 1144d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); 1154d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("driver strength mask", val); 1164d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); 1174d67852dSPhilippe Mathieu-Daudé 1184d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); 1194d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("timer re-tuning", val); 1204d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); 1214d67852dSPhilippe Mathieu-Daudé 1224d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); 1234d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("use SDR50 tuning", val); 1244d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); 1254d67852dSPhilippe Mathieu-Daudé 1264d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); 1274d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("re-tuning mode", val); 1284d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); 1294d67852dSPhilippe Mathieu-Daudé 1304d67852dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); 1314d67852dSPhilippe Mathieu-Daudé trace_sdhci_capareg("clock multiplier", val); 1324d67852dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); 1334d67852dSPhilippe Mathieu-Daudé 1344d67852dSPhilippe Mathieu-Daudé /* fallthrough */ 1356ff37c3dSPhilippe Mathieu-Daudé case 2: /* default version */ 1360540fba9SPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); 1370540fba9SPhilippe Mathieu-Daudé trace_sdhci_capareg("ADMA2", val); 1380540fba9SPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); 1390540fba9SPhilippe Mathieu-Daudé 1400540fba9SPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); 1410540fba9SPhilippe Mathieu-Daudé trace_sdhci_capareg("ADMA1", val); 1420540fba9SPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); 1430540fba9SPhilippe Mathieu-Daudé 1440540fba9SPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); 1451e23b63fSPhilippe Mathieu-Daudé trace_sdhci_capareg("64-bit system bus (v3)", val); 1460540fba9SPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); 1476ff37c3dSPhilippe Mathieu-Daudé 1486ff37c3dSPhilippe Mathieu-Daudé /* fallthrough */ 1496ff37c3dSPhilippe Mathieu-Daudé case 1: 1506ff37c3dSPhilippe Mathieu-Daudé y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); 1516ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); 1526ff37c3dSPhilippe Mathieu-Daudé 1536ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); 1546ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); 1556ff37c3dSPhilippe Mathieu-Daudé if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { 1566ff37c3dSPhilippe Mathieu-Daudé return; 1576ff37c3dSPhilippe Mathieu-Daudé } 1586ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); 1596ff37c3dSPhilippe Mathieu-Daudé 1606ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); 1616ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); 1626ff37c3dSPhilippe Mathieu-Daudé if (sdhci_check_capab_freq_range(s, "base", val, errp)) { 1636ff37c3dSPhilippe Mathieu-Daudé return; 1646ff37c3dSPhilippe Mathieu-Daudé } 1656ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); 1666ff37c3dSPhilippe Mathieu-Daudé 1676ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); 1686ff37c3dSPhilippe Mathieu-Daudé if (val >= 3) { 1696ff37c3dSPhilippe Mathieu-Daudé error_setg(errp, "block size can be 512, 1024 or 2048 only"); 1706ff37c3dSPhilippe Mathieu-Daudé return; 1716ff37c3dSPhilippe Mathieu-Daudé } 1726ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); 1736ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); 1746ff37c3dSPhilippe Mathieu-Daudé 1756ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); 1766ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("high speed", val); 1776ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); 1786ff37c3dSPhilippe Mathieu-Daudé 1796ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); 1806ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("SDMA", val); 1816ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); 1826ff37c3dSPhilippe Mathieu-Daudé 1836ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); 1846ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("suspend/resume", val); 1856ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); 1866ff37c3dSPhilippe Mathieu-Daudé 1876ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); 1886ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("3.3v", val); 1896ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); 1906ff37c3dSPhilippe Mathieu-Daudé 1916ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); 1926ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("3.0v", val); 1936ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); 1946ff37c3dSPhilippe Mathieu-Daudé 1956ff37c3dSPhilippe Mathieu-Daudé val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); 1966ff37c3dSPhilippe Mathieu-Daudé trace_sdhci_capareg("1.8v", val); 1976ff37c3dSPhilippe Mathieu-Daudé msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); 1986ff37c3dSPhilippe Mathieu-Daudé break; 1996ff37c3dSPhilippe Mathieu-Daudé 2006ff37c3dSPhilippe Mathieu-Daudé default: 2016ff37c3dSPhilippe Mathieu-Daudé error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); 2026ff37c3dSPhilippe Mathieu-Daudé } 2036ff37c3dSPhilippe Mathieu-Daudé if (msk) { 2046ff37c3dSPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, 2056ff37c3dSPhilippe Mathieu-Daudé "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); 2066ff37c3dSPhilippe Mathieu-Daudé } 2076ff37c3dSPhilippe Mathieu-Daudé } 2086ff37c3dSPhilippe Mathieu-Daudé 20949ab747fSPaolo Bonzini static uint8_t sdhci_slotint(SDHCIState *s) 21049ab747fSPaolo Bonzini { 21149ab747fSPaolo Bonzini return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 21249ab747fSPaolo Bonzini ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 21349ab747fSPaolo Bonzini ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 21449ab747fSPaolo Bonzini } 21549ab747fSPaolo Bonzini 21649ab747fSPaolo Bonzini static inline void sdhci_update_irq(SDHCIState *s) 21749ab747fSPaolo Bonzini { 21849ab747fSPaolo Bonzini qemu_set_irq(s->irq, sdhci_slotint(s)); 21949ab747fSPaolo Bonzini } 22049ab747fSPaolo Bonzini 22149ab747fSPaolo Bonzini static void sdhci_raise_insertion_irq(void *opaque) 22249ab747fSPaolo Bonzini { 22349ab747fSPaolo Bonzini SDHCIState *s = (SDHCIState *)opaque; 22449ab747fSPaolo Bonzini 22549ab747fSPaolo Bonzini if (s->norintsts & SDHC_NIS_REMOVE) { 226bc72ad67SAlex Bligh timer_mod(s->insert_timer, 227bc72ad67SAlex Bligh qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 22849ab747fSPaolo Bonzini } else { 22949ab747fSPaolo Bonzini s->prnsts = 0x1ff0000; 23049ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_INSERT) { 23149ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_INSERT; 23249ab747fSPaolo Bonzini } 23349ab747fSPaolo Bonzini sdhci_update_irq(s); 23449ab747fSPaolo Bonzini } 23549ab747fSPaolo Bonzini } 23649ab747fSPaolo Bonzini 23740bbc194SPeter Maydell static void sdhci_set_inserted(DeviceState *dev, bool level) 23849ab747fSPaolo Bonzini { 23940bbc194SPeter Maydell SDHCIState *s = (SDHCIState *)dev; 24049ab747fSPaolo Bonzini 2418be487d8SPhilippe Mathieu-Daudé trace_sdhci_set_inserted(level ? "insert" : "eject"); 24249ab747fSPaolo Bonzini if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 24349ab747fSPaolo Bonzini /* Give target some time to notice card ejection */ 244bc72ad67SAlex Bligh timer_mod(s->insert_timer, 245bc72ad67SAlex Bligh qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 24649ab747fSPaolo Bonzini } else { 24749ab747fSPaolo Bonzini if (level) { 24849ab747fSPaolo Bonzini s->prnsts = 0x1ff0000; 24949ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_INSERT) { 25049ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_INSERT; 25149ab747fSPaolo Bonzini } 25249ab747fSPaolo Bonzini } else { 25349ab747fSPaolo Bonzini s->prnsts = 0x1fa0000; 25449ab747fSPaolo Bonzini s->pwrcon &= ~SDHC_POWER_ON; 25549ab747fSPaolo Bonzini s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 25649ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_REMOVE) { 25749ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_REMOVE; 25849ab747fSPaolo Bonzini } 25949ab747fSPaolo Bonzini } 26049ab747fSPaolo Bonzini sdhci_update_irq(s); 26149ab747fSPaolo Bonzini } 26249ab747fSPaolo Bonzini } 26349ab747fSPaolo Bonzini 26440bbc194SPeter Maydell static void sdhci_set_readonly(DeviceState *dev, bool level) 26549ab747fSPaolo Bonzini { 26640bbc194SPeter Maydell SDHCIState *s = (SDHCIState *)dev; 26749ab747fSPaolo Bonzini 26849ab747fSPaolo Bonzini if (level) { 26949ab747fSPaolo Bonzini s->prnsts &= ~SDHC_WRITE_PROTECT; 27049ab747fSPaolo Bonzini } else { 27149ab747fSPaolo Bonzini /* Write enabled */ 27249ab747fSPaolo Bonzini s->prnsts |= SDHC_WRITE_PROTECT; 27349ab747fSPaolo Bonzini } 27449ab747fSPaolo Bonzini } 27549ab747fSPaolo Bonzini 27649ab747fSPaolo Bonzini static void sdhci_reset(SDHCIState *s) 27749ab747fSPaolo Bonzini { 27840bbc194SPeter Maydell DeviceState *dev = DEVICE(s); 27940bbc194SPeter Maydell 280bc72ad67SAlex Bligh timer_del(s->insert_timer); 281bc72ad67SAlex Bligh timer_del(s->transfer_timer); 282aceb5b06SPhilippe Mathieu-Daudé 283aceb5b06SPhilippe Mathieu-Daudé /* Set all registers to 0. Capabilities/Version registers are not cleared 28449ab747fSPaolo Bonzini * and assumed to always preserve their value, given to them during 28549ab747fSPaolo Bonzini * initialization */ 28649ab747fSPaolo Bonzini memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 28749ab747fSPaolo Bonzini 28840bbc194SPeter Maydell /* Reset other state based on current card insertion/readonly status */ 28940bbc194SPeter Maydell sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 29040bbc194SPeter Maydell sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 29140bbc194SPeter Maydell 29249ab747fSPaolo Bonzini s->data_count = 0; 29349ab747fSPaolo Bonzini s->stopped_state = sdhc_not_stopped; 2940a7ac9f9SAndrew Baumann s->pending_insert_state = false; 29549ab747fSPaolo Bonzini } 29649ab747fSPaolo Bonzini 2978b41c305SPeter Maydell static void sdhci_poweron_reset(DeviceState *dev) 2988b41c305SPeter Maydell { 2998b41c305SPeter Maydell /* QOM (ie power-on) reset. This is identical to reset 3008b41c305SPeter Maydell * commanded via device register apart from handling of the 3018b41c305SPeter Maydell * 'pending insert on powerup' quirk. 3028b41c305SPeter Maydell */ 3038b41c305SPeter Maydell SDHCIState *s = (SDHCIState *)dev; 3048b41c305SPeter Maydell 3058b41c305SPeter Maydell sdhci_reset(s); 3068b41c305SPeter Maydell 3078b41c305SPeter Maydell if (s->pending_insert_quirk) { 3088b41c305SPeter Maydell s->pending_insert_state = true; 3098b41c305SPeter Maydell } 3108b41c305SPeter Maydell } 3118b41c305SPeter Maydell 312d368ba43SKevin O'Connor static void sdhci_data_transfer(void *opaque); 31349ab747fSPaolo Bonzini 31449ab747fSPaolo Bonzini static void sdhci_send_command(SDHCIState *s) 31549ab747fSPaolo Bonzini { 31649ab747fSPaolo Bonzini SDRequest request; 31749ab747fSPaolo Bonzini uint8_t response[16]; 31849ab747fSPaolo Bonzini int rlen; 31949ab747fSPaolo Bonzini 32049ab747fSPaolo Bonzini s->errintsts = 0; 32149ab747fSPaolo Bonzini s->acmd12errsts = 0; 32249ab747fSPaolo Bonzini request.cmd = s->cmdreg >> 8; 32349ab747fSPaolo Bonzini request.arg = s->argument; 3248be487d8SPhilippe Mathieu-Daudé 3258be487d8SPhilippe Mathieu-Daudé trace_sdhci_send_command(request.cmd, request.arg); 32640bbc194SPeter Maydell rlen = sdbus_do_command(&s->sdbus, &request, response); 32749ab747fSPaolo Bonzini 32849ab747fSPaolo Bonzini if (s->cmdreg & SDHC_CMD_RESPONSE) { 32949ab747fSPaolo Bonzini if (rlen == 4) { 330b3141c06SPhilippe Mathieu-Daudé s->rspreg[0] = ldl_be_p(response); 33149ab747fSPaolo Bonzini s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 3328be487d8SPhilippe Mathieu-Daudé trace_sdhci_response4(s->rspreg[0]); 33349ab747fSPaolo Bonzini } else if (rlen == 16) { 334b3141c06SPhilippe Mathieu-Daudé s->rspreg[0] = ldl_be_p(&response[11]); 335b3141c06SPhilippe Mathieu-Daudé s->rspreg[1] = ldl_be_p(&response[7]); 336b3141c06SPhilippe Mathieu-Daudé s->rspreg[2] = ldl_be_p(&response[3]); 33749ab747fSPaolo Bonzini s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 33849ab747fSPaolo Bonzini response[2]; 3398be487d8SPhilippe Mathieu-Daudé trace_sdhci_response16(s->rspreg[3], s->rspreg[2], 3408be487d8SPhilippe Mathieu-Daudé s->rspreg[1], s->rspreg[0]); 34149ab747fSPaolo Bonzini } else { 3428be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("timeout waiting for command response"); 34349ab747fSPaolo Bonzini if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 34449ab747fSPaolo Bonzini s->errintsts |= SDHC_EIS_CMDTIMEOUT; 34549ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_ERR; 34649ab747fSPaolo Bonzini } 34749ab747fSPaolo Bonzini } 34849ab747fSPaolo Bonzini 349fd1e5c81SAndrey Smirnov if (!(s->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && 350fd1e5c81SAndrey Smirnov (s->norintstsen & SDHC_NISEN_TRSCMP) && 35149ab747fSPaolo Bonzini (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 35249ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_TRSCMP; 35349ab747fSPaolo Bonzini } 35449ab747fSPaolo Bonzini } 35549ab747fSPaolo Bonzini 35649ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_CMDCMP) { 35749ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_CMDCMP; 35849ab747fSPaolo Bonzini } 35949ab747fSPaolo Bonzini 36049ab747fSPaolo Bonzini sdhci_update_irq(s); 36149ab747fSPaolo Bonzini 36249ab747fSPaolo Bonzini if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 363656f416cSPeter Crosthwaite s->data_count = 0; 364d368ba43SKevin O'Connor sdhci_data_transfer(s); 36549ab747fSPaolo Bonzini } 36649ab747fSPaolo Bonzini } 36749ab747fSPaolo Bonzini 36849ab747fSPaolo Bonzini static void sdhci_end_transfer(SDHCIState *s) 36949ab747fSPaolo Bonzini { 37049ab747fSPaolo Bonzini /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 37149ab747fSPaolo Bonzini if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 37249ab747fSPaolo Bonzini SDRequest request; 37349ab747fSPaolo Bonzini uint8_t response[16]; 37449ab747fSPaolo Bonzini 37549ab747fSPaolo Bonzini request.cmd = 0x0C; 37649ab747fSPaolo Bonzini request.arg = 0; 3778be487d8SPhilippe Mathieu-Daudé trace_sdhci_end_transfer(request.cmd, request.arg); 37840bbc194SPeter Maydell sdbus_do_command(&s->sdbus, &request, response); 37949ab747fSPaolo Bonzini /* Auto CMD12 response goes to the upper Response register */ 380b3141c06SPhilippe Mathieu-Daudé s->rspreg[3] = ldl_be_p(response); 38149ab747fSPaolo Bonzini } 38249ab747fSPaolo Bonzini 38349ab747fSPaolo Bonzini s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 38449ab747fSPaolo Bonzini SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 38549ab747fSPaolo Bonzini SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 38649ab747fSPaolo Bonzini 38749ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_TRSCMP) { 38849ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_TRSCMP; 38949ab747fSPaolo Bonzini } 39049ab747fSPaolo Bonzini 39149ab747fSPaolo Bonzini sdhci_update_irq(s); 39249ab747fSPaolo Bonzini } 39349ab747fSPaolo Bonzini 39449ab747fSPaolo Bonzini /* 39549ab747fSPaolo Bonzini * Programmed i/o data transfer 39649ab747fSPaolo Bonzini */ 397d23b6caaSPhilippe Mathieu-Daudé #define BLOCK_SIZE_MASK (4 * KiB - 1) 39849ab747fSPaolo Bonzini 39949ab747fSPaolo Bonzini /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 40049ab747fSPaolo Bonzini static void sdhci_read_block_from_card(SDHCIState *s) 40149ab747fSPaolo Bonzini { 402ea55a221SPhilippe Mathieu-Daudé const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; 40349ab747fSPaolo Bonzini 40449ab747fSPaolo Bonzini if ((s->trnmod & SDHC_TRNS_MULTI) && 40549ab747fSPaolo Bonzini (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 40649ab747fSPaolo Bonzini return; 40749ab747fSPaolo Bonzini } 40849ab747fSPaolo Bonzini 409ea55a221SPhilippe Mathieu-Daudé if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 41008022a91SPhilippe Mathieu-Daudé /* Device is not in tuning */ 411*618e0be1SPhilippe Mathieu-Daudé sdbus_read_data(&s->sdbus, s->fifo_buffer, blk_size); 412ea55a221SPhilippe Mathieu-Daudé } 413ea55a221SPhilippe Mathieu-Daudé 414ea55a221SPhilippe Mathieu-Daudé if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { 41508022a91SPhilippe Mathieu-Daudé /* Device is in tuning */ 416ea55a221SPhilippe Mathieu-Daudé s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; 417ea55a221SPhilippe Mathieu-Daudé s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; 418ea55a221SPhilippe Mathieu-Daudé s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | 419ea55a221SPhilippe Mathieu-Daudé SDHC_DATA_INHIBIT); 420ea55a221SPhilippe Mathieu-Daudé goto read_done; 42149ab747fSPaolo Bonzini } 42249ab747fSPaolo Bonzini 42349ab747fSPaolo Bonzini /* New data now available for READ through Buffer Port Register */ 42449ab747fSPaolo Bonzini s->prnsts |= SDHC_DATA_AVAILABLE; 42549ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 42649ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_RBUFRDY; 42749ab747fSPaolo Bonzini } 42849ab747fSPaolo Bonzini 42949ab747fSPaolo Bonzini /* Clear DAT line active status if that was the last block */ 43049ab747fSPaolo Bonzini if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 43149ab747fSPaolo Bonzini ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 43249ab747fSPaolo Bonzini s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 43349ab747fSPaolo Bonzini } 43449ab747fSPaolo Bonzini 43549ab747fSPaolo Bonzini /* If stop at block gap request was set and it's not the last block of 43649ab747fSPaolo Bonzini * data - generate Block Event interrupt */ 43749ab747fSPaolo Bonzini if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 43849ab747fSPaolo Bonzini s->blkcnt != 1) { 43949ab747fSPaolo Bonzini s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 44049ab747fSPaolo Bonzini if (s->norintstsen & SDHC_EISEN_BLKGAP) { 44149ab747fSPaolo Bonzini s->norintsts |= SDHC_EIS_BLKGAP; 44249ab747fSPaolo Bonzini } 44349ab747fSPaolo Bonzini } 44449ab747fSPaolo Bonzini 445ea55a221SPhilippe Mathieu-Daudé read_done: 44649ab747fSPaolo Bonzini sdhci_update_irq(s); 44749ab747fSPaolo Bonzini } 44849ab747fSPaolo Bonzini 44949ab747fSPaolo Bonzini /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 45049ab747fSPaolo Bonzini static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 45149ab747fSPaolo Bonzini { 45249ab747fSPaolo Bonzini uint32_t value = 0; 45349ab747fSPaolo Bonzini int i; 45449ab747fSPaolo Bonzini 45549ab747fSPaolo Bonzini /* first check that a valid data exists in host controller input buffer */ 45649ab747fSPaolo Bonzini if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 4578be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("read from empty buffer"); 45849ab747fSPaolo Bonzini return 0; 45949ab747fSPaolo Bonzini } 46049ab747fSPaolo Bonzini 46149ab747fSPaolo Bonzini for (i = 0; i < size; i++) { 46249ab747fSPaolo Bonzini value |= s->fifo_buffer[s->data_count] << i * 8; 46349ab747fSPaolo Bonzini s->data_count++; 46449ab747fSPaolo Bonzini /* check if we've read all valid data (blksize bytes) from buffer */ 465bf8ec38eSPhilippe Mathieu-Daudé if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { 4668be487d8SPhilippe Mathieu-Daudé trace_sdhci_read_dataport(s->data_count); 46749ab747fSPaolo Bonzini s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 46849ab747fSPaolo Bonzini s->data_count = 0; /* next buff read must start at position [0] */ 46949ab747fSPaolo Bonzini 47049ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 47149ab747fSPaolo Bonzini s->blkcnt--; 47249ab747fSPaolo Bonzini } 47349ab747fSPaolo Bonzini 47449ab747fSPaolo Bonzini /* if that was the last block of data */ 47549ab747fSPaolo Bonzini if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 47649ab747fSPaolo Bonzini ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 47749ab747fSPaolo Bonzini /* stop at gap request */ 47849ab747fSPaolo Bonzini (s->stopped_state == sdhc_gap_read && 47949ab747fSPaolo Bonzini !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 480d368ba43SKevin O'Connor sdhci_end_transfer(s); 48149ab747fSPaolo Bonzini } else { /* if there are more data, read next block from card */ 482d368ba43SKevin O'Connor sdhci_read_block_from_card(s); 48349ab747fSPaolo Bonzini } 48449ab747fSPaolo Bonzini break; 48549ab747fSPaolo Bonzini } 48649ab747fSPaolo Bonzini } 48749ab747fSPaolo Bonzini 48849ab747fSPaolo Bonzini return value; 48949ab747fSPaolo Bonzini } 49049ab747fSPaolo Bonzini 49149ab747fSPaolo Bonzini /* Write data from host controller FIFO to card */ 49249ab747fSPaolo Bonzini static void sdhci_write_block_to_card(SDHCIState *s) 49349ab747fSPaolo Bonzini { 49449ab747fSPaolo Bonzini if (s->prnsts & SDHC_SPACE_AVAILABLE) { 49549ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 49649ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_WBUFRDY; 49749ab747fSPaolo Bonzini } 49849ab747fSPaolo Bonzini sdhci_update_irq(s); 49949ab747fSPaolo Bonzini return; 50049ab747fSPaolo Bonzini } 50149ab747fSPaolo Bonzini 50249ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 50349ab747fSPaolo Bonzini if (s->blkcnt == 0) { 50449ab747fSPaolo Bonzini return; 50549ab747fSPaolo Bonzini } else { 50649ab747fSPaolo Bonzini s->blkcnt--; 50749ab747fSPaolo Bonzini } 50849ab747fSPaolo Bonzini } 50949ab747fSPaolo Bonzini 51062a21be6SPhilippe Mathieu-Daudé sdbus_write_data(&s->sdbus, s->fifo_buffer, s->blksize & BLOCK_SIZE_MASK); 51149ab747fSPaolo Bonzini 51249ab747fSPaolo Bonzini /* Next data can be written through BUFFER DATORT register */ 51349ab747fSPaolo Bonzini s->prnsts |= SDHC_SPACE_AVAILABLE; 51449ab747fSPaolo Bonzini 51549ab747fSPaolo Bonzini /* Finish transfer if that was the last block of data */ 51649ab747fSPaolo Bonzini if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 51749ab747fSPaolo Bonzini ((s->trnmod & SDHC_TRNS_MULTI) && 51849ab747fSPaolo Bonzini (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 519d368ba43SKevin O'Connor sdhci_end_transfer(s); 520dcdb4cd8SPeter Crosthwaite } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 521dcdb4cd8SPeter Crosthwaite s->norintsts |= SDHC_NIS_WBUFRDY; 52249ab747fSPaolo Bonzini } 52349ab747fSPaolo Bonzini 52449ab747fSPaolo Bonzini /* Generate Block Gap Event if requested and if not the last block */ 52549ab747fSPaolo Bonzini if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 52649ab747fSPaolo Bonzini s->blkcnt > 0) { 52749ab747fSPaolo Bonzini s->prnsts &= ~SDHC_DOING_WRITE; 52849ab747fSPaolo Bonzini if (s->norintstsen & SDHC_EISEN_BLKGAP) { 52949ab747fSPaolo Bonzini s->norintsts |= SDHC_EIS_BLKGAP; 53049ab747fSPaolo Bonzini } 531d368ba43SKevin O'Connor sdhci_end_transfer(s); 53249ab747fSPaolo Bonzini } 53349ab747fSPaolo Bonzini 53449ab747fSPaolo Bonzini sdhci_update_irq(s); 53549ab747fSPaolo Bonzini } 53649ab747fSPaolo Bonzini 53749ab747fSPaolo Bonzini /* Write @size bytes of @value data to host controller @s Buffer Data Port 53849ab747fSPaolo Bonzini * register */ 53949ab747fSPaolo Bonzini static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 54049ab747fSPaolo Bonzini { 54149ab747fSPaolo Bonzini unsigned i; 54249ab747fSPaolo Bonzini 54349ab747fSPaolo Bonzini /* Check that there is free space left in a buffer */ 54449ab747fSPaolo Bonzini if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 5458be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("Can't write to data buffer: buffer full"); 54649ab747fSPaolo Bonzini return; 54749ab747fSPaolo Bonzini } 54849ab747fSPaolo Bonzini 54949ab747fSPaolo Bonzini for (i = 0; i < size; i++) { 55049ab747fSPaolo Bonzini s->fifo_buffer[s->data_count] = value & 0xFF; 55149ab747fSPaolo Bonzini s->data_count++; 55249ab747fSPaolo Bonzini value >>= 8; 553bf8ec38eSPhilippe Mathieu-Daudé if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { 5548be487d8SPhilippe Mathieu-Daudé trace_sdhci_write_dataport(s->data_count); 55549ab747fSPaolo Bonzini s->data_count = 0; 55649ab747fSPaolo Bonzini s->prnsts &= ~SDHC_SPACE_AVAILABLE; 55749ab747fSPaolo Bonzini if (s->prnsts & SDHC_DOING_WRITE) { 558d368ba43SKevin O'Connor sdhci_write_block_to_card(s); 55949ab747fSPaolo Bonzini } 56049ab747fSPaolo Bonzini } 56149ab747fSPaolo Bonzini } 56249ab747fSPaolo Bonzini } 56349ab747fSPaolo Bonzini 56449ab747fSPaolo Bonzini /* 56549ab747fSPaolo Bonzini * Single DMA data transfer 56649ab747fSPaolo Bonzini */ 56749ab747fSPaolo Bonzini 56849ab747fSPaolo Bonzini /* Multi block SDMA transfer */ 56949ab747fSPaolo Bonzini static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 57049ab747fSPaolo Bonzini { 57149ab747fSPaolo Bonzini bool page_aligned = false; 572*618e0be1SPhilippe Mathieu-Daudé unsigned int begin; 573bf8ec38eSPhilippe Mathieu-Daudé const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 574bf8ec38eSPhilippe Mathieu-Daudé uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); 57549ab747fSPaolo Bonzini uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 57649ab747fSPaolo Bonzini 5776e86d903SPrasad J Pandit if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { 5786e86d903SPrasad J Pandit qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n"); 5796e86d903SPrasad J Pandit return; 5806e86d903SPrasad J Pandit } 5816e86d903SPrasad J Pandit 58249ab747fSPaolo Bonzini /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 58349ab747fSPaolo Bonzini * possible stop at page boundary if initial address is not page aligned, 58449ab747fSPaolo Bonzini * allow them to work properly */ 58549ab747fSPaolo Bonzini if ((s->sdmasysad % boundary_chk) == 0) { 58649ab747fSPaolo Bonzini page_aligned = true; 58749ab747fSPaolo Bonzini } 58849ab747fSPaolo Bonzini 58949ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_READ) { 59049ab747fSPaolo Bonzini s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 59149ab747fSPaolo Bonzini SDHC_DAT_LINE_ACTIVE; 59249ab747fSPaolo Bonzini while (s->blkcnt) { 59349ab747fSPaolo Bonzini if (s->data_count == 0) { 594*618e0be1SPhilippe Mathieu-Daudé sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 59549ab747fSPaolo Bonzini } 59649ab747fSPaolo Bonzini begin = s->data_count; 59749ab747fSPaolo Bonzini if (((boundary_count + begin) < block_size) && page_aligned) { 59849ab747fSPaolo Bonzini s->data_count = boundary_count + begin; 59949ab747fSPaolo Bonzini boundary_count = 0; 60049ab747fSPaolo Bonzini } else { 60149ab747fSPaolo Bonzini s->data_count = block_size; 60249ab747fSPaolo Bonzini boundary_count -= block_size - begin; 60349ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 60449ab747fSPaolo Bonzini s->blkcnt--; 60549ab747fSPaolo Bonzini } 60649ab747fSPaolo Bonzini } 607dd55c485SPhilippe Mathieu-Daudé dma_memory_write(s->dma_as, s->sdmasysad, 60849ab747fSPaolo Bonzini &s->fifo_buffer[begin], s->data_count - begin); 60949ab747fSPaolo Bonzini s->sdmasysad += s->data_count - begin; 61049ab747fSPaolo Bonzini if (s->data_count == block_size) { 61149ab747fSPaolo Bonzini s->data_count = 0; 61249ab747fSPaolo Bonzini } 61349ab747fSPaolo Bonzini if (page_aligned && boundary_count == 0) { 61449ab747fSPaolo Bonzini break; 61549ab747fSPaolo Bonzini } 61649ab747fSPaolo Bonzini } 61749ab747fSPaolo Bonzini } else { 61849ab747fSPaolo Bonzini s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 61949ab747fSPaolo Bonzini SDHC_DAT_LINE_ACTIVE; 62049ab747fSPaolo Bonzini while (s->blkcnt) { 62149ab747fSPaolo Bonzini begin = s->data_count; 62249ab747fSPaolo Bonzini if (((boundary_count + begin) < block_size) && page_aligned) { 62349ab747fSPaolo Bonzini s->data_count = boundary_count + begin; 62449ab747fSPaolo Bonzini boundary_count = 0; 62549ab747fSPaolo Bonzini } else { 62649ab747fSPaolo Bonzini s->data_count = block_size; 62749ab747fSPaolo Bonzini boundary_count -= block_size - begin; 62849ab747fSPaolo Bonzini } 629dd55c485SPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, s->sdmasysad, 63042922105SPrasad J Pandit &s->fifo_buffer[begin], s->data_count - begin); 63149ab747fSPaolo Bonzini s->sdmasysad += s->data_count - begin; 63249ab747fSPaolo Bonzini if (s->data_count == block_size) { 63362a21be6SPhilippe Mathieu-Daudé sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 63449ab747fSPaolo Bonzini s->data_count = 0; 63549ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 63649ab747fSPaolo Bonzini s->blkcnt--; 63749ab747fSPaolo Bonzini } 63849ab747fSPaolo Bonzini } 63949ab747fSPaolo Bonzini if (page_aligned && boundary_count == 0) { 64049ab747fSPaolo Bonzini break; 64149ab747fSPaolo Bonzini } 64249ab747fSPaolo Bonzini } 64349ab747fSPaolo Bonzini } 64449ab747fSPaolo Bonzini 64549ab747fSPaolo Bonzini if (s->blkcnt == 0) { 646d368ba43SKevin O'Connor sdhci_end_transfer(s); 64749ab747fSPaolo Bonzini } else { 64849ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_DMA) { 64949ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_DMA; 65049ab747fSPaolo Bonzini } 65149ab747fSPaolo Bonzini sdhci_update_irq(s); 65249ab747fSPaolo Bonzini } 65349ab747fSPaolo Bonzini } 65449ab747fSPaolo Bonzini 65549ab747fSPaolo Bonzini /* single block SDMA transfer */ 65649ab747fSPaolo Bonzini static void sdhci_sdma_transfer_single_block(SDHCIState *s) 65749ab747fSPaolo Bonzini { 658bf8ec38eSPhilippe Mathieu-Daudé uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; 65949ab747fSPaolo Bonzini 66049ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_READ) { 661*618e0be1SPhilippe Mathieu-Daudé sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt); 662dd55c485SPhilippe Mathieu-Daudé dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 66349ab747fSPaolo Bonzini } else { 664dd55c485SPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt); 66562a21be6SPhilippe Mathieu-Daudé sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt); 66649ab747fSPaolo Bonzini } 66749ab747fSPaolo Bonzini s->blkcnt--; 66849ab747fSPaolo Bonzini 669d368ba43SKevin O'Connor sdhci_end_transfer(s); 67049ab747fSPaolo Bonzini } 67149ab747fSPaolo Bonzini 67249ab747fSPaolo Bonzini typedef struct ADMADescr { 67349ab747fSPaolo Bonzini hwaddr addr; 67449ab747fSPaolo Bonzini uint16_t length; 67549ab747fSPaolo Bonzini uint8_t attr; 67649ab747fSPaolo Bonzini uint8_t incr; 67749ab747fSPaolo Bonzini } ADMADescr; 67849ab747fSPaolo Bonzini 67949ab747fSPaolo Bonzini static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 68049ab747fSPaolo Bonzini { 68149ab747fSPaolo Bonzini uint32_t adma1 = 0; 68249ab747fSPaolo Bonzini uint64_t adma2 = 0; 68349ab747fSPaolo Bonzini hwaddr entry_addr = (hwaddr)s->admasysaddr; 68406c5120bSPhilippe Mathieu-Daudé switch (SDHC_DMA_TYPE(s->hostctl1)) { 68549ab747fSPaolo Bonzini case SDHC_CTRL_ADMA2_32: 68618610bfdSPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); 68749ab747fSPaolo Bonzini adma2 = le64_to_cpu(adma2); 68849ab747fSPaolo Bonzini /* The spec does not specify endianness of descriptor table. 68949ab747fSPaolo Bonzini * We currently assume that it is LE. 69049ab747fSPaolo Bonzini */ 69149ab747fSPaolo Bonzini dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 69249ab747fSPaolo Bonzini dscr->length = (uint16_t)extract64(adma2, 16, 16); 69349ab747fSPaolo Bonzini dscr->attr = (uint8_t)extract64(adma2, 0, 7); 69449ab747fSPaolo Bonzini dscr->incr = 8; 69549ab747fSPaolo Bonzini break; 69649ab747fSPaolo Bonzini case SDHC_CTRL_ADMA1_32: 69718610bfdSPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); 69849ab747fSPaolo Bonzini adma1 = le32_to_cpu(adma1); 69949ab747fSPaolo Bonzini dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 70049ab747fSPaolo Bonzini dscr->attr = (uint8_t)extract32(adma1, 0, 7); 70149ab747fSPaolo Bonzini dscr->incr = 4; 70249ab747fSPaolo Bonzini if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 70349ab747fSPaolo Bonzini dscr->length = (uint16_t)extract32(adma1, 12, 16); 70449ab747fSPaolo Bonzini } else { 7054c8f9735SPhilippe Mathieu-Daudé dscr->length = 4 * KiB; 70649ab747fSPaolo Bonzini } 70749ab747fSPaolo Bonzini break; 70849ab747fSPaolo Bonzini case SDHC_CTRL_ADMA2_64: 70918610bfdSPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); 71018610bfdSPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); 71149ab747fSPaolo Bonzini dscr->length = le16_to_cpu(dscr->length); 71218610bfdSPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); 71304654b5aSSai Pavan Boddu dscr->addr = le64_to_cpu(dscr->addr); 71404654b5aSSai Pavan Boddu dscr->attr &= (uint8_t) ~0xC0; 71549ab747fSPaolo Bonzini dscr->incr = 12; 71649ab747fSPaolo Bonzini break; 71749ab747fSPaolo Bonzini } 71849ab747fSPaolo Bonzini } 71949ab747fSPaolo Bonzini 72049ab747fSPaolo Bonzini /* Advanced DMA data transfer */ 72149ab747fSPaolo Bonzini 72249ab747fSPaolo Bonzini static void sdhci_do_adma(SDHCIState *s) 72349ab747fSPaolo Bonzini { 724*618e0be1SPhilippe Mathieu-Daudé unsigned int begin, length; 725bf8ec38eSPhilippe Mathieu-Daudé const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; 7268be487d8SPhilippe Mathieu-Daudé ADMADescr dscr = {}; 72749ab747fSPaolo Bonzini int i; 72849ab747fSPaolo Bonzini 72949ab747fSPaolo Bonzini for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 73049ab747fSPaolo Bonzini s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 73149ab747fSPaolo Bonzini 73249ab747fSPaolo Bonzini get_adma_description(s, &dscr); 7338be487d8SPhilippe Mathieu-Daudé trace_sdhci_adma_loop(dscr.addr, dscr.length, dscr.attr); 73449ab747fSPaolo Bonzini 73549ab747fSPaolo Bonzini if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 73649ab747fSPaolo Bonzini /* Indicate that error occurred in ST_FDS state */ 73749ab747fSPaolo Bonzini s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 73849ab747fSPaolo Bonzini s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 73949ab747fSPaolo Bonzini 74049ab747fSPaolo Bonzini /* Generate ADMA error interrupt */ 74149ab747fSPaolo Bonzini if (s->errintstsen & SDHC_EISEN_ADMAERR) { 74249ab747fSPaolo Bonzini s->errintsts |= SDHC_EIS_ADMAERR; 74349ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_ERR; 74449ab747fSPaolo Bonzini } 74549ab747fSPaolo Bonzini 74649ab747fSPaolo Bonzini sdhci_update_irq(s); 74749ab747fSPaolo Bonzini return; 74849ab747fSPaolo Bonzini } 74949ab747fSPaolo Bonzini 7504c8f9735SPhilippe Mathieu-Daudé length = dscr.length ? dscr.length : 64 * KiB; 75149ab747fSPaolo Bonzini 75249ab747fSPaolo Bonzini switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 75349ab747fSPaolo Bonzini case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 75449ab747fSPaolo Bonzini 75549ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_READ) { 75649ab747fSPaolo Bonzini while (length) { 75749ab747fSPaolo Bonzini if (s->data_count == 0) { 758*618e0be1SPhilippe Mathieu-Daudé sdbus_read_data(&s->sdbus, s->fifo_buffer, block_size); 75949ab747fSPaolo Bonzini } 76049ab747fSPaolo Bonzini begin = s->data_count; 76149ab747fSPaolo Bonzini if ((length + begin) < block_size) { 76249ab747fSPaolo Bonzini s->data_count = length + begin; 76349ab747fSPaolo Bonzini length = 0; 76449ab747fSPaolo Bonzini } else { 76549ab747fSPaolo Bonzini s->data_count = block_size; 76649ab747fSPaolo Bonzini length -= block_size - begin; 76749ab747fSPaolo Bonzini } 768dd55c485SPhilippe Mathieu-Daudé dma_memory_write(s->dma_as, dscr.addr, 76949ab747fSPaolo Bonzini &s->fifo_buffer[begin], 77049ab747fSPaolo Bonzini s->data_count - begin); 77149ab747fSPaolo Bonzini dscr.addr += s->data_count - begin; 77249ab747fSPaolo Bonzini if (s->data_count == block_size) { 77349ab747fSPaolo Bonzini s->data_count = 0; 77449ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 77549ab747fSPaolo Bonzini s->blkcnt--; 77649ab747fSPaolo Bonzini if (s->blkcnt == 0) { 77749ab747fSPaolo Bonzini break; 77849ab747fSPaolo Bonzini } 77949ab747fSPaolo Bonzini } 78049ab747fSPaolo Bonzini } 78149ab747fSPaolo Bonzini } 78249ab747fSPaolo Bonzini } else { 78349ab747fSPaolo Bonzini while (length) { 78449ab747fSPaolo Bonzini begin = s->data_count; 78549ab747fSPaolo Bonzini if ((length + begin) < block_size) { 78649ab747fSPaolo Bonzini s->data_count = length + begin; 78749ab747fSPaolo Bonzini length = 0; 78849ab747fSPaolo Bonzini } else { 78949ab747fSPaolo Bonzini s->data_count = block_size; 79049ab747fSPaolo Bonzini length -= block_size - begin; 79149ab747fSPaolo Bonzini } 792dd55c485SPhilippe Mathieu-Daudé dma_memory_read(s->dma_as, dscr.addr, 7939db11cefSPeter Crosthwaite &s->fifo_buffer[begin], 7949db11cefSPeter Crosthwaite s->data_count - begin); 79549ab747fSPaolo Bonzini dscr.addr += s->data_count - begin; 79649ab747fSPaolo Bonzini if (s->data_count == block_size) { 79762a21be6SPhilippe Mathieu-Daudé sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size); 79849ab747fSPaolo Bonzini s->data_count = 0; 79949ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 80049ab747fSPaolo Bonzini s->blkcnt--; 80149ab747fSPaolo Bonzini if (s->blkcnt == 0) { 80249ab747fSPaolo Bonzini break; 80349ab747fSPaolo Bonzini } 80449ab747fSPaolo Bonzini } 80549ab747fSPaolo Bonzini } 80649ab747fSPaolo Bonzini } 80749ab747fSPaolo Bonzini } 80849ab747fSPaolo Bonzini s->admasysaddr += dscr.incr; 80949ab747fSPaolo Bonzini break; 81049ab747fSPaolo Bonzini case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 81149ab747fSPaolo Bonzini s->admasysaddr = dscr.addr; 8128be487d8SPhilippe Mathieu-Daudé trace_sdhci_adma("link", s->admasysaddr); 81349ab747fSPaolo Bonzini break; 81449ab747fSPaolo Bonzini default: 81549ab747fSPaolo Bonzini s->admasysaddr += dscr.incr; 81649ab747fSPaolo Bonzini break; 81749ab747fSPaolo Bonzini } 81849ab747fSPaolo Bonzini 8191d32c26fSPeter Crosthwaite if (dscr.attr & SDHC_ADMA_ATTR_INT) { 8208be487d8SPhilippe Mathieu-Daudé trace_sdhci_adma("interrupt", s->admasysaddr); 8211d32c26fSPeter Crosthwaite if (s->norintstsen & SDHC_NISEN_DMA) { 8221d32c26fSPeter Crosthwaite s->norintsts |= SDHC_NIS_DMA; 8231d32c26fSPeter Crosthwaite } 8241d32c26fSPeter Crosthwaite 8251d32c26fSPeter Crosthwaite sdhci_update_irq(s); 8261d32c26fSPeter Crosthwaite } 8271d32c26fSPeter Crosthwaite 82849ab747fSPaolo Bonzini /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 82949ab747fSPaolo Bonzini if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 83049ab747fSPaolo Bonzini (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 8318be487d8SPhilippe Mathieu-Daudé trace_sdhci_adma_transfer_completed(); 83249ab747fSPaolo Bonzini if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 83349ab747fSPaolo Bonzini (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 83449ab747fSPaolo Bonzini s->blkcnt != 0)) { 8358be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("SD/MMC host ADMA length mismatch"); 83649ab747fSPaolo Bonzini s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 83749ab747fSPaolo Bonzini SDHC_ADMAERR_STATE_ST_TFR; 83849ab747fSPaolo Bonzini if (s->errintstsen & SDHC_EISEN_ADMAERR) { 8398be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("Set ADMA error flag"); 84049ab747fSPaolo Bonzini s->errintsts |= SDHC_EIS_ADMAERR; 84149ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_ERR; 84249ab747fSPaolo Bonzini } 84349ab747fSPaolo Bonzini 84449ab747fSPaolo Bonzini sdhci_update_irq(s); 84549ab747fSPaolo Bonzini } 846d368ba43SKevin O'Connor sdhci_end_transfer(s); 84749ab747fSPaolo Bonzini return; 84849ab747fSPaolo Bonzini } 84949ab747fSPaolo Bonzini 85049ab747fSPaolo Bonzini } 85149ab747fSPaolo Bonzini 85249ab747fSPaolo Bonzini /* we have unfinished business - reschedule to continue ADMA */ 853bc72ad67SAlex Bligh timer_mod(s->transfer_timer, 854bc72ad67SAlex Bligh qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 85549ab747fSPaolo Bonzini } 85649ab747fSPaolo Bonzini 85749ab747fSPaolo Bonzini /* Perform data transfer according to controller configuration */ 85849ab747fSPaolo Bonzini 859d368ba43SKevin O'Connor static void sdhci_data_transfer(void *opaque) 86049ab747fSPaolo Bonzini { 861d368ba43SKevin O'Connor SDHCIState *s = (SDHCIState *)opaque; 86249ab747fSPaolo Bonzini 86349ab747fSPaolo Bonzini if (s->trnmod & SDHC_TRNS_DMA) { 86406c5120bSPhilippe Mathieu-Daudé switch (SDHC_DMA_TYPE(s->hostctl1)) { 86549ab747fSPaolo Bonzini case SDHC_CTRL_SDMA: 86649ab747fSPaolo Bonzini if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 867d368ba43SKevin O'Connor sdhci_sdma_transfer_single_block(s); 86849ab747fSPaolo Bonzini } else { 869d368ba43SKevin O'Connor sdhci_sdma_transfer_multi_blocks(s); 87049ab747fSPaolo Bonzini } 87149ab747fSPaolo Bonzini 87249ab747fSPaolo Bonzini break; 87349ab747fSPaolo Bonzini case SDHC_CTRL_ADMA1_32: 8740540fba9SPhilippe Mathieu-Daudé if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { 8758be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("ADMA1 not supported"); 87649ab747fSPaolo Bonzini break; 87749ab747fSPaolo Bonzini } 87849ab747fSPaolo Bonzini 879d368ba43SKevin O'Connor sdhci_do_adma(s); 88049ab747fSPaolo Bonzini break; 88149ab747fSPaolo Bonzini case SDHC_CTRL_ADMA2_32: 8820540fba9SPhilippe Mathieu-Daudé if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { 8838be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("ADMA2 not supported"); 88449ab747fSPaolo Bonzini break; 88549ab747fSPaolo Bonzini } 88649ab747fSPaolo Bonzini 887d368ba43SKevin O'Connor sdhci_do_adma(s); 88849ab747fSPaolo Bonzini break; 88949ab747fSPaolo Bonzini case SDHC_CTRL_ADMA2_64: 8900540fba9SPhilippe Mathieu-Daudé if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || 8910540fba9SPhilippe Mathieu-Daudé !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { 8928be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("64 bit ADMA not supported"); 89349ab747fSPaolo Bonzini break; 89449ab747fSPaolo Bonzini } 89549ab747fSPaolo Bonzini 896d368ba43SKevin O'Connor sdhci_do_adma(s); 89749ab747fSPaolo Bonzini break; 89849ab747fSPaolo Bonzini default: 8998be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("Unsupported DMA type"); 90049ab747fSPaolo Bonzini break; 90149ab747fSPaolo Bonzini } 90249ab747fSPaolo Bonzini } else { 90340bbc194SPeter Maydell if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 90449ab747fSPaolo Bonzini s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 90549ab747fSPaolo Bonzini SDHC_DAT_LINE_ACTIVE; 906d368ba43SKevin O'Connor sdhci_read_block_from_card(s); 90749ab747fSPaolo Bonzini } else { 90849ab747fSPaolo Bonzini s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 90949ab747fSPaolo Bonzini SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 910d368ba43SKevin O'Connor sdhci_write_block_to_card(s); 91149ab747fSPaolo Bonzini } 91249ab747fSPaolo Bonzini } 91349ab747fSPaolo Bonzini } 91449ab747fSPaolo Bonzini 91549ab747fSPaolo Bonzini static bool sdhci_can_issue_command(SDHCIState *s) 91649ab747fSPaolo Bonzini { 9176890a695SPeter Crosthwaite if (!SDHC_CLOCK_IS_ON(s->clkcon) || 91849ab747fSPaolo Bonzini (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 91949ab747fSPaolo Bonzini ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 92049ab747fSPaolo Bonzini ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 92149ab747fSPaolo Bonzini !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 92249ab747fSPaolo Bonzini return false; 92349ab747fSPaolo Bonzini } 92449ab747fSPaolo Bonzini 92549ab747fSPaolo Bonzini return true; 92649ab747fSPaolo Bonzini } 92749ab747fSPaolo Bonzini 92849ab747fSPaolo Bonzini /* The Buffer Data Port register must be accessed in sequential and 92949ab747fSPaolo Bonzini * continuous manner */ 93049ab747fSPaolo Bonzini static inline bool 93149ab747fSPaolo Bonzini sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 93249ab747fSPaolo Bonzini { 93349ab747fSPaolo Bonzini if ((s->data_count & 0x3) != byte_num) { 9348be487d8SPhilippe Mathieu-Daudé trace_sdhci_error("Non-sequential access to Buffer Data Port register" 93549ab747fSPaolo Bonzini "is prohibited\n"); 93649ab747fSPaolo Bonzini return false; 93749ab747fSPaolo Bonzini } 93849ab747fSPaolo Bonzini return true; 93949ab747fSPaolo Bonzini } 94049ab747fSPaolo Bonzini 941d368ba43SKevin O'Connor static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 94249ab747fSPaolo Bonzini { 943d368ba43SKevin O'Connor SDHCIState *s = (SDHCIState *)opaque; 94449ab747fSPaolo Bonzini uint32_t ret = 0; 94549ab747fSPaolo Bonzini 94649ab747fSPaolo Bonzini switch (offset & ~0x3) { 94749ab747fSPaolo Bonzini case SDHC_SYSAD: 94849ab747fSPaolo Bonzini ret = s->sdmasysad; 94949ab747fSPaolo Bonzini break; 95049ab747fSPaolo Bonzini case SDHC_BLKSIZE: 95149ab747fSPaolo Bonzini ret = s->blksize | (s->blkcnt << 16); 95249ab747fSPaolo Bonzini break; 95349ab747fSPaolo Bonzini case SDHC_ARGUMENT: 95449ab747fSPaolo Bonzini ret = s->argument; 95549ab747fSPaolo Bonzini break; 95649ab747fSPaolo Bonzini case SDHC_TRNMOD: 95749ab747fSPaolo Bonzini ret = s->trnmod | (s->cmdreg << 16); 95849ab747fSPaolo Bonzini break; 95949ab747fSPaolo Bonzini case SDHC_RSPREG0 ... SDHC_RSPREG3: 96049ab747fSPaolo Bonzini ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 96149ab747fSPaolo Bonzini break; 96249ab747fSPaolo Bonzini case SDHC_BDATA: 96349ab747fSPaolo Bonzini if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 964d368ba43SKevin O'Connor ret = sdhci_read_dataport(s, size); 9658be487d8SPhilippe Mathieu-Daudé trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 96649ab747fSPaolo Bonzini return ret; 96749ab747fSPaolo Bonzini } 96849ab747fSPaolo Bonzini break; 96949ab747fSPaolo Bonzini case SDHC_PRNSTS: 97049ab747fSPaolo Bonzini ret = s->prnsts; 971da346922SPhilippe Mathieu-Daudé ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, 972da346922SPhilippe Mathieu-Daudé sdbus_get_dat_lines(&s->sdbus)); 973da346922SPhilippe Mathieu-Daudé ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, 974da346922SPhilippe Mathieu-Daudé sdbus_get_cmd_line(&s->sdbus)); 97549ab747fSPaolo Bonzini break; 97649ab747fSPaolo Bonzini case SDHC_HOSTCTL: 97706c5120bSPhilippe Mathieu-Daudé ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | 97849ab747fSPaolo Bonzini (s->wakcon << 24); 97949ab747fSPaolo Bonzini break; 98049ab747fSPaolo Bonzini case SDHC_CLKCON: 98149ab747fSPaolo Bonzini ret = s->clkcon | (s->timeoutcon << 16); 98249ab747fSPaolo Bonzini break; 98349ab747fSPaolo Bonzini case SDHC_NORINTSTS: 98449ab747fSPaolo Bonzini ret = s->norintsts | (s->errintsts << 16); 98549ab747fSPaolo Bonzini break; 98649ab747fSPaolo Bonzini case SDHC_NORINTSTSEN: 98749ab747fSPaolo Bonzini ret = s->norintstsen | (s->errintstsen << 16); 98849ab747fSPaolo Bonzini break; 98949ab747fSPaolo Bonzini case SDHC_NORINTSIGEN: 99049ab747fSPaolo Bonzini ret = s->norintsigen | (s->errintsigen << 16); 99149ab747fSPaolo Bonzini break; 99249ab747fSPaolo Bonzini case SDHC_ACMD12ERRSTS: 993ea55a221SPhilippe Mathieu-Daudé ret = s->acmd12errsts | (s->hostctl2 << 16); 99449ab747fSPaolo Bonzini break; 995cd209421SPhilippe Mathieu-Daudé case SDHC_CAPAB: 9965efc9016SPhilippe Mathieu-Daudé ret = (uint32_t)s->capareg; 9975efc9016SPhilippe Mathieu-Daudé break; 9985efc9016SPhilippe Mathieu-Daudé case SDHC_CAPAB + 4: 9995efc9016SPhilippe Mathieu-Daudé ret = (uint32_t)(s->capareg >> 32); 100049ab747fSPaolo Bonzini break; 100149ab747fSPaolo Bonzini case SDHC_MAXCURR: 10025efc9016SPhilippe Mathieu-Daudé ret = (uint32_t)s->maxcurr; 10035efc9016SPhilippe Mathieu-Daudé break; 10045efc9016SPhilippe Mathieu-Daudé case SDHC_MAXCURR + 4: 10055efc9016SPhilippe Mathieu-Daudé ret = (uint32_t)(s->maxcurr >> 32); 100649ab747fSPaolo Bonzini break; 100749ab747fSPaolo Bonzini case SDHC_ADMAERR: 100849ab747fSPaolo Bonzini ret = s->admaerr; 100949ab747fSPaolo Bonzini break; 101049ab747fSPaolo Bonzini case SDHC_ADMASYSADDR: 101149ab747fSPaolo Bonzini ret = (uint32_t)s->admasysaddr; 101249ab747fSPaolo Bonzini break; 101349ab747fSPaolo Bonzini case SDHC_ADMASYSADDR + 4: 101449ab747fSPaolo Bonzini ret = (uint32_t)(s->admasysaddr >> 32); 101549ab747fSPaolo Bonzini break; 101649ab747fSPaolo Bonzini case SDHC_SLOT_INT_STATUS: 1017aceb5b06SPhilippe Mathieu-Daudé ret = (s->version << 16) | sdhci_slotint(s); 101849ab747fSPaolo Bonzini break; 101949ab747fSPaolo Bonzini default: 102000b004b3SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " 102100b004b3SPhilippe Mathieu-Daudé "not implemented\n", size, offset); 102249ab747fSPaolo Bonzini break; 102349ab747fSPaolo Bonzini } 102449ab747fSPaolo Bonzini 102549ab747fSPaolo Bonzini ret >>= (offset & 0x3) * 8; 102649ab747fSPaolo Bonzini ret &= (1ULL << (size * 8)) - 1; 10278be487d8SPhilippe Mathieu-Daudé trace_sdhci_access("rd", size << 3, offset, "->", ret, ret); 102849ab747fSPaolo Bonzini return ret; 102949ab747fSPaolo Bonzini } 103049ab747fSPaolo Bonzini 103149ab747fSPaolo Bonzini static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 103249ab747fSPaolo Bonzini { 103349ab747fSPaolo Bonzini if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 103449ab747fSPaolo Bonzini return; 103549ab747fSPaolo Bonzini } 103649ab747fSPaolo Bonzini s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 103749ab747fSPaolo Bonzini 103849ab747fSPaolo Bonzini if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 103949ab747fSPaolo Bonzini (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 104049ab747fSPaolo Bonzini if (s->stopped_state == sdhc_gap_read) { 104149ab747fSPaolo Bonzini s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 1042d368ba43SKevin O'Connor sdhci_read_block_from_card(s); 104349ab747fSPaolo Bonzini } else { 104449ab747fSPaolo Bonzini s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 1045d368ba43SKevin O'Connor sdhci_write_block_to_card(s); 104649ab747fSPaolo Bonzini } 104749ab747fSPaolo Bonzini s->stopped_state = sdhc_not_stopped; 104849ab747fSPaolo Bonzini } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 104949ab747fSPaolo Bonzini if (s->prnsts & SDHC_DOING_READ) { 105049ab747fSPaolo Bonzini s->stopped_state = sdhc_gap_read; 105149ab747fSPaolo Bonzini } else if (s->prnsts & SDHC_DOING_WRITE) { 105249ab747fSPaolo Bonzini s->stopped_state = sdhc_gap_write; 105349ab747fSPaolo Bonzini } 105449ab747fSPaolo Bonzini } 105549ab747fSPaolo Bonzini } 105649ab747fSPaolo Bonzini 105749ab747fSPaolo Bonzini static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 105849ab747fSPaolo Bonzini { 105949ab747fSPaolo Bonzini switch (value) { 106049ab747fSPaolo Bonzini case SDHC_RESET_ALL: 1061d368ba43SKevin O'Connor sdhci_reset(s); 106249ab747fSPaolo Bonzini break; 106349ab747fSPaolo Bonzini case SDHC_RESET_CMD: 106449ab747fSPaolo Bonzini s->prnsts &= ~SDHC_CMD_INHIBIT; 106549ab747fSPaolo Bonzini s->norintsts &= ~SDHC_NIS_CMDCMP; 106649ab747fSPaolo Bonzini break; 106749ab747fSPaolo Bonzini case SDHC_RESET_DATA: 106849ab747fSPaolo Bonzini s->data_count = 0; 106949ab747fSPaolo Bonzini s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 107049ab747fSPaolo Bonzini SDHC_DOING_READ | SDHC_DOING_WRITE | 107149ab747fSPaolo Bonzini SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 107249ab747fSPaolo Bonzini s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 107349ab747fSPaolo Bonzini s->stopped_state = sdhc_not_stopped; 107449ab747fSPaolo Bonzini s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 107549ab747fSPaolo Bonzini SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 107649ab747fSPaolo Bonzini break; 107749ab747fSPaolo Bonzini } 107849ab747fSPaolo Bonzini } 107949ab747fSPaolo Bonzini 108049ab747fSPaolo Bonzini static void 1081d368ba43SKevin O'Connor sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 108249ab747fSPaolo Bonzini { 1083d368ba43SKevin O'Connor SDHCIState *s = (SDHCIState *)opaque; 108449ab747fSPaolo Bonzini unsigned shift = 8 * (offset & 0x3); 108549ab747fSPaolo Bonzini uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1086d368ba43SKevin O'Connor uint32_t value = val; 108749ab747fSPaolo Bonzini value <<= shift; 108849ab747fSPaolo Bonzini 108949ab747fSPaolo Bonzini switch (offset & ~0x3) { 109049ab747fSPaolo Bonzini case SDHC_SYSAD: 109149ab747fSPaolo Bonzini s->sdmasysad = (s->sdmasysad & mask) | value; 109249ab747fSPaolo Bonzini MASKED_WRITE(s->sdmasysad, mask, value); 109349ab747fSPaolo Bonzini /* Writing to last byte of sdmasysad might trigger transfer */ 109449ab747fSPaolo Bonzini if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 109506c5120bSPhilippe Mathieu-Daudé s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { 109645ba9f76SPrasad J Pandit if (s->trnmod & SDHC_TRNS_MULTI) { 1097d368ba43SKevin O'Connor sdhci_sdma_transfer_multi_blocks(s); 109845ba9f76SPrasad J Pandit } else { 109945ba9f76SPrasad J Pandit sdhci_sdma_transfer_single_block(s); 110045ba9f76SPrasad J Pandit } 110149ab747fSPaolo Bonzini } 110249ab747fSPaolo Bonzini break; 110349ab747fSPaolo Bonzini case SDHC_BLKSIZE: 110449ab747fSPaolo Bonzini if (!TRANSFERRING_DATA(s->prnsts)) { 110549ab747fSPaolo Bonzini MASKED_WRITE(s->blksize, mask, value); 110649ab747fSPaolo Bonzini MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 110749ab747fSPaolo Bonzini } 11089201bb9aSAlistair Francis 11099201bb9aSAlistair Francis /* Limit block size to the maximum buffer size */ 11109201bb9aSAlistair Francis if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 111178ee6bd0SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " 11129201bb9aSAlistair Francis "the maximum buffer 0x%x", __func__, s->blksize, 11139201bb9aSAlistair Francis s->buf_maxsz); 11149201bb9aSAlistair Francis 11159201bb9aSAlistair Francis s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 11169201bb9aSAlistair Francis } 11179201bb9aSAlistair Francis 111849ab747fSPaolo Bonzini break; 111949ab747fSPaolo Bonzini case SDHC_ARGUMENT: 112049ab747fSPaolo Bonzini MASKED_WRITE(s->argument, mask, value); 112149ab747fSPaolo Bonzini break; 112249ab747fSPaolo Bonzini case SDHC_TRNMOD: 112349ab747fSPaolo Bonzini /* DMA can be enabled only if it is supported as indicated by 112449ab747fSPaolo Bonzini * capabilities register */ 11256ff37c3dSPhilippe Mathieu-Daudé if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { 112649ab747fSPaolo Bonzini value &= ~SDHC_TRNS_DMA; 112749ab747fSPaolo Bonzini } 112824bddf9dSPhilippe Mathieu-Daudé MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); 112949ab747fSPaolo Bonzini MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 113049ab747fSPaolo Bonzini 113149ab747fSPaolo Bonzini /* Writing to the upper byte of CMDREG triggers SD command generation */ 1132d368ba43SKevin O'Connor if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 113349ab747fSPaolo Bonzini break; 113449ab747fSPaolo Bonzini } 113549ab747fSPaolo Bonzini 1136d368ba43SKevin O'Connor sdhci_send_command(s); 113749ab747fSPaolo Bonzini break; 113849ab747fSPaolo Bonzini case SDHC_BDATA: 113949ab747fSPaolo Bonzini if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1140d368ba43SKevin O'Connor sdhci_write_dataport(s, value >> shift, size); 114149ab747fSPaolo Bonzini } 114249ab747fSPaolo Bonzini break; 114349ab747fSPaolo Bonzini case SDHC_HOSTCTL: 114449ab747fSPaolo Bonzini if (!(mask & 0xFF0000)) { 114549ab747fSPaolo Bonzini sdhci_blkgap_write(s, value >> 16); 114649ab747fSPaolo Bonzini } 114706c5120bSPhilippe Mathieu-Daudé MASKED_WRITE(s->hostctl1, mask, value); 114849ab747fSPaolo Bonzini MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 114949ab747fSPaolo Bonzini MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 115049ab747fSPaolo Bonzini if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 115149ab747fSPaolo Bonzini !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 115249ab747fSPaolo Bonzini s->pwrcon &= ~SDHC_POWER_ON; 115349ab747fSPaolo Bonzini } 115449ab747fSPaolo Bonzini break; 115549ab747fSPaolo Bonzini case SDHC_CLKCON: 115649ab747fSPaolo Bonzini if (!(mask & 0xFF000000)) { 115749ab747fSPaolo Bonzini sdhci_reset_write(s, value >> 24); 115849ab747fSPaolo Bonzini } 115949ab747fSPaolo Bonzini MASKED_WRITE(s->clkcon, mask, value); 116049ab747fSPaolo Bonzini MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 116149ab747fSPaolo Bonzini if (s->clkcon & SDHC_CLOCK_INT_EN) { 116249ab747fSPaolo Bonzini s->clkcon |= SDHC_CLOCK_INT_STABLE; 116349ab747fSPaolo Bonzini } else { 116449ab747fSPaolo Bonzini s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 116549ab747fSPaolo Bonzini } 116649ab747fSPaolo Bonzini break; 116749ab747fSPaolo Bonzini case SDHC_NORINTSTS: 116849ab747fSPaolo Bonzini if (s->norintstsen & SDHC_NISEN_CARDINT) { 116949ab747fSPaolo Bonzini value &= ~SDHC_NIS_CARDINT; 117049ab747fSPaolo Bonzini } 117149ab747fSPaolo Bonzini s->norintsts &= mask | ~value; 117249ab747fSPaolo Bonzini s->errintsts &= (mask >> 16) | ~(value >> 16); 117349ab747fSPaolo Bonzini if (s->errintsts) { 117449ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_ERR; 117549ab747fSPaolo Bonzini } else { 117649ab747fSPaolo Bonzini s->norintsts &= ~SDHC_NIS_ERR; 117749ab747fSPaolo Bonzini } 117849ab747fSPaolo Bonzini sdhci_update_irq(s); 117949ab747fSPaolo Bonzini break; 118049ab747fSPaolo Bonzini case SDHC_NORINTSTSEN: 118149ab747fSPaolo Bonzini MASKED_WRITE(s->norintstsen, mask, value); 118249ab747fSPaolo Bonzini MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 118349ab747fSPaolo Bonzini s->norintsts &= s->norintstsen; 118449ab747fSPaolo Bonzini s->errintsts &= s->errintstsen; 118549ab747fSPaolo Bonzini if (s->errintsts) { 118649ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_ERR; 118749ab747fSPaolo Bonzini } else { 118849ab747fSPaolo Bonzini s->norintsts &= ~SDHC_NIS_ERR; 118949ab747fSPaolo Bonzini } 11900a7ac9f9SAndrew Baumann /* Quirk for Raspberry Pi: pending card insert interrupt 11910a7ac9f9SAndrew Baumann * appears when first enabled after power on */ 11920a7ac9f9SAndrew Baumann if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 11930a7ac9f9SAndrew Baumann assert(s->pending_insert_quirk); 11940a7ac9f9SAndrew Baumann s->norintsts |= SDHC_NIS_INSERT; 11950a7ac9f9SAndrew Baumann s->pending_insert_state = false; 11960a7ac9f9SAndrew Baumann } 119749ab747fSPaolo Bonzini sdhci_update_irq(s); 119849ab747fSPaolo Bonzini break; 119949ab747fSPaolo Bonzini case SDHC_NORINTSIGEN: 120049ab747fSPaolo Bonzini MASKED_WRITE(s->norintsigen, mask, value); 120149ab747fSPaolo Bonzini MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 120249ab747fSPaolo Bonzini sdhci_update_irq(s); 120349ab747fSPaolo Bonzini break; 120449ab747fSPaolo Bonzini case SDHC_ADMAERR: 120549ab747fSPaolo Bonzini MASKED_WRITE(s->admaerr, mask, value); 120649ab747fSPaolo Bonzini break; 120749ab747fSPaolo Bonzini case SDHC_ADMASYSADDR: 120849ab747fSPaolo Bonzini s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 120949ab747fSPaolo Bonzini (uint64_t)mask)) | (uint64_t)value; 121049ab747fSPaolo Bonzini break; 121149ab747fSPaolo Bonzini case SDHC_ADMASYSADDR + 4: 121249ab747fSPaolo Bonzini s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 121349ab747fSPaolo Bonzini ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 121449ab747fSPaolo Bonzini break; 121549ab747fSPaolo Bonzini case SDHC_FEAER: 121649ab747fSPaolo Bonzini s->acmd12errsts |= value; 121749ab747fSPaolo Bonzini s->errintsts |= (value >> 16) & s->errintstsen; 121849ab747fSPaolo Bonzini if (s->acmd12errsts) { 121949ab747fSPaolo Bonzini s->errintsts |= SDHC_EIS_CMD12ERR; 122049ab747fSPaolo Bonzini } 122149ab747fSPaolo Bonzini if (s->errintsts) { 122249ab747fSPaolo Bonzini s->norintsts |= SDHC_NIS_ERR; 122349ab747fSPaolo Bonzini } 122449ab747fSPaolo Bonzini sdhci_update_irq(s); 122549ab747fSPaolo Bonzini break; 12265d2c0464SAndrey Smirnov case SDHC_ACMD12ERRSTS: 12270034ebe6SPhilippe Mathieu-Daudé MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); 12280034ebe6SPhilippe Mathieu-Daudé if (s->uhs_mode >= UHS_I) { 12290034ebe6SPhilippe Mathieu-Daudé MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); 12300034ebe6SPhilippe Mathieu-Daudé 12310034ebe6SPhilippe Mathieu-Daudé if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { 12320034ebe6SPhilippe Mathieu-Daudé sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); 12330034ebe6SPhilippe Mathieu-Daudé } else { 12340034ebe6SPhilippe Mathieu-Daudé sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); 12350034ebe6SPhilippe Mathieu-Daudé } 12360034ebe6SPhilippe Mathieu-Daudé } 12375d2c0464SAndrey Smirnov break; 12385efc9016SPhilippe Mathieu-Daudé 12395efc9016SPhilippe Mathieu-Daudé case SDHC_CAPAB: 12405efc9016SPhilippe Mathieu-Daudé case SDHC_CAPAB + 4: 12415efc9016SPhilippe Mathieu-Daudé case SDHC_MAXCURR: 12425efc9016SPhilippe Mathieu-Daudé case SDHC_MAXCURR + 4: 12435efc9016SPhilippe Mathieu-Daudé qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx 12445efc9016SPhilippe Mathieu-Daudé " <- 0x%08x read-only\n", size, offset, value >> shift); 12455efc9016SPhilippe Mathieu-Daudé break; 12465efc9016SPhilippe Mathieu-Daudé 124749ab747fSPaolo Bonzini default: 124800b004b3SPhilippe Mathieu-Daudé qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x " 124900b004b3SPhilippe Mathieu-Daudé "not implemented\n", size, offset, value >> shift); 125049ab747fSPaolo Bonzini break; 125149ab747fSPaolo Bonzini } 12528be487d8SPhilippe Mathieu-Daudé trace_sdhci_access("wr", size << 3, offset, "<-", 12538be487d8SPhilippe Mathieu-Daudé value >> shift, value >> shift); 125449ab747fSPaolo Bonzini } 125549ab747fSPaolo Bonzini 125649ab747fSPaolo Bonzini static const MemoryRegionOps sdhci_mmio_ops = { 1257d368ba43SKevin O'Connor .read = sdhci_read, 1258d368ba43SKevin O'Connor .write = sdhci_write, 125949ab747fSPaolo Bonzini .valid = { 126049ab747fSPaolo Bonzini .min_access_size = 1, 126149ab747fSPaolo Bonzini .max_access_size = 4, 126249ab747fSPaolo Bonzini .unaligned = false 126349ab747fSPaolo Bonzini }, 126449ab747fSPaolo Bonzini .endianness = DEVICE_LITTLE_ENDIAN, 126549ab747fSPaolo Bonzini }; 126649ab747fSPaolo Bonzini 1267aceb5b06SPhilippe Mathieu-Daudé static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) 1268aceb5b06SPhilippe Mathieu-Daudé { 1269de1b3800SVladimir Sementsov-Ogievskiy ERRP_GUARD(); 12706ff37c3dSPhilippe Mathieu-Daudé 12714d67852dSPhilippe Mathieu-Daudé switch (s->sd_spec_version) { 12724d67852dSPhilippe Mathieu-Daudé case 2 ... 3: 12734d67852dSPhilippe Mathieu-Daudé break; 12744d67852dSPhilippe Mathieu-Daudé default: 12754d67852dSPhilippe Mathieu-Daudé error_setg(errp, "Only Spec v2/v3 are supported"); 1276aceb5b06SPhilippe Mathieu-Daudé return; 1277aceb5b06SPhilippe Mathieu-Daudé } 1278aceb5b06SPhilippe Mathieu-Daudé s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); 12796ff37c3dSPhilippe Mathieu-Daudé 1280de1b3800SVladimir Sementsov-Ogievskiy sdhci_check_capareg(s, errp); 1281de1b3800SVladimir Sementsov-Ogievskiy if (*errp) { 12826ff37c3dSPhilippe Mathieu-Daudé return; 12836ff37c3dSPhilippe Mathieu-Daudé } 1284aceb5b06SPhilippe Mathieu-Daudé } 1285aceb5b06SPhilippe Mathieu-Daudé 1286b635d98cSPhilippe Mathieu-Daudé /* --- qdev common --- */ 1287b635d98cSPhilippe Mathieu-Daudé 1288ce864603SThomas Huth void sdhci_initfn(SDHCIState *s) 128949ab747fSPaolo Bonzini { 129040bbc194SPeter Maydell qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 129140bbc194SPeter Maydell TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 129249ab747fSPaolo Bonzini 1293bc72ad67SAlex Bligh s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1294d368ba43SKevin O'Connor s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1295fd1e5c81SAndrey Smirnov 1296fd1e5c81SAndrey Smirnov s->io_ops = &sdhci_mmio_ops; 129749ab747fSPaolo Bonzini } 129849ab747fSPaolo Bonzini 1299ce864603SThomas Huth void sdhci_uninitfn(SDHCIState *s) 130049ab747fSPaolo Bonzini { 1301bc72ad67SAlex Bligh timer_del(s->insert_timer); 1302bc72ad67SAlex Bligh timer_free(s->insert_timer); 1303bc72ad67SAlex Bligh timer_del(s->transfer_timer); 1304bc72ad67SAlex Bligh timer_free(s->transfer_timer); 130549ab747fSPaolo Bonzini 130649ab747fSPaolo Bonzini g_free(s->fifo_buffer); 130749ab747fSPaolo Bonzini s->fifo_buffer = NULL; 130849ab747fSPaolo Bonzini } 130949ab747fSPaolo Bonzini 1310ce864603SThomas Huth void sdhci_common_realize(SDHCIState *s, Error **errp) 131125367498SPhilippe Mathieu-Daudé { 1312de1b3800SVladimir Sementsov-Ogievskiy ERRP_GUARD(); 1313aceb5b06SPhilippe Mathieu-Daudé 1314de1b3800SVladimir Sementsov-Ogievskiy sdhci_init_readonly_registers(s, errp); 1315de1b3800SVladimir Sementsov-Ogievskiy if (*errp) { 1316aceb5b06SPhilippe Mathieu-Daudé return; 1317aceb5b06SPhilippe Mathieu-Daudé } 131825367498SPhilippe Mathieu-Daudé s->buf_maxsz = sdhci_get_fifolen(s); 131925367498SPhilippe Mathieu-Daudé s->fifo_buffer = g_malloc0(s->buf_maxsz); 132025367498SPhilippe Mathieu-Daudé 1321c0983085SPeter Maydell memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci", 132225367498SPhilippe Mathieu-Daudé SDHC_REGISTERS_MAP_SIZE); 132325367498SPhilippe Mathieu-Daudé } 132425367498SPhilippe Mathieu-Daudé 1325b69c3c21SMarkus Armbruster void sdhci_common_unrealize(SDHCIState *s) 13268b7455c7SPhilippe Mathieu-Daudé { 13278b7455c7SPhilippe Mathieu-Daudé /* This function is expected to be called only once for each class: 13288b7455c7SPhilippe Mathieu-Daudé * - SysBus: via DeviceClass->unrealize(), 13298b7455c7SPhilippe Mathieu-Daudé * - PCI: via PCIDeviceClass->exit(). 13308b7455c7SPhilippe Mathieu-Daudé * However to avoid double-free and/or use-after-free we still nullify 13318b7455c7SPhilippe Mathieu-Daudé * this variable (better safe than sorry!). */ 13328b7455c7SPhilippe Mathieu-Daudé g_free(s->fifo_buffer); 13338b7455c7SPhilippe Mathieu-Daudé s->fifo_buffer = NULL; 13348b7455c7SPhilippe Mathieu-Daudé } 13358b7455c7SPhilippe Mathieu-Daudé 13360a7ac9f9SAndrew Baumann static bool sdhci_pending_insert_vmstate_needed(void *opaque) 13370a7ac9f9SAndrew Baumann { 13380a7ac9f9SAndrew Baumann SDHCIState *s = opaque; 13390a7ac9f9SAndrew Baumann 13400a7ac9f9SAndrew Baumann return s->pending_insert_state; 13410a7ac9f9SAndrew Baumann } 13420a7ac9f9SAndrew Baumann 13430a7ac9f9SAndrew Baumann static const VMStateDescription sdhci_pending_insert_vmstate = { 13440a7ac9f9SAndrew Baumann .name = "sdhci/pending-insert", 13450a7ac9f9SAndrew Baumann .version_id = 1, 13460a7ac9f9SAndrew Baumann .minimum_version_id = 1, 13470a7ac9f9SAndrew Baumann .needed = sdhci_pending_insert_vmstate_needed, 13480a7ac9f9SAndrew Baumann .fields = (VMStateField[]) { 13490a7ac9f9SAndrew Baumann VMSTATE_BOOL(pending_insert_state, SDHCIState), 13500a7ac9f9SAndrew Baumann VMSTATE_END_OF_LIST() 13510a7ac9f9SAndrew Baumann }, 13520a7ac9f9SAndrew Baumann }; 13530a7ac9f9SAndrew Baumann 135449ab747fSPaolo Bonzini const VMStateDescription sdhci_vmstate = { 135549ab747fSPaolo Bonzini .name = "sdhci", 135649ab747fSPaolo Bonzini .version_id = 1, 135749ab747fSPaolo Bonzini .minimum_version_id = 1, 135849ab747fSPaolo Bonzini .fields = (VMStateField[]) { 135949ab747fSPaolo Bonzini VMSTATE_UINT32(sdmasysad, SDHCIState), 136049ab747fSPaolo Bonzini VMSTATE_UINT16(blksize, SDHCIState), 136149ab747fSPaolo Bonzini VMSTATE_UINT16(blkcnt, SDHCIState), 136249ab747fSPaolo Bonzini VMSTATE_UINT32(argument, SDHCIState), 136349ab747fSPaolo Bonzini VMSTATE_UINT16(trnmod, SDHCIState), 136449ab747fSPaolo Bonzini VMSTATE_UINT16(cmdreg, SDHCIState), 136549ab747fSPaolo Bonzini VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 136649ab747fSPaolo Bonzini VMSTATE_UINT32(prnsts, SDHCIState), 136706c5120bSPhilippe Mathieu-Daudé VMSTATE_UINT8(hostctl1, SDHCIState), 136849ab747fSPaolo Bonzini VMSTATE_UINT8(pwrcon, SDHCIState), 136949ab747fSPaolo Bonzini VMSTATE_UINT8(blkgap, SDHCIState), 137049ab747fSPaolo Bonzini VMSTATE_UINT8(wakcon, SDHCIState), 137149ab747fSPaolo Bonzini VMSTATE_UINT16(clkcon, SDHCIState), 137249ab747fSPaolo Bonzini VMSTATE_UINT8(timeoutcon, SDHCIState), 137349ab747fSPaolo Bonzini VMSTATE_UINT8(admaerr, SDHCIState), 137449ab747fSPaolo Bonzini VMSTATE_UINT16(norintsts, SDHCIState), 137549ab747fSPaolo Bonzini VMSTATE_UINT16(errintsts, SDHCIState), 137649ab747fSPaolo Bonzini VMSTATE_UINT16(norintstsen, SDHCIState), 137749ab747fSPaolo Bonzini VMSTATE_UINT16(errintstsen, SDHCIState), 137849ab747fSPaolo Bonzini VMSTATE_UINT16(norintsigen, SDHCIState), 137949ab747fSPaolo Bonzini VMSTATE_UINT16(errintsigen, SDHCIState), 138049ab747fSPaolo Bonzini VMSTATE_UINT16(acmd12errsts, SDHCIState), 138149ab747fSPaolo Bonzini VMSTATE_UINT16(data_count, SDHCIState), 138249ab747fSPaolo Bonzini VMSTATE_UINT64(admasysaddr, SDHCIState), 138349ab747fSPaolo Bonzini VMSTATE_UINT8(stopped_state, SDHCIState), 138459046ec2SHalil Pasic VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, buf_maxsz), 1385e720677eSPaolo Bonzini VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1386e720677eSPaolo Bonzini VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 138749ab747fSPaolo Bonzini VMSTATE_END_OF_LIST() 13880a7ac9f9SAndrew Baumann }, 13890a7ac9f9SAndrew Baumann .subsections = (const VMStateDescription*[]) { 13900a7ac9f9SAndrew Baumann &sdhci_pending_insert_vmstate, 13910a7ac9f9SAndrew Baumann NULL 13920a7ac9f9SAndrew Baumann }, 139349ab747fSPaolo Bonzini }; 139449ab747fSPaolo Bonzini 1395ce864603SThomas Huth void sdhci_common_class_init(ObjectClass *klass, void *data) 13961c92c505SPhilippe Mathieu-Daudé { 13971c92c505SPhilippe Mathieu-Daudé DeviceClass *dc = DEVICE_CLASS(klass); 13981c92c505SPhilippe Mathieu-Daudé 13991c92c505SPhilippe Mathieu-Daudé set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 14001c92c505SPhilippe Mathieu-Daudé dc->vmsd = &sdhci_vmstate; 14011c92c505SPhilippe Mathieu-Daudé dc->reset = sdhci_poweron_reset; 14021c92c505SPhilippe Mathieu-Daudé } 14031c92c505SPhilippe Mathieu-Daudé 1404b635d98cSPhilippe Mathieu-Daudé /* --- qdev SysBus --- */ 1405b635d98cSPhilippe Mathieu-Daudé 14065ec911c3SKevin O'Connor static Property sdhci_sysbus_properties[] = { 1407b635d98cSPhilippe Mathieu-Daudé DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), 14080a7ac9f9SAndrew Baumann DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 14090a7ac9f9SAndrew Baumann false), 141060765b6cSPhilippe Mathieu-Daudé DEFINE_PROP_LINK("dma", SDHCIState, 141160765b6cSPhilippe Mathieu-Daudé dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), 14125ec911c3SKevin O'Connor DEFINE_PROP_END_OF_LIST(), 14135ec911c3SKevin O'Connor }; 14145ec911c3SKevin O'Connor 14157302dcd6SKevin O'Connor static void sdhci_sysbus_init(Object *obj) 141649ab747fSPaolo Bonzini { 14177302dcd6SKevin O'Connor SDHCIState *s = SYSBUS_SDHCI(obj); 14185ec911c3SKevin O'Connor 141940bbc194SPeter Maydell sdhci_initfn(s); 14207302dcd6SKevin O'Connor } 14217302dcd6SKevin O'Connor 14227302dcd6SKevin O'Connor static void sdhci_sysbus_finalize(Object *obj) 14237302dcd6SKevin O'Connor { 14247302dcd6SKevin O'Connor SDHCIState *s = SYSBUS_SDHCI(obj); 142560765b6cSPhilippe Mathieu-Daudé 142660765b6cSPhilippe Mathieu-Daudé if (s->dma_mr) { 142760765b6cSPhilippe Mathieu-Daudé object_unparent(OBJECT(s->dma_mr)); 142860765b6cSPhilippe Mathieu-Daudé } 142960765b6cSPhilippe Mathieu-Daudé 14307302dcd6SKevin O'Connor sdhci_uninitfn(s); 14317302dcd6SKevin O'Connor } 14327302dcd6SKevin O'Connor 14337302dcd6SKevin O'Connor static void sdhci_sysbus_realize(DeviceState *dev, Error **errp) 14347302dcd6SKevin O'Connor { 1435de1b3800SVladimir Sementsov-Ogievskiy ERRP_GUARD(); 14367302dcd6SKevin O'Connor SDHCIState *s = SYSBUS_SDHCI(dev); 143749ab747fSPaolo Bonzini SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 143849ab747fSPaolo Bonzini 1439de1b3800SVladimir Sementsov-Ogievskiy sdhci_common_realize(s, errp); 1440de1b3800SVladimir Sementsov-Ogievskiy if (*errp) { 144125367498SPhilippe Mathieu-Daudé return; 144225367498SPhilippe Mathieu-Daudé } 144325367498SPhilippe Mathieu-Daudé 144460765b6cSPhilippe Mathieu-Daudé if (s->dma_mr) { 144502e57e1cSPhilippe Mathieu-Daudé s->dma_as = &s->sysbus_dma_as; 144660765b6cSPhilippe Mathieu-Daudé address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); 144760765b6cSPhilippe Mathieu-Daudé } else { 144860765b6cSPhilippe Mathieu-Daudé /* use system_memory() if property "dma" not set */ 1449dd55c485SPhilippe Mathieu-Daudé s->dma_as = &address_space_memory; 145060765b6cSPhilippe Mathieu-Daudé } 1451dd55c485SPhilippe Mathieu-Daudé 145249ab747fSPaolo Bonzini sysbus_init_irq(sbd, &s->irq); 1453fd1e5c81SAndrey Smirnov 145449ab747fSPaolo Bonzini sysbus_init_mmio(sbd, &s->iomem); 145549ab747fSPaolo Bonzini } 145649ab747fSPaolo Bonzini 1457b69c3c21SMarkus Armbruster static void sdhci_sysbus_unrealize(DeviceState *dev) 14588b7455c7SPhilippe Mathieu-Daudé { 14598b7455c7SPhilippe Mathieu-Daudé SDHCIState *s = SYSBUS_SDHCI(dev); 14608b7455c7SPhilippe Mathieu-Daudé 1461b69c3c21SMarkus Armbruster sdhci_common_unrealize(s); 146260765b6cSPhilippe Mathieu-Daudé 146360765b6cSPhilippe Mathieu-Daudé if (s->dma_mr) { 146460765b6cSPhilippe Mathieu-Daudé address_space_destroy(s->dma_as); 146560765b6cSPhilippe Mathieu-Daudé } 14668b7455c7SPhilippe Mathieu-Daudé } 14678b7455c7SPhilippe Mathieu-Daudé 14687302dcd6SKevin O'Connor static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 146949ab747fSPaolo Bonzini { 147049ab747fSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 147149ab747fSPaolo Bonzini 14724f67d30bSMarc-André Lureau device_class_set_props(dc, sdhci_sysbus_properties); 14737302dcd6SKevin O'Connor dc->realize = sdhci_sysbus_realize; 14748b7455c7SPhilippe Mathieu-Daudé dc->unrealize = sdhci_sysbus_unrealize; 14751c92c505SPhilippe Mathieu-Daudé 14761c92c505SPhilippe Mathieu-Daudé sdhci_common_class_init(klass, data); 147749ab747fSPaolo Bonzini } 147849ab747fSPaolo Bonzini 14797302dcd6SKevin O'Connor static const TypeInfo sdhci_sysbus_info = { 14807302dcd6SKevin O'Connor .name = TYPE_SYSBUS_SDHCI, 148149ab747fSPaolo Bonzini .parent = TYPE_SYS_BUS_DEVICE, 148249ab747fSPaolo Bonzini .instance_size = sizeof(SDHCIState), 14837302dcd6SKevin O'Connor .instance_init = sdhci_sysbus_init, 14847302dcd6SKevin O'Connor .instance_finalize = sdhci_sysbus_finalize, 14857302dcd6SKevin O'Connor .class_init = sdhci_sysbus_class_init, 148649ab747fSPaolo Bonzini }; 148749ab747fSPaolo Bonzini 1488b635d98cSPhilippe Mathieu-Daudé /* --- qdev bus master --- */ 1489b635d98cSPhilippe Mathieu-Daudé 149040bbc194SPeter Maydell static void sdhci_bus_class_init(ObjectClass *klass, void *data) 149140bbc194SPeter Maydell { 149240bbc194SPeter Maydell SDBusClass *sbc = SD_BUS_CLASS(klass); 149340bbc194SPeter Maydell 149440bbc194SPeter Maydell sbc->set_inserted = sdhci_set_inserted; 149540bbc194SPeter Maydell sbc->set_readonly = sdhci_set_readonly; 149640bbc194SPeter Maydell } 149740bbc194SPeter Maydell 149840bbc194SPeter Maydell static const TypeInfo sdhci_bus_info = { 149940bbc194SPeter Maydell .name = TYPE_SDHCI_BUS, 150040bbc194SPeter Maydell .parent = TYPE_SD_BUS, 150140bbc194SPeter Maydell .instance_size = sizeof(SDBus), 150240bbc194SPeter Maydell .class_init = sdhci_bus_class_init, 150340bbc194SPeter Maydell }; 150440bbc194SPeter Maydell 1505efadc818SPhilippe Mathieu-Daudé /* --- qdev i.MX eSDHC --- */ 1506efadc818SPhilippe Mathieu-Daudé 1507fd1e5c81SAndrey Smirnov static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) 1508fd1e5c81SAndrey Smirnov { 1509fd1e5c81SAndrey Smirnov SDHCIState *s = SYSBUS_SDHCI(opaque); 1510fd1e5c81SAndrey Smirnov uint32_t ret; 151106c5120bSPhilippe Mathieu-Daudé uint16_t hostctl1; 1512fd1e5c81SAndrey Smirnov 1513fd1e5c81SAndrey Smirnov switch (offset) { 1514fd1e5c81SAndrey Smirnov default: 1515fd1e5c81SAndrey Smirnov return sdhci_read(opaque, offset, size); 1516fd1e5c81SAndrey Smirnov 1517fd1e5c81SAndrey Smirnov case SDHC_HOSTCTL: 1518fd1e5c81SAndrey Smirnov /* 1519fd1e5c81SAndrey Smirnov * For a detailed explanation on the following bit 1520fd1e5c81SAndrey Smirnov * manipulation code see comments in a similar part of 1521fd1e5c81SAndrey Smirnov * usdhc_write() 1522fd1e5c81SAndrey Smirnov */ 152306c5120bSPhilippe Mathieu-Daudé hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); 1524fd1e5c81SAndrey Smirnov 152506c5120bSPhilippe Mathieu-Daudé if (s->hostctl1 & SDHC_CTRL_8BITBUS) { 152606c5120bSPhilippe Mathieu-Daudé hostctl1 |= ESDHC_CTRL_8BITBUS; 1527fd1e5c81SAndrey Smirnov } 1528fd1e5c81SAndrey Smirnov 152906c5120bSPhilippe Mathieu-Daudé if (s->hostctl1 & SDHC_CTRL_4BITBUS) { 153006c5120bSPhilippe Mathieu-Daudé hostctl1 |= ESDHC_CTRL_4BITBUS; 1531fd1e5c81SAndrey Smirnov } 1532fd1e5c81SAndrey Smirnov 153306c5120bSPhilippe Mathieu-Daudé ret = hostctl1; 1534fd1e5c81SAndrey Smirnov ret |= (uint32_t)s->blkgap << 16; 1535fd1e5c81SAndrey Smirnov ret |= (uint32_t)s->wakcon << 24; 1536fd1e5c81SAndrey Smirnov 1537fd1e5c81SAndrey Smirnov break; 1538fd1e5c81SAndrey Smirnov 15396bfd06daSHans-Erik Floryd case SDHC_PRNSTS: 15406bfd06daSHans-Erik Floryd /* Add SDSTB (SD Clock Stable) bit to PRNSTS */ 15416bfd06daSHans-Erik Floryd ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB; 15426bfd06daSHans-Erik Floryd if (s->clkcon & SDHC_CLOCK_INT_STABLE) { 15436bfd06daSHans-Erik Floryd ret |= ESDHC_PRNSTS_SDSTB; 15446bfd06daSHans-Erik Floryd } 15456bfd06daSHans-Erik Floryd break; 15466bfd06daSHans-Erik Floryd 15473b2d8176SGuenter Roeck case ESDHC_VENDOR_SPEC: 15483b2d8176SGuenter Roeck ret = s->vendor_spec; 15493b2d8176SGuenter Roeck break; 1550fd1e5c81SAndrey Smirnov case ESDHC_DLL_CTRL: 1551fd1e5c81SAndrey Smirnov case ESDHC_TUNE_CTRL_STATUS: 1552fd1e5c81SAndrey Smirnov case ESDHC_UNDOCUMENTED_REG27: 1553fd1e5c81SAndrey Smirnov case ESDHC_TUNING_CTRL: 1554fd1e5c81SAndrey Smirnov case ESDHC_MIX_CTRL: 1555fd1e5c81SAndrey Smirnov case ESDHC_WTMK_LVL: 1556fd1e5c81SAndrey Smirnov ret = 0; 1557fd1e5c81SAndrey Smirnov break; 1558fd1e5c81SAndrey Smirnov } 1559fd1e5c81SAndrey Smirnov 1560fd1e5c81SAndrey Smirnov return ret; 1561fd1e5c81SAndrey Smirnov } 1562fd1e5c81SAndrey Smirnov 1563fd1e5c81SAndrey Smirnov static void 1564fd1e5c81SAndrey Smirnov usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1565fd1e5c81SAndrey Smirnov { 1566fd1e5c81SAndrey Smirnov SDHCIState *s = SYSBUS_SDHCI(opaque); 156706c5120bSPhilippe Mathieu-Daudé uint8_t hostctl1; 1568fd1e5c81SAndrey Smirnov uint32_t value = (uint32_t)val; 1569fd1e5c81SAndrey Smirnov 1570fd1e5c81SAndrey Smirnov switch (offset) { 1571fd1e5c81SAndrey Smirnov case ESDHC_DLL_CTRL: 1572fd1e5c81SAndrey Smirnov case ESDHC_TUNE_CTRL_STATUS: 1573fd1e5c81SAndrey Smirnov case ESDHC_UNDOCUMENTED_REG27: 1574fd1e5c81SAndrey Smirnov case ESDHC_TUNING_CTRL: 1575fd1e5c81SAndrey Smirnov case ESDHC_WTMK_LVL: 15763b2d8176SGuenter Roeck break; 15773b2d8176SGuenter Roeck 1578fd1e5c81SAndrey Smirnov case ESDHC_VENDOR_SPEC: 15793b2d8176SGuenter Roeck s->vendor_spec = value; 15803b2d8176SGuenter Roeck switch (s->vendor) { 15813b2d8176SGuenter Roeck case SDHCI_VENDOR_IMX: 15823b2d8176SGuenter Roeck if (value & ESDHC_IMX_FRC_SDCLK_ON) { 15833b2d8176SGuenter Roeck s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF; 15843b2d8176SGuenter Roeck } else { 15853b2d8176SGuenter Roeck s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF; 15863b2d8176SGuenter Roeck } 15873b2d8176SGuenter Roeck break; 15883b2d8176SGuenter Roeck default: 15893b2d8176SGuenter Roeck break; 15903b2d8176SGuenter Roeck } 1591fd1e5c81SAndrey Smirnov break; 1592fd1e5c81SAndrey Smirnov 1593fd1e5c81SAndrey Smirnov case SDHC_HOSTCTL: 1594fd1e5c81SAndrey Smirnov /* 1595fd1e5c81SAndrey Smirnov * Here's What ESDHCI has at offset 0x28 (SDHC_HOSTCTL) 1596fd1e5c81SAndrey Smirnov * 1597fd1e5c81SAndrey Smirnov * 7 6 5 4 3 2 1 0 1598fd1e5c81SAndrey Smirnov * |-----------+--------+--------+-----------+----------+---------| 1599fd1e5c81SAndrey Smirnov * | Card | Card | Endian | DATA3 | Data | Led | 1600fd1e5c81SAndrey Smirnov * | Detect | Detect | Mode | as Card | Transfer | Control | 1601fd1e5c81SAndrey Smirnov * | Signal | Test | | Detection | Width | | 1602fd1e5c81SAndrey Smirnov * | Selection | Level | | Pin | | | 1603fd1e5c81SAndrey Smirnov * |-----------+--------+--------+-----------+----------+---------| 1604fd1e5c81SAndrey Smirnov * 1605fd1e5c81SAndrey Smirnov * and 0x29 1606fd1e5c81SAndrey Smirnov * 1607fd1e5c81SAndrey Smirnov * 15 10 9 8 1608fd1e5c81SAndrey Smirnov * |----------+------| 1609fd1e5c81SAndrey Smirnov * | Reserved | DMA | 1610fd1e5c81SAndrey Smirnov * | | Sel. | 1611fd1e5c81SAndrey Smirnov * | | | 1612fd1e5c81SAndrey Smirnov * |----------+------| 1613fd1e5c81SAndrey Smirnov * 1614fd1e5c81SAndrey Smirnov * and here's what SDCHI spec expects those offsets to be: 1615fd1e5c81SAndrey Smirnov * 1616fd1e5c81SAndrey Smirnov * 0x28 (Host Control Register) 1617fd1e5c81SAndrey Smirnov * 1618fd1e5c81SAndrey Smirnov * 7 6 5 4 3 2 1 0 1619fd1e5c81SAndrey Smirnov * |--------+--------+----------+------+--------+----------+---------| 1620fd1e5c81SAndrey Smirnov * | Card | Card | Extended | DMA | High | Data | LED | 1621fd1e5c81SAndrey Smirnov * | Detect | Detect | Data | Sel. | Speed | Transfer | Control | 1622fd1e5c81SAndrey Smirnov * | Signal | Test | Transfer | | Enable | Width | | 1623fd1e5c81SAndrey Smirnov * | Sel. | Level | Width | | | | | 1624fd1e5c81SAndrey Smirnov * |--------+--------+----------+------+--------+----------+---------| 1625fd1e5c81SAndrey Smirnov * 1626fd1e5c81SAndrey Smirnov * and 0x29 (Power Control Register) 1627fd1e5c81SAndrey Smirnov * 1628fd1e5c81SAndrey Smirnov * |----------------------------------| 1629fd1e5c81SAndrey Smirnov * | Power Control Register | 1630fd1e5c81SAndrey Smirnov * | | 1631fd1e5c81SAndrey Smirnov * | Description omitted, | 1632fd1e5c81SAndrey Smirnov * | since it has no analog in ESDHCI | 1633fd1e5c81SAndrey Smirnov * | | 1634fd1e5c81SAndrey Smirnov * |----------------------------------| 1635fd1e5c81SAndrey Smirnov * 1636fd1e5c81SAndrey Smirnov * Since offsets 0x2A and 0x2B should be compatible between 1637fd1e5c81SAndrey Smirnov * both IP specs we only need to reconcile least 16-bit of the 1638fd1e5c81SAndrey Smirnov * word we've been given. 1639fd1e5c81SAndrey Smirnov */ 1640fd1e5c81SAndrey Smirnov 1641fd1e5c81SAndrey Smirnov /* 1642fd1e5c81SAndrey Smirnov * First, save bits 7 6 and 0 since they are identical 1643fd1e5c81SAndrey Smirnov */ 164406c5120bSPhilippe Mathieu-Daudé hostctl1 = value & (SDHC_CTRL_LED | 1645fd1e5c81SAndrey Smirnov SDHC_CTRL_CDTEST_INS | 1646fd1e5c81SAndrey Smirnov SDHC_CTRL_CDTEST_EN); 1647fd1e5c81SAndrey Smirnov /* 1648fd1e5c81SAndrey Smirnov * Second, split "Data Transfer Width" from bits 2 and 1 in to 1649fd1e5c81SAndrey Smirnov * bits 5 and 1 1650fd1e5c81SAndrey Smirnov */ 1651fd1e5c81SAndrey Smirnov if (value & ESDHC_CTRL_8BITBUS) { 165206c5120bSPhilippe Mathieu-Daudé hostctl1 |= SDHC_CTRL_8BITBUS; 1653fd1e5c81SAndrey Smirnov } 1654fd1e5c81SAndrey Smirnov 1655fd1e5c81SAndrey Smirnov if (value & ESDHC_CTRL_4BITBUS) { 165606c5120bSPhilippe Mathieu-Daudé hostctl1 |= ESDHC_CTRL_4BITBUS; 1657fd1e5c81SAndrey Smirnov } 1658fd1e5c81SAndrey Smirnov 1659fd1e5c81SAndrey Smirnov /* 1660fd1e5c81SAndrey Smirnov * Third, move DMA select from bits 9 and 8 to bits 4 and 3 1661fd1e5c81SAndrey Smirnov */ 166206c5120bSPhilippe Mathieu-Daudé hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); 1663fd1e5c81SAndrey Smirnov 1664fd1e5c81SAndrey Smirnov /* 1665fd1e5c81SAndrey Smirnov * Now place the corrected value into low 16-bit of the value 1666fd1e5c81SAndrey Smirnov * we are going to give standard SDHCI write function 1667fd1e5c81SAndrey Smirnov * 1668fd1e5c81SAndrey Smirnov * NOTE: This transformation should be the inverse of what can 1669fd1e5c81SAndrey Smirnov * be found in drivers/mmc/host/sdhci-esdhc-imx.c in Linux 1670fd1e5c81SAndrey Smirnov * kernel 1671fd1e5c81SAndrey Smirnov */ 1672fd1e5c81SAndrey Smirnov value &= ~UINT16_MAX; 167306c5120bSPhilippe Mathieu-Daudé value |= hostctl1; 1674fd1e5c81SAndrey Smirnov value |= (uint16_t)s->pwrcon << 8; 1675fd1e5c81SAndrey Smirnov 1676fd1e5c81SAndrey Smirnov sdhci_write(opaque, offset, value, size); 1677fd1e5c81SAndrey Smirnov break; 1678fd1e5c81SAndrey Smirnov 1679fd1e5c81SAndrey Smirnov case ESDHC_MIX_CTRL: 1680fd1e5c81SAndrey Smirnov /* 1681fd1e5c81SAndrey Smirnov * So, when SD/MMC stack in Linux tries to write to "Transfer 1682fd1e5c81SAndrey Smirnov * Mode Register", ESDHC i.MX quirk code will translate it 1683fd1e5c81SAndrey Smirnov * into a write to ESDHC_MIX_CTRL, so we do the opposite in 1684fd1e5c81SAndrey Smirnov * order to get where we started 1685fd1e5c81SAndrey Smirnov * 1686fd1e5c81SAndrey Smirnov * Note that Auto CMD23 Enable bit is located in a wrong place 1687fd1e5c81SAndrey Smirnov * on i.MX, but since it is not used by QEMU we do not care. 1688fd1e5c81SAndrey Smirnov * 1689fd1e5c81SAndrey Smirnov * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) 1690fd1e5c81SAndrey Smirnov * here becuase it will result in a call to 1691fd1e5c81SAndrey Smirnov * sdhci_send_command(s) which we don't want. 1692fd1e5c81SAndrey Smirnov * 1693fd1e5c81SAndrey Smirnov */ 1694fd1e5c81SAndrey Smirnov s->trnmod = value & UINT16_MAX; 1695fd1e5c81SAndrey Smirnov break; 1696fd1e5c81SAndrey Smirnov case SDHC_TRNMOD: 1697fd1e5c81SAndrey Smirnov /* 1698fd1e5c81SAndrey Smirnov * Similar to above, but this time a write to "Command 1699fd1e5c81SAndrey Smirnov * Register" will be translated into a 4-byte write to 1700fd1e5c81SAndrey Smirnov * "Transfer Mode register" where lower 16-bit of value would 1701fd1e5c81SAndrey Smirnov * be set to zero. So what we do is fill those bits with 1702fd1e5c81SAndrey Smirnov * cached value from s->trnmod and let the SDHCI 1703fd1e5c81SAndrey Smirnov * infrastructure handle the rest 1704fd1e5c81SAndrey Smirnov */ 1705fd1e5c81SAndrey Smirnov sdhci_write(opaque, offset, val | s->trnmod, size); 1706fd1e5c81SAndrey Smirnov break; 1707fd1e5c81SAndrey Smirnov case SDHC_BLKSIZE: 1708fd1e5c81SAndrey Smirnov /* 1709fd1e5c81SAndrey Smirnov * ESDHCI does not implement "Host SDMA Buffer Boundary", and 1710fd1e5c81SAndrey Smirnov * Linux driver will try to zero this field out which will 1711fd1e5c81SAndrey Smirnov * break the rest of SDHCI emulation. 1712fd1e5c81SAndrey Smirnov * 1713fd1e5c81SAndrey Smirnov * Linux defaults to maximum possible setting (512K boundary) 1714fd1e5c81SAndrey Smirnov * and it seems to be the only option that i.MX IP implements, 1715fd1e5c81SAndrey Smirnov * so we artificially set it to that value. 1716fd1e5c81SAndrey Smirnov */ 1717fd1e5c81SAndrey Smirnov val |= 0x7 << 12; 1718fd1e5c81SAndrey Smirnov /* FALLTHROUGH */ 1719fd1e5c81SAndrey Smirnov default: 1720fd1e5c81SAndrey Smirnov sdhci_write(opaque, offset, val, size); 1721fd1e5c81SAndrey Smirnov break; 1722fd1e5c81SAndrey Smirnov } 1723fd1e5c81SAndrey Smirnov } 1724fd1e5c81SAndrey Smirnov 1725fd1e5c81SAndrey Smirnov static const MemoryRegionOps usdhc_mmio_ops = { 1726fd1e5c81SAndrey Smirnov .read = usdhc_read, 1727fd1e5c81SAndrey Smirnov .write = usdhc_write, 1728fd1e5c81SAndrey Smirnov .valid = { 1729fd1e5c81SAndrey Smirnov .min_access_size = 1, 1730fd1e5c81SAndrey Smirnov .max_access_size = 4, 1731fd1e5c81SAndrey Smirnov .unaligned = false 1732fd1e5c81SAndrey Smirnov }, 1733fd1e5c81SAndrey Smirnov .endianness = DEVICE_LITTLE_ENDIAN, 1734fd1e5c81SAndrey Smirnov }; 1735fd1e5c81SAndrey Smirnov 1736fd1e5c81SAndrey Smirnov static void imx_usdhc_init(Object *obj) 1737fd1e5c81SAndrey Smirnov { 1738fd1e5c81SAndrey Smirnov SDHCIState *s = SYSBUS_SDHCI(obj); 1739fd1e5c81SAndrey Smirnov 1740fd1e5c81SAndrey Smirnov s->io_ops = &usdhc_mmio_ops; 1741fd1e5c81SAndrey Smirnov s->quirks = SDHCI_QUIRK_NO_BUSY_IRQ; 1742fd1e5c81SAndrey Smirnov } 1743fd1e5c81SAndrey Smirnov 1744fd1e5c81SAndrey Smirnov static const TypeInfo imx_usdhc_info = { 1745fd1e5c81SAndrey Smirnov .name = TYPE_IMX_USDHC, 1746fd1e5c81SAndrey Smirnov .parent = TYPE_SYSBUS_SDHCI, 1747fd1e5c81SAndrey Smirnov .instance_init = imx_usdhc_init, 1748fd1e5c81SAndrey Smirnov }; 1749fd1e5c81SAndrey Smirnov 1750c85fba50SPhilippe Mathieu-Daudé /* --- qdev Samsung s3c --- */ 1751c85fba50SPhilippe Mathieu-Daudé 1752c85fba50SPhilippe Mathieu-Daudé #define S3C_SDHCI_CONTROL2 0x80 1753c85fba50SPhilippe Mathieu-Daudé #define S3C_SDHCI_CONTROL3 0x84 1754c85fba50SPhilippe Mathieu-Daudé #define S3C_SDHCI_CONTROL4 0x8c 1755c85fba50SPhilippe Mathieu-Daudé 1756c85fba50SPhilippe Mathieu-Daudé static uint64_t sdhci_s3c_read(void *opaque, hwaddr offset, unsigned size) 1757c85fba50SPhilippe Mathieu-Daudé { 1758c85fba50SPhilippe Mathieu-Daudé uint64_t ret; 1759c85fba50SPhilippe Mathieu-Daudé 1760c85fba50SPhilippe Mathieu-Daudé switch (offset) { 1761c85fba50SPhilippe Mathieu-Daudé case S3C_SDHCI_CONTROL2: 1762c85fba50SPhilippe Mathieu-Daudé case S3C_SDHCI_CONTROL3: 1763c85fba50SPhilippe Mathieu-Daudé case S3C_SDHCI_CONTROL4: 1764c85fba50SPhilippe Mathieu-Daudé /* ignore */ 1765c85fba50SPhilippe Mathieu-Daudé ret = 0; 1766c85fba50SPhilippe Mathieu-Daudé break; 1767c85fba50SPhilippe Mathieu-Daudé default: 1768c85fba50SPhilippe Mathieu-Daudé ret = sdhci_read(opaque, offset, size); 1769c85fba50SPhilippe Mathieu-Daudé break; 1770c85fba50SPhilippe Mathieu-Daudé } 1771c85fba50SPhilippe Mathieu-Daudé 1772c85fba50SPhilippe Mathieu-Daudé return ret; 1773c85fba50SPhilippe Mathieu-Daudé } 1774c85fba50SPhilippe Mathieu-Daudé 1775c85fba50SPhilippe Mathieu-Daudé static void sdhci_s3c_write(void *opaque, hwaddr offset, uint64_t val, 1776c85fba50SPhilippe Mathieu-Daudé unsigned size) 1777c85fba50SPhilippe Mathieu-Daudé { 1778c85fba50SPhilippe Mathieu-Daudé switch (offset) { 1779c85fba50SPhilippe Mathieu-Daudé case S3C_SDHCI_CONTROL2: 1780c85fba50SPhilippe Mathieu-Daudé case S3C_SDHCI_CONTROL3: 1781c85fba50SPhilippe Mathieu-Daudé case S3C_SDHCI_CONTROL4: 1782c85fba50SPhilippe Mathieu-Daudé /* ignore */ 1783c85fba50SPhilippe Mathieu-Daudé break; 1784c85fba50SPhilippe Mathieu-Daudé default: 1785c85fba50SPhilippe Mathieu-Daudé sdhci_write(opaque, offset, val, size); 1786c85fba50SPhilippe Mathieu-Daudé break; 1787c85fba50SPhilippe Mathieu-Daudé } 1788c85fba50SPhilippe Mathieu-Daudé } 1789c85fba50SPhilippe Mathieu-Daudé 1790c85fba50SPhilippe Mathieu-Daudé static const MemoryRegionOps sdhci_s3c_mmio_ops = { 1791c85fba50SPhilippe Mathieu-Daudé .read = sdhci_s3c_read, 1792c85fba50SPhilippe Mathieu-Daudé .write = sdhci_s3c_write, 1793c85fba50SPhilippe Mathieu-Daudé .valid = { 1794c85fba50SPhilippe Mathieu-Daudé .min_access_size = 1, 1795c85fba50SPhilippe Mathieu-Daudé .max_access_size = 4, 1796c85fba50SPhilippe Mathieu-Daudé .unaligned = false 1797c85fba50SPhilippe Mathieu-Daudé }, 1798c85fba50SPhilippe Mathieu-Daudé .endianness = DEVICE_LITTLE_ENDIAN, 1799c85fba50SPhilippe Mathieu-Daudé }; 1800c85fba50SPhilippe Mathieu-Daudé 1801c85fba50SPhilippe Mathieu-Daudé static void sdhci_s3c_init(Object *obj) 1802c85fba50SPhilippe Mathieu-Daudé { 1803c85fba50SPhilippe Mathieu-Daudé SDHCIState *s = SYSBUS_SDHCI(obj); 1804c85fba50SPhilippe Mathieu-Daudé 1805c85fba50SPhilippe Mathieu-Daudé s->io_ops = &sdhci_s3c_mmio_ops; 1806c85fba50SPhilippe Mathieu-Daudé } 1807c85fba50SPhilippe Mathieu-Daudé 1808c85fba50SPhilippe Mathieu-Daudé static const TypeInfo sdhci_s3c_info = { 1809c85fba50SPhilippe Mathieu-Daudé .name = TYPE_S3C_SDHCI , 1810c85fba50SPhilippe Mathieu-Daudé .parent = TYPE_SYSBUS_SDHCI, 1811c85fba50SPhilippe Mathieu-Daudé .instance_init = sdhci_s3c_init, 1812c85fba50SPhilippe Mathieu-Daudé }; 1813c85fba50SPhilippe Mathieu-Daudé 181449ab747fSPaolo Bonzini static void sdhci_register_types(void) 181549ab747fSPaolo Bonzini { 18167302dcd6SKevin O'Connor type_register_static(&sdhci_sysbus_info); 181740bbc194SPeter Maydell type_register_static(&sdhci_bus_info); 1818fd1e5c81SAndrey Smirnov type_register_static(&imx_usdhc_info); 1819c85fba50SPhilippe Mathieu-Daudé type_register_static(&sdhci_s3c_info); 182049ab747fSPaolo Bonzini } 182149ab747fSPaolo Bonzini 182249ab747fSPaolo Bonzini type_init(sdhci_register_types) 1823