1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/hw.h" 27 #include "sysemu/block-backend.h" 28 #include "sysemu/blockdev.h" 29 #include "sysemu/dma.h" 30 #include "qemu/timer.h" 31 #include "qemu/bitops.h" 32 #include "sdhci-internal.h" 33 #include "qemu/log.h" 34 35 /* host controller debug messages */ 36 #ifndef SDHC_DEBUG 37 #define SDHC_DEBUG 0 38 #endif 39 40 #define DPRINT_L1(fmt, args...) \ 41 do { \ 42 if (SDHC_DEBUG) { \ 43 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ 44 } \ 45 } while (0) 46 #define DPRINT_L2(fmt, args...) \ 47 do { \ 48 if (SDHC_DEBUG > 1) { \ 49 fprintf(stderr, "QEMU SDHC: " fmt, ## args); \ 50 } \ 51 } while (0) 52 #define ERRPRINT(fmt, args...) \ 53 do { \ 54 if (SDHC_DEBUG) { \ 55 fprintf(stderr, "QEMU SDHC ERROR: " fmt, ## args); \ 56 } \ 57 } while (0) 58 59 #define TYPE_SDHCI_BUS "sdhci-bus" 60 #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) 61 62 /* Default SD/MMC host controller features information, which will be 63 * presented in CAPABILITIES register of generic SD host controller at reset. 64 * If not stated otherwise: 65 * 0 - not supported, 1 - supported, other - prohibited. 66 */ 67 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ 68 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ 69 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ 70 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ 71 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ 72 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */ 73 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ 74 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ 75 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ 76 /* Maximum host controller R/W buffers size 77 * Possible values: 512, 1024, 2048 bytes */ 78 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul 79 /* Maximum clock frequency for SDclock in MHz 80 * value in range 10-63 MHz, 0 - not defined */ 81 #define SDHC_CAPAB_BASECLKFREQ 52ul 82 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ 83 /* Timeout clock frequency 1-63, 0 - not defined */ 84 #define SDHC_CAPAB_TOCLKFREQ 52ul 85 86 /* Now check all parameters and calculate CAPABILITIES REGISTER value */ 87 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ 88 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ 89 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ 90 SDHC_CAPAB_TOUNIT > 1 91 #error Capabilities features can have value 0 or 1 only! 92 #endif 93 94 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512 95 #define MAX_BLOCK_LENGTH 0ul 96 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 97 #define MAX_BLOCK_LENGTH 1ul 98 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 99 #define MAX_BLOCK_LENGTH 2ul 100 #else 101 #error Max host controller block size can have value 512, 1024 or 2048 only! 102 #endif 103 104 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ 105 SDHC_CAPAB_BASECLKFREQ > 63 106 #error SDclock frequency can have value in range 0, 10-63 only! 107 #endif 108 109 #if SDHC_CAPAB_TOCLKFREQ > 63 110 #error Timeout clock frequency can have value in range 0-63 only! 111 #endif 112 113 #define SDHC_CAPAB_REG_DEFAULT \ 114 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ 115 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ 116 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ 117 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ 118 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ 119 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ 120 (SDHC_CAPAB_TOCLKFREQ)) 121 122 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 123 124 static uint8_t sdhci_slotint(SDHCIState *s) 125 { 126 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 127 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 128 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 129 } 130 131 static inline void sdhci_update_irq(SDHCIState *s) 132 { 133 qemu_set_irq(s->irq, sdhci_slotint(s)); 134 } 135 136 static void sdhci_raise_insertion_irq(void *opaque) 137 { 138 SDHCIState *s = (SDHCIState *)opaque; 139 140 if (s->norintsts & SDHC_NIS_REMOVE) { 141 timer_mod(s->insert_timer, 142 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 143 } else { 144 s->prnsts = 0x1ff0000; 145 if (s->norintstsen & SDHC_NISEN_INSERT) { 146 s->norintsts |= SDHC_NIS_INSERT; 147 } 148 sdhci_update_irq(s); 149 } 150 } 151 152 static void sdhci_set_inserted(DeviceState *dev, bool level) 153 { 154 SDHCIState *s = (SDHCIState *)dev; 155 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); 156 157 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 158 /* Give target some time to notice card ejection */ 159 timer_mod(s->insert_timer, 160 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 161 } else { 162 if (level) { 163 s->prnsts = 0x1ff0000; 164 if (s->norintstsen & SDHC_NISEN_INSERT) { 165 s->norintsts |= SDHC_NIS_INSERT; 166 } 167 } else { 168 s->prnsts = 0x1fa0000; 169 s->pwrcon &= ~SDHC_POWER_ON; 170 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 171 if (s->norintstsen & SDHC_NISEN_REMOVE) { 172 s->norintsts |= SDHC_NIS_REMOVE; 173 } 174 } 175 sdhci_update_irq(s); 176 } 177 } 178 179 static void sdhci_set_readonly(DeviceState *dev, bool level) 180 { 181 SDHCIState *s = (SDHCIState *)dev; 182 183 if (level) { 184 s->prnsts &= ~SDHC_WRITE_PROTECT; 185 } else { 186 /* Write enabled */ 187 s->prnsts |= SDHC_WRITE_PROTECT; 188 } 189 } 190 191 static void sdhci_reset(SDHCIState *s) 192 { 193 DeviceState *dev = DEVICE(s); 194 195 timer_del(s->insert_timer); 196 timer_del(s->transfer_timer); 197 /* Set all registers to 0. Capabilities registers are not cleared 198 * and assumed to always preserve their value, given to them during 199 * initialization */ 200 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 201 202 /* Reset other state based on current card insertion/readonly status */ 203 sdhci_set_inserted(dev, sdbus_get_inserted(&s->sdbus)); 204 sdhci_set_readonly(dev, sdbus_get_readonly(&s->sdbus)); 205 206 s->data_count = 0; 207 s->stopped_state = sdhc_not_stopped; 208 s->pending_insert_state = false; 209 } 210 211 static void sdhci_poweron_reset(DeviceState *dev) 212 { 213 /* QOM (ie power-on) reset. This is identical to reset 214 * commanded via device register apart from handling of the 215 * 'pending insert on powerup' quirk. 216 */ 217 SDHCIState *s = (SDHCIState *)dev; 218 219 sdhci_reset(s); 220 221 if (s->pending_insert_quirk) { 222 s->pending_insert_state = true; 223 } 224 } 225 226 static void sdhci_data_transfer(void *opaque); 227 228 static void sdhci_send_command(SDHCIState *s) 229 { 230 SDRequest request; 231 uint8_t response[16]; 232 int rlen; 233 234 s->errintsts = 0; 235 s->acmd12errsts = 0; 236 request.cmd = s->cmdreg >> 8; 237 request.arg = s->argument; 238 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); 239 rlen = sdbus_do_command(&s->sdbus, &request, response); 240 241 if (s->cmdreg & SDHC_CMD_RESPONSE) { 242 if (rlen == 4) { 243 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 244 (response[2] << 8) | response[3]; 245 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 246 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); 247 } else if (rlen == 16) { 248 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 249 (response[13] << 8) | response[14]; 250 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 251 (response[9] << 8) | response[10]; 252 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 253 (response[5] << 8) | response[6]; 254 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 255 response[2]; 256 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." 257 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", 258 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); 259 } else { 260 ERRPRINT("Timeout waiting for command response\n"); 261 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 262 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 263 s->norintsts |= SDHC_NIS_ERR; 264 } 265 } 266 267 if ((s->norintstsen & SDHC_NISEN_TRSCMP) && 268 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 269 s->norintsts |= SDHC_NIS_TRSCMP; 270 } 271 } 272 273 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 274 s->norintsts |= SDHC_NIS_CMDCMP; 275 } 276 277 sdhci_update_irq(s); 278 279 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 280 s->data_count = 0; 281 sdhci_data_transfer(s); 282 } 283 } 284 285 static void sdhci_end_transfer(SDHCIState *s) 286 { 287 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 288 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 289 SDRequest request; 290 uint8_t response[16]; 291 292 request.cmd = 0x0C; 293 request.arg = 0; 294 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); 295 sdbus_do_command(&s->sdbus, &request, response); 296 /* Auto CMD12 response goes to the upper Response register */ 297 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 298 (response[2] << 8) | response[3]; 299 } 300 301 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 302 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 303 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 304 305 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 306 s->norintsts |= SDHC_NIS_TRSCMP; 307 } 308 309 sdhci_update_irq(s); 310 } 311 312 /* 313 * Programmed i/o data transfer 314 */ 315 316 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 317 static void sdhci_read_block_from_card(SDHCIState *s) 318 { 319 int index = 0; 320 321 if ((s->trnmod & SDHC_TRNS_MULTI) && 322 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 323 return; 324 } 325 326 for (index = 0; index < (s->blksize & 0x0fff); index++) { 327 s->fifo_buffer[index] = sdbus_read_data(&s->sdbus); 328 } 329 330 /* New data now available for READ through Buffer Port Register */ 331 s->prnsts |= SDHC_DATA_AVAILABLE; 332 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 333 s->norintsts |= SDHC_NIS_RBUFRDY; 334 } 335 336 /* Clear DAT line active status if that was the last block */ 337 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 338 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 339 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 340 } 341 342 /* If stop at block gap request was set and it's not the last block of 343 * data - generate Block Event interrupt */ 344 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 345 s->blkcnt != 1) { 346 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 347 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 348 s->norintsts |= SDHC_EIS_BLKGAP; 349 } 350 } 351 352 sdhci_update_irq(s); 353 } 354 355 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 356 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 357 { 358 uint32_t value = 0; 359 int i; 360 361 /* first check that a valid data exists in host controller input buffer */ 362 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 363 ERRPRINT("Trying to read from empty buffer\n"); 364 return 0; 365 } 366 367 for (i = 0; i < size; i++) { 368 value |= s->fifo_buffer[s->data_count] << i * 8; 369 s->data_count++; 370 /* check if we've read all valid data (blksize bytes) from buffer */ 371 if ((s->data_count) >= (s->blksize & 0x0fff)) { 372 DPRINT_L2("All %u bytes of data have been read from input buffer\n", 373 s->data_count); 374 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 375 s->data_count = 0; /* next buff read must start at position [0] */ 376 377 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 378 s->blkcnt--; 379 } 380 381 /* if that was the last block of data */ 382 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 383 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 384 /* stop at gap request */ 385 (s->stopped_state == sdhc_gap_read && 386 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 387 sdhci_end_transfer(s); 388 } else { /* if there are more data, read next block from card */ 389 sdhci_read_block_from_card(s); 390 } 391 break; 392 } 393 } 394 395 return value; 396 } 397 398 /* Write data from host controller FIFO to card */ 399 static void sdhci_write_block_to_card(SDHCIState *s) 400 { 401 int index = 0; 402 403 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 404 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 405 s->norintsts |= SDHC_NIS_WBUFRDY; 406 } 407 sdhci_update_irq(s); 408 return; 409 } 410 411 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 412 if (s->blkcnt == 0) { 413 return; 414 } else { 415 s->blkcnt--; 416 } 417 } 418 419 for (index = 0; index < (s->blksize & 0x0fff); index++) { 420 sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); 421 } 422 423 /* Next data can be written through BUFFER DATORT register */ 424 s->prnsts |= SDHC_SPACE_AVAILABLE; 425 426 /* Finish transfer if that was the last block of data */ 427 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 428 ((s->trnmod & SDHC_TRNS_MULTI) && 429 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 430 sdhci_end_transfer(s); 431 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 432 s->norintsts |= SDHC_NIS_WBUFRDY; 433 } 434 435 /* Generate Block Gap Event if requested and if not the last block */ 436 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 437 s->blkcnt > 0) { 438 s->prnsts &= ~SDHC_DOING_WRITE; 439 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 440 s->norintsts |= SDHC_EIS_BLKGAP; 441 } 442 sdhci_end_transfer(s); 443 } 444 445 sdhci_update_irq(s); 446 } 447 448 /* Write @size bytes of @value data to host controller @s Buffer Data Port 449 * register */ 450 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 451 { 452 unsigned i; 453 454 /* Check that there is free space left in a buffer */ 455 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 456 ERRPRINT("Can't write to data buffer: buffer full\n"); 457 return; 458 } 459 460 for (i = 0; i < size; i++) { 461 s->fifo_buffer[s->data_count] = value & 0xFF; 462 s->data_count++; 463 value >>= 8; 464 if (s->data_count >= (s->blksize & 0x0fff)) { 465 DPRINT_L2("write buffer filled with %u bytes of data\n", 466 s->data_count); 467 s->data_count = 0; 468 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 469 if (s->prnsts & SDHC_DOING_WRITE) { 470 sdhci_write_block_to_card(s); 471 } 472 } 473 } 474 } 475 476 /* 477 * Single DMA data transfer 478 */ 479 480 /* Multi block SDMA transfer */ 481 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 482 { 483 bool page_aligned = false; 484 unsigned int n, begin; 485 const uint16_t block_size = s->blksize & 0x0fff; 486 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); 487 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 488 489 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 490 * possible stop at page boundary if initial address is not page aligned, 491 * allow them to work properly */ 492 if ((s->sdmasysad % boundary_chk) == 0) { 493 page_aligned = true; 494 } 495 496 if (s->trnmod & SDHC_TRNS_READ) { 497 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 498 SDHC_DAT_LINE_ACTIVE; 499 while (s->blkcnt) { 500 if (s->data_count == 0) { 501 for (n = 0; n < block_size; n++) { 502 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 503 } 504 } 505 begin = s->data_count; 506 if (((boundary_count + begin) < block_size) && page_aligned) { 507 s->data_count = boundary_count + begin; 508 boundary_count = 0; 509 } else { 510 s->data_count = block_size; 511 boundary_count -= block_size - begin; 512 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 513 s->blkcnt--; 514 } 515 } 516 dma_memory_write(&address_space_memory, s->sdmasysad, 517 &s->fifo_buffer[begin], s->data_count - begin); 518 s->sdmasysad += s->data_count - begin; 519 if (s->data_count == block_size) { 520 s->data_count = 0; 521 } 522 if (page_aligned && boundary_count == 0) { 523 break; 524 } 525 } 526 } else { 527 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 528 SDHC_DAT_LINE_ACTIVE; 529 while (s->blkcnt) { 530 begin = s->data_count; 531 if (((boundary_count + begin) < block_size) && page_aligned) { 532 s->data_count = boundary_count + begin; 533 boundary_count = 0; 534 } else { 535 s->data_count = block_size; 536 boundary_count -= block_size - begin; 537 } 538 dma_memory_read(&address_space_memory, s->sdmasysad, 539 &s->fifo_buffer[begin], s->data_count); 540 s->sdmasysad += s->data_count - begin; 541 if (s->data_count == block_size) { 542 for (n = 0; n < block_size; n++) { 543 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 544 } 545 s->data_count = 0; 546 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 547 s->blkcnt--; 548 } 549 } 550 if (page_aligned && boundary_count == 0) { 551 break; 552 } 553 } 554 } 555 556 if (s->blkcnt == 0) { 557 sdhci_end_transfer(s); 558 } else { 559 if (s->norintstsen & SDHC_NISEN_DMA) { 560 s->norintsts |= SDHC_NIS_DMA; 561 } 562 sdhci_update_irq(s); 563 } 564 } 565 566 /* single block SDMA transfer */ 567 568 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 569 { 570 int n; 571 uint32_t datacnt = s->blksize & 0x0fff; 572 573 if (s->trnmod & SDHC_TRNS_READ) { 574 for (n = 0; n < datacnt; n++) { 575 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 576 } 577 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, 578 datacnt); 579 } else { 580 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, 581 datacnt); 582 for (n = 0; n < datacnt; n++) { 583 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 584 } 585 } 586 587 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 588 s->blkcnt--; 589 } 590 591 sdhci_end_transfer(s); 592 } 593 594 typedef struct ADMADescr { 595 hwaddr addr; 596 uint16_t length; 597 uint8_t attr; 598 uint8_t incr; 599 } ADMADescr; 600 601 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 602 { 603 uint32_t adma1 = 0; 604 uint64_t adma2 = 0; 605 hwaddr entry_addr = (hwaddr)s->admasysaddr; 606 switch (SDHC_DMA_TYPE(s->hostctl)) { 607 case SDHC_CTRL_ADMA2_32: 608 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, 609 sizeof(adma2)); 610 adma2 = le64_to_cpu(adma2); 611 /* The spec does not specify endianness of descriptor table. 612 * We currently assume that it is LE. 613 */ 614 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 615 dscr->length = (uint16_t)extract64(adma2, 16, 16); 616 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 617 dscr->incr = 8; 618 break; 619 case SDHC_CTRL_ADMA1_32: 620 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, 621 sizeof(adma1)); 622 adma1 = le32_to_cpu(adma1); 623 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 624 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 625 dscr->incr = 4; 626 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 627 dscr->length = (uint16_t)extract32(adma1, 12, 16); 628 } else { 629 dscr->length = 4096; 630 } 631 break; 632 case SDHC_CTRL_ADMA2_64: 633 dma_memory_read(&address_space_memory, entry_addr, 634 (uint8_t *)(&dscr->attr), 1); 635 dma_memory_read(&address_space_memory, entry_addr + 2, 636 (uint8_t *)(&dscr->length), 2); 637 dscr->length = le16_to_cpu(dscr->length); 638 dma_memory_read(&address_space_memory, entry_addr + 4, 639 (uint8_t *)(&dscr->addr), 8); 640 dscr->attr = le64_to_cpu(dscr->attr); 641 dscr->attr &= 0xfffffff8; 642 dscr->incr = 12; 643 break; 644 } 645 } 646 647 /* Advanced DMA data transfer */ 648 649 static void sdhci_do_adma(SDHCIState *s) 650 { 651 unsigned int n, begin, length; 652 const uint16_t block_size = s->blksize & 0x0fff; 653 ADMADescr dscr; 654 int i; 655 656 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 657 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 658 659 get_adma_description(s, &dscr); 660 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", 661 dscr.addr, dscr.length, dscr.attr); 662 663 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 664 /* Indicate that error occurred in ST_FDS state */ 665 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 666 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 667 668 /* Generate ADMA error interrupt */ 669 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 670 s->errintsts |= SDHC_EIS_ADMAERR; 671 s->norintsts |= SDHC_NIS_ERR; 672 } 673 674 sdhci_update_irq(s); 675 return; 676 } 677 678 length = dscr.length ? dscr.length : 65536; 679 680 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 681 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 682 683 if (s->trnmod & SDHC_TRNS_READ) { 684 while (length) { 685 if (s->data_count == 0) { 686 for (n = 0; n < block_size; n++) { 687 s->fifo_buffer[n] = sdbus_read_data(&s->sdbus); 688 } 689 } 690 begin = s->data_count; 691 if ((length + begin) < block_size) { 692 s->data_count = length + begin; 693 length = 0; 694 } else { 695 s->data_count = block_size; 696 length -= block_size - begin; 697 } 698 dma_memory_write(&address_space_memory, dscr.addr, 699 &s->fifo_buffer[begin], 700 s->data_count - begin); 701 dscr.addr += s->data_count - begin; 702 if (s->data_count == block_size) { 703 s->data_count = 0; 704 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 705 s->blkcnt--; 706 if (s->blkcnt == 0) { 707 break; 708 } 709 } 710 } 711 } 712 } else { 713 while (length) { 714 begin = s->data_count; 715 if ((length + begin) < block_size) { 716 s->data_count = length + begin; 717 length = 0; 718 } else { 719 s->data_count = block_size; 720 length -= block_size - begin; 721 } 722 dma_memory_read(&address_space_memory, dscr.addr, 723 &s->fifo_buffer[begin], 724 s->data_count - begin); 725 dscr.addr += s->data_count - begin; 726 if (s->data_count == block_size) { 727 for (n = 0; n < block_size; n++) { 728 sdbus_write_data(&s->sdbus, s->fifo_buffer[n]); 729 } 730 s->data_count = 0; 731 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 732 s->blkcnt--; 733 if (s->blkcnt == 0) { 734 break; 735 } 736 } 737 } 738 } 739 } 740 s->admasysaddr += dscr.incr; 741 break; 742 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 743 s->admasysaddr = dscr.addr; 744 DPRINT_L1("ADMA link: admasysaddr=0x%" PRIx64 "\n", 745 s->admasysaddr); 746 break; 747 default: 748 s->admasysaddr += dscr.incr; 749 break; 750 } 751 752 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 753 DPRINT_L1("ADMA interrupt: admasysaddr=0x%" PRIx64 "\n", 754 s->admasysaddr); 755 if (s->norintstsen & SDHC_NISEN_DMA) { 756 s->norintsts |= SDHC_NIS_DMA; 757 } 758 759 sdhci_update_irq(s); 760 } 761 762 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 763 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 764 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 765 DPRINT_L2("ADMA transfer completed\n"); 766 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 767 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 768 s->blkcnt != 0)) { 769 ERRPRINT("SD/MMC host ADMA length mismatch\n"); 770 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 771 SDHC_ADMAERR_STATE_ST_TFR; 772 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 773 ERRPRINT("Set ADMA error flag\n"); 774 s->errintsts |= SDHC_EIS_ADMAERR; 775 s->norintsts |= SDHC_NIS_ERR; 776 } 777 778 sdhci_update_irq(s); 779 } 780 sdhci_end_transfer(s); 781 return; 782 } 783 784 } 785 786 /* we have unfinished business - reschedule to continue ADMA */ 787 timer_mod(s->transfer_timer, 788 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 789 } 790 791 /* Perform data transfer according to controller configuration */ 792 793 static void sdhci_data_transfer(void *opaque) 794 { 795 SDHCIState *s = (SDHCIState *)opaque; 796 797 if (s->trnmod & SDHC_TRNS_DMA) { 798 switch (SDHC_DMA_TYPE(s->hostctl)) { 799 case SDHC_CTRL_SDMA: 800 if ((s->trnmod & SDHC_TRNS_MULTI) && 801 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) { 802 break; 803 } 804 805 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 806 sdhci_sdma_transfer_single_block(s); 807 } else { 808 sdhci_sdma_transfer_multi_blocks(s); 809 } 810 811 break; 812 case SDHC_CTRL_ADMA1_32: 813 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { 814 ERRPRINT("ADMA1 not supported\n"); 815 break; 816 } 817 818 sdhci_do_adma(s); 819 break; 820 case SDHC_CTRL_ADMA2_32: 821 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { 822 ERRPRINT("ADMA2 not supported\n"); 823 break; 824 } 825 826 sdhci_do_adma(s); 827 break; 828 case SDHC_CTRL_ADMA2_64: 829 if (!(s->capareg & SDHC_CAN_DO_ADMA2) || 830 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { 831 ERRPRINT("64 bit ADMA not supported\n"); 832 break; 833 } 834 835 sdhci_do_adma(s); 836 break; 837 default: 838 ERRPRINT("Unsupported DMA type\n"); 839 break; 840 } 841 } else { 842 if ((s->trnmod & SDHC_TRNS_READ) && sdbus_data_ready(&s->sdbus)) { 843 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 844 SDHC_DAT_LINE_ACTIVE; 845 sdhci_read_block_from_card(s); 846 } else { 847 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 848 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 849 sdhci_write_block_to_card(s); 850 } 851 } 852 } 853 854 static bool sdhci_can_issue_command(SDHCIState *s) 855 { 856 if (!SDHC_CLOCK_IS_ON(s->clkcon) || 857 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 858 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 859 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 860 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 861 return false; 862 } 863 864 return true; 865 } 866 867 /* The Buffer Data Port register must be accessed in sequential and 868 * continuous manner */ 869 static inline bool 870 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 871 { 872 if ((s->data_count & 0x3) != byte_num) { 873 ERRPRINT("Non-sequential access to Buffer Data Port register" 874 "is prohibited\n"); 875 return false; 876 } 877 return true; 878 } 879 880 static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) 881 { 882 SDHCIState *s = (SDHCIState *)opaque; 883 uint32_t ret = 0; 884 885 switch (offset & ~0x3) { 886 case SDHC_SYSAD: 887 ret = s->sdmasysad; 888 break; 889 case SDHC_BLKSIZE: 890 ret = s->blksize | (s->blkcnt << 16); 891 break; 892 case SDHC_ARGUMENT: 893 ret = s->argument; 894 break; 895 case SDHC_TRNMOD: 896 ret = s->trnmod | (s->cmdreg << 16); 897 break; 898 case SDHC_RSPREG0 ... SDHC_RSPREG3: 899 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 900 break; 901 case SDHC_BDATA: 902 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 903 ret = sdhci_read_dataport(s, size); 904 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, 905 ret, ret); 906 return ret; 907 } 908 break; 909 case SDHC_PRNSTS: 910 ret = s->prnsts; 911 break; 912 case SDHC_HOSTCTL: 913 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | 914 (s->wakcon << 24); 915 break; 916 case SDHC_CLKCON: 917 ret = s->clkcon | (s->timeoutcon << 16); 918 break; 919 case SDHC_NORINTSTS: 920 ret = s->norintsts | (s->errintsts << 16); 921 break; 922 case SDHC_NORINTSTSEN: 923 ret = s->norintstsen | (s->errintstsen << 16); 924 break; 925 case SDHC_NORINTSIGEN: 926 ret = s->norintsigen | (s->errintsigen << 16); 927 break; 928 case SDHC_ACMD12ERRSTS: 929 ret = s->acmd12errsts; 930 break; 931 case SDHC_CAPAREG: 932 ret = s->capareg; 933 break; 934 case SDHC_MAXCURR: 935 ret = s->maxcurr; 936 break; 937 case SDHC_ADMAERR: 938 ret = s->admaerr; 939 break; 940 case SDHC_ADMASYSADDR: 941 ret = (uint32_t)s->admasysaddr; 942 break; 943 case SDHC_ADMASYSADDR + 4: 944 ret = (uint32_t)(s->admasysaddr >> 32); 945 break; 946 case SDHC_SLOT_INT_STATUS: 947 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); 948 break; 949 default: 950 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, (int)offset); 951 break; 952 } 953 954 ret >>= (offset & 0x3) * 8; 955 ret &= (1ULL << (size * 8)) - 1; 956 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, (int)offset, ret, ret); 957 return ret; 958 } 959 960 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 961 { 962 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 963 return; 964 } 965 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 966 967 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 968 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 969 if (s->stopped_state == sdhc_gap_read) { 970 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 971 sdhci_read_block_from_card(s); 972 } else { 973 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 974 sdhci_write_block_to_card(s); 975 } 976 s->stopped_state = sdhc_not_stopped; 977 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 978 if (s->prnsts & SDHC_DOING_READ) { 979 s->stopped_state = sdhc_gap_read; 980 } else if (s->prnsts & SDHC_DOING_WRITE) { 981 s->stopped_state = sdhc_gap_write; 982 } 983 } 984 } 985 986 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 987 { 988 switch (value) { 989 case SDHC_RESET_ALL: 990 sdhci_reset(s); 991 break; 992 case SDHC_RESET_CMD: 993 s->prnsts &= ~SDHC_CMD_INHIBIT; 994 s->norintsts &= ~SDHC_NIS_CMDCMP; 995 break; 996 case SDHC_RESET_DATA: 997 s->data_count = 0; 998 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 999 SDHC_DOING_READ | SDHC_DOING_WRITE | 1000 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 1001 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 1002 s->stopped_state = sdhc_not_stopped; 1003 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 1004 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 1005 break; 1006 } 1007 } 1008 1009 static void 1010 sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) 1011 { 1012 SDHCIState *s = (SDHCIState *)opaque; 1013 unsigned shift = 8 * (offset & 0x3); 1014 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 1015 uint32_t value = val; 1016 value <<= shift; 1017 1018 switch (offset & ~0x3) { 1019 case SDHC_SYSAD: 1020 s->sdmasysad = (s->sdmasysad & mask) | value; 1021 MASKED_WRITE(s->sdmasysad, mask, value); 1022 /* Writing to last byte of sdmasysad might trigger transfer */ 1023 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1024 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { 1025 sdhci_sdma_transfer_multi_blocks(s); 1026 } 1027 break; 1028 case SDHC_BLKSIZE: 1029 if (!TRANSFERRING_DATA(s->prnsts)) { 1030 MASKED_WRITE(s->blksize, mask, value); 1031 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1032 } 1033 1034 /* Limit block size to the maximum buffer size */ 1035 if (extract32(s->blksize, 0, 12) > s->buf_maxsz) { 1036 qemu_log_mask(LOG_GUEST_ERROR, "%s: Size 0x%x is larger than " \ 1037 "the maximum buffer 0x%x", __func__, s->blksize, 1038 s->buf_maxsz); 1039 1040 s->blksize = deposit32(s->blksize, 0, 12, s->buf_maxsz); 1041 } 1042 1043 break; 1044 case SDHC_ARGUMENT: 1045 MASKED_WRITE(s->argument, mask, value); 1046 break; 1047 case SDHC_TRNMOD: 1048 /* DMA can be enabled only if it is supported as indicated by 1049 * capabilities register */ 1050 if (!(s->capareg & SDHC_CAN_DO_DMA)) { 1051 value &= ~SDHC_TRNS_DMA; 1052 } 1053 MASKED_WRITE(s->trnmod, mask, value); 1054 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1055 1056 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1057 if ((mask & 0xFF000000) || !sdhci_can_issue_command(s)) { 1058 break; 1059 } 1060 1061 sdhci_send_command(s); 1062 break; 1063 case SDHC_BDATA: 1064 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1065 sdhci_write_dataport(s, value >> shift, size); 1066 } 1067 break; 1068 case SDHC_HOSTCTL: 1069 if (!(mask & 0xFF0000)) { 1070 sdhci_blkgap_write(s, value >> 16); 1071 } 1072 MASKED_WRITE(s->hostctl, mask, value); 1073 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1074 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1075 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1076 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1077 s->pwrcon &= ~SDHC_POWER_ON; 1078 } 1079 break; 1080 case SDHC_CLKCON: 1081 if (!(mask & 0xFF000000)) { 1082 sdhci_reset_write(s, value >> 24); 1083 } 1084 MASKED_WRITE(s->clkcon, mask, value); 1085 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1086 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1087 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1088 } else { 1089 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1090 } 1091 break; 1092 case SDHC_NORINTSTS: 1093 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1094 value &= ~SDHC_NIS_CARDINT; 1095 } 1096 s->norintsts &= mask | ~value; 1097 s->errintsts &= (mask >> 16) | ~(value >> 16); 1098 if (s->errintsts) { 1099 s->norintsts |= SDHC_NIS_ERR; 1100 } else { 1101 s->norintsts &= ~SDHC_NIS_ERR; 1102 } 1103 sdhci_update_irq(s); 1104 break; 1105 case SDHC_NORINTSTSEN: 1106 MASKED_WRITE(s->norintstsen, mask, value); 1107 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1108 s->norintsts &= s->norintstsen; 1109 s->errintsts &= s->errintstsen; 1110 if (s->errintsts) { 1111 s->norintsts |= SDHC_NIS_ERR; 1112 } else { 1113 s->norintsts &= ~SDHC_NIS_ERR; 1114 } 1115 /* Quirk for Raspberry Pi: pending card insert interrupt 1116 * appears when first enabled after power on */ 1117 if ((s->norintstsen & SDHC_NISEN_INSERT) && s->pending_insert_state) { 1118 assert(s->pending_insert_quirk); 1119 s->norintsts |= SDHC_NIS_INSERT; 1120 s->pending_insert_state = false; 1121 } 1122 sdhci_update_irq(s); 1123 break; 1124 case SDHC_NORINTSIGEN: 1125 MASKED_WRITE(s->norintsigen, mask, value); 1126 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1127 sdhci_update_irq(s); 1128 break; 1129 case SDHC_ADMAERR: 1130 MASKED_WRITE(s->admaerr, mask, value); 1131 break; 1132 case SDHC_ADMASYSADDR: 1133 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1134 (uint64_t)mask)) | (uint64_t)value; 1135 break; 1136 case SDHC_ADMASYSADDR + 4: 1137 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1138 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1139 break; 1140 case SDHC_FEAER: 1141 s->acmd12errsts |= value; 1142 s->errintsts |= (value >> 16) & s->errintstsen; 1143 if (s->acmd12errsts) { 1144 s->errintsts |= SDHC_EIS_CMD12ERR; 1145 } 1146 if (s->errintsts) { 1147 s->norintsts |= SDHC_NIS_ERR; 1148 } 1149 sdhci_update_irq(s); 1150 break; 1151 default: 1152 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", 1153 size, (int)offset, value >> shift, value >> shift); 1154 break; 1155 } 1156 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", 1157 size, (int)offset, value >> shift, value >> shift); 1158 } 1159 1160 static const MemoryRegionOps sdhci_mmio_ops = { 1161 .read = sdhci_read, 1162 .write = sdhci_write, 1163 .valid = { 1164 .min_access_size = 1, 1165 .max_access_size = 4, 1166 .unaligned = false 1167 }, 1168 .endianness = DEVICE_LITTLE_ENDIAN, 1169 }; 1170 1171 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 1172 { 1173 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { 1174 case 0: 1175 return 512; 1176 case 1: 1177 return 1024; 1178 case 2: 1179 return 2048; 1180 default: 1181 hw_error("SDHC: unsupported value for maximum block size\n"); 1182 return 0; 1183 } 1184 } 1185 1186 static void sdhci_initfn(SDHCIState *s) 1187 { 1188 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), 1189 TYPE_SDHCI_BUS, DEVICE(s), "sd-bus"); 1190 1191 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1192 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_data_transfer, s); 1193 } 1194 1195 static void sdhci_uninitfn(SDHCIState *s) 1196 { 1197 timer_del(s->insert_timer); 1198 timer_free(s->insert_timer); 1199 timer_del(s->transfer_timer); 1200 timer_free(s->transfer_timer); 1201 qemu_free_irq(s->eject_cb); 1202 qemu_free_irq(s->ro_cb); 1203 1204 g_free(s->fifo_buffer); 1205 s->fifo_buffer = NULL; 1206 } 1207 1208 static bool sdhci_pending_insert_vmstate_needed(void *opaque) 1209 { 1210 SDHCIState *s = opaque; 1211 1212 return s->pending_insert_state; 1213 } 1214 1215 static const VMStateDescription sdhci_pending_insert_vmstate = { 1216 .name = "sdhci/pending-insert", 1217 .version_id = 1, 1218 .minimum_version_id = 1, 1219 .needed = sdhci_pending_insert_vmstate_needed, 1220 .fields = (VMStateField[]) { 1221 VMSTATE_BOOL(pending_insert_state, SDHCIState), 1222 VMSTATE_END_OF_LIST() 1223 }, 1224 }; 1225 1226 const VMStateDescription sdhci_vmstate = { 1227 .name = "sdhci", 1228 .version_id = 1, 1229 .minimum_version_id = 1, 1230 .fields = (VMStateField[]) { 1231 VMSTATE_UINT32(sdmasysad, SDHCIState), 1232 VMSTATE_UINT16(blksize, SDHCIState), 1233 VMSTATE_UINT16(blkcnt, SDHCIState), 1234 VMSTATE_UINT32(argument, SDHCIState), 1235 VMSTATE_UINT16(trnmod, SDHCIState), 1236 VMSTATE_UINT16(cmdreg, SDHCIState), 1237 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1238 VMSTATE_UINT32(prnsts, SDHCIState), 1239 VMSTATE_UINT8(hostctl, SDHCIState), 1240 VMSTATE_UINT8(pwrcon, SDHCIState), 1241 VMSTATE_UINT8(blkgap, SDHCIState), 1242 VMSTATE_UINT8(wakcon, SDHCIState), 1243 VMSTATE_UINT16(clkcon, SDHCIState), 1244 VMSTATE_UINT8(timeoutcon, SDHCIState), 1245 VMSTATE_UINT8(admaerr, SDHCIState), 1246 VMSTATE_UINT16(norintsts, SDHCIState), 1247 VMSTATE_UINT16(errintsts, SDHCIState), 1248 VMSTATE_UINT16(norintstsen, SDHCIState), 1249 VMSTATE_UINT16(errintstsen, SDHCIState), 1250 VMSTATE_UINT16(norintsigen, SDHCIState), 1251 VMSTATE_UINT16(errintsigen, SDHCIState), 1252 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1253 VMSTATE_UINT16(data_count, SDHCIState), 1254 VMSTATE_UINT64(admasysaddr, SDHCIState), 1255 VMSTATE_UINT8(stopped_state, SDHCIState), 1256 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz), 1257 VMSTATE_TIMER_PTR(insert_timer, SDHCIState), 1258 VMSTATE_TIMER_PTR(transfer_timer, SDHCIState), 1259 VMSTATE_END_OF_LIST() 1260 }, 1261 .subsections = (const VMStateDescription*[]) { 1262 &sdhci_pending_insert_vmstate, 1263 NULL 1264 }, 1265 }; 1266 1267 /* Capabilities registers provide information on supported features of this 1268 * specific host controller implementation */ 1269 static Property sdhci_pci_properties[] = { 1270 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1271 SDHC_CAPAB_REG_DEFAULT), 1272 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1273 DEFINE_PROP_END_OF_LIST(), 1274 }; 1275 1276 static void sdhci_pci_realize(PCIDevice *dev, Error **errp) 1277 { 1278 SDHCIState *s = PCI_SDHCI(dev); 1279 dev->config[PCI_CLASS_PROG] = 0x01; /* Standard Host supported DMA */ 1280 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */ 1281 sdhci_initfn(s); 1282 s->buf_maxsz = sdhci_get_fifolen(s); 1283 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1284 s->irq = pci_allocate_irq(dev); 1285 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1286 SDHC_REGISTERS_MAP_SIZE); 1287 pci_register_bar(dev, 0, 0, &s->iomem); 1288 } 1289 1290 static void sdhci_pci_exit(PCIDevice *dev) 1291 { 1292 SDHCIState *s = PCI_SDHCI(dev); 1293 sdhci_uninitfn(s); 1294 } 1295 1296 static void sdhci_pci_class_init(ObjectClass *klass, void *data) 1297 { 1298 DeviceClass *dc = DEVICE_CLASS(klass); 1299 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1300 1301 k->realize = sdhci_pci_realize; 1302 k->exit = sdhci_pci_exit; 1303 k->vendor_id = PCI_VENDOR_ID_REDHAT; 1304 k->device_id = PCI_DEVICE_ID_REDHAT_SDHCI; 1305 k->class_id = PCI_CLASS_SYSTEM_SDHCI; 1306 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); 1307 dc->vmsd = &sdhci_vmstate; 1308 dc->props = sdhci_pci_properties; 1309 dc->reset = sdhci_poweron_reset; 1310 } 1311 1312 static const TypeInfo sdhci_pci_info = { 1313 .name = TYPE_PCI_SDHCI, 1314 .parent = TYPE_PCI_DEVICE, 1315 .instance_size = sizeof(SDHCIState), 1316 .class_init = sdhci_pci_class_init, 1317 }; 1318 1319 static Property sdhci_sysbus_properties[] = { 1320 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1321 SDHC_CAPAB_REG_DEFAULT), 1322 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1323 DEFINE_PROP_BOOL("pending-insert-quirk", SDHCIState, pending_insert_quirk, 1324 false), 1325 DEFINE_PROP_END_OF_LIST(), 1326 }; 1327 1328 static void sdhci_sysbus_init(Object *obj) 1329 { 1330 SDHCIState *s = SYSBUS_SDHCI(obj); 1331 1332 sdhci_initfn(s); 1333 } 1334 1335 static void sdhci_sysbus_finalize(Object *obj) 1336 { 1337 SDHCIState *s = SYSBUS_SDHCI(obj); 1338 sdhci_uninitfn(s); 1339 } 1340 1341 static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) 1342 { 1343 SDHCIState *s = SYSBUS_SDHCI(dev); 1344 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1345 1346 s->buf_maxsz = sdhci_get_fifolen(s); 1347 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1348 sysbus_init_irq(sbd, &s->irq); 1349 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1350 SDHC_REGISTERS_MAP_SIZE); 1351 sysbus_init_mmio(sbd, &s->iomem); 1352 } 1353 1354 static void sdhci_sysbus_class_init(ObjectClass *klass, void *data) 1355 { 1356 DeviceClass *dc = DEVICE_CLASS(klass); 1357 1358 dc->vmsd = &sdhci_vmstate; 1359 dc->props = sdhci_sysbus_properties; 1360 dc->realize = sdhci_sysbus_realize; 1361 dc->reset = sdhci_poweron_reset; 1362 } 1363 1364 static const TypeInfo sdhci_sysbus_info = { 1365 .name = TYPE_SYSBUS_SDHCI, 1366 .parent = TYPE_SYS_BUS_DEVICE, 1367 .instance_size = sizeof(SDHCIState), 1368 .instance_init = sdhci_sysbus_init, 1369 .instance_finalize = sdhci_sysbus_finalize, 1370 .class_init = sdhci_sysbus_class_init, 1371 }; 1372 1373 static void sdhci_bus_class_init(ObjectClass *klass, void *data) 1374 { 1375 SDBusClass *sbc = SD_BUS_CLASS(klass); 1376 1377 sbc->set_inserted = sdhci_set_inserted; 1378 sbc->set_readonly = sdhci_set_readonly; 1379 } 1380 1381 static const TypeInfo sdhci_bus_info = { 1382 .name = TYPE_SDHCI_BUS, 1383 .parent = TYPE_SD_BUS, 1384 .instance_size = sizeof(SDBus), 1385 .class_init = sdhci_bus_class_init, 1386 }; 1387 1388 static void sdhci_register_types(void) 1389 { 1390 type_register_static(&sdhci_pci_info); 1391 type_register_static(&sdhci_sysbus_info); 1392 type_register_static(&sdhci_bus_info); 1393 } 1394 1395 type_init(sdhci_register_types) 1396