1 /* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #include "hw/hw.h" 26 #include "sysemu/blockdev.h" 27 #include "sysemu/dma.h" 28 #include "qemu/timer.h" 29 #include "qemu/bitops.h" 30 31 #include "sdhci.h" 32 33 /* host controller debug messages */ 34 #ifndef SDHC_DEBUG 35 #define SDHC_DEBUG 0 36 #endif 37 38 #if SDHC_DEBUG == 0 39 #define DPRINT_L1(fmt, args...) do { } while (0) 40 #define DPRINT_L2(fmt, args...) do { } while (0) 41 #define ERRPRINT(fmt, args...) do { } while (0) 42 #elif SDHC_DEBUG == 1 43 #define DPRINT_L1(fmt, args...) \ 44 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) 45 #define DPRINT_L2(fmt, args...) do { } while (0) 46 #define ERRPRINT(fmt, args...) \ 47 do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0) 48 #else 49 #define DPRINT_L1(fmt, args...) \ 50 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) 51 #define DPRINT_L2(fmt, args...) \ 52 do {fprintf(stderr, "QEMU SDHC: "fmt, ## args); } while (0) 53 #define ERRPRINT(fmt, args...) \ 54 do {fprintf(stderr, "QEMU SDHC ERROR: "fmt, ## args); } while (0) 55 #endif 56 57 /* Default SD/MMC host controller features information, which will be 58 * presented in CAPABILITIES register of generic SD host controller at reset. 59 * If not stated otherwise: 60 * 0 - not supported, 1 - supported, other - prohibited. 61 */ 62 #define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ 63 #define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ 64 #define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ 65 #define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ 66 #define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ 67 #define SDHC_CAPAB_SDMA 1ul /* SDMA support */ 68 #define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ 69 #define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ 70 #define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ 71 /* Maximum host controller R/W buffers size 72 * Possible values: 512, 1024, 2048 bytes */ 73 #define SDHC_CAPAB_MAXBLOCKLENGTH 512ul 74 /* Maximum clock frequency for SDclock in MHz 75 * value in range 10-63 MHz, 0 - not defined */ 76 #define SDHC_CAPAB_BASECLKFREQ 0ul 77 #define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ 78 /* Timeout clock frequency 1-63, 0 - not defined */ 79 #define SDHC_CAPAB_TOCLKFREQ 0ul 80 81 /* Now check all parameters and calculate CAPABILITIES REGISTER value */ 82 #if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ 83 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ 84 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ 85 SDHC_CAPAB_TOUNIT > 1 86 #error Capabilities features can have value 0 or 1 only! 87 #endif 88 89 #if SDHC_CAPAB_MAXBLOCKLENGTH == 512 90 #define MAX_BLOCK_LENGTH 0ul 91 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 92 #define MAX_BLOCK_LENGTH 1ul 93 #elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 94 #define MAX_BLOCK_LENGTH 2ul 95 #else 96 #error Max host controller block size can have value 512, 1024 or 2048 only! 97 #endif 98 99 #if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ 100 SDHC_CAPAB_BASECLKFREQ > 63 101 #error SDclock frequency can have value in range 0, 10-63 only! 102 #endif 103 104 #if SDHC_CAPAB_TOCLKFREQ > 63 105 #error Timeout clock frequency can have value in range 0-63 only! 106 #endif 107 108 #define SDHC_CAPAB_REG_DEFAULT \ 109 ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ 110 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ 111 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ 112 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ 113 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ 114 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ 115 (SDHC_CAPAB_TOCLKFREQ)) 116 117 #define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) 118 119 static uint8_t sdhci_slotint(SDHCIState *s) 120 { 121 return (s->norintsts & s->norintsigen) || (s->errintsts & s->errintsigen) || 122 ((s->norintsts & SDHC_NIS_INSERT) && (s->wakcon & SDHC_WKUP_ON_INS)) || 123 ((s->norintsts & SDHC_NIS_REMOVE) && (s->wakcon & SDHC_WKUP_ON_RMV)); 124 } 125 126 static inline void sdhci_update_irq(SDHCIState *s) 127 { 128 qemu_set_irq(s->irq, sdhci_slotint(s)); 129 } 130 131 static void sdhci_raise_insertion_irq(void *opaque) 132 { 133 SDHCIState *s = (SDHCIState *)opaque; 134 135 if (s->norintsts & SDHC_NIS_REMOVE) { 136 timer_mod(s->insert_timer, 137 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 138 } else { 139 s->prnsts = 0x1ff0000; 140 if (s->norintstsen & SDHC_NISEN_INSERT) { 141 s->norintsts |= SDHC_NIS_INSERT; 142 } 143 sdhci_update_irq(s); 144 } 145 } 146 147 static void sdhci_insert_eject_cb(void *opaque, int irq, int level) 148 { 149 SDHCIState *s = (SDHCIState *)opaque; 150 DPRINT_L1("Card state changed: %s!\n", level ? "insert" : "eject"); 151 152 if ((s->norintsts & SDHC_NIS_REMOVE) && level) { 153 /* Give target some time to notice card ejection */ 154 timer_mod(s->insert_timer, 155 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_INSERTION_DELAY); 156 } else { 157 if (level) { 158 s->prnsts = 0x1ff0000; 159 if (s->norintstsen & SDHC_NISEN_INSERT) { 160 s->norintsts |= SDHC_NIS_INSERT; 161 } 162 } else { 163 s->prnsts = 0x1fa0000; 164 s->pwrcon &= ~SDHC_POWER_ON; 165 s->clkcon &= ~SDHC_CLOCK_SDCLK_EN; 166 if (s->norintstsen & SDHC_NISEN_REMOVE) { 167 s->norintsts |= SDHC_NIS_REMOVE; 168 } 169 } 170 sdhci_update_irq(s); 171 } 172 } 173 174 static void sdhci_card_readonly_cb(void *opaque, int irq, int level) 175 { 176 SDHCIState *s = (SDHCIState *)opaque; 177 178 if (level) { 179 s->prnsts &= ~SDHC_WRITE_PROTECT; 180 } else { 181 /* Write enabled */ 182 s->prnsts |= SDHC_WRITE_PROTECT; 183 } 184 } 185 186 static void sdhci_reset(SDHCIState *s) 187 { 188 timer_del(s->insert_timer); 189 timer_del(s->transfer_timer); 190 /* Set all registers to 0. Capabilities registers are not cleared 191 * and assumed to always preserve their value, given to them during 192 * initialization */ 193 memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); 194 195 sd_set_cb(s->card, s->ro_cb, s->eject_cb); 196 s->data_count = 0; 197 s->stopped_state = sdhc_not_stopped; 198 } 199 200 static void sdhci_do_data_transfer(void *opaque) 201 { 202 SDHCIState *s = (SDHCIState *)opaque; 203 204 SDHCI_GET_CLASS(s)->data_transfer(s); 205 } 206 207 static void sdhci_send_command(SDHCIState *s) 208 { 209 SDRequest request; 210 uint8_t response[16]; 211 int rlen; 212 213 s->errintsts = 0; 214 s->acmd12errsts = 0; 215 request.cmd = s->cmdreg >> 8; 216 request.arg = s->argument; 217 DPRINT_L1("sending CMD%u ARG[0x%08x]\n", request.cmd, request.arg); 218 rlen = sd_do_command(s->card, &request, response); 219 220 if (s->cmdreg & SDHC_CMD_RESPONSE) { 221 if (rlen == 4) { 222 s->rspreg[0] = (response[0] << 24) | (response[1] << 16) | 223 (response[2] << 8) | response[3]; 224 s->rspreg[1] = s->rspreg[2] = s->rspreg[3] = 0; 225 DPRINT_L1("Response: RSPREG[31..0]=0x%08x\n", s->rspreg[0]); 226 } else if (rlen == 16) { 227 s->rspreg[0] = (response[11] << 24) | (response[12] << 16) | 228 (response[13] << 8) | response[14]; 229 s->rspreg[1] = (response[7] << 24) | (response[8] << 16) | 230 (response[9] << 8) | response[10]; 231 s->rspreg[2] = (response[3] << 24) | (response[4] << 16) | 232 (response[5] << 8) | response[6]; 233 s->rspreg[3] = (response[0] << 16) | (response[1] << 8) | 234 response[2]; 235 DPRINT_L1("Response received:\n RSPREG[127..96]=0x%08x, RSPREG[95.." 236 "64]=0x%08x,\n RSPREG[63..32]=0x%08x, RSPREG[31..0]=0x%08x\n", 237 s->rspreg[3], s->rspreg[2], s->rspreg[1], s->rspreg[0]); 238 } else { 239 ERRPRINT("Timeout waiting for command response\n"); 240 if (s->errintstsen & SDHC_EISEN_CMDTIMEOUT) { 241 s->errintsts |= SDHC_EIS_CMDTIMEOUT; 242 s->norintsts |= SDHC_NIS_ERR; 243 } 244 } 245 246 if ((s->norintstsen & SDHC_NISEN_TRSCMP) && 247 (s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY) { 248 s->norintsts |= SDHC_NIS_TRSCMP; 249 } 250 } else if (rlen != 0 && (s->errintstsen & SDHC_EISEN_CMDIDX)) { 251 s->errintsts |= SDHC_EIS_CMDIDX; 252 s->norintsts |= SDHC_NIS_ERR; 253 } 254 255 if (s->norintstsen & SDHC_NISEN_CMDCMP) { 256 s->norintsts |= SDHC_NIS_CMDCMP; 257 } 258 259 sdhci_update_irq(s); 260 261 if (s->blksize && (s->cmdreg & SDHC_CMD_DATA_PRESENT)) { 262 s->data_count = 0; 263 sdhci_do_data_transfer(s); 264 } 265 } 266 267 static void sdhci_end_transfer(SDHCIState *s) 268 { 269 /* Automatically send CMD12 to stop transfer if AutoCMD12 enabled */ 270 if ((s->trnmod & SDHC_TRNS_ACMD12) != 0) { 271 SDRequest request; 272 uint8_t response[16]; 273 274 request.cmd = 0x0C; 275 request.arg = 0; 276 DPRINT_L1("Automatically issue CMD%d %08x\n", request.cmd, request.arg); 277 sd_do_command(s->card, &request, response); 278 /* Auto CMD12 response goes to the upper Response register */ 279 s->rspreg[3] = (response[0] << 24) | (response[1] << 16) | 280 (response[2] << 8) | response[3]; 281 } 282 283 s->prnsts &= ~(SDHC_DOING_READ | SDHC_DOING_WRITE | 284 SDHC_DAT_LINE_ACTIVE | SDHC_DATA_INHIBIT | 285 SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE); 286 287 if (s->norintstsen & SDHC_NISEN_TRSCMP) { 288 s->norintsts |= SDHC_NIS_TRSCMP; 289 } 290 291 sdhci_update_irq(s); 292 } 293 294 /* 295 * Programmed i/o data transfer 296 */ 297 298 /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ 299 static void sdhci_read_block_from_card(SDHCIState *s) 300 { 301 int index = 0; 302 303 if ((s->trnmod & SDHC_TRNS_MULTI) && 304 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { 305 return; 306 } 307 308 for (index = 0; index < (s->blksize & 0x0fff); index++) { 309 s->fifo_buffer[index] = sd_read_data(s->card); 310 } 311 312 /* New data now available for READ through Buffer Port Register */ 313 s->prnsts |= SDHC_DATA_AVAILABLE; 314 if (s->norintstsen & SDHC_NISEN_RBUFRDY) { 315 s->norintsts |= SDHC_NIS_RBUFRDY; 316 } 317 318 /* Clear DAT line active status if that was the last block */ 319 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 320 ((s->trnmod & SDHC_TRNS_MULTI) && s->blkcnt == 1)) { 321 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 322 } 323 324 /* If stop at block gap request was set and it's not the last block of 325 * data - generate Block Event interrupt */ 326 if (s->stopped_state == sdhc_gap_read && (s->trnmod & SDHC_TRNS_MULTI) && 327 s->blkcnt != 1) { 328 s->prnsts &= ~SDHC_DAT_LINE_ACTIVE; 329 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 330 s->norintsts |= SDHC_EIS_BLKGAP; 331 } 332 } 333 334 sdhci_update_irq(s); 335 } 336 337 /* Read @size byte of data from host controller @s BUFFER DATA PORT register */ 338 static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) 339 { 340 uint32_t value = 0; 341 int i; 342 343 /* first check that a valid data exists in host controller input buffer */ 344 if ((s->prnsts & SDHC_DATA_AVAILABLE) == 0) { 345 ERRPRINT("Trying to read from empty buffer\n"); 346 return 0; 347 } 348 349 for (i = 0; i < size; i++) { 350 value |= s->fifo_buffer[s->data_count] << i * 8; 351 s->data_count++; 352 /* check if we've read all valid data (blksize bytes) from buffer */ 353 if ((s->data_count) >= (s->blksize & 0x0fff)) { 354 DPRINT_L2("All %u bytes of data have been read from input buffer\n", 355 s->data_count); 356 s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ 357 s->data_count = 0; /* next buff read must start at position [0] */ 358 359 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 360 s->blkcnt--; 361 } 362 363 /* if that was the last block of data */ 364 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 365 ((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) || 366 /* stop at gap request */ 367 (s->stopped_state == sdhc_gap_read && 368 !(s->prnsts & SDHC_DAT_LINE_ACTIVE))) { 369 SDHCI_GET_CLASS(s)->end_data_transfer(s); 370 } else { /* if there are more data, read next block from card */ 371 SDHCI_GET_CLASS(s)->read_block_from_card(s); 372 } 373 break; 374 } 375 } 376 377 return value; 378 } 379 380 /* Write data from host controller FIFO to card */ 381 static void sdhci_write_block_to_card(SDHCIState *s) 382 { 383 int index = 0; 384 385 if (s->prnsts & SDHC_SPACE_AVAILABLE) { 386 if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 387 s->norintsts |= SDHC_NIS_WBUFRDY; 388 } 389 sdhci_update_irq(s); 390 return; 391 } 392 393 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 394 if (s->blkcnt == 0) { 395 return; 396 } else { 397 s->blkcnt--; 398 } 399 } 400 401 for (index = 0; index < (s->blksize & 0x0fff); index++) { 402 sd_write_data(s->card, s->fifo_buffer[index]); 403 } 404 405 /* Next data can be written through BUFFER DATORT register */ 406 s->prnsts |= SDHC_SPACE_AVAILABLE; 407 408 /* Finish transfer if that was the last block of data */ 409 if ((s->trnmod & SDHC_TRNS_MULTI) == 0 || 410 ((s->trnmod & SDHC_TRNS_MULTI) && 411 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0))) { 412 SDHCI_GET_CLASS(s)->end_data_transfer(s); 413 } else if (s->norintstsen & SDHC_NISEN_WBUFRDY) { 414 s->norintsts |= SDHC_NIS_WBUFRDY; 415 } 416 417 /* Generate Block Gap Event if requested and if not the last block */ 418 if (s->stopped_state == sdhc_gap_write && (s->trnmod & SDHC_TRNS_MULTI) && 419 s->blkcnt > 0) { 420 s->prnsts &= ~SDHC_DOING_WRITE; 421 if (s->norintstsen & SDHC_EISEN_BLKGAP) { 422 s->norintsts |= SDHC_EIS_BLKGAP; 423 } 424 SDHCI_GET_CLASS(s)->end_data_transfer(s); 425 } 426 427 sdhci_update_irq(s); 428 } 429 430 /* Write @size bytes of @value data to host controller @s Buffer Data Port 431 * register */ 432 static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) 433 { 434 unsigned i; 435 436 /* Check that there is free space left in a buffer */ 437 if (!(s->prnsts & SDHC_SPACE_AVAILABLE)) { 438 ERRPRINT("Can't write to data buffer: buffer full\n"); 439 return; 440 } 441 442 for (i = 0; i < size; i++) { 443 s->fifo_buffer[s->data_count] = value & 0xFF; 444 s->data_count++; 445 value >>= 8; 446 if (s->data_count >= (s->blksize & 0x0fff)) { 447 DPRINT_L2("write buffer filled with %u bytes of data\n", 448 s->data_count); 449 s->data_count = 0; 450 s->prnsts &= ~SDHC_SPACE_AVAILABLE; 451 if (s->prnsts & SDHC_DOING_WRITE) { 452 SDHCI_GET_CLASS(s)->write_block_to_card(s); 453 } 454 } 455 } 456 } 457 458 /* 459 * Single DMA data transfer 460 */ 461 462 /* Multi block SDMA transfer */ 463 static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) 464 { 465 bool page_aligned = false; 466 unsigned int n, begin; 467 const uint16_t block_size = s->blksize & 0x0fff; 468 uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); 469 uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); 470 471 /* XXX: Some sd/mmc drivers (for example, u-boot-slp) do not account for 472 * possible stop at page boundary if initial address is not page aligned, 473 * allow them to work properly */ 474 if ((s->sdmasysad % boundary_chk) == 0) { 475 page_aligned = true; 476 } 477 478 if (s->trnmod & SDHC_TRNS_READ) { 479 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 480 SDHC_DAT_LINE_ACTIVE; 481 while (s->blkcnt) { 482 if (s->data_count == 0) { 483 for (n = 0; n < block_size; n++) { 484 s->fifo_buffer[n] = sd_read_data(s->card); 485 } 486 } 487 begin = s->data_count; 488 if (((boundary_count + begin) < block_size) && page_aligned) { 489 s->data_count = boundary_count + begin; 490 boundary_count = 0; 491 } else { 492 s->data_count = block_size; 493 boundary_count -= block_size - begin; 494 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 495 s->blkcnt--; 496 } 497 } 498 dma_memory_write(&address_space_memory, s->sdmasysad, 499 &s->fifo_buffer[begin], s->data_count - begin); 500 s->sdmasysad += s->data_count - begin; 501 if (s->data_count == block_size) { 502 s->data_count = 0; 503 } 504 if (page_aligned && boundary_count == 0) { 505 break; 506 } 507 } 508 } else { 509 s->prnsts |= SDHC_DOING_WRITE | SDHC_DATA_INHIBIT | 510 SDHC_DAT_LINE_ACTIVE; 511 while (s->blkcnt) { 512 begin = s->data_count; 513 if (((boundary_count + begin) < block_size) && page_aligned) { 514 s->data_count = boundary_count + begin; 515 boundary_count = 0; 516 } else { 517 s->data_count = block_size; 518 boundary_count -= block_size - begin; 519 } 520 dma_memory_read(&address_space_memory, s->sdmasysad, 521 &s->fifo_buffer[begin], s->data_count); 522 s->sdmasysad += s->data_count - begin; 523 if (s->data_count == block_size) { 524 for (n = 0; n < block_size; n++) { 525 sd_write_data(s->card, s->fifo_buffer[n]); 526 } 527 s->data_count = 0; 528 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 529 s->blkcnt--; 530 } 531 } 532 if (page_aligned && boundary_count == 0) { 533 break; 534 } 535 } 536 } 537 538 if (s->blkcnt == 0) { 539 SDHCI_GET_CLASS(s)->end_data_transfer(s); 540 } else { 541 if (s->norintstsen & SDHC_NISEN_DMA) { 542 s->norintsts |= SDHC_NIS_DMA; 543 } 544 sdhci_update_irq(s); 545 } 546 } 547 548 /* single block SDMA transfer */ 549 550 static void sdhci_sdma_transfer_single_block(SDHCIState *s) 551 { 552 int n; 553 uint32_t datacnt = s->blksize & 0x0fff; 554 555 if (s->trnmod & SDHC_TRNS_READ) { 556 for (n = 0; n < datacnt; n++) { 557 s->fifo_buffer[n] = sd_read_data(s->card); 558 } 559 dma_memory_write(&address_space_memory, s->sdmasysad, s->fifo_buffer, 560 datacnt); 561 } else { 562 dma_memory_read(&address_space_memory, s->sdmasysad, s->fifo_buffer, 563 datacnt); 564 for (n = 0; n < datacnt; n++) { 565 sd_write_data(s->card, s->fifo_buffer[n]); 566 } 567 } 568 569 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 570 s->blkcnt--; 571 } 572 573 SDHCI_GET_CLASS(s)->end_data_transfer(s); 574 } 575 576 typedef struct ADMADescr { 577 hwaddr addr; 578 uint16_t length; 579 uint8_t attr; 580 uint8_t incr; 581 } ADMADescr; 582 583 static void get_adma_description(SDHCIState *s, ADMADescr *dscr) 584 { 585 uint32_t adma1 = 0; 586 uint64_t adma2 = 0; 587 hwaddr entry_addr = (hwaddr)s->admasysaddr; 588 switch (SDHC_DMA_TYPE(s->hostctl)) { 589 case SDHC_CTRL_ADMA2_32: 590 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma2, 591 sizeof(adma2)); 592 adma2 = le64_to_cpu(adma2); 593 /* The spec does not specify endianness of descriptor table. 594 * We currently assume that it is LE. 595 */ 596 dscr->addr = (hwaddr)extract64(adma2, 32, 32) & ~0x3ull; 597 dscr->length = (uint16_t)extract64(adma2, 16, 16); 598 dscr->attr = (uint8_t)extract64(adma2, 0, 7); 599 dscr->incr = 8; 600 break; 601 case SDHC_CTRL_ADMA1_32: 602 dma_memory_read(&address_space_memory, entry_addr, (uint8_t *)&adma1, 603 sizeof(adma1)); 604 adma1 = le32_to_cpu(adma1); 605 dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); 606 dscr->attr = (uint8_t)extract32(adma1, 0, 7); 607 dscr->incr = 4; 608 if ((dscr->attr & SDHC_ADMA_ATTR_ACT_MASK) == SDHC_ADMA_ATTR_SET_LEN) { 609 dscr->length = (uint16_t)extract32(adma1, 12, 16); 610 } else { 611 dscr->length = 4096; 612 } 613 break; 614 case SDHC_CTRL_ADMA2_64: 615 dma_memory_read(&address_space_memory, entry_addr, 616 (uint8_t *)(&dscr->attr), 1); 617 dma_memory_read(&address_space_memory, entry_addr + 2, 618 (uint8_t *)(&dscr->length), 2); 619 dscr->length = le16_to_cpu(dscr->length); 620 dma_memory_read(&address_space_memory, entry_addr + 4, 621 (uint8_t *)(&dscr->addr), 8); 622 dscr->attr = le64_to_cpu(dscr->attr); 623 dscr->attr &= 0xfffffff8; 624 dscr->incr = 12; 625 break; 626 } 627 } 628 629 /* Advanced DMA data transfer */ 630 631 static void sdhci_do_adma(SDHCIState *s) 632 { 633 unsigned int n, begin, length; 634 const uint16_t block_size = s->blksize & 0x0fff; 635 ADMADescr dscr; 636 int i; 637 638 for (i = 0; i < SDHC_ADMA_DESCS_PER_DELAY; ++i) { 639 s->admaerr &= ~SDHC_ADMAERR_LENGTH_MISMATCH; 640 641 get_adma_description(s, &dscr); 642 DPRINT_L2("ADMA loop: addr=" TARGET_FMT_plx ", len=%d, attr=%x\n", 643 dscr.addr, dscr.length, dscr.attr); 644 645 if ((dscr.attr & SDHC_ADMA_ATTR_VALID) == 0) { 646 /* Indicate that error occurred in ST_FDS state */ 647 s->admaerr &= ~SDHC_ADMAERR_STATE_MASK; 648 s->admaerr |= SDHC_ADMAERR_STATE_ST_FDS; 649 650 /* Generate ADMA error interrupt */ 651 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 652 s->errintsts |= SDHC_EIS_ADMAERR; 653 s->norintsts |= SDHC_NIS_ERR; 654 } 655 656 sdhci_update_irq(s); 657 return; 658 } 659 660 length = dscr.length ? dscr.length : 65536; 661 662 switch (dscr.attr & SDHC_ADMA_ATTR_ACT_MASK) { 663 case SDHC_ADMA_ATTR_ACT_TRAN: /* data transfer */ 664 665 if (s->trnmod & SDHC_TRNS_READ) { 666 while (length) { 667 if (s->data_count == 0) { 668 for (n = 0; n < block_size; n++) { 669 s->fifo_buffer[n] = sd_read_data(s->card); 670 } 671 } 672 begin = s->data_count; 673 if ((length + begin) < block_size) { 674 s->data_count = length + begin; 675 length = 0; 676 } else { 677 s->data_count = block_size; 678 length -= block_size - begin; 679 } 680 dma_memory_write(&address_space_memory, dscr.addr, 681 &s->fifo_buffer[begin], 682 s->data_count - begin); 683 dscr.addr += s->data_count - begin; 684 if (s->data_count == block_size) { 685 s->data_count = 0; 686 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 687 s->blkcnt--; 688 if (s->blkcnt == 0) { 689 break; 690 } 691 } 692 } 693 } 694 } else { 695 while (length) { 696 begin = s->data_count; 697 if ((length + begin) < block_size) { 698 s->data_count = length + begin; 699 length = 0; 700 } else { 701 s->data_count = block_size; 702 length -= block_size - begin; 703 } 704 dma_memory_read(&address_space_memory, dscr.addr, 705 &s->fifo_buffer[begin], 706 s->data_count - begin); 707 dscr.addr += s->data_count - begin; 708 if (s->data_count == block_size) { 709 for (n = 0; n < block_size; n++) { 710 sd_write_data(s->card, s->fifo_buffer[n]); 711 } 712 s->data_count = 0; 713 if (s->trnmod & SDHC_TRNS_BLK_CNT_EN) { 714 s->blkcnt--; 715 if (s->blkcnt == 0) { 716 break; 717 } 718 } 719 } 720 } 721 } 722 s->admasysaddr += dscr.incr; 723 break; 724 case SDHC_ADMA_ATTR_ACT_LINK: /* link to next descriptor table */ 725 s->admasysaddr = dscr.addr; 726 DPRINT_L1("ADMA link: admasysaddr=0x%lx\n", s->admasysaddr); 727 break; 728 default: 729 s->admasysaddr += dscr.incr; 730 break; 731 } 732 733 if (dscr.attr & SDHC_ADMA_ATTR_INT) { 734 DPRINT_L1("ADMA interrupt: admasysaddr=0x%lx\n", s->admasysaddr); 735 if (s->norintstsen & SDHC_NISEN_DMA) { 736 s->norintsts |= SDHC_NIS_DMA; 737 } 738 739 sdhci_update_irq(s); 740 } 741 742 /* ADMA transfer terminates if blkcnt == 0 or by END attribute */ 743 if (((s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 744 (s->blkcnt == 0)) || (dscr.attr & SDHC_ADMA_ATTR_END)) { 745 DPRINT_L2("ADMA transfer completed\n"); 746 if (length || ((dscr.attr & SDHC_ADMA_ATTR_END) && 747 (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && 748 s->blkcnt != 0)) { 749 ERRPRINT("SD/MMC host ADMA length mismatch\n"); 750 s->admaerr |= SDHC_ADMAERR_LENGTH_MISMATCH | 751 SDHC_ADMAERR_STATE_ST_TFR; 752 if (s->errintstsen & SDHC_EISEN_ADMAERR) { 753 ERRPRINT("Set ADMA error flag\n"); 754 s->errintsts |= SDHC_EIS_ADMAERR; 755 s->norintsts |= SDHC_NIS_ERR; 756 } 757 758 sdhci_update_irq(s); 759 } 760 SDHCI_GET_CLASS(s)->end_data_transfer(s); 761 return; 762 } 763 764 } 765 766 /* we have unfinished business - reschedule to continue ADMA */ 767 timer_mod(s->transfer_timer, 768 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + SDHC_TRANSFER_DELAY); 769 } 770 771 /* Perform data transfer according to controller configuration */ 772 773 static void sdhci_data_transfer(SDHCIState *s) 774 { 775 SDHCIClass *k = SDHCI_GET_CLASS(s); 776 777 if (s->trnmod & SDHC_TRNS_DMA) { 778 switch (SDHC_DMA_TYPE(s->hostctl)) { 779 case SDHC_CTRL_SDMA: 780 if ((s->trnmod & SDHC_TRNS_MULTI) && 781 (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || s->blkcnt == 0)) { 782 break; 783 } 784 785 if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { 786 k->do_sdma_single(s); 787 } else { 788 k->do_sdma_multi(s); 789 } 790 791 break; 792 case SDHC_CTRL_ADMA1_32: 793 if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { 794 ERRPRINT("ADMA1 not supported\n"); 795 break; 796 } 797 798 k->do_adma(s); 799 break; 800 case SDHC_CTRL_ADMA2_32: 801 if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { 802 ERRPRINT("ADMA2 not supported\n"); 803 break; 804 } 805 806 k->do_adma(s); 807 break; 808 case SDHC_CTRL_ADMA2_64: 809 if (!(s->capareg & SDHC_CAN_DO_ADMA2) || 810 !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { 811 ERRPRINT("64 bit ADMA not supported\n"); 812 break; 813 } 814 815 k->do_adma(s); 816 break; 817 default: 818 ERRPRINT("Unsupported DMA type\n"); 819 break; 820 } 821 } else { 822 if ((s->trnmod & SDHC_TRNS_READ) && sd_data_ready(s->card)) { 823 s->prnsts |= SDHC_DOING_READ | SDHC_DATA_INHIBIT | 824 SDHC_DAT_LINE_ACTIVE; 825 SDHCI_GET_CLASS(s)->read_block_from_card(s); 826 } else { 827 s->prnsts |= SDHC_DOING_WRITE | SDHC_DAT_LINE_ACTIVE | 828 SDHC_SPACE_AVAILABLE | SDHC_DATA_INHIBIT; 829 SDHCI_GET_CLASS(s)->write_block_to_card(s); 830 } 831 } 832 } 833 834 static bool sdhci_can_issue_command(SDHCIState *s) 835 { 836 if (!SDHC_CLOCK_IS_ON(s->clkcon) || !(s->pwrcon & SDHC_POWER_ON) || 837 (((s->prnsts & SDHC_DATA_INHIBIT) || s->stopped_state) && 838 ((s->cmdreg & SDHC_CMD_DATA_PRESENT) || 839 ((s->cmdreg & SDHC_CMD_RESPONSE) == SDHC_CMD_RSP_WITH_BUSY && 840 !(SDHC_COMMAND_TYPE(s->cmdreg) == SDHC_CMD_ABORT))))) { 841 return false; 842 } 843 844 return true; 845 } 846 847 /* The Buffer Data Port register must be accessed in sequential and 848 * continuous manner */ 849 static inline bool 850 sdhci_buff_access_is_sequential(SDHCIState *s, unsigned byte_num) 851 { 852 if ((s->data_count & 0x3) != byte_num) { 853 ERRPRINT("Non-sequential access to Buffer Data Port register" 854 "is prohibited\n"); 855 return false; 856 } 857 return true; 858 } 859 860 static uint32_t sdhci_read(SDHCIState *s, unsigned int offset, unsigned size) 861 { 862 uint32_t ret = 0; 863 864 switch (offset & ~0x3) { 865 case SDHC_SYSAD: 866 ret = s->sdmasysad; 867 break; 868 case SDHC_BLKSIZE: 869 ret = s->blksize | (s->blkcnt << 16); 870 break; 871 case SDHC_ARGUMENT: 872 ret = s->argument; 873 break; 874 case SDHC_TRNMOD: 875 ret = s->trnmod | (s->cmdreg << 16); 876 break; 877 case SDHC_RSPREG0 ... SDHC_RSPREG3: 878 ret = s->rspreg[((offset & ~0x3) - SDHC_RSPREG0) >> 2]; 879 break; 880 case SDHC_BDATA: 881 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 882 ret = SDHCI_GET_CLASS(s)->bdata_read(s, size); 883 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset, 884 ret, ret); 885 return ret; 886 } 887 break; 888 case SDHC_PRNSTS: 889 ret = s->prnsts; 890 break; 891 case SDHC_HOSTCTL: 892 ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | 893 (s->wakcon << 24); 894 break; 895 case SDHC_CLKCON: 896 ret = s->clkcon | (s->timeoutcon << 16); 897 break; 898 case SDHC_NORINTSTS: 899 ret = s->norintsts | (s->errintsts << 16); 900 break; 901 case SDHC_NORINTSTSEN: 902 ret = s->norintstsen | (s->errintstsen << 16); 903 break; 904 case SDHC_NORINTSIGEN: 905 ret = s->norintsigen | (s->errintsigen << 16); 906 break; 907 case SDHC_ACMD12ERRSTS: 908 ret = s->acmd12errsts; 909 break; 910 case SDHC_CAPAREG: 911 ret = s->capareg; 912 break; 913 case SDHC_MAXCURR: 914 ret = s->maxcurr; 915 break; 916 case SDHC_ADMAERR: 917 ret = s->admaerr; 918 break; 919 case SDHC_ADMASYSADDR: 920 ret = (uint32_t)s->admasysaddr; 921 break; 922 case SDHC_ADMASYSADDR + 4: 923 ret = (uint32_t)(s->admasysaddr >> 32); 924 break; 925 case SDHC_SLOT_INT_STATUS: 926 ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); 927 break; 928 default: 929 ERRPRINT("bad %ub read: addr[0x%04x]\n", size, offset); 930 break; 931 } 932 933 ret >>= (offset & 0x3) * 8; 934 ret &= (1ULL << (size * 8)) - 1; 935 DPRINT_L2("read %ub: addr[0x%04x] -> %u(0x%x)\n", size, offset, ret, ret); 936 return ret; 937 } 938 939 static inline void sdhci_blkgap_write(SDHCIState *s, uint8_t value) 940 { 941 if ((value & SDHC_STOP_AT_GAP_REQ) && (s->blkgap & SDHC_STOP_AT_GAP_REQ)) { 942 return; 943 } 944 s->blkgap = value & SDHC_STOP_AT_GAP_REQ; 945 946 if ((value & SDHC_CONTINUE_REQ) && s->stopped_state && 947 (s->blkgap & SDHC_STOP_AT_GAP_REQ) == 0) { 948 if (s->stopped_state == sdhc_gap_read) { 949 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ; 950 SDHCI_GET_CLASS(s)->read_block_from_card(s); 951 } else { 952 s->prnsts |= SDHC_DAT_LINE_ACTIVE | SDHC_DOING_WRITE; 953 SDHCI_GET_CLASS(s)->write_block_to_card(s); 954 } 955 s->stopped_state = sdhc_not_stopped; 956 } else if (!s->stopped_state && (value & SDHC_STOP_AT_GAP_REQ)) { 957 if (s->prnsts & SDHC_DOING_READ) { 958 s->stopped_state = sdhc_gap_read; 959 } else if (s->prnsts & SDHC_DOING_WRITE) { 960 s->stopped_state = sdhc_gap_write; 961 } 962 } 963 } 964 965 static inline void sdhci_reset_write(SDHCIState *s, uint8_t value) 966 { 967 switch (value) { 968 case SDHC_RESET_ALL: 969 DEVICE_GET_CLASS(s)->reset(DEVICE(s)); 970 break; 971 case SDHC_RESET_CMD: 972 s->prnsts &= ~SDHC_CMD_INHIBIT; 973 s->norintsts &= ~SDHC_NIS_CMDCMP; 974 break; 975 case SDHC_RESET_DATA: 976 s->data_count = 0; 977 s->prnsts &= ~(SDHC_SPACE_AVAILABLE | SDHC_DATA_AVAILABLE | 978 SDHC_DOING_READ | SDHC_DOING_WRITE | 979 SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE); 980 s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ); 981 s->stopped_state = sdhc_not_stopped; 982 s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY | 983 SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP); 984 break; 985 } 986 } 987 988 static void 989 sdhci_write(SDHCIState *s, unsigned int offset, uint32_t value, unsigned size) 990 { 991 unsigned shift = 8 * (offset & 0x3); 992 uint32_t mask = ~(((1ULL << (size * 8)) - 1) << shift); 993 value <<= shift; 994 995 switch (offset & ~0x3) { 996 case SDHC_SYSAD: 997 s->sdmasysad = (s->sdmasysad & mask) | value; 998 MASKED_WRITE(s->sdmasysad, mask, value); 999 /* Writing to last byte of sdmasysad might trigger transfer */ 1000 if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && 1001 s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { 1002 SDHCI_GET_CLASS(s)->do_sdma_multi(s); 1003 } 1004 break; 1005 case SDHC_BLKSIZE: 1006 if (!TRANSFERRING_DATA(s->prnsts)) { 1007 MASKED_WRITE(s->blksize, mask, value); 1008 MASKED_WRITE(s->blkcnt, mask >> 16, value >> 16); 1009 } 1010 break; 1011 case SDHC_ARGUMENT: 1012 MASKED_WRITE(s->argument, mask, value); 1013 break; 1014 case SDHC_TRNMOD: 1015 /* DMA can be enabled only if it is supported as indicated by 1016 * capabilities register */ 1017 if (!(s->capareg & SDHC_CAN_DO_DMA)) { 1018 value &= ~SDHC_TRNS_DMA; 1019 } 1020 MASKED_WRITE(s->trnmod, mask, value); 1021 MASKED_WRITE(s->cmdreg, mask >> 16, value >> 16); 1022 1023 /* Writing to the upper byte of CMDREG triggers SD command generation */ 1024 if ((mask & 0xFF000000) || !SDHCI_GET_CLASS(s)->can_issue_command(s)) { 1025 break; 1026 } 1027 1028 SDHCI_GET_CLASS(s)->send_command(s); 1029 break; 1030 case SDHC_BDATA: 1031 if (sdhci_buff_access_is_sequential(s, offset - SDHC_BDATA)) { 1032 SDHCI_GET_CLASS(s)->bdata_write(s, value >> shift, size); 1033 } 1034 break; 1035 case SDHC_HOSTCTL: 1036 if (!(mask & 0xFF0000)) { 1037 sdhci_blkgap_write(s, value >> 16); 1038 } 1039 MASKED_WRITE(s->hostctl, mask, value); 1040 MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); 1041 MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); 1042 if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || 1043 !(s->capareg & (1 << (31 - ((s->pwrcon >> 1) & 0x7))))) { 1044 s->pwrcon &= ~SDHC_POWER_ON; 1045 } 1046 break; 1047 case SDHC_CLKCON: 1048 if (!(mask & 0xFF000000)) { 1049 sdhci_reset_write(s, value >> 24); 1050 } 1051 MASKED_WRITE(s->clkcon, mask, value); 1052 MASKED_WRITE(s->timeoutcon, mask >> 16, value >> 16); 1053 if (s->clkcon & SDHC_CLOCK_INT_EN) { 1054 s->clkcon |= SDHC_CLOCK_INT_STABLE; 1055 } else { 1056 s->clkcon &= ~SDHC_CLOCK_INT_STABLE; 1057 } 1058 break; 1059 case SDHC_NORINTSTS: 1060 if (s->norintstsen & SDHC_NISEN_CARDINT) { 1061 value &= ~SDHC_NIS_CARDINT; 1062 } 1063 s->norintsts &= mask | ~value; 1064 s->errintsts &= (mask >> 16) | ~(value >> 16); 1065 if (s->errintsts) { 1066 s->norintsts |= SDHC_NIS_ERR; 1067 } else { 1068 s->norintsts &= ~SDHC_NIS_ERR; 1069 } 1070 sdhci_update_irq(s); 1071 break; 1072 case SDHC_NORINTSTSEN: 1073 MASKED_WRITE(s->norintstsen, mask, value); 1074 MASKED_WRITE(s->errintstsen, mask >> 16, value >> 16); 1075 s->norintsts &= s->norintstsen; 1076 s->errintsts &= s->errintstsen; 1077 if (s->errintsts) { 1078 s->norintsts |= SDHC_NIS_ERR; 1079 } else { 1080 s->norintsts &= ~SDHC_NIS_ERR; 1081 } 1082 sdhci_update_irq(s); 1083 break; 1084 case SDHC_NORINTSIGEN: 1085 MASKED_WRITE(s->norintsigen, mask, value); 1086 MASKED_WRITE(s->errintsigen, mask >> 16, value >> 16); 1087 sdhci_update_irq(s); 1088 break; 1089 case SDHC_ADMAERR: 1090 MASKED_WRITE(s->admaerr, mask, value); 1091 break; 1092 case SDHC_ADMASYSADDR: 1093 s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL | 1094 (uint64_t)mask)) | (uint64_t)value; 1095 break; 1096 case SDHC_ADMASYSADDR + 4: 1097 s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL | 1098 ((uint64_t)mask << 32))) | ((uint64_t)value << 32); 1099 break; 1100 case SDHC_FEAER: 1101 s->acmd12errsts |= value; 1102 s->errintsts |= (value >> 16) & s->errintstsen; 1103 if (s->acmd12errsts) { 1104 s->errintsts |= SDHC_EIS_CMD12ERR; 1105 } 1106 if (s->errintsts) { 1107 s->norintsts |= SDHC_NIS_ERR; 1108 } 1109 sdhci_update_irq(s); 1110 break; 1111 default: 1112 ERRPRINT("bad %ub write offset: addr[0x%04x] <- %u(0x%x)\n", 1113 size, offset, value >> shift, value >> shift); 1114 break; 1115 } 1116 DPRINT_L2("write %ub: addr[0x%04x] <- %u(0x%x)\n", 1117 size, offset, value >> shift, value >> shift); 1118 } 1119 1120 static uint64_t 1121 sdhci_readfn(void *opaque, hwaddr offset, unsigned size) 1122 { 1123 SDHCIState *s = (SDHCIState *)opaque; 1124 1125 return SDHCI_GET_CLASS(s)->mem_read(s, offset, size); 1126 } 1127 1128 static void 1129 sdhci_writefn(void *opaque, hwaddr off, uint64_t val, unsigned sz) 1130 { 1131 SDHCIState *s = (SDHCIState *)opaque; 1132 1133 SDHCI_GET_CLASS(s)->mem_write(s, off, val, sz); 1134 } 1135 1136 static const MemoryRegionOps sdhci_mmio_ops = { 1137 .read = sdhci_readfn, 1138 .write = sdhci_writefn, 1139 .valid = { 1140 .min_access_size = 1, 1141 .max_access_size = 4, 1142 .unaligned = false 1143 }, 1144 .endianness = DEVICE_LITTLE_ENDIAN, 1145 }; 1146 1147 static inline unsigned int sdhci_get_fifolen(SDHCIState *s) 1148 { 1149 switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { 1150 case 0: 1151 return 512; 1152 case 1: 1153 return 1024; 1154 case 2: 1155 return 2048; 1156 default: 1157 hw_error("SDHC: unsupported value for maximum block size\n"); 1158 return 0; 1159 } 1160 } 1161 1162 static void sdhci_initfn(Object *obj) 1163 { 1164 SDHCIState *s = SDHCI(obj); 1165 DriveInfo *di; 1166 1167 di = drive_get_next(IF_SD); 1168 s->card = sd_init(di ? di->bdrv : NULL, false); 1169 if (s->card == NULL) { 1170 exit(1); 1171 } 1172 s->eject_cb = qemu_allocate_irq(sdhci_insert_eject_cb, s, 0); 1173 s->ro_cb = qemu_allocate_irq(sdhci_card_readonly_cb, s, 0); 1174 sd_set_cb(s->card, s->ro_cb, s->eject_cb); 1175 1176 s->insert_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_raise_insertion_irq, s); 1177 s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, sdhci_do_data_transfer, s); 1178 } 1179 1180 static void sdhci_uninitfn(Object *obj) 1181 { 1182 SDHCIState *s = SDHCI(obj); 1183 1184 timer_del(s->insert_timer); 1185 timer_free(s->insert_timer); 1186 timer_del(s->transfer_timer); 1187 timer_free(s->transfer_timer); 1188 qemu_free_irq(s->eject_cb); 1189 qemu_free_irq(s->ro_cb); 1190 1191 if (s->fifo_buffer) { 1192 g_free(s->fifo_buffer); 1193 s->fifo_buffer = NULL; 1194 } 1195 } 1196 1197 const VMStateDescription sdhci_vmstate = { 1198 .name = "sdhci", 1199 .version_id = 1, 1200 .minimum_version_id = 1, 1201 .fields = (VMStateField[]) { 1202 VMSTATE_UINT32(sdmasysad, SDHCIState), 1203 VMSTATE_UINT16(blksize, SDHCIState), 1204 VMSTATE_UINT16(blkcnt, SDHCIState), 1205 VMSTATE_UINT32(argument, SDHCIState), 1206 VMSTATE_UINT16(trnmod, SDHCIState), 1207 VMSTATE_UINT16(cmdreg, SDHCIState), 1208 VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), 1209 VMSTATE_UINT32(prnsts, SDHCIState), 1210 VMSTATE_UINT8(hostctl, SDHCIState), 1211 VMSTATE_UINT8(pwrcon, SDHCIState), 1212 VMSTATE_UINT8(blkgap, SDHCIState), 1213 VMSTATE_UINT8(wakcon, SDHCIState), 1214 VMSTATE_UINT16(clkcon, SDHCIState), 1215 VMSTATE_UINT8(timeoutcon, SDHCIState), 1216 VMSTATE_UINT8(admaerr, SDHCIState), 1217 VMSTATE_UINT16(norintsts, SDHCIState), 1218 VMSTATE_UINT16(errintsts, SDHCIState), 1219 VMSTATE_UINT16(norintstsen, SDHCIState), 1220 VMSTATE_UINT16(errintstsen, SDHCIState), 1221 VMSTATE_UINT16(norintsigen, SDHCIState), 1222 VMSTATE_UINT16(errintsigen, SDHCIState), 1223 VMSTATE_UINT16(acmd12errsts, SDHCIState), 1224 VMSTATE_UINT16(data_count, SDHCIState), 1225 VMSTATE_UINT64(admasysaddr, SDHCIState), 1226 VMSTATE_UINT8(stopped_state, SDHCIState), 1227 VMSTATE_VBUFFER_UINT32(fifo_buffer, SDHCIState, 1, NULL, 0, buf_maxsz), 1228 VMSTATE_TIMER(insert_timer, SDHCIState), 1229 VMSTATE_TIMER(transfer_timer, SDHCIState), 1230 VMSTATE_END_OF_LIST() 1231 } 1232 }; 1233 1234 /* Capabilities registers provide information on supported features of this 1235 * specific host controller implementation */ 1236 static Property sdhci_properties[] = { 1237 DEFINE_PROP_UINT32("capareg", SDHCIState, capareg, 1238 SDHC_CAPAB_REG_DEFAULT), 1239 DEFINE_PROP_UINT32("maxcurr", SDHCIState, maxcurr, 0), 1240 DEFINE_PROP_END_OF_LIST(), 1241 }; 1242 1243 static void sdhci_realize(DeviceState *dev, Error ** errp) 1244 { 1245 SDHCIState *s = SDHCI(dev); 1246 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1247 1248 s->buf_maxsz = sdhci_get_fifolen(s); 1249 s->fifo_buffer = g_malloc0(s->buf_maxsz); 1250 sysbus_init_irq(sbd, &s->irq); 1251 memory_region_init_io(&s->iomem, OBJECT(s), &sdhci_mmio_ops, s, "sdhci", 1252 SDHC_REGISTERS_MAP_SIZE); 1253 sysbus_init_mmio(sbd, &s->iomem); 1254 } 1255 1256 static void sdhci_generic_reset(DeviceState *ds) 1257 { 1258 SDHCIState *s = SDHCI(ds); 1259 SDHCI_GET_CLASS(s)->reset(s); 1260 } 1261 1262 static void sdhci_class_init(ObjectClass *klass, void *data) 1263 { 1264 DeviceClass *dc = DEVICE_CLASS(klass); 1265 SDHCIClass *k = SDHCI_CLASS(klass); 1266 1267 dc->vmsd = &sdhci_vmstate; 1268 dc->props = sdhci_properties; 1269 dc->reset = sdhci_generic_reset; 1270 dc->realize = sdhci_realize; 1271 1272 k->reset = sdhci_reset; 1273 k->mem_read = sdhci_read; 1274 k->mem_write = sdhci_write; 1275 k->send_command = sdhci_send_command; 1276 k->can_issue_command = sdhci_can_issue_command; 1277 k->data_transfer = sdhci_data_transfer; 1278 k->end_data_transfer = sdhci_end_transfer; 1279 k->do_sdma_single = sdhci_sdma_transfer_single_block; 1280 k->do_sdma_multi = sdhci_sdma_transfer_multi_blocks; 1281 k->do_adma = sdhci_do_adma; 1282 k->read_block_from_card = sdhci_read_block_from_card; 1283 k->write_block_to_card = sdhci_write_block_to_card; 1284 k->bdata_read = sdhci_read_dataport; 1285 k->bdata_write = sdhci_write_dataport; 1286 } 1287 1288 static const TypeInfo sdhci_type_info = { 1289 .name = TYPE_SDHCI, 1290 .parent = TYPE_SYS_BUS_DEVICE, 1291 .instance_size = sizeof(SDHCIState), 1292 .instance_init = sdhci_initfn, 1293 .instance_finalize = sdhci_uninitfn, 1294 .class_init = sdhci_class_init, 1295 .class_size = sizeof(SDHCIClass) 1296 }; 1297 1298 static void sdhci_register_types(void) 1299 { 1300 type_register_static(&sdhci_type_info); 1301 } 1302 1303 type_init(sdhci_register_types) 1304