1 /* 2 * SMBIOS Support 3 * 4 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P. 5 * Copyright (C) 2013 Red Hat, Inc. 6 * 7 * Authors: 8 * Alex Williamson <alex.williamson@hp.com> 9 * Markus Armbruster <armbru@redhat.com> 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2. See 12 * the COPYING file in the top-level directory. 13 * 14 * Contributions after 2012-01-13 are licensed under the terms of the 15 * GNU GPL, version 2 or (at your option) any later version. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/units.h" 20 #include "qapi/error.h" 21 #include "qemu/config-file.h" 22 #include "qemu/module.h" 23 #include "qemu/option.h" 24 #include "sysemu/sysemu.h" 25 #include "qemu/uuid.h" 26 #include "hw/firmware/smbios.h" 27 #include "hw/loader.h" 28 #include "hw/boards.h" 29 #include "hw/pci/pci_bus.h" 30 #include "hw/pci/pci_device.h" 31 #include "smbios_build.h" 32 33 static bool smbios_uuid_encoded = true; 34 /* 35 * SMBIOS tables provided by user with '-smbios file=<foo>' option 36 */ 37 uint8_t *usr_blobs; 38 size_t usr_blobs_len; 39 static unsigned usr_table_max; 40 static unsigned usr_table_cnt; 41 42 uint8_t *smbios_tables; 43 size_t smbios_tables_len; 44 unsigned smbios_table_max; 45 unsigned smbios_table_cnt; 46 47 static SmbiosEntryPoint ep; 48 49 static int smbios_type4_count = 0; 50 static bool smbios_have_defaults; 51 static uint32_t smbios_cpuid_version, smbios_cpuid_features; 52 53 DECLARE_BITMAP(smbios_have_binfile_bitmap, SMBIOS_MAX_TYPE + 1); 54 DECLARE_BITMAP(smbios_have_fields_bitmap, SMBIOS_MAX_TYPE + 1); 55 56 smbios_type0_t smbios_type0; 57 smbios_type1_t smbios_type1; 58 59 static struct { 60 const char *manufacturer, *product, *version, *serial, *asset, *location; 61 } type2; 62 63 static struct { 64 const char *manufacturer, *version, *serial, *asset, *sku; 65 } type3; 66 67 /* 68 * SVVP requires max_speed and current_speed to be set and not being 69 * 0 which counts as unknown (SMBIOS 3.1.0/Table 21). Set the 70 * default value to 2000MHz as we did before. 71 */ 72 #define DEFAULT_CPU_SPEED 2000 73 74 static struct { 75 uint16_t processor_family; 76 const char *sock_pfx, *manufacturer, *version, *serial, *asset, *part; 77 uint64_t max_speed; 78 uint64_t current_speed; 79 uint64_t processor_id; 80 } type4 = { 81 .max_speed = DEFAULT_CPU_SPEED, 82 .current_speed = DEFAULT_CPU_SPEED, 83 .processor_id = 0, 84 .processor_family = 0x01, /* Other */ 85 }; 86 87 struct type8_instance { 88 const char *internal_reference, *external_reference; 89 uint8_t connector_type, port_type; 90 QTAILQ_ENTRY(type8_instance) next; 91 }; 92 static QTAILQ_HEAD(, type8_instance) type8 = QTAILQ_HEAD_INITIALIZER(type8); 93 94 /* type 9 instance for parsing */ 95 struct type9_instance { 96 const char *slot_designation, *pcidev; 97 uint8_t slot_type, slot_data_bus_width, current_usage, slot_length, 98 slot_characteristics1, slot_characteristics2; 99 uint16_t slot_id; 100 QTAILQ_ENTRY(type9_instance) next; 101 }; 102 static QTAILQ_HEAD(, type9_instance) type9 = QTAILQ_HEAD_INITIALIZER(type9); 103 104 static struct { 105 size_t nvalues; 106 char **values; 107 } type11; 108 109 static struct { 110 const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part; 111 uint16_t speed; 112 } type17; 113 114 static QEnumLookup type41_kind_lookup = { 115 .array = (const char *const[]) { 116 "other", 117 "unknown", 118 "video", 119 "scsi", 120 "ethernet", 121 "tokenring", 122 "sound", 123 "pata", 124 "sata", 125 "sas", 126 }, 127 .size = 10 128 }; 129 struct type41_instance { 130 const char *designation, *pcidev; 131 uint8_t instance, kind; 132 QTAILQ_ENTRY(type41_instance) next; 133 }; 134 static QTAILQ_HEAD(, type41_instance) type41 = QTAILQ_HEAD_INITIALIZER(type41); 135 136 static QemuOptsList qemu_smbios_opts = { 137 .name = "smbios", 138 .head = QTAILQ_HEAD_INITIALIZER(qemu_smbios_opts.head), 139 .desc = { 140 /* 141 * no elements => accept any params 142 * validation will happen later 143 */ 144 { /* end of list */ } 145 } 146 }; 147 148 static const QemuOptDesc qemu_smbios_file_opts[] = { 149 { 150 .name = "file", 151 .type = QEMU_OPT_STRING, 152 .help = "binary file containing an SMBIOS element", 153 }, 154 { /* end of list */ } 155 }; 156 157 static const QemuOptDesc qemu_smbios_type0_opts[] = { 158 { 159 .name = "type", 160 .type = QEMU_OPT_NUMBER, 161 .help = "SMBIOS element type", 162 },{ 163 .name = "vendor", 164 .type = QEMU_OPT_STRING, 165 .help = "vendor name", 166 },{ 167 .name = "version", 168 .type = QEMU_OPT_STRING, 169 .help = "version number", 170 },{ 171 .name = "date", 172 .type = QEMU_OPT_STRING, 173 .help = "release date", 174 },{ 175 .name = "release", 176 .type = QEMU_OPT_STRING, 177 .help = "revision number", 178 },{ 179 .name = "uefi", 180 .type = QEMU_OPT_BOOL, 181 .help = "uefi support", 182 }, 183 { /* end of list */ } 184 }; 185 186 static const QemuOptDesc qemu_smbios_type1_opts[] = { 187 { 188 .name = "type", 189 .type = QEMU_OPT_NUMBER, 190 .help = "SMBIOS element type", 191 },{ 192 .name = "manufacturer", 193 .type = QEMU_OPT_STRING, 194 .help = "manufacturer name", 195 },{ 196 .name = "product", 197 .type = QEMU_OPT_STRING, 198 .help = "product name", 199 },{ 200 .name = "version", 201 .type = QEMU_OPT_STRING, 202 .help = "version number", 203 },{ 204 .name = "serial", 205 .type = QEMU_OPT_STRING, 206 .help = "serial number", 207 },{ 208 .name = "uuid", 209 .type = QEMU_OPT_STRING, 210 .help = "UUID", 211 },{ 212 .name = "sku", 213 .type = QEMU_OPT_STRING, 214 .help = "SKU number", 215 },{ 216 .name = "family", 217 .type = QEMU_OPT_STRING, 218 .help = "family name", 219 }, 220 { /* end of list */ } 221 }; 222 223 static const QemuOptDesc qemu_smbios_type2_opts[] = { 224 { 225 .name = "type", 226 .type = QEMU_OPT_NUMBER, 227 .help = "SMBIOS element type", 228 },{ 229 .name = "manufacturer", 230 .type = QEMU_OPT_STRING, 231 .help = "manufacturer name", 232 },{ 233 .name = "product", 234 .type = QEMU_OPT_STRING, 235 .help = "product name", 236 },{ 237 .name = "version", 238 .type = QEMU_OPT_STRING, 239 .help = "version number", 240 },{ 241 .name = "serial", 242 .type = QEMU_OPT_STRING, 243 .help = "serial number", 244 },{ 245 .name = "asset", 246 .type = QEMU_OPT_STRING, 247 .help = "asset tag number", 248 },{ 249 .name = "location", 250 .type = QEMU_OPT_STRING, 251 .help = "location in chassis", 252 }, 253 { /* end of list */ } 254 }; 255 256 static const QemuOptDesc qemu_smbios_type3_opts[] = { 257 { 258 .name = "type", 259 .type = QEMU_OPT_NUMBER, 260 .help = "SMBIOS element type", 261 },{ 262 .name = "manufacturer", 263 .type = QEMU_OPT_STRING, 264 .help = "manufacturer name", 265 },{ 266 .name = "version", 267 .type = QEMU_OPT_STRING, 268 .help = "version number", 269 },{ 270 .name = "serial", 271 .type = QEMU_OPT_STRING, 272 .help = "serial number", 273 },{ 274 .name = "asset", 275 .type = QEMU_OPT_STRING, 276 .help = "asset tag number", 277 },{ 278 .name = "sku", 279 .type = QEMU_OPT_STRING, 280 .help = "SKU number", 281 }, 282 { /* end of list */ } 283 }; 284 285 static const QemuOptDesc qemu_smbios_type4_opts[] = { 286 { 287 .name = "type", 288 .type = QEMU_OPT_NUMBER, 289 .help = "SMBIOS element type", 290 },{ 291 .name = "sock_pfx", 292 .type = QEMU_OPT_STRING, 293 .help = "socket designation string prefix", 294 },{ 295 .name = "manufacturer", 296 .type = QEMU_OPT_STRING, 297 .help = "manufacturer name", 298 },{ 299 .name = "version", 300 .type = QEMU_OPT_STRING, 301 .help = "version number", 302 },{ 303 .name = "max-speed", 304 .type = QEMU_OPT_NUMBER, 305 .help = "max speed in MHz", 306 },{ 307 .name = "current-speed", 308 .type = QEMU_OPT_NUMBER, 309 .help = "speed at system boot in MHz", 310 },{ 311 .name = "serial", 312 .type = QEMU_OPT_STRING, 313 .help = "serial number", 314 },{ 315 .name = "asset", 316 .type = QEMU_OPT_STRING, 317 .help = "asset tag number", 318 },{ 319 .name = "part", 320 .type = QEMU_OPT_STRING, 321 .help = "part number", 322 }, { 323 .name = "processor-family", 324 .type = QEMU_OPT_NUMBER, 325 .help = "processor family", 326 }, { 327 .name = "processor-id", 328 .type = QEMU_OPT_NUMBER, 329 .help = "processor id", 330 }, 331 { /* end of list */ } 332 }; 333 334 static const QemuOptDesc qemu_smbios_type8_opts[] = { 335 { 336 .name = "type", 337 .type = QEMU_OPT_NUMBER, 338 .help = "SMBIOS element type", 339 }, 340 { 341 .name = "internal_reference", 342 .type = QEMU_OPT_STRING, 343 .help = "internal reference designator", 344 }, 345 { 346 .name = "external_reference", 347 .type = QEMU_OPT_STRING, 348 .help = "external reference designator", 349 }, 350 { 351 .name = "connector_type", 352 .type = QEMU_OPT_NUMBER, 353 .help = "connector type", 354 }, 355 { 356 .name = "port_type", 357 .type = QEMU_OPT_NUMBER, 358 .help = "port type", 359 }, 360 { /* end of list */ } 361 }; 362 363 static const QemuOptDesc qemu_smbios_type9_opts[] = { 364 { 365 .name = "type", 366 .type = QEMU_OPT_NUMBER, 367 .help = "SMBIOS element type", 368 }, 369 { 370 .name = "slot_designation", 371 .type = QEMU_OPT_STRING, 372 .help = "string number for reference designation", 373 }, 374 { 375 .name = "slot_type", 376 .type = QEMU_OPT_NUMBER, 377 .help = "connector type", 378 }, 379 { 380 .name = "slot_data_bus_width", 381 .type = QEMU_OPT_NUMBER, 382 .help = "port type", 383 }, 384 { 385 .name = "current_usage", 386 .type = QEMU_OPT_NUMBER, 387 .help = "current usage", 388 }, 389 { 390 .name = "slot_length", 391 .type = QEMU_OPT_NUMBER, 392 .help = "system slot length", 393 }, 394 { 395 .name = "slot_id", 396 .type = QEMU_OPT_NUMBER, 397 .help = "system slot id", 398 }, 399 { 400 .name = "slot_characteristics1", 401 .type = QEMU_OPT_NUMBER, 402 .help = "slot characteristics1, see the spec", 403 }, 404 { 405 .name = "slot_characteristics2", 406 .type = QEMU_OPT_NUMBER, 407 .help = "slot characteristics2, see the spec", 408 }, 409 { 410 .name = "pci_device", 411 .type = QEMU_OPT_STRING, 412 .help = "PCI device, if provided." 413 } 414 }; 415 416 static const QemuOptDesc qemu_smbios_type11_opts[] = { 417 { 418 .name = "type", 419 .type = QEMU_OPT_NUMBER, 420 .help = "SMBIOS element type", 421 }, 422 { 423 .name = "value", 424 .type = QEMU_OPT_STRING, 425 .help = "OEM string data", 426 }, 427 { 428 .name = "path", 429 .type = QEMU_OPT_STRING, 430 .help = "OEM string data from file", 431 }, 432 { /* end of list */ } 433 }; 434 435 static const QemuOptDesc qemu_smbios_type17_opts[] = { 436 { 437 .name = "type", 438 .type = QEMU_OPT_NUMBER, 439 .help = "SMBIOS element type", 440 },{ 441 .name = "loc_pfx", 442 .type = QEMU_OPT_STRING, 443 .help = "device locator string prefix", 444 },{ 445 .name = "bank", 446 .type = QEMU_OPT_STRING, 447 .help = "bank locator string", 448 },{ 449 .name = "manufacturer", 450 .type = QEMU_OPT_STRING, 451 .help = "manufacturer name", 452 },{ 453 .name = "serial", 454 .type = QEMU_OPT_STRING, 455 .help = "serial number", 456 },{ 457 .name = "asset", 458 .type = QEMU_OPT_STRING, 459 .help = "asset tag number", 460 },{ 461 .name = "part", 462 .type = QEMU_OPT_STRING, 463 .help = "part number", 464 },{ 465 .name = "speed", 466 .type = QEMU_OPT_NUMBER, 467 .help = "maximum capable speed", 468 }, 469 { /* end of list */ } 470 }; 471 472 static const QemuOptDesc qemu_smbios_type41_opts[] = { 473 { 474 .name = "type", 475 .type = QEMU_OPT_NUMBER, 476 .help = "SMBIOS element type", 477 },{ 478 .name = "designation", 479 .type = QEMU_OPT_STRING, 480 .help = "reference designation string", 481 },{ 482 .name = "kind", 483 .type = QEMU_OPT_STRING, 484 .help = "device type", 485 .def_value_str = "other", 486 },{ 487 .name = "instance", 488 .type = QEMU_OPT_NUMBER, 489 .help = "device type instance", 490 },{ 491 .name = "pcidev", 492 .type = QEMU_OPT_STRING, 493 .help = "PCI device", 494 }, 495 { /* end of list */ } 496 }; 497 498 static void smbios_register_config(void) 499 { 500 qemu_add_opts(&qemu_smbios_opts); 501 } 502 503 opts_init(smbios_register_config); 504 505 /* 506 * The SMBIOS 2.1 "structure table length" field in the 507 * entry point uses a 16-bit integer, so we're limited 508 * in total table size 509 */ 510 #define SMBIOS_21_MAX_TABLES_LEN 0xffff 511 512 static bool smbios_check_type4_count(uint32_t expected_t4_count, Error **errp) 513 { 514 if (smbios_type4_count && smbios_type4_count != expected_t4_count) { 515 error_setg(errp, "Expected %d SMBIOS Type 4 tables, got %d instead", 516 expected_t4_count, smbios_type4_count); 517 return false; 518 } 519 return true; 520 } 521 522 bool smbios_validate_table(SmbiosEntryPointType ep_type, Error **errp) 523 { 524 if (ep_type == SMBIOS_ENTRY_POINT_TYPE_32 && 525 smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) { 526 error_setg(errp, "SMBIOS 2.1 table length %zu exceeds %d", 527 smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN); 528 return false; 529 } 530 return true; 531 } 532 533 bool smbios_skip_table(uint8_t type, bool required_table) 534 { 535 if (test_bit(type, smbios_have_binfile_bitmap)) { 536 return true; /* user provided their own binary blob(s) */ 537 } 538 if (test_bit(type, smbios_have_fields_bitmap)) { 539 return false; /* user provided fields via command line */ 540 } 541 if (smbios_have_defaults && required_table) { 542 return false; /* we're building tables, and this one's required */ 543 } 544 return true; 545 } 546 547 #define T0_BASE 0x000 548 #define T1_BASE 0x100 549 #define T2_BASE 0x200 550 #define T3_BASE 0x300 551 #define T4_BASE 0x400 552 #define T9_BASE 0x900 553 #define T11_BASE 0xe00 554 555 #define T16_BASE 0x1000 556 #define T17_BASE 0x1100 557 #define T19_BASE 0x1300 558 #define T32_BASE 0x2000 559 #define T41_BASE 0x2900 560 #define T127_BASE 0x7F00 561 562 static void smbios_build_type_0_table(void) 563 { 564 SMBIOS_BUILD_TABLE_PRE(0, T0_BASE, false); /* optional, leave up to BIOS */ 565 566 SMBIOS_TABLE_SET_STR(0, vendor_str, smbios_type0.vendor); 567 SMBIOS_TABLE_SET_STR(0, bios_version_str, smbios_type0.version); 568 569 t->bios_starting_address_segment = cpu_to_le16(0xE800); /* from SeaBIOS */ 570 571 SMBIOS_TABLE_SET_STR(0, bios_release_date_str, smbios_type0.date); 572 573 t->bios_rom_size = 0; /* hardcoded in SeaBIOS with FIXME comment */ 574 575 t->bios_characteristics = cpu_to_le64(0x08); /* Not supported */ 576 t->bios_characteristics_extension_bytes[0] = 0; 577 t->bios_characteristics_extension_bytes[1] = 0x14; /* TCD/SVVP | VM */ 578 if (smbios_type0.uefi) { 579 t->bios_characteristics_extension_bytes[1] |= 0x08; /* |= UEFI */ 580 } 581 582 if (smbios_type0.have_major_minor) { 583 t->system_bios_major_release = smbios_type0.major; 584 t->system_bios_minor_release = smbios_type0.minor; 585 } else { 586 t->system_bios_major_release = 0; 587 t->system_bios_minor_release = 0; 588 } 589 590 /* hardcoded in SeaBIOS */ 591 t->embedded_controller_major_release = 0xFF; 592 t->embedded_controller_minor_release = 0xFF; 593 594 SMBIOS_BUILD_TABLE_POST; 595 } 596 597 /* Encode UUID from the big endian encoding described on RFC4122 to the wire 598 * format specified by SMBIOS version 2.6. 599 */ 600 static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in) 601 { 602 memcpy(uuid, in, 16); 603 if (smbios_uuid_encoded) { 604 uuid->time_low = bswap32(uuid->time_low); 605 uuid->time_mid = bswap16(uuid->time_mid); 606 uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version); 607 } 608 } 609 610 static void smbios_build_type_1_table(void) 611 { 612 SMBIOS_BUILD_TABLE_PRE(1, T1_BASE, true); /* required */ 613 614 SMBIOS_TABLE_SET_STR(1, manufacturer_str, smbios_type1.manufacturer); 615 SMBIOS_TABLE_SET_STR(1, product_name_str, smbios_type1.product); 616 SMBIOS_TABLE_SET_STR(1, version_str, smbios_type1.version); 617 SMBIOS_TABLE_SET_STR(1, serial_number_str, smbios_type1.serial); 618 if (qemu_uuid_set) { 619 smbios_encode_uuid(&t->uuid, &qemu_uuid); 620 } else { 621 memset(&t->uuid, 0, 16); 622 } 623 t->wake_up_type = 0x06; /* power switch */ 624 SMBIOS_TABLE_SET_STR(1, sku_number_str, smbios_type1.sku); 625 SMBIOS_TABLE_SET_STR(1, family_str, smbios_type1.family); 626 627 SMBIOS_BUILD_TABLE_POST; 628 } 629 630 static void smbios_build_type_2_table(void) 631 { 632 SMBIOS_BUILD_TABLE_PRE(2, T2_BASE, false); /* optional */ 633 634 SMBIOS_TABLE_SET_STR(2, manufacturer_str, type2.manufacturer); 635 SMBIOS_TABLE_SET_STR(2, product_str, type2.product); 636 SMBIOS_TABLE_SET_STR(2, version_str, type2.version); 637 SMBIOS_TABLE_SET_STR(2, serial_number_str, type2.serial); 638 SMBIOS_TABLE_SET_STR(2, asset_tag_number_str, type2.asset); 639 t->feature_flags = 0x01; /* Motherboard */ 640 SMBIOS_TABLE_SET_STR(2, location_str, type2.location); 641 t->chassis_handle = cpu_to_le16(0x300); /* Type 3 (System enclosure) */ 642 t->board_type = 0x0A; /* Motherboard */ 643 t->contained_element_count = 0; 644 645 SMBIOS_BUILD_TABLE_POST; 646 } 647 648 static void smbios_build_type_3_table(void) 649 { 650 SMBIOS_BUILD_TABLE_PRE(3, T3_BASE, true); /* required */ 651 652 SMBIOS_TABLE_SET_STR(3, manufacturer_str, type3.manufacturer); 653 t->type = 0x01; /* Other */ 654 SMBIOS_TABLE_SET_STR(3, version_str, type3.version); 655 SMBIOS_TABLE_SET_STR(3, serial_number_str, type3.serial); 656 SMBIOS_TABLE_SET_STR(3, asset_tag_number_str, type3.asset); 657 t->boot_up_state = 0x03; /* Safe */ 658 t->power_supply_state = 0x03; /* Safe */ 659 t->thermal_state = 0x03; /* Safe */ 660 t->security_status = 0x02; /* Unknown */ 661 t->oem_defined = cpu_to_le32(0); 662 t->height = 0; 663 t->number_of_power_cords = 0; 664 t->contained_element_count = 0; 665 t->contained_element_record_length = 0; 666 SMBIOS_TABLE_SET_STR(3, sku_number_str, type3.sku); 667 668 SMBIOS_BUILD_TABLE_POST; 669 } 670 671 static void smbios_build_type_4_table(MachineState *ms, unsigned instance, 672 SmbiosEntryPointType ep_type) 673 { 674 char sock_str[128]; 675 size_t tbl_len = SMBIOS_TYPE_4_LEN_V28; 676 unsigned threads_per_socket; 677 unsigned cores_per_socket; 678 679 if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) { 680 tbl_len = SMBIOS_TYPE_4_LEN_V30; 681 } 682 683 SMBIOS_BUILD_TABLE_PRE_SIZE(4, T4_BASE + instance, 684 true, tbl_len); /* required */ 685 686 snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance); 687 SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str); 688 t->processor_type = 0x03; /* CPU */ 689 t->processor_family = 0xfe; /* use Processor Family 2 field */ 690 SMBIOS_TABLE_SET_STR(4, processor_manufacturer_str, type4.manufacturer); 691 if (type4.processor_id == 0) { 692 t->processor_id[0] = cpu_to_le32(smbios_cpuid_version); 693 t->processor_id[1] = cpu_to_le32(smbios_cpuid_features); 694 } else { 695 t->processor_id[0] = cpu_to_le32((uint32_t)type4.processor_id); 696 t->processor_id[1] = cpu_to_le32(type4.processor_id >> 32); 697 } 698 SMBIOS_TABLE_SET_STR(4, processor_version_str, type4.version); 699 t->voltage = 0; 700 t->external_clock = cpu_to_le16(0); /* Unknown */ 701 t->max_speed = cpu_to_le16(type4.max_speed); 702 t->current_speed = cpu_to_le16(type4.current_speed); 703 t->status = 0x41; /* Socket populated, CPU enabled */ 704 t->processor_upgrade = 0x01; /* Other */ 705 t->l1_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 706 t->l2_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 707 t->l3_cache_handle = cpu_to_le16(0xFFFF); /* N/A */ 708 SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial); 709 SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset); 710 SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part); 711 712 threads_per_socket = machine_topo_get_threads_per_socket(ms); 713 cores_per_socket = machine_topo_get_cores_per_socket(ms); 714 715 t->core_count = (cores_per_socket > 255) ? 0xFF : cores_per_socket; 716 t->core_enabled = t->core_count; 717 718 t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket; 719 720 t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */ 721 t->processor_family2 = cpu_to_le16(type4.processor_family); 722 723 if (tbl_len == SMBIOS_TYPE_4_LEN_V30) { 724 t->core_count2 = t->core_enabled2 = cpu_to_le16(cores_per_socket); 725 t->thread_count2 = cpu_to_le16(threads_per_socket); 726 } 727 728 SMBIOS_BUILD_TABLE_POST; 729 smbios_type4_count++; 730 } 731 732 static void smbios_build_type_8_table(void) 733 { 734 unsigned instance = 0; 735 struct type8_instance *t8; 736 737 QTAILQ_FOREACH(t8, &type8, next) { 738 SMBIOS_BUILD_TABLE_PRE(8, T0_BASE + instance, true); 739 740 SMBIOS_TABLE_SET_STR(8, internal_reference_str, t8->internal_reference); 741 SMBIOS_TABLE_SET_STR(8, external_reference_str, t8->external_reference); 742 /* most vendors seem to set this to None */ 743 t->internal_connector_type = 0x0; 744 t->external_connector_type = t8->connector_type; 745 t->port_type = t8->port_type; 746 747 SMBIOS_BUILD_TABLE_POST; 748 instance++; 749 } 750 } 751 752 static void smbios_build_type_9_table(Error **errp) 753 { 754 unsigned instance = 0; 755 struct type9_instance *t9; 756 757 QTAILQ_FOREACH(t9, &type9, next) { 758 SMBIOS_BUILD_TABLE_PRE(9, T9_BASE + instance, true); 759 760 SMBIOS_TABLE_SET_STR(9, slot_designation, t9->slot_designation); 761 t->slot_type = t9->slot_type; 762 t->slot_data_bus_width = t9->slot_data_bus_width; 763 t->current_usage = t9->current_usage; 764 t->slot_length = t9->slot_length; 765 t->slot_id = t9->slot_id; 766 t->slot_characteristics1 = t9->slot_characteristics1; 767 t->slot_characteristics2 = t9->slot_characteristics2; 768 769 if (t9->pcidev) { 770 PCIDevice *pdev = NULL; 771 int rc = pci_qdev_find_device(t9->pcidev, &pdev); 772 if (rc != 0) { 773 error_setg(errp, 774 "No PCI device %s for SMBIOS type 9 entry %s", 775 t9->pcidev, t9->slot_designation); 776 return; 777 } 778 /* 779 * We only handle the case were the device is attached to 780 * the PCI root bus. The general case is more complex as 781 * bridges are enumerated later and the table would need 782 * to be updated at this moment. 783 */ 784 if (!pci_bus_is_root(pci_get_bus(pdev))) { 785 error_setg(errp, 786 "Cannot create type 9 entry for PCI device %s: " 787 "not attached to the root bus", 788 t9->pcidev); 789 return; 790 } 791 t->segment_group_number = cpu_to_le16(0); 792 t->bus_number = pci_dev_bus_num(pdev); 793 t->device_number = pdev->devfn; 794 } else { 795 /* 796 * Per SMBIOS spec, For slots that are not of the PCI, AGP, PCI-X, 797 * or PCI-Express type that do not have bus/device/function 798 * information, 0FFh should be populated in the fields of Segment 799 * Group Number, Bus Number, Device/Function Number. 800 */ 801 t->segment_group_number = 0xff; 802 t->bus_number = 0xff; 803 t->device_number = 0xff; 804 } 805 806 SMBIOS_BUILD_TABLE_POST; 807 instance++; 808 } 809 } 810 811 static void smbios_build_type_11_table(void) 812 { 813 char count_str[128]; 814 size_t i; 815 816 if (type11.nvalues == 0) { 817 return; 818 } 819 820 SMBIOS_BUILD_TABLE_PRE(11, T11_BASE, true); /* required */ 821 822 snprintf(count_str, sizeof(count_str), "%zu", type11.nvalues); 823 t->count = type11.nvalues; 824 825 for (i = 0; i < type11.nvalues; i++) { 826 SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]); 827 g_free(type11.values[i]); 828 type11.values[i] = NULL; 829 } 830 831 SMBIOS_BUILD_TABLE_POST; 832 } 833 834 #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */ 835 836 static void smbios_build_type_16_table(unsigned dimm_cnt) 837 { 838 uint64_t size_kb; 839 840 SMBIOS_BUILD_TABLE_PRE(16, T16_BASE, true); /* required */ 841 842 t->location = 0x01; /* Other */ 843 t->use = 0x03; /* System memory */ 844 t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */ 845 size_kb = QEMU_ALIGN_UP(current_machine->ram_size, KiB) / KiB; 846 if (size_kb < MAX_T16_STD_SZ) { 847 t->maximum_capacity = cpu_to_le32(size_kb); 848 t->extended_maximum_capacity = cpu_to_le64(0); 849 } else { 850 t->maximum_capacity = cpu_to_le32(MAX_T16_STD_SZ); 851 t->extended_maximum_capacity = cpu_to_le64(current_machine->ram_size); 852 } 853 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ 854 t->number_of_memory_devices = cpu_to_le16(dimm_cnt); 855 856 SMBIOS_BUILD_TABLE_POST; 857 } 858 859 #define MAX_T17_STD_SZ 0x7FFF /* (32G - 1M), in Megabytes */ 860 #define MAX_T17_EXT_SZ 0x80000000 /* 2P, in Megabytes */ 861 862 static void smbios_build_type_17_table(unsigned instance, uint64_t size) 863 { 864 char loc_str[128]; 865 uint64_t size_mb; 866 867 SMBIOS_BUILD_TABLE_PRE(17, T17_BASE + instance, true); /* required */ 868 869 t->physical_memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ 870 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */ 871 t->total_width = cpu_to_le16(0xFFFF); /* Unknown */ 872 t->data_width = cpu_to_le16(0xFFFF); /* Unknown */ 873 size_mb = QEMU_ALIGN_UP(size, MiB) / MiB; 874 if (size_mb < MAX_T17_STD_SZ) { 875 t->size = cpu_to_le16(size_mb); 876 t->extended_size = cpu_to_le32(0); 877 } else { 878 assert(size_mb < MAX_T17_EXT_SZ); 879 t->size = cpu_to_le16(MAX_T17_STD_SZ); 880 t->extended_size = cpu_to_le32(size_mb); 881 } 882 t->form_factor = 0x09; /* DIMM */ 883 t->device_set = 0; /* Not in a set */ 884 snprintf(loc_str, sizeof(loc_str), "%s %d", type17.loc_pfx, instance); 885 SMBIOS_TABLE_SET_STR(17, device_locator_str, loc_str); 886 SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank); 887 t->memory_type = 0x07; /* RAM */ 888 t->type_detail = cpu_to_le16(0x02); /* Other */ 889 t->speed = cpu_to_le16(type17.speed); 890 SMBIOS_TABLE_SET_STR(17, manufacturer_str, type17.manufacturer); 891 SMBIOS_TABLE_SET_STR(17, serial_number_str, type17.serial); 892 SMBIOS_TABLE_SET_STR(17, asset_tag_number_str, type17.asset); 893 SMBIOS_TABLE_SET_STR(17, part_number_str, type17.part); 894 t->attributes = 0; /* Unknown */ 895 t->configured_clock_speed = t->speed; /* reuse value for max speed */ 896 t->minimum_voltage = cpu_to_le16(0); /* Unknown */ 897 t->maximum_voltage = cpu_to_le16(0); /* Unknown */ 898 t->configured_voltage = cpu_to_le16(0); /* Unknown */ 899 900 SMBIOS_BUILD_TABLE_POST; 901 } 902 903 static void smbios_build_type_19_table(unsigned instance, unsigned offset, 904 uint64_t start, uint64_t size) 905 { 906 uint64_t end, start_kb, end_kb; 907 908 SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + offset + instance, 909 true); /* required */ 910 911 end = start + size - 1; 912 assert(end > start); 913 start_kb = start / KiB; 914 end_kb = end / KiB; 915 if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) { 916 t->starting_address = cpu_to_le32(start_kb); 917 t->ending_address = cpu_to_le32(end_kb); 918 t->extended_starting_address = 919 t->extended_ending_address = cpu_to_le64(0); 920 } else { 921 t->starting_address = t->ending_address = cpu_to_le32(UINT32_MAX); 922 t->extended_starting_address = cpu_to_le64(start); 923 t->extended_ending_address = cpu_to_le64(end); 924 } 925 t->memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */ 926 t->partition_width = 1; /* One device per row */ 927 928 SMBIOS_BUILD_TABLE_POST; 929 } 930 931 static void smbios_build_type_32_table(void) 932 { 933 SMBIOS_BUILD_TABLE_PRE(32, T32_BASE, true); /* required */ 934 935 memset(t->reserved, 0, 6); 936 t->boot_status = 0; /* No errors detected */ 937 938 SMBIOS_BUILD_TABLE_POST; 939 } 940 941 static void smbios_build_type_41_table(Error **errp) 942 { 943 unsigned instance = 0; 944 struct type41_instance *t41; 945 946 QTAILQ_FOREACH(t41, &type41, next) { 947 SMBIOS_BUILD_TABLE_PRE(41, T41_BASE + instance, true); 948 949 SMBIOS_TABLE_SET_STR(41, reference_designation_str, t41->designation); 950 t->device_type = t41->kind; 951 t->device_type_instance = t41->instance; 952 t->segment_group_number = cpu_to_le16(0); 953 t->bus_number = 0; 954 t->device_number = 0; 955 956 if (t41->pcidev) { 957 PCIDevice *pdev = NULL; 958 int rc = pci_qdev_find_device(t41->pcidev, &pdev); 959 if (rc != 0) { 960 error_setg(errp, 961 "No PCI device %s for SMBIOS type 41 entry %s", 962 t41->pcidev, t41->designation); 963 return; 964 } 965 /* 966 * We only handle the case were the device is attached to 967 * the PCI root bus. The general case is more complex as 968 * bridges are enumerated later and the table would need 969 * to be updated at this moment. 970 */ 971 if (!pci_bus_is_root(pci_get_bus(pdev))) { 972 error_setg(errp, 973 "Cannot create type 41 entry for PCI device %s: " 974 "not attached to the root bus", 975 t41->pcidev); 976 return; 977 } 978 t->segment_group_number = cpu_to_le16(0); 979 t->bus_number = pci_dev_bus_num(pdev); 980 t->device_number = pdev->devfn; 981 } 982 983 SMBIOS_BUILD_TABLE_POST; 984 instance++; 985 } 986 } 987 988 static void smbios_build_type_127_table(void) 989 { 990 SMBIOS_BUILD_TABLE_PRE(127, T127_BASE, true); /* required */ 991 SMBIOS_BUILD_TABLE_POST; 992 } 993 994 void smbios_set_cpuid(uint32_t version, uint32_t features) 995 { 996 smbios_cpuid_version = version; 997 smbios_cpuid_features = features; 998 } 999 1000 #define SMBIOS_SET_DEFAULT(field, value) \ 1001 if (!field) { \ 1002 field = value; \ 1003 } 1004 1005 void smbios_set_default_processor_family(uint16_t processor_family) 1006 { 1007 if (type4.processor_family <= 0x01) { 1008 type4.processor_family = processor_family; 1009 } 1010 } 1011 1012 void smbios_set_defaults(const char *manufacturer, const char *product, 1013 const char *version, 1014 bool uuid_encoded) 1015 { 1016 smbios_have_defaults = true; 1017 smbios_uuid_encoded = uuid_encoded; 1018 1019 SMBIOS_SET_DEFAULT(smbios_type1.manufacturer, manufacturer); 1020 SMBIOS_SET_DEFAULT(smbios_type1.product, product); 1021 SMBIOS_SET_DEFAULT(smbios_type1.version, version); 1022 SMBIOS_SET_DEFAULT(type2.manufacturer, manufacturer); 1023 SMBIOS_SET_DEFAULT(type2.product, product); 1024 SMBIOS_SET_DEFAULT(type2.version, version); 1025 SMBIOS_SET_DEFAULT(type3.manufacturer, manufacturer); 1026 SMBIOS_SET_DEFAULT(type3.version, version); 1027 SMBIOS_SET_DEFAULT(type4.sock_pfx, "CPU"); 1028 SMBIOS_SET_DEFAULT(type4.manufacturer, manufacturer); 1029 SMBIOS_SET_DEFAULT(type4.version, version); 1030 SMBIOS_SET_DEFAULT(type17.loc_pfx, "DIMM"); 1031 SMBIOS_SET_DEFAULT(type17.manufacturer, manufacturer); 1032 } 1033 1034 static void smbios_entry_point_setup(SmbiosEntryPointType ep_type) 1035 { 1036 switch (ep_type) { 1037 case SMBIOS_ENTRY_POINT_TYPE_32: 1038 memcpy(ep.ep21.anchor_string, "_SM_", 4); 1039 memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5); 1040 ep.ep21.length = sizeof(struct smbios_21_entry_point); 1041 ep.ep21.entry_point_revision = 0; /* formatted_area reserved */ 1042 memset(ep.ep21.formatted_area, 0, 5); 1043 1044 /* compliant with smbios spec v2.8 */ 1045 ep.ep21.smbios_major_version = 2; 1046 ep.ep21.smbios_minor_version = 8; 1047 ep.ep21.smbios_bcd_revision = 0x28; 1048 1049 /* set during table construction, but BIOS may override: */ 1050 ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len); 1051 ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max); 1052 ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt); 1053 1054 /* BIOS must recalculate */ 1055 ep.ep21.checksum = 0; 1056 ep.ep21.intermediate_checksum = 0; 1057 ep.ep21.structure_table_address = cpu_to_le32(0); 1058 1059 break; 1060 case SMBIOS_ENTRY_POINT_TYPE_64: 1061 memcpy(ep.ep30.anchor_string, "_SM3_", 5); 1062 ep.ep30.length = sizeof(struct smbios_30_entry_point); 1063 ep.ep30.entry_point_revision = 1; 1064 ep.ep30.reserved = 0; 1065 1066 /* compliant with smbios spec 3.0 */ 1067 ep.ep30.smbios_major_version = 3; 1068 ep.ep30.smbios_minor_version = 0; 1069 ep.ep30.smbios_doc_rev = 0; 1070 1071 /* set during table construct, but BIOS might override */ 1072 ep.ep30.structure_table_max_size = cpu_to_le32(smbios_tables_len); 1073 1074 /* BIOS must recalculate */ 1075 ep.ep30.checksum = 0; 1076 ep.ep30.structure_table_address = cpu_to_le64(0); 1077 1078 break; 1079 default: 1080 abort(); 1081 break; 1082 } 1083 } 1084 1085 void smbios_get_tables(MachineState *ms, 1086 SmbiosEntryPointType ep_type, 1087 const struct smbios_phys_mem_area *mem_array, 1088 const unsigned int mem_array_size, 1089 uint8_t **tables, size_t *tables_len, 1090 uint8_t **anchor, size_t *anchor_len, 1091 Error **errp) 1092 { 1093 unsigned i, dimm_cnt, offset; 1094 1095 assert(ep_type == SMBIOS_ENTRY_POINT_TYPE_32 || 1096 ep_type == SMBIOS_ENTRY_POINT_TYPE_64); 1097 1098 g_free(smbios_tables); 1099 smbios_type4_count = 0; 1100 smbios_tables = g_memdup2(usr_blobs, usr_blobs_len); 1101 smbios_tables_len = usr_blobs_len; 1102 smbios_table_max = usr_table_max; 1103 smbios_table_cnt = usr_table_cnt; 1104 1105 smbios_build_type_0_table(); 1106 smbios_build_type_1_table(); 1107 smbios_build_type_2_table(); 1108 smbios_build_type_3_table(); 1109 1110 assert(ms->smp.sockets >= 1); 1111 1112 for (i = 0; i < ms->smp.sockets; i++) { 1113 smbios_build_type_4_table(ms, i, ep_type); 1114 } 1115 1116 smbios_build_type_8_table(); 1117 smbios_build_type_9_table(errp); 1118 smbios_build_type_11_table(); 1119 1120 #define MAX_DIMM_SZ (16 * GiB) 1121 #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? MAX_DIMM_SZ \ 1122 : ((current_machine->ram_size - 1) % MAX_DIMM_SZ) + 1) 1123 1124 dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size, MAX_DIMM_SZ) / 1125 MAX_DIMM_SZ; 1126 1127 /* 1128 * The offset determines if we need to keep additional space between 1129 * table 17 and table 19 header handle numbers so that they do 1130 * not overlap. For example, for a VM with larger than 8 TB guest 1131 * memory and DIMM like chunks of 16 GiB, the default space between 1132 * the two tables (T19_BASE - T17_BASE = 512) is not enough. 1133 */ 1134 offset = (dimm_cnt > (T19_BASE - T17_BASE)) ? \ 1135 dimm_cnt - (T19_BASE - T17_BASE) : 0; 1136 1137 smbios_build_type_16_table(dimm_cnt); 1138 1139 for (i = 0; i < dimm_cnt; i++) { 1140 smbios_build_type_17_table(i, GET_DIMM_SZ); 1141 } 1142 1143 for (i = 0; i < mem_array_size; i++) { 1144 smbios_build_type_19_table(i, offset, mem_array[i].address, 1145 mem_array[i].length); 1146 } 1147 1148 /* 1149 * make sure 16 bit handle numbers in the headers of tables 19 1150 * and 32 do not overlap. 1151 */ 1152 assert((mem_array_size + offset) < (T32_BASE - T19_BASE)); 1153 1154 smbios_build_type_32_table(); 1155 smbios_build_type_38_table(); 1156 smbios_build_type_41_table(errp); 1157 smbios_build_type_127_table(); 1158 1159 if (!smbios_check_type4_count(ms->smp.sockets, errp)) { 1160 goto err_exit; 1161 } 1162 if (!smbios_validate_table(ep_type, errp)) { 1163 goto err_exit; 1164 } 1165 smbios_entry_point_setup(ep_type); 1166 1167 /* return tables blob and entry point (anchor), and their sizes */ 1168 *tables = smbios_tables; 1169 *tables_len = smbios_tables_len; 1170 *anchor = (uint8_t *)&ep; 1171 /* calculate length based on anchor string */ 1172 if (!strncmp((char *)&ep, "_SM_", 4)) { 1173 *anchor_len = sizeof(struct smbios_21_entry_point); 1174 } else if (!strncmp((char *)&ep, "_SM3_", 5)) { 1175 *anchor_len = sizeof(struct smbios_30_entry_point); 1176 } else { 1177 abort(); 1178 } 1179 1180 return; 1181 err_exit: 1182 g_free(smbios_tables); 1183 smbios_tables = NULL; 1184 return; 1185 } 1186 1187 static void save_opt(const char **dest, QemuOpts *opts, const char *name) 1188 { 1189 const char *val = qemu_opt_get(opts, name); 1190 1191 if (val) { 1192 *dest = val; 1193 } 1194 } 1195 1196 1197 struct opt_list { 1198 size_t *ndest; 1199 char ***dest; 1200 }; 1201 1202 static int save_opt_one(void *opaque, 1203 const char *name, const char *value, 1204 Error **errp) 1205 { 1206 struct opt_list *opt = opaque; 1207 1208 if (g_str_equal(name, "path")) { 1209 g_autoptr(GByteArray) data = g_byte_array_new(); 1210 g_autofree char *buf = g_new(char, 4096); 1211 ssize_t ret; 1212 int fd = qemu_open(value, O_RDONLY, errp); 1213 if (fd < 0) { 1214 return -1; 1215 } 1216 1217 while (1) { 1218 ret = read(fd, buf, 4096); 1219 if (ret == 0) { 1220 break; 1221 } 1222 if (ret < 0) { 1223 error_setg(errp, "Unable to read from %s: %s", 1224 value, strerror(errno)); 1225 qemu_close(fd); 1226 return -1; 1227 } 1228 if (memchr(buf, '\0', ret)) { 1229 error_setg(errp, "NUL in OEM strings value in %s", value); 1230 qemu_close(fd); 1231 return -1; 1232 } 1233 g_byte_array_append(data, (guint8 *)buf, ret); 1234 } 1235 1236 qemu_close(fd); 1237 1238 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); 1239 (*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data, FALSE); 1240 (*opt->ndest)++; 1241 data = NULL; 1242 } else if (g_str_equal(name, "value")) { 1243 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); 1244 (*opt->dest)[*opt->ndest] = g_strdup(value); 1245 (*opt->ndest)++; 1246 } else if (!g_str_equal(name, "type")) { 1247 error_setg(errp, "Unexpected option %s", name); 1248 return -1; 1249 } 1250 1251 return 0; 1252 } 1253 1254 static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts, 1255 Error **errp) 1256 { 1257 struct opt_list opt = { 1258 ndest, dest, 1259 }; 1260 if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) { 1261 return false; 1262 } 1263 return true; 1264 } 1265 1266 void smbios_entry_add(QemuOpts *opts, Error **errp) 1267 { 1268 const char *val; 1269 1270 val = qemu_opt_get(opts, "file"); 1271 if (val) { 1272 struct smbios_structure_header *header; 1273 size_t size; 1274 1275 if (!qemu_opts_validate(opts, qemu_smbios_file_opts, errp)) { 1276 return; 1277 } 1278 1279 size = get_image_size(val); 1280 if (size == -1 || size < sizeof(struct smbios_structure_header)) { 1281 error_setg(errp, "Cannot read SMBIOS file %s", val); 1282 return; 1283 } 1284 1285 /* 1286 * NOTE: standard double '\0' terminator expected, per smbios spec. 1287 * (except in legacy mode, where the second '\0' is implicit and 1288 * will be inserted by the BIOS). 1289 */ 1290 usr_blobs = g_realloc(usr_blobs, usr_blobs_len + size); 1291 header = (struct smbios_structure_header *)(usr_blobs + 1292 usr_blobs_len); 1293 1294 if (load_image_size(val, (uint8_t *)header, size) != size) { 1295 error_setg(errp, "Failed to load SMBIOS file %s", val); 1296 return; 1297 } 1298 1299 if (header->type <= SMBIOS_MAX_TYPE) { 1300 if (test_bit(header->type, smbios_have_fields_bitmap)) { 1301 error_setg(errp, 1302 "can't load type %d struct, fields already specified!", 1303 header->type); 1304 return; 1305 } 1306 set_bit(header->type, smbios_have_binfile_bitmap); 1307 } 1308 1309 if (header->type == 4) { 1310 smbios_type4_count++; 1311 } 1312 1313 /* 1314 * preserve blob size for legacy mode so it could build its 1315 * blobs flavor from 'usr_blobs' 1316 */ 1317 smbios_add_usr_blob_size(size); 1318 1319 usr_blobs_len += size; 1320 if (size > usr_table_max) { 1321 usr_table_max = size; 1322 } 1323 usr_table_cnt++; 1324 1325 return; 1326 } 1327 1328 val = qemu_opt_get(opts, "type"); 1329 if (val) { 1330 unsigned long type = strtoul(val, NULL, 0); 1331 1332 if (type > SMBIOS_MAX_TYPE) { 1333 error_setg(errp, "out of range!"); 1334 return; 1335 } 1336 1337 if (test_bit(type, smbios_have_binfile_bitmap)) { 1338 error_setg(errp, "can't add fields, binary file already loaded!"); 1339 return; 1340 } 1341 set_bit(type, smbios_have_fields_bitmap); 1342 1343 switch (type) { 1344 case 0: 1345 if (!qemu_opts_validate(opts, qemu_smbios_type0_opts, errp)) { 1346 return; 1347 } 1348 save_opt(&smbios_type0.vendor, opts, "vendor"); 1349 save_opt(&smbios_type0.version, opts, "version"); 1350 save_opt(&smbios_type0.date, opts, "date"); 1351 smbios_type0.uefi = qemu_opt_get_bool(opts, "uefi", false); 1352 1353 val = qemu_opt_get(opts, "release"); 1354 if (val) { 1355 if (sscanf(val, "%hhu.%hhu", &smbios_type0.major, 1356 &smbios_type0.minor) != 2) { 1357 error_setg(errp, "Invalid release"); 1358 return; 1359 } 1360 smbios_type0.have_major_minor = true; 1361 } 1362 return; 1363 case 1: 1364 if (!qemu_opts_validate(opts, qemu_smbios_type1_opts, errp)) { 1365 return; 1366 } 1367 save_opt(&smbios_type1.manufacturer, opts, "manufacturer"); 1368 save_opt(&smbios_type1.product, opts, "product"); 1369 save_opt(&smbios_type1.version, opts, "version"); 1370 save_opt(&smbios_type1.serial, opts, "serial"); 1371 save_opt(&smbios_type1.sku, opts, "sku"); 1372 save_opt(&smbios_type1.family, opts, "family"); 1373 1374 val = qemu_opt_get(opts, "uuid"); 1375 if (val) { 1376 if (qemu_uuid_parse(val, &qemu_uuid) != 0) { 1377 error_setg(errp, "Invalid UUID"); 1378 return; 1379 } 1380 qemu_uuid_set = true; 1381 } 1382 return; 1383 case 2: 1384 if (!qemu_opts_validate(opts, qemu_smbios_type2_opts, errp)) { 1385 return; 1386 } 1387 save_opt(&type2.manufacturer, opts, "manufacturer"); 1388 save_opt(&type2.product, opts, "product"); 1389 save_opt(&type2.version, opts, "version"); 1390 save_opt(&type2.serial, opts, "serial"); 1391 save_opt(&type2.asset, opts, "asset"); 1392 save_opt(&type2.location, opts, "location"); 1393 return; 1394 case 3: 1395 if (!qemu_opts_validate(opts, qemu_smbios_type3_opts, errp)) { 1396 return; 1397 } 1398 save_opt(&type3.manufacturer, opts, "manufacturer"); 1399 save_opt(&type3.version, opts, "version"); 1400 save_opt(&type3.serial, opts, "serial"); 1401 save_opt(&type3.asset, opts, "asset"); 1402 save_opt(&type3.sku, opts, "sku"); 1403 return; 1404 case 4: 1405 if (!qemu_opts_validate(opts, qemu_smbios_type4_opts, errp)) { 1406 return; 1407 } 1408 save_opt(&type4.sock_pfx, opts, "sock_pfx"); 1409 type4.processor_family = qemu_opt_get_number(opts, 1410 "processor-family", 1411 0x01 /* Other */); 1412 save_opt(&type4.manufacturer, opts, "manufacturer"); 1413 save_opt(&type4.version, opts, "version"); 1414 save_opt(&type4.serial, opts, "serial"); 1415 save_opt(&type4.asset, opts, "asset"); 1416 save_opt(&type4.part, opts, "part"); 1417 /* If the value is 0, it will take the value from the CPU model. */ 1418 type4.processor_id = qemu_opt_get_number(opts, "processor-id", 0); 1419 type4.max_speed = qemu_opt_get_number(opts, "max-speed", 1420 DEFAULT_CPU_SPEED); 1421 type4.current_speed = qemu_opt_get_number(opts, "current-speed", 1422 DEFAULT_CPU_SPEED); 1423 if (type4.max_speed > UINT16_MAX || 1424 type4.current_speed > UINT16_MAX) { 1425 error_setg(errp, "SMBIOS CPU speed is too large (> %d)", 1426 UINT16_MAX); 1427 } 1428 return; 1429 case 8: 1430 if (!qemu_opts_validate(opts, qemu_smbios_type8_opts, errp)) { 1431 return; 1432 } 1433 struct type8_instance *t8_i; 1434 t8_i = g_new0(struct type8_instance, 1); 1435 save_opt(&t8_i->internal_reference, opts, "internal_reference"); 1436 save_opt(&t8_i->external_reference, opts, "external_reference"); 1437 t8_i->connector_type = qemu_opt_get_number(opts, 1438 "connector_type", 0); 1439 t8_i->port_type = qemu_opt_get_number(opts, "port_type", 0); 1440 QTAILQ_INSERT_TAIL(&type8, t8_i, next); 1441 return; 1442 case 9: { 1443 if (!qemu_opts_validate(opts, qemu_smbios_type9_opts, errp)) { 1444 return; 1445 } 1446 struct type9_instance *t; 1447 t = g_new0(struct type9_instance, 1); 1448 save_opt(&t->slot_designation, opts, "slot_designation"); 1449 t->slot_type = qemu_opt_get_number(opts, "slot_type", 0); 1450 t->slot_data_bus_width = 1451 qemu_opt_get_number(opts, "slot_data_bus_width", 0); 1452 t->current_usage = qemu_opt_get_number(opts, "current_usage", 0); 1453 t->slot_length = qemu_opt_get_number(opts, "slot_length", 0); 1454 t->slot_id = qemu_opt_get_number(opts, "slot_id", 0); 1455 t->slot_characteristics1 = 1456 qemu_opt_get_number(opts, "slot_characteristics1", 0); 1457 t->slot_characteristics2 = 1458 qemu_opt_get_number(opts, "slot_characteristics2", 0); 1459 save_opt(&t->pcidev, opts, "pcidev"); 1460 QTAILQ_INSERT_TAIL(&type9, t, next); 1461 return; 1462 } 1463 case 11: 1464 if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) { 1465 return; 1466 } 1467 if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) { 1468 return; 1469 } 1470 return; 1471 case 17: 1472 if (!qemu_opts_validate(opts, qemu_smbios_type17_opts, errp)) { 1473 return; 1474 } 1475 save_opt(&type17.loc_pfx, opts, "loc_pfx"); 1476 save_opt(&type17.bank, opts, "bank"); 1477 save_opt(&type17.manufacturer, opts, "manufacturer"); 1478 save_opt(&type17.serial, opts, "serial"); 1479 save_opt(&type17.asset, opts, "asset"); 1480 save_opt(&type17.part, opts, "part"); 1481 type17.speed = qemu_opt_get_number(opts, "speed", 0); 1482 return; 1483 case 41: { 1484 struct type41_instance *t41_i; 1485 Error *local_err = NULL; 1486 1487 if (!qemu_opts_validate(opts, qemu_smbios_type41_opts, errp)) { 1488 return; 1489 } 1490 t41_i = g_new0(struct type41_instance, 1); 1491 save_opt(&t41_i->designation, opts, "designation"); 1492 t41_i->kind = qapi_enum_parse(&type41_kind_lookup, 1493 qemu_opt_get(opts, "kind"), 1494 0, &local_err) + 1; 1495 t41_i->kind |= 0x80; /* enabled */ 1496 if (local_err != NULL) { 1497 error_propagate(errp, local_err); 1498 g_free(t41_i); 1499 return; 1500 } 1501 t41_i->instance = qemu_opt_get_number(opts, "instance", 1); 1502 save_opt(&t41_i->pcidev, opts, "pcidev"); 1503 1504 QTAILQ_INSERT_TAIL(&type41, t41_i, next); 1505 return; 1506 } 1507 default: 1508 error_setg(errp, 1509 "Don't know how to build fields for SMBIOS type %ld", 1510 type); 1511 return; 1512 } 1513 } 1514 1515 error_setg(errp, "Must specify type= or file="); 1516 } 1517