1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "qemu-common.h" 30 #include "cpu.h" 31 #include "hw/sysbus.h" 32 #include "qemu/error-report.h" 33 #include "qemu/timer.h" 34 #include "hw/sparc/sun4m_iommu.h" 35 #include "hw/rtc/m48t59.h" 36 #include "migration/vmstate.h" 37 #include "hw/sparc/sparc32_dma.h" 38 #include "hw/block/fdc.h" 39 #include "sysemu/reset.h" 40 #include "sysemu/runstate.h" 41 #include "sysemu/sysemu.h" 42 #include "net/net.h" 43 #include "hw/boards.h" 44 #include "hw/scsi/esp.h" 45 #include "hw/nvram/sun_nvram.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/nvram/chrp_nvram.h" 48 #include "hw/nvram/fw_cfg.h" 49 #include "hw/char/escc.h" 50 #include "hw/misc/empty_slot.h" 51 #include "hw/misc/unimp.h" 52 #include "hw/irq.h" 53 #include "hw/or-irq.h" 54 #include "hw/loader.h" 55 #include "elf.h" 56 #include "trace.h" 57 #include "qom/object.h" 58 59 /* 60 * Sun4m architecture was used in the following machines: 61 * 62 * SPARCserver 6xxMP/xx 63 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 64 * SPARCclassic X (4/10) 65 * SPARCstation LX/ZX (4/30) 66 * SPARCstation Voyager 67 * SPARCstation 10/xx, SPARCserver 10/xx 68 * SPARCstation 5, SPARCserver 5 69 * SPARCstation 20/xx, SPARCserver 20 70 * SPARCstation 4 71 * 72 * See for example: http://www.sunhelp.org/faq/sunref1.html 73 */ 74 75 #define KERNEL_LOAD_ADDR 0x00004000 76 #define CMDLINE_ADDR 0x007ff000 77 #define INITRD_LOAD_ADDR 0x00800000 78 #define PROM_SIZE_MAX (1 * MiB) 79 #define PROM_VADDR 0xffd00000 80 #define PROM_FILENAME "openbios-sparc32" 81 #define CFG_ADDR 0xd00000510ULL 82 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 83 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 84 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 85 86 #define MAX_CPUS 16 87 #define MAX_PILS 16 88 #define MAX_VSIMMS 4 89 90 #define ESCC_CLOCK 4915200 91 92 struct sun4m_hwdef { 93 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 94 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 95 hwaddr serial_base, fd_base; 96 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 97 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 98 hwaddr bpp_base, dbri_base, sx_base; 99 struct { 100 hwaddr reg_base, vram_base; 101 } vsimm[MAX_VSIMMS]; 102 hwaddr ecc_base; 103 uint64_t max_mem; 104 uint32_t ecc_version; 105 uint32_t iommu_version; 106 uint16_t machine_id; 107 uint8_t nvram_machine_id; 108 }; 109 110 const char *fw_cfg_arch_key_name(uint16_t key) 111 { 112 static const struct { 113 uint16_t key; 114 const char *name; 115 } fw_cfg_arch_wellknown_keys[] = { 116 {FW_CFG_SUN4M_DEPTH, "depth"}, 117 {FW_CFG_SUN4M_WIDTH, "width"}, 118 {FW_CFG_SUN4M_HEIGHT, "height"}, 119 }; 120 121 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 122 if (fw_cfg_arch_wellknown_keys[i].key == key) { 123 return fw_cfg_arch_wellknown_keys[i].name; 124 } 125 } 126 return NULL; 127 } 128 129 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 130 Error **errp) 131 { 132 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 133 } 134 135 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 136 const char *cmdline, const char *boot_devices, 137 ram_addr_t RAM_size, uint32_t kernel_size, 138 int width, int height, int depth, 139 int nvram_machine_id, const char *arch) 140 { 141 unsigned int i; 142 int sysp_end; 143 uint8_t image[0x1ff0]; 144 NvramClass *k = NVRAM_GET_CLASS(nvram); 145 146 memset(image, '\0', sizeof(image)); 147 148 /* OpenBIOS nvram variables partition */ 149 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 150 151 /* Free space partition */ 152 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 153 154 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 155 nvram_machine_id); 156 157 for (i = 0; i < sizeof(image); i++) { 158 (k->write)(nvram, i, image[i]); 159 } 160 } 161 162 void cpu_check_irqs(CPUSPARCState *env) 163 { 164 CPUState *cs; 165 166 /* We should be holding the BQL before we mess with IRQs */ 167 g_assert(qemu_mutex_iothread_locked()); 168 169 if (env->pil_in && (env->interrupt_index == 0 || 170 (env->interrupt_index & ~15) == TT_EXTINT)) { 171 unsigned int i; 172 173 for (i = 15; i > 0; i--) { 174 if (env->pil_in & (1 << i)) { 175 int old_interrupt = env->interrupt_index; 176 177 env->interrupt_index = TT_EXTINT | i; 178 if (old_interrupt != env->interrupt_index) { 179 cs = env_cpu(env); 180 trace_sun4m_cpu_interrupt(i); 181 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 182 } 183 break; 184 } 185 } 186 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { 187 cs = env_cpu(env); 188 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); 189 env->interrupt_index = 0; 190 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 191 } 192 } 193 194 static void cpu_kick_irq(SPARCCPU *cpu) 195 { 196 CPUSPARCState *env = &cpu->env; 197 CPUState *cs = CPU(cpu); 198 199 cs->halted = 0; 200 cpu_check_irqs(env); 201 qemu_cpu_kick(cs); 202 } 203 204 static void cpu_set_irq(void *opaque, int irq, int level) 205 { 206 SPARCCPU *cpu = opaque; 207 CPUSPARCState *env = &cpu->env; 208 209 if (level) { 210 trace_sun4m_cpu_set_irq_raise(irq); 211 env->pil_in |= 1 << irq; 212 cpu_kick_irq(cpu); 213 } else { 214 trace_sun4m_cpu_set_irq_lower(irq); 215 env->pil_in &= ~(1 << irq); 216 cpu_check_irqs(env); 217 } 218 } 219 220 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 221 { 222 } 223 224 static void sun4m_cpu_reset(void *opaque) 225 { 226 SPARCCPU *cpu = opaque; 227 CPUState *cs = CPU(cpu); 228 229 cpu_reset(cs); 230 } 231 232 static void cpu_halt_signal(void *opaque, int irq, int level) 233 { 234 if (level && current_cpu) { 235 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 236 } 237 } 238 239 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 240 { 241 return addr - 0xf0000000ULL; 242 } 243 244 static unsigned long sun4m_load_kernel(const char *kernel_filename, 245 const char *initrd_filename, 246 ram_addr_t RAM_size, 247 uint32_t *initrd_size) 248 { 249 int linux_boot; 250 unsigned int i; 251 long kernel_size; 252 uint8_t *ptr; 253 254 linux_boot = (kernel_filename != NULL); 255 256 kernel_size = 0; 257 if (linux_boot) { 258 int bswap_needed; 259 260 #ifdef BSWAP_NEEDED 261 bswap_needed = 1; 262 #else 263 bswap_needed = 0; 264 #endif 265 kernel_size = load_elf(kernel_filename, NULL, 266 translate_kernel_address, NULL, 267 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 268 if (kernel_size < 0) 269 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 270 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 271 TARGET_PAGE_SIZE); 272 if (kernel_size < 0) 273 kernel_size = load_image_targphys(kernel_filename, 274 KERNEL_LOAD_ADDR, 275 RAM_size - KERNEL_LOAD_ADDR); 276 if (kernel_size < 0) { 277 error_report("could not load kernel '%s'", kernel_filename); 278 exit(1); 279 } 280 281 /* load initrd */ 282 *initrd_size = 0; 283 if (initrd_filename) { 284 *initrd_size = load_image_targphys(initrd_filename, 285 INITRD_LOAD_ADDR, 286 RAM_size - INITRD_LOAD_ADDR); 287 if ((int)*initrd_size < 0) { 288 error_report("could not load initial ram disk '%s'", 289 initrd_filename); 290 exit(1); 291 } 292 } 293 if (*initrd_size > 0) { 294 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 295 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 296 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 297 stl_p(ptr + 16, INITRD_LOAD_ADDR); 298 stl_p(ptr + 20, *initrd_size); 299 break; 300 } 301 } 302 } 303 } 304 return kernel_size; 305 } 306 307 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 308 { 309 DeviceState *dev; 310 SysBusDevice *s; 311 312 dev = qdev_new(TYPE_SUN4M_IOMMU); 313 qdev_prop_set_uint32(dev, "version", version); 314 s = SYS_BUS_DEVICE(dev); 315 sysbus_realize_and_unref(s, &error_fatal); 316 sysbus_connect_irq(s, 0, irq); 317 sysbus_mmio_map(s, 0, addr); 318 319 return s; 320 } 321 322 static void *sparc32_dma_init(hwaddr dma_base, 323 hwaddr esp_base, qemu_irq espdma_irq, 324 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) 325 { 326 DeviceState *dma; 327 ESPDMADeviceState *espdma; 328 LEDMADeviceState *ledma; 329 SysBusESPState *esp; 330 SysBusPCNetState *lance; 331 332 dma = qdev_new(TYPE_SPARC32_DMA); 333 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 334 OBJECT(dma), "espdma")); 335 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 336 337 esp = ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 338 339 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 340 OBJECT(dma), "ledma")); 341 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 342 343 lance = SYSBUS_PCNET(object_resolve_path_component( 344 OBJECT(ledma), "lance")); 345 qdev_set_nic_properties(DEVICE(lance), nd); 346 347 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 348 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 349 350 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 351 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 352 353 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 354 355 return dma; 356 } 357 358 static DeviceState *slavio_intctl_init(hwaddr addr, 359 hwaddr addrg, 360 qemu_irq **parent_irq) 361 { 362 DeviceState *dev; 363 SysBusDevice *s; 364 unsigned int i, j; 365 366 dev = qdev_new("slavio_intctl"); 367 368 s = SYS_BUS_DEVICE(dev); 369 sysbus_realize_and_unref(s, &error_fatal); 370 371 for (i = 0; i < MAX_CPUS; i++) { 372 for (j = 0; j < MAX_PILS; j++) { 373 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 374 } 375 } 376 sysbus_mmio_map(s, 0, addrg); 377 for (i = 0; i < MAX_CPUS; i++) { 378 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 379 } 380 381 return dev; 382 } 383 384 #define SYS_TIMER_OFFSET 0x10000ULL 385 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 386 387 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 388 qemu_irq *cpu_irqs, unsigned int num_cpus) 389 { 390 DeviceState *dev; 391 SysBusDevice *s; 392 unsigned int i; 393 394 dev = qdev_new("slavio_timer"); 395 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 396 s = SYS_BUS_DEVICE(dev); 397 sysbus_realize_and_unref(s, &error_fatal); 398 sysbus_connect_irq(s, 0, master_irq); 399 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 400 401 for (i = 0; i < MAX_CPUS; i++) { 402 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 403 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 404 } 405 } 406 407 static qemu_irq slavio_system_powerdown; 408 409 static void slavio_powerdown_req(Notifier *n, void *opaque) 410 { 411 qemu_irq_raise(slavio_system_powerdown); 412 } 413 414 static Notifier slavio_system_powerdown_notifier = { 415 .notify = slavio_powerdown_req 416 }; 417 418 #define MISC_LEDS 0x01600000 419 #define MISC_CFG 0x01800000 420 #define MISC_DIAG 0x01a00000 421 #define MISC_MDM 0x01b00000 422 #define MISC_SYS 0x01f00000 423 424 static void slavio_misc_init(hwaddr base, 425 hwaddr aux1_base, 426 hwaddr aux2_base, qemu_irq irq, 427 qemu_irq fdc_tc) 428 { 429 DeviceState *dev; 430 SysBusDevice *s; 431 432 dev = qdev_new("slavio_misc"); 433 s = SYS_BUS_DEVICE(dev); 434 sysbus_realize_and_unref(s, &error_fatal); 435 if (base) { 436 /* 8 bit registers */ 437 /* Slavio control */ 438 sysbus_mmio_map(s, 0, base + MISC_CFG); 439 /* Diagnostics */ 440 sysbus_mmio_map(s, 1, base + MISC_DIAG); 441 /* Modem control */ 442 sysbus_mmio_map(s, 2, base + MISC_MDM); 443 /* 16 bit registers */ 444 /* ss600mp diag LEDs */ 445 sysbus_mmio_map(s, 3, base + MISC_LEDS); 446 /* 32 bit registers */ 447 /* System control */ 448 sysbus_mmio_map(s, 4, base + MISC_SYS); 449 } 450 if (aux1_base) { 451 /* AUX 1 (Misc System Functions) */ 452 sysbus_mmio_map(s, 5, aux1_base); 453 } 454 if (aux2_base) { 455 /* AUX 2 (Software Powerdown Control) */ 456 sysbus_mmio_map(s, 6, aux2_base); 457 } 458 sysbus_connect_irq(s, 0, irq); 459 sysbus_connect_irq(s, 1, fdc_tc); 460 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 461 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 462 } 463 464 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 465 { 466 DeviceState *dev; 467 SysBusDevice *s; 468 469 dev = qdev_new("eccmemctl"); 470 qdev_prop_set_uint32(dev, "version", version); 471 s = SYS_BUS_DEVICE(dev); 472 sysbus_realize_and_unref(s, &error_fatal); 473 sysbus_connect_irq(s, 0, irq); 474 sysbus_mmio_map(s, 0, base); 475 if (version == 0) { // SS-600MP only 476 sysbus_mmio_map(s, 1, base + 0x1000); 477 } 478 } 479 480 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 481 { 482 DeviceState *dev; 483 SysBusDevice *s; 484 485 dev = qdev_new("apc"); 486 s = SYS_BUS_DEVICE(dev); 487 sysbus_realize_and_unref(s, &error_fatal); 488 /* Power management (APC) XXX: not a Slavio device */ 489 sysbus_mmio_map(s, 0, power_base); 490 sysbus_connect_irq(s, 0, cpu_halt); 491 } 492 493 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 494 int height, int depth) 495 { 496 DeviceState *dev; 497 SysBusDevice *s; 498 499 dev = qdev_new("SUNW,tcx"); 500 qdev_prop_set_uint32(dev, "vram_size", vram_size); 501 qdev_prop_set_uint16(dev, "width", width); 502 qdev_prop_set_uint16(dev, "height", height); 503 qdev_prop_set_uint16(dev, "depth", depth); 504 s = SYS_BUS_DEVICE(dev); 505 sysbus_realize_and_unref(s, &error_fatal); 506 507 /* 10/ROM : FCode ROM */ 508 sysbus_mmio_map(s, 0, addr); 509 /* 2/STIP : Stipple */ 510 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 511 /* 3/BLIT : Blitter */ 512 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 513 /* 5/RSTIP : Raw Stipple */ 514 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 515 /* 6/RBLIT : Raw Blitter */ 516 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 517 /* 7/TEC : Transform Engine */ 518 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 519 /* 8/CMAP : DAC */ 520 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 521 /* 9/THC : */ 522 if (depth == 8) { 523 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 524 } else { 525 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 526 } 527 /* 11/DHC : */ 528 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 529 /* 12/ALT : */ 530 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 531 /* 0/DFB8 : 8-bit plane */ 532 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 533 /* 1/DFB24 : 24bit plane */ 534 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 535 /* 4/RDFB32: Raw framebuffer. Control plane */ 536 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 537 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 538 if (depth == 8) { 539 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 540 } 541 542 sysbus_connect_irq(s, 0, irq); 543 } 544 545 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 546 int height, int depth) 547 { 548 DeviceState *dev; 549 SysBusDevice *s; 550 551 dev = qdev_new("cgthree"); 552 qdev_prop_set_uint32(dev, "vram-size", vram_size); 553 qdev_prop_set_uint16(dev, "width", width); 554 qdev_prop_set_uint16(dev, "height", height); 555 qdev_prop_set_uint16(dev, "depth", depth); 556 s = SYS_BUS_DEVICE(dev); 557 sysbus_realize_and_unref(s, &error_fatal); 558 559 /* FCode ROM */ 560 sysbus_mmio_map(s, 0, addr); 561 /* DAC */ 562 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 563 /* 8-bit plane */ 564 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 565 566 sysbus_connect_irq(s, 0, irq); 567 } 568 569 /* NCR89C100/MACIO Internal ID register */ 570 571 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 572 573 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 574 575 static void idreg_init(hwaddr addr) 576 { 577 DeviceState *dev; 578 SysBusDevice *s; 579 580 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 581 s = SYS_BUS_DEVICE(dev); 582 sysbus_realize_and_unref(s, &error_fatal); 583 584 sysbus_mmio_map(s, 0, addr); 585 address_space_write_rom(&address_space_memory, addr, 586 MEMTXATTRS_UNSPECIFIED, 587 idreg_data, sizeof(idreg_data)); 588 } 589 590 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 591 592 struct IDRegState { 593 SysBusDevice parent_obj; 594 595 MemoryRegion mem; 596 }; 597 598 static void idreg_realize(DeviceState *ds, Error **errp) 599 { 600 IDRegState *s = MACIO_ID_REGISTER(ds); 601 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 602 Error *local_err = NULL; 603 604 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 605 sizeof(idreg_data), &local_err); 606 if (local_err) { 607 error_propagate(errp, local_err); 608 return; 609 } 610 611 vmstate_register_ram_global(&s->mem); 612 memory_region_set_readonly(&s->mem, true); 613 sysbus_init_mmio(dev, &s->mem); 614 } 615 616 static void idreg_class_init(ObjectClass *oc, void *data) 617 { 618 DeviceClass *dc = DEVICE_CLASS(oc); 619 620 dc->realize = idreg_realize; 621 } 622 623 static const TypeInfo idreg_info = { 624 .name = TYPE_MACIO_ID_REGISTER, 625 .parent = TYPE_SYS_BUS_DEVICE, 626 .instance_size = sizeof(IDRegState), 627 .class_init = idreg_class_init, 628 }; 629 630 #define TYPE_TCX_AFX "tcx_afx" 631 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 632 633 struct AFXState { 634 SysBusDevice parent_obj; 635 636 MemoryRegion mem; 637 }; 638 639 /* SS-5 TCX AFX register */ 640 static void afx_init(hwaddr addr) 641 { 642 DeviceState *dev; 643 SysBusDevice *s; 644 645 dev = qdev_new(TYPE_TCX_AFX); 646 s = SYS_BUS_DEVICE(dev); 647 sysbus_realize_and_unref(s, &error_fatal); 648 649 sysbus_mmio_map(s, 0, addr); 650 } 651 652 static void afx_realize(DeviceState *ds, Error **errp) 653 { 654 AFXState *s = TCX_AFX(ds); 655 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 656 Error *local_err = NULL; 657 658 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 659 &local_err); 660 if (local_err) { 661 error_propagate(errp, local_err); 662 return; 663 } 664 665 vmstate_register_ram_global(&s->mem); 666 sysbus_init_mmio(dev, &s->mem); 667 } 668 669 static void afx_class_init(ObjectClass *oc, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(oc); 672 673 dc->realize = afx_realize; 674 } 675 676 static const TypeInfo afx_info = { 677 .name = TYPE_TCX_AFX, 678 .parent = TYPE_SYS_BUS_DEVICE, 679 .instance_size = sizeof(AFXState), 680 .class_init = afx_class_init, 681 }; 682 683 #define TYPE_OPENPROM "openprom" 684 typedef struct PROMState PROMState; 685 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 686 TYPE_OPENPROM) 687 688 struct PROMState { 689 SysBusDevice parent_obj; 690 691 MemoryRegion prom; 692 }; 693 694 /* Boot PROM (OpenBIOS) */ 695 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 696 { 697 hwaddr *base_addr = (hwaddr *)opaque; 698 return addr + *base_addr - PROM_VADDR; 699 } 700 701 static void prom_init(hwaddr addr, const char *bios_name) 702 { 703 DeviceState *dev; 704 SysBusDevice *s; 705 char *filename; 706 int ret; 707 708 dev = qdev_new(TYPE_OPENPROM); 709 s = SYS_BUS_DEVICE(dev); 710 sysbus_realize_and_unref(s, &error_fatal); 711 712 sysbus_mmio_map(s, 0, addr); 713 714 /* load boot prom */ 715 if (bios_name == NULL) { 716 bios_name = PROM_FILENAME; 717 } 718 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 719 if (filename) { 720 ret = load_elf(filename, NULL, 721 translate_prom_address, &addr, NULL, 722 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 723 if (ret < 0 || ret > PROM_SIZE_MAX) { 724 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 725 } 726 g_free(filename); 727 } else { 728 ret = -1; 729 } 730 if (ret < 0 || ret > PROM_SIZE_MAX) { 731 error_report("could not load prom '%s'", bios_name); 732 exit(1); 733 } 734 } 735 736 static void prom_realize(DeviceState *ds, Error **errp) 737 { 738 PROMState *s = OPENPROM(ds); 739 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 740 Error *local_err = NULL; 741 742 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 743 PROM_SIZE_MAX, &local_err); 744 if (local_err) { 745 error_propagate(errp, local_err); 746 return; 747 } 748 749 vmstate_register_ram_global(&s->prom); 750 memory_region_set_readonly(&s->prom, true); 751 sysbus_init_mmio(dev, &s->prom); 752 } 753 754 static Property prom_properties[] = { 755 {/* end of property list */}, 756 }; 757 758 static void prom_class_init(ObjectClass *klass, void *data) 759 { 760 DeviceClass *dc = DEVICE_CLASS(klass); 761 762 device_class_set_props(dc, prom_properties); 763 dc->realize = prom_realize; 764 } 765 766 static const TypeInfo prom_info = { 767 .name = TYPE_OPENPROM, 768 .parent = TYPE_SYS_BUS_DEVICE, 769 .instance_size = sizeof(PROMState), 770 .class_init = prom_class_init, 771 }; 772 773 #define TYPE_SUN4M_MEMORY "memory" 774 typedef struct RamDevice RamDevice; 775 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 776 TYPE_SUN4M_MEMORY) 777 778 struct RamDevice { 779 SysBusDevice parent_obj; 780 HostMemoryBackend *memdev; 781 }; 782 783 /* System RAM */ 784 static void ram_realize(DeviceState *dev, Error **errp) 785 { 786 RamDevice *d = SUN4M_RAM(dev); 787 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 788 789 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 790 } 791 792 static void ram_initfn(Object *obj) 793 { 794 RamDevice *d = SUN4M_RAM(obj); 795 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 796 (Object **)&d->memdev, 797 object_property_allow_set_link, 798 OBJ_PROP_LINK_STRONG); 799 object_property_set_description(obj, "memdev", "Set RAM backend" 800 "Valid value is ID of a hostmem backend"); 801 } 802 803 static void ram_class_init(ObjectClass *klass, void *data) 804 { 805 DeviceClass *dc = DEVICE_CLASS(klass); 806 807 dc->realize = ram_realize; 808 } 809 810 static const TypeInfo ram_info = { 811 .name = TYPE_SUN4M_MEMORY, 812 .parent = TYPE_SYS_BUS_DEVICE, 813 .instance_size = sizeof(RamDevice), 814 .instance_init = ram_initfn, 815 .class_init = ram_class_init, 816 }; 817 818 static void cpu_devinit(const char *cpu_type, unsigned int id, 819 uint64_t prom_addr, qemu_irq **cpu_irqs) 820 { 821 SPARCCPU *cpu; 822 CPUSPARCState *env; 823 824 cpu = SPARC_CPU(object_new(cpu_type)); 825 env = &cpu->env; 826 827 cpu_sparc_set_id(env, id); 828 qemu_register_reset(sun4m_cpu_reset, cpu); 829 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 830 &error_fatal); 831 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 832 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 833 env->prom_addr = prom_addr; 834 } 835 836 static void dummy_fdc_tc(void *opaque, int irq, int level) 837 { 838 } 839 840 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, 841 MachineState *machine) 842 { 843 DeviceState *slavio_intctl; 844 unsigned int i; 845 Nvram *nvram; 846 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 847 qemu_irq fdc_tc; 848 unsigned long kernel_size; 849 uint32_t initrd_size; 850 DriveInfo *fd[MAX_FD]; 851 FWCfgState *fw_cfg; 852 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 853 SysBusDevice *s; 854 unsigned int smp_cpus = machine->smp.cpus; 855 unsigned int max_cpus = machine->smp.max_cpus; 856 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, 857 TYPE_MEMORY_BACKEND, NULL); 858 NICInfo *nd = &nd_table[0]; 859 860 if (machine->ram_size > hwdef->max_mem) { 861 error_report("Too much memory for this machine: %" PRId64 "," 862 " maximum %" PRId64, 863 machine->ram_size / MiB, hwdef->max_mem / MiB); 864 exit(1); 865 } 866 867 /* init CPUs */ 868 for(i = 0; i < smp_cpus; i++) { 869 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 870 } 871 872 for (i = smp_cpus; i < MAX_CPUS; i++) 873 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 874 875 /* Create and map RAM frontend */ 876 dev = qdev_new("memory"); 877 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); 878 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 879 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 880 881 /* models without ECC don't trap when missing ram is accessed */ 882 if (!hwdef->ecc_base) { 883 empty_slot_init("ecc", machine->ram_size, 884 hwdef->max_mem - machine->ram_size); 885 } 886 887 prom_init(hwdef->slavio_base, machine->firmware); 888 889 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 890 hwdef->intctl_base + 0x10000ULL, 891 cpu_irqs); 892 893 for (i = 0; i < 32; i++) { 894 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 895 } 896 for (i = 0; i < MAX_CPUS; i++) { 897 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 898 } 899 900 if (hwdef->idreg_base) { 901 idreg_init(hwdef->idreg_base); 902 } 903 904 if (hwdef->afx_base) { 905 afx_init(hwdef->afx_base); 906 } 907 908 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 909 910 if (hwdef->iommu_pad_base) { 911 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 912 Software shouldn't use aliased addresses, neither should it crash 913 when does. Using empty_slot instead of aliasing can help with 914 debugging such accesses */ 915 empty_slot_init("iommu.alias", 916 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 917 } 918 919 qemu_check_nic_model(nd, TYPE_LANCE); 920 sparc32_dma_init(hwdef->dma_base, 921 hwdef->esp_base, slavio_irq[18], 922 hwdef->le_base, slavio_irq[16], nd); 923 924 if (graphic_depth != 8 && graphic_depth != 24) { 925 error_report("Unsupported depth: %d", graphic_depth); 926 exit (1); 927 } 928 if (vga_interface_type != VGA_NONE) { 929 if (vga_interface_type == VGA_CG3) { 930 if (graphic_depth != 8) { 931 error_report("Unsupported depth: %d", graphic_depth); 932 exit(1); 933 } 934 935 if (!(graphic_width == 1024 && graphic_height == 768) && 936 !(graphic_width == 1152 && graphic_height == 900)) { 937 error_report("Unsupported resolution: %d x %d", graphic_width, 938 graphic_height); 939 exit(1); 940 } 941 942 /* sbus irq 5 */ 943 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 944 graphic_width, graphic_height, graphic_depth); 945 } else { 946 /* If no display specified, default to TCX */ 947 if (graphic_depth != 8 && graphic_depth != 24) { 948 error_report("Unsupported depth: %d", graphic_depth); 949 exit(1); 950 } 951 952 if (!(graphic_width == 1024 && graphic_height == 768)) { 953 error_report("Unsupported resolution: %d x %d", 954 graphic_width, graphic_height); 955 exit(1); 956 } 957 958 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 959 graphic_width, graphic_height, graphic_depth); 960 } 961 } 962 963 for (i = 0; i < MAX_VSIMMS; i++) { 964 /* vsimm registers probed by OBP */ 965 if (hwdef->vsimm[i].reg_base) { 966 char *name = g_strdup_printf("vsimm[%d]", i); 967 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 968 g_free(name); 969 } 970 } 971 972 if (hwdef->sx_base) { 973 create_unimplemented_device("SUNW,sx", hwdef->sx_base, 0x2000); 974 } 975 976 dev = qdev_new("sysbus-m48t08"); 977 qdev_prop_set_int32(dev, "base-year", 1968); 978 s = SYS_BUS_DEVICE(dev); 979 sysbus_realize_and_unref(s, &error_fatal); 980 sysbus_connect_irq(s, 0, slavio_irq[0]); 981 sysbus_mmio_map(s, 0, hwdef->nvram_base); 982 nvram = NVRAM(dev); 983 984 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 985 986 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 987 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 988 dev = qdev_new(TYPE_ESCC); 989 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 990 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 991 qdev_prop_set_uint32(dev, "it_shift", 1); 992 qdev_prop_set_chr(dev, "chrB", NULL); 993 qdev_prop_set_chr(dev, "chrA", NULL); 994 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 995 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 996 s = SYS_BUS_DEVICE(dev); 997 sysbus_realize_and_unref(s, &error_fatal); 998 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 999 1000 /* Logically OR both its IRQs together */ 1001 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1002 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 1003 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 1004 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 1005 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 1006 qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]); 1007 1008 dev = qdev_new(TYPE_ESCC); 1009 qdev_prop_set_uint32(dev, "disabled", 0); 1010 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 1011 qdev_prop_set_uint32(dev, "it_shift", 1); 1012 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 1013 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 1014 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 1015 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 1016 1017 s = SYS_BUS_DEVICE(dev); 1018 sysbus_realize_and_unref(s, &error_fatal); 1019 sysbus_mmio_map(s, 0, hwdef->serial_base); 1020 1021 /* Logically OR both its IRQs together */ 1022 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1023 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 1024 &error_fatal); 1025 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 1026 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 1027 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 1028 qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]); 1029 1030 if (hwdef->apc_base) { 1031 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1032 } 1033 1034 if (hwdef->fd_base) { 1035 /* there is zero or one floppy drive */ 1036 memset(fd, 0, sizeof(fd)); 1037 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1038 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1039 &fdc_tc); 1040 } else { 1041 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1042 } 1043 1044 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1045 slavio_irq[30], fdc_tc); 1046 1047 if (hwdef->cs_base) { 1048 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, 1049 slavio_irq[5]); 1050 } 1051 1052 if (hwdef->dbri_base) { 1053 /* ISDN chip with attached CS4215 audio codec */ 1054 /* prom space */ 1055 create_unimplemented_device("SUNW,DBRI.prom", 1056 hwdef->dbri_base + 0x1000, 0x30); 1057 /* reg space */ 1058 create_unimplemented_device("SUNW,DBRI", 1059 hwdef->dbri_base + 0x10000, 0x100); 1060 } 1061 1062 if (hwdef->bpp_base) { 1063 /* parallel port */ 1064 create_unimplemented_device("SUNW,bpp", hwdef->bpp_base, 0x20); 1065 } 1066 1067 initrd_size = 0; 1068 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1069 machine->initrd_filename, 1070 machine->ram_size, &initrd_size); 1071 1072 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, 1073 machine->boot_order, machine->ram_size, kernel_size, 1074 graphic_width, graphic_height, graphic_depth, 1075 hwdef->nvram_machine_id, "Sun4m"); 1076 1077 if (hwdef->ecc_base) 1078 ecc_init(hwdef->ecc_base, slavio_irq[28], 1079 hwdef->ecc_version); 1080 1081 dev = qdev_new(TYPE_FW_CFG_MEM); 1082 fw_cfg = FW_CFG(dev); 1083 qdev_prop_set_uint32(dev, "data_width", 1); 1084 qdev_prop_set_bit(dev, "dma_enabled", false); 1085 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1086 OBJECT(fw_cfg)); 1087 s = SYS_BUS_DEVICE(dev); 1088 sysbus_realize_and_unref(s, &error_fatal); 1089 sysbus_mmio_map(s, 0, CFG_ADDR); 1090 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1091 1092 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1093 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1094 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1095 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1096 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1097 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1098 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1099 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1100 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1101 if (machine->kernel_cmdline) { 1102 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1103 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1104 machine->kernel_cmdline); 1105 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1106 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1107 strlen(machine->kernel_cmdline) + 1); 1108 } else { 1109 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1110 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1111 } 1112 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1113 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1114 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1115 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1116 } 1117 1118 enum { 1119 ss5_id = 32, 1120 vger_id, 1121 lx_id, 1122 ss4_id, 1123 scls_id, 1124 sbook_id, 1125 ss10_id = 64, 1126 ss20_id, 1127 ss600mp_id, 1128 }; 1129 1130 static const struct sun4m_hwdef sun4m_hwdefs[] = { 1131 /* SS-5 */ 1132 { 1133 .iommu_base = 0x10000000, 1134 .iommu_pad_base = 0x10004000, 1135 .iommu_pad_len = 0x0fffb000, 1136 .tcx_base = 0x50000000, 1137 .cs_base = 0x6c000000, 1138 .slavio_base = 0x70000000, 1139 .ms_kb_base = 0x71000000, 1140 .serial_base = 0x71100000, 1141 .nvram_base = 0x71200000, 1142 .fd_base = 0x71400000, 1143 .counter_base = 0x71d00000, 1144 .intctl_base = 0x71e00000, 1145 .idreg_base = 0x78000000, 1146 .dma_base = 0x78400000, 1147 .esp_base = 0x78800000, 1148 .le_base = 0x78c00000, 1149 .apc_base = 0x6a000000, 1150 .afx_base = 0x6e000000, 1151 .aux1_base = 0x71900000, 1152 .aux2_base = 0x71910000, 1153 .nvram_machine_id = 0x80, 1154 .machine_id = ss5_id, 1155 .iommu_version = 0x05000000, 1156 .max_mem = 0x10000000, 1157 }, 1158 /* SS-10 */ 1159 { 1160 .iommu_base = 0xfe0000000ULL, 1161 .tcx_base = 0xe20000000ULL, 1162 .slavio_base = 0xff0000000ULL, 1163 .ms_kb_base = 0xff1000000ULL, 1164 .serial_base = 0xff1100000ULL, 1165 .nvram_base = 0xff1200000ULL, 1166 .fd_base = 0xff1700000ULL, 1167 .counter_base = 0xff1300000ULL, 1168 .intctl_base = 0xff1400000ULL, 1169 .idreg_base = 0xef0000000ULL, 1170 .dma_base = 0xef0400000ULL, 1171 .esp_base = 0xef0800000ULL, 1172 .le_base = 0xef0c00000ULL, 1173 .apc_base = 0xefa000000ULL, // XXX should not exist 1174 .aux1_base = 0xff1800000ULL, 1175 .aux2_base = 0xff1a01000ULL, 1176 .ecc_base = 0xf00000000ULL, 1177 .ecc_version = 0x10000000, // version 0, implementation 1 1178 .nvram_machine_id = 0x72, 1179 .machine_id = ss10_id, 1180 .iommu_version = 0x03000000, 1181 .max_mem = 0xf00000000ULL, 1182 }, 1183 /* SS-600MP */ 1184 { 1185 .iommu_base = 0xfe0000000ULL, 1186 .tcx_base = 0xe20000000ULL, 1187 .slavio_base = 0xff0000000ULL, 1188 .ms_kb_base = 0xff1000000ULL, 1189 .serial_base = 0xff1100000ULL, 1190 .nvram_base = 0xff1200000ULL, 1191 .counter_base = 0xff1300000ULL, 1192 .intctl_base = 0xff1400000ULL, 1193 .dma_base = 0xef0081000ULL, 1194 .esp_base = 0xef0080000ULL, 1195 .le_base = 0xef0060000ULL, 1196 .apc_base = 0xefa000000ULL, // XXX should not exist 1197 .aux1_base = 0xff1800000ULL, 1198 .aux2_base = 0xff1a01000ULL, // XXX should not exist 1199 .ecc_base = 0xf00000000ULL, 1200 .ecc_version = 0x00000000, // version 0, implementation 0 1201 .nvram_machine_id = 0x71, 1202 .machine_id = ss600mp_id, 1203 .iommu_version = 0x01000000, 1204 .max_mem = 0xf00000000ULL, 1205 }, 1206 /* SS-20 */ 1207 { 1208 .iommu_base = 0xfe0000000ULL, 1209 .tcx_base = 0xe20000000ULL, 1210 .slavio_base = 0xff0000000ULL, 1211 .ms_kb_base = 0xff1000000ULL, 1212 .serial_base = 0xff1100000ULL, 1213 .nvram_base = 0xff1200000ULL, 1214 .fd_base = 0xff1700000ULL, 1215 .counter_base = 0xff1300000ULL, 1216 .intctl_base = 0xff1400000ULL, 1217 .idreg_base = 0xef0000000ULL, 1218 .dma_base = 0xef0400000ULL, 1219 .esp_base = 0xef0800000ULL, 1220 .le_base = 0xef0c00000ULL, 1221 .bpp_base = 0xef4800000ULL, 1222 .apc_base = 0xefa000000ULL, // XXX should not exist 1223 .aux1_base = 0xff1800000ULL, 1224 .aux2_base = 0xff1a01000ULL, 1225 .dbri_base = 0xee0000000ULL, 1226 .sx_base = 0xf80000000ULL, 1227 .vsimm = { 1228 { 1229 .reg_base = 0x9c000000ULL, 1230 .vram_base = 0xfc000000ULL 1231 }, { 1232 .reg_base = 0x90000000ULL, 1233 .vram_base = 0xf0000000ULL 1234 }, { 1235 .reg_base = 0x94000000ULL 1236 }, { 1237 .reg_base = 0x98000000ULL 1238 } 1239 }, 1240 .ecc_base = 0xf00000000ULL, 1241 .ecc_version = 0x20000000, // version 0, implementation 2 1242 .nvram_machine_id = 0x72, 1243 .machine_id = ss20_id, 1244 .iommu_version = 0x13000000, 1245 .max_mem = 0xf00000000ULL, 1246 }, 1247 /* Voyager */ 1248 { 1249 .iommu_base = 0x10000000, 1250 .tcx_base = 0x50000000, 1251 .slavio_base = 0x70000000, 1252 .ms_kb_base = 0x71000000, 1253 .serial_base = 0x71100000, 1254 .nvram_base = 0x71200000, 1255 .fd_base = 0x71400000, 1256 .counter_base = 0x71d00000, 1257 .intctl_base = 0x71e00000, 1258 .idreg_base = 0x78000000, 1259 .dma_base = 0x78400000, 1260 .esp_base = 0x78800000, 1261 .le_base = 0x78c00000, 1262 .apc_base = 0x71300000, // pmc 1263 .aux1_base = 0x71900000, 1264 .aux2_base = 0x71910000, 1265 .nvram_machine_id = 0x80, 1266 .machine_id = vger_id, 1267 .iommu_version = 0x05000000, 1268 .max_mem = 0x10000000, 1269 }, 1270 /* LX */ 1271 { 1272 .iommu_base = 0x10000000, 1273 .iommu_pad_base = 0x10004000, 1274 .iommu_pad_len = 0x0fffb000, 1275 .tcx_base = 0x50000000, 1276 .slavio_base = 0x70000000, 1277 .ms_kb_base = 0x71000000, 1278 .serial_base = 0x71100000, 1279 .nvram_base = 0x71200000, 1280 .fd_base = 0x71400000, 1281 .counter_base = 0x71d00000, 1282 .intctl_base = 0x71e00000, 1283 .idreg_base = 0x78000000, 1284 .dma_base = 0x78400000, 1285 .esp_base = 0x78800000, 1286 .le_base = 0x78c00000, 1287 .aux1_base = 0x71900000, 1288 .aux2_base = 0x71910000, 1289 .nvram_machine_id = 0x80, 1290 .machine_id = lx_id, 1291 .iommu_version = 0x04000000, 1292 .max_mem = 0x10000000, 1293 }, 1294 /* SS-4 */ 1295 { 1296 .iommu_base = 0x10000000, 1297 .tcx_base = 0x50000000, 1298 .cs_base = 0x6c000000, 1299 .slavio_base = 0x70000000, 1300 .ms_kb_base = 0x71000000, 1301 .serial_base = 0x71100000, 1302 .nvram_base = 0x71200000, 1303 .fd_base = 0x71400000, 1304 .counter_base = 0x71d00000, 1305 .intctl_base = 0x71e00000, 1306 .idreg_base = 0x78000000, 1307 .dma_base = 0x78400000, 1308 .esp_base = 0x78800000, 1309 .le_base = 0x78c00000, 1310 .apc_base = 0x6a000000, 1311 .aux1_base = 0x71900000, 1312 .aux2_base = 0x71910000, 1313 .nvram_machine_id = 0x80, 1314 .machine_id = ss4_id, 1315 .iommu_version = 0x05000000, 1316 .max_mem = 0x10000000, 1317 }, 1318 /* SPARCClassic */ 1319 { 1320 .iommu_base = 0x10000000, 1321 .tcx_base = 0x50000000, 1322 .slavio_base = 0x70000000, 1323 .ms_kb_base = 0x71000000, 1324 .serial_base = 0x71100000, 1325 .nvram_base = 0x71200000, 1326 .fd_base = 0x71400000, 1327 .counter_base = 0x71d00000, 1328 .intctl_base = 0x71e00000, 1329 .idreg_base = 0x78000000, 1330 .dma_base = 0x78400000, 1331 .esp_base = 0x78800000, 1332 .le_base = 0x78c00000, 1333 .apc_base = 0x6a000000, 1334 .aux1_base = 0x71900000, 1335 .aux2_base = 0x71910000, 1336 .nvram_machine_id = 0x80, 1337 .machine_id = scls_id, 1338 .iommu_version = 0x05000000, 1339 .max_mem = 0x10000000, 1340 }, 1341 /* SPARCbook */ 1342 { 1343 .iommu_base = 0x10000000, 1344 .tcx_base = 0x50000000, // XXX 1345 .slavio_base = 0x70000000, 1346 .ms_kb_base = 0x71000000, 1347 .serial_base = 0x71100000, 1348 .nvram_base = 0x71200000, 1349 .fd_base = 0x71400000, 1350 .counter_base = 0x71d00000, 1351 .intctl_base = 0x71e00000, 1352 .idreg_base = 0x78000000, 1353 .dma_base = 0x78400000, 1354 .esp_base = 0x78800000, 1355 .le_base = 0x78c00000, 1356 .apc_base = 0x6a000000, 1357 .aux1_base = 0x71900000, 1358 .aux2_base = 0x71910000, 1359 .nvram_machine_id = 0x80, 1360 .machine_id = sbook_id, 1361 .iommu_version = 0x05000000, 1362 .max_mem = 0x10000000, 1363 }, 1364 }; 1365 1366 /* SPARCstation 5 hardware initialisation */ 1367 static void ss5_init(MachineState *machine) 1368 { 1369 sun4m_hw_init(&sun4m_hwdefs[0], machine); 1370 } 1371 1372 /* SPARCstation 10 hardware initialisation */ 1373 static void ss10_init(MachineState *machine) 1374 { 1375 sun4m_hw_init(&sun4m_hwdefs[1], machine); 1376 } 1377 1378 /* SPARCserver 600MP hardware initialisation */ 1379 static void ss600mp_init(MachineState *machine) 1380 { 1381 sun4m_hw_init(&sun4m_hwdefs[2], machine); 1382 } 1383 1384 /* SPARCstation 20 hardware initialisation */ 1385 static void ss20_init(MachineState *machine) 1386 { 1387 sun4m_hw_init(&sun4m_hwdefs[3], machine); 1388 } 1389 1390 /* SPARCstation Voyager hardware initialisation */ 1391 static void vger_init(MachineState *machine) 1392 { 1393 sun4m_hw_init(&sun4m_hwdefs[4], machine); 1394 } 1395 1396 /* SPARCstation LX hardware initialisation */ 1397 static void ss_lx_init(MachineState *machine) 1398 { 1399 sun4m_hw_init(&sun4m_hwdefs[5], machine); 1400 } 1401 1402 /* SPARCstation 4 hardware initialisation */ 1403 static void ss4_init(MachineState *machine) 1404 { 1405 sun4m_hw_init(&sun4m_hwdefs[6], machine); 1406 } 1407 1408 /* SPARCClassic hardware initialisation */ 1409 static void scls_init(MachineState *machine) 1410 { 1411 sun4m_hw_init(&sun4m_hwdefs[7], machine); 1412 } 1413 1414 /* SPARCbook hardware initialisation */ 1415 static void sbook_init(MachineState *machine) 1416 { 1417 sun4m_hw_init(&sun4m_hwdefs[8], machine); 1418 } 1419 1420 static void ss5_class_init(ObjectClass *oc, void *data) 1421 { 1422 MachineClass *mc = MACHINE_CLASS(oc); 1423 1424 mc->desc = "Sun4m platform, SPARCstation 5"; 1425 mc->init = ss5_init; 1426 mc->block_default_type = IF_SCSI; 1427 mc->is_default = true; 1428 mc->default_boot_order = "c"; 1429 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1430 mc->default_display = "tcx"; 1431 mc->default_ram_id = "sun4m.ram"; 1432 } 1433 1434 static const TypeInfo ss5_type = { 1435 .name = MACHINE_TYPE_NAME("SS-5"), 1436 .parent = TYPE_MACHINE, 1437 .class_init = ss5_class_init, 1438 }; 1439 1440 static void ss10_class_init(ObjectClass *oc, void *data) 1441 { 1442 MachineClass *mc = MACHINE_CLASS(oc); 1443 1444 mc->desc = "Sun4m platform, SPARCstation 10"; 1445 mc->init = ss10_init; 1446 mc->block_default_type = IF_SCSI; 1447 mc->max_cpus = 4; 1448 mc->default_boot_order = "c"; 1449 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1450 mc->default_display = "tcx"; 1451 mc->default_ram_id = "sun4m.ram"; 1452 } 1453 1454 static const TypeInfo ss10_type = { 1455 .name = MACHINE_TYPE_NAME("SS-10"), 1456 .parent = TYPE_MACHINE, 1457 .class_init = ss10_class_init, 1458 }; 1459 1460 static void ss600mp_class_init(ObjectClass *oc, void *data) 1461 { 1462 MachineClass *mc = MACHINE_CLASS(oc); 1463 1464 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1465 mc->init = ss600mp_init; 1466 mc->block_default_type = IF_SCSI; 1467 mc->max_cpus = 4; 1468 mc->default_boot_order = "c"; 1469 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1470 mc->default_display = "tcx"; 1471 mc->default_ram_id = "sun4m.ram"; 1472 } 1473 1474 static const TypeInfo ss600mp_type = { 1475 .name = MACHINE_TYPE_NAME("SS-600MP"), 1476 .parent = TYPE_MACHINE, 1477 .class_init = ss600mp_class_init, 1478 }; 1479 1480 static void ss20_class_init(ObjectClass *oc, void *data) 1481 { 1482 MachineClass *mc = MACHINE_CLASS(oc); 1483 1484 mc->desc = "Sun4m platform, SPARCstation 20"; 1485 mc->init = ss20_init; 1486 mc->block_default_type = IF_SCSI; 1487 mc->max_cpus = 4; 1488 mc->default_boot_order = "c"; 1489 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1490 mc->default_display = "tcx"; 1491 mc->default_ram_id = "sun4m.ram"; 1492 } 1493 1494 static const TypeInfo ss20_type = { 1495 .name = MACHINE_TYPE_NAME("SS-20"), 1496 .parent = TYPE_MACHINE, 1497 .class_init = ss20_class_init, 1498 }; 1499 1500 static void voyager_class_init(ObjectClass *oc, void *data) 1501 { 1502 MachineClass *mc = MACHINE_CLASS(oc); 1503 1504 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1505 mc->init = vger_init; 1506 mc->block_default_type = IF_SCSI; 1507 mc->default_boot_order = "c"; 1508 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1509 mc->default_display = "tcx"; 1510 mc->default_ram_id = "sun4m.ram"; 1511 } 1512 1513 static const TypeInfo voyager_type = { 1514 .name = MACHINE_TYPE_NAME("Voyager"), 1515 .parent = TYPE_MACHINE, 1516 .class_init = voyager_class_init, 1517 }; 1518 1519 static void ss_lx_class_init(ObjectClass *oc, void *data) 1520 { 1521 MachineClass *mc = MACHINE_CLASS(oc); 1522 1523 mc->desc = "Sun4m platform, SPARCstation LX"; 1524 mc->init = ss_lx_init; 1525 mc->block_default_type = IF_SCSI; 1526 mc->default_boot_order = "c"; 1527 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1528 mc->default_display = "tcx"; 1529 mc->default_ram_id = "sun4m.ram"; 1530 } 1531 1532 static const TypeInfo ss_lx_type = { 1533 .name = MACHINE_TYPE_NAME("LX"), 1534 .parent = TYPE_MACHINE, 1535 .class_init = ss_lx_class_init, 1536 }; 1537 1538 static void ss4_class_init(ObjectClass *oc, void *data) 1539 { 1540 MachineClass *mc = MACHINE_CLASS(oc); 1541 1542 mc->desc = "Sun4m platform, SPARCstation 4"; 1543 mc->init = ss4_init; 1544 mc->block_default_type = IF_SCSI; 1545 mc->default_boot_order = "c"; 1546 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1547 mc->default_display = "tcx"; 1548 mc->default_ram_id = "sun4m.ram"; 1549 } 1550 1551 static const TypeInfo ss4_type = { 1552 .name = MACHINE_TYPE_NAME("SS-4"), 1553 .parent = TYPE_MACHINE, 1554 .class_init = ss4_class_init, 1555 }; 1556 1557 static void scls_class_init(ObjectClass *oc, void *data) 1558 { 1559 MachineClass *mc = MACHINE_CLASS(oc); 1560 1561 mc->desc = "Sun4m platform, SPARCClassic"; 1562 mc->init = scls_init; 1563 mc->block_default_type = IF_SCSI; 1564 mc->default_boot_order = "c"; 1565 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1566 mc->default_display = "tcx"; 1567 mc->default_ram_id = "sun4m.ram"; 1568 } 1569 1570 static const TypeInfo scls_type = { 1571 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1572 .parent = TYPE_MACHINE, 1573 .class_init = scls_class_init, 1574 }; 1575 1576 static void sbook_class_init(ObjectClass *oc, void *data) 1577 { 1578 MachineClass *mc = MACHINE_CLASS(oc); 1579 1580 mc->desc = "Sun4m platform, SPARCbook"; 1581 mc->init = sbook_init; 1582 mc->block_default_type = IF_SCSI; 1583 mc->default_boot_order = "c"; 1584 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1585 mc->default_display = "tcx"; 1586 mc->default_ram_id = "sun4m.ram"; 1587 } 1588 1589 static const TypeInfo sbook_type = { 1590 .name = MACHINE_TYPE_NAME("SPARCbook"), 1591 .parent = TYPE_MACHINE, 1592 .class_init = sbook_class_init, 1593 }; 1594 1595 static void sun4m_register_types(void) 1596 { 1597 type_register_static(&idreg_info); 1598 type_register_static(&afx_info); 1599 type_register_static(&prom_info); 1600 type_register_static(&ram_info); 1601 1602 type_register_static(&ss5_type); 1603 type_register_static(&ss10_type); 1604 type_register_static(&ss600mp_type); 1605 type_register_static(&ss20_type); 1606 type_register_static(&voyager_type); 1607 type_register_static(&ss_lx_type); 1608 type_register_static(&ss4_type); 1609 type_register_static(&scls_type); 1610 type_register_static(&sbook_type); 1611 } 1612 1613 type_init(sun4m_register_types) 1614