1 /* 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator 3 * 4 * Copyright (c) 2003-2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qapi/error.h" 28 #include "qemu/datadir.h" 29 #include "cpu.h" 30 #include "hw/sysbus.h" 31 #include "qemu/error-report.h" 32 #include "qemu/timer.h" 33 #include "hw/sparc/sun4m_iommu.h" 34 #include "hw/rtc/m48t59.h" 35 #include "migration/vmstate.h" 36 #include "hw/sparc/sparc32_dma.h" 37 #include "hw/block/fdc.h" 38 #include "sysemu/reset.h" 39 #include "sysemu/runstate.h" 40 #include "sysemu/sysemu.h" 41 #include "net/net.h" 42 #include "hw/boards.h" 43 #include "hw/scsi/esp.h" 44 #include "hw/nvram/sun_nvram.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/nvram/chrp_nvram.h" 47 #include "hw/nvram/fw_cfg.h" 48 #include "hw/char/escc.h" 49 #include "hw/misc/empty_slot.h" 50 #include "hw/misc/unimp.h" 51 #include "hw/irq.h" 52 #include "hw/or-irq.h" 53 #include "hw/loader.h" 54 #include "elf.h" 55 #include "trace.h" 56 #include "qom/object.h" 57 58 /* 59 * Sun4m architecture was used in the following machines: 60 * 61 * SPARCserver 6xxMP/xx 62 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), 63 * SPARCclassic X (4/10) 64 * SPARCstation LX/ZX (4/30) 65 * SPARCstation Voyager 66 * SPARCstation 10/xx, SPARCserver 10/xx 67 * SPARCstation 5, SPARCserver 5 68 * SPARCstation 20/xx, SPARCserver 20 69 * SPARCstation 4 70 * 71 * See for example: http://www.sunhelp.org/faq/sunref1.html 72 */ 73 74 #define KERNEL_LOAD_ADDR 0x00004000 75 #define CMDLINE_ADDR 0x007ff000 76 #define INITRD_LOAD_ADDR 0x00800000 77 #define PROM_SIZE_MAX (1 * MiB) 78 #define PROM_VADDR 0xffd00000 79 #define PROM_FILENAME "openbios-sparc32" 80 #define CFG_ADDR 0xd00000510ULL 81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) 82 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) 83 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) 84 85 #define MAX_CPUS 16 86 #define MAX_PILS 16 87 #define MAX_VSIMMS 4 88 89 #define ESCC_CLOCK 4915200 90 91 struct sun4m_hwdef { 92 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; 93 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; 94 hwaddr serial_base, fd_base; 95 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; 96 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; 97 hwaddr bpp_base, dbri_base, sx_base; 98 struct { 99 hwaddr reg_base, vram_base; 100 } vsimm[MAX_VSIMMS]; 101 hwaddr ecc_base; 102 uint64_t max_mem; 103 uint32_t ecc_version; 104 uint32_t iommu_version; 105 uint16_t machine_id; 106 uint8_t nvram_machine_id; 107 }; 108 109 struct Sun4mMachineClass { 110 /*< private >*/ 111 MachineClass parent_obj; 112 /*< public >*/ 113 const struct sun4m_hwdef *hwdef; 114 }; 115 typedef struct Sun4mMachineClass Sun4mMachineClass; 116 117 #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") 118 DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) 119 120 const char *fw_cfg_arch_key_name(uint16_t key) 121 { 122 static const struct { 123 uint16_t key; 124 const char *name; 125 } fw_cfg_arch_wellknown_keys[] = { 126 {FW_CFG_SUN4M_DEPTH, "depth"}, 127 {FW_CFG_SUN4M_WIDTH, "width"}, 128 {FW_CFG_SUN4M_HEIGHT, "height"}, 129 }; 130 131 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { 132 if (fw_cfg_arch_wellknown_keys[i].key == key) { 133 return fw_cfg_arch_wellknown_keys[i].name; 134 } 135 } 136 return NULL; 137 } 138 139 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 140 Error **errp) 141 { 142 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 143 } 144 145 static void nvram_init(Nvram *nvram, uint8_t *macaddr, 146 const char *cmdline, const char *boot_devices, 147 ram_addr_t RAM_size, uint32_t kernel_size, 148 int width, int height, int depth, 149 int nvram_machine_id, const char *arch) 150 { 151 unsigned int i; 152 int sysp_end; 153 uint8_t image[0x1ff0]; 154 NvramClass *k = NVRAM_GET_CLASS(nvram); 155 156 memset(image, '\0', sizeof(image)); 157 158 /* OpenBIOS nvram variables partition */ 159 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); 160 161 /* Free space partition */ 162 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 163 164 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 165 nvram_machine_id); 166 167 for (i = 0; i < sizeof(image); i++) { 168 (k->write)(nvram, i, image[i]); 169 } 170 } 171 172 static void cpu_kick_irq(SPARCCPU *cpu) 173 { 174 CPUSPARCState *env = &cpu->env; 175 CPUState *cs = CPU(cpu); 176 177 cs->halted = 0; 178 cpu_check_irqs(env); 179 qemu_cpu_kick(cs); 180 } 181 182 static void cpu_set_irq(void *opaque, int irq, int level) 183 { 184 SPARCCPU *cpu = opaque; 185 CPUSPARCState *env = &cpu->env; 186 187 if (level) { 188 trace_sun4m_cpu_set_irq_raise(irq); 189 env->pil_in |= 1 << irq; 190 cpu_kick_irq(cpu); 191 } else { 192 trace_sun4m_cpu_set_irq_lower(irq); 193 env->pil_in &= ~(1 << irq); 194 cpu_check_irqs(env); 195 } 196 } 197 198 static void dummy_cpu_set_irq(void *opaque, int irq, int level) 199 { 200 } 201 202 static void sun4m_cpu_reset(void *opaque) 203 { 204 SPARCCPU *cpu = opaque; 205 CPUState *cs = CPU(cpu); 206 207 cpu_reset(cs); 208 } 209 210 static void cpu_halt_signal(void *opaque, int irq, int level) 211 { 212 if (level && current_cpu) { 213 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); 214 } 215 } 216 217 static uint64_t translate_kernel_address(void *opaque, uint64_t addr) 218 { 219 return addr - 0xf0000000ULL; 220 } 221 222 static unsigned long sun4m_load_kernel(const char *kernel_filename, 223 const char *initrd_filename, 224 ram_addr_t RAM_size, 225 uint32_t *initrd_size) 226 { 227 int linux_boot; 228 unsigned int i; 229 long kernel_size; 230 uint8_t *ptr; 231 232 linux_boot = (kernel_filename != NULL); 233 234 kernel_size = 0; 235 if (linux_boot) { 236 int bswap_needed; 237 238 #ifdef BSWAP_NEEDED 239 bswap_needed = 1; 240 #else 241 bswap_needed = 0; 242 #endif 243 kernel_size = load_elf(kernel_filename, NULL, 244 translate_kernel_address, NULL, 245 NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 246 if (kernel_size < 0) 247 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 248 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 249 TARGET_PAGE_SIZE); 250 if (kernel_size < 0) 251 kernel_size = load_image_targphys(kernel_filename, 252 KERNEL_LOAD_ADDR, 253 RAM_size - KERNEL_LOAD_ADDR); 254 if (kernel_size < 0) { 255 error_report("could not load kernel '%s'", kernel_filename); 256 exit(1); 257 } 258 259 /* load initrd */ 260 *initrd_size = 0; 261 if (initrd_filename) { 262 *initrd_size = load_image_targphys(initrd_filename, 263 INITRD_LOAD_ADDR, 264 RAM_size - INITRD_LOAD_ADDR); 265 if ((int)*initrd_size < 0) { 266 error_report("could not load initial ram disk '%s'", 267 initrd_filename); 268 exit(1); 269 } 270 } 271 if (*initrd_size > 0) { 272 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 273 ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); 274 if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ 275 stl_p(ptr + 16, INITRD_LOAD_ADDR); 276 stl_p(ptr + 20, *initrd_size); 277 break; 278 } 279 } 280 } 281 } 282 return kernel_size; 283 } 284 285 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) 286 { 287 DeviceState *dev; 288 SysBusDevice *s; 289 290 dev = qdev_new(TYPE_SUN4M_IOMMU); 291 qdev_prop_set_uint32(dev, "version", version); 292 s = SYS_BUS_DEVICE(dev); 293 sysbus_realize_and_unref(s, &error_fatal); 294 sysbus_connect_irq(s, 0, irq); 295 sysbus_mmio_map(s, 0, addr); 296 297 return s; 298 } 299 300 static void *sparc32_dma_init(hwaddr dma_base, 301 hwaddr esp_base, qemu_irq espdma_irq, 302 hwaddr le_base, qemu_irq ledma_irq, NICInfo *nd) 303 { 304 DeviceState *dma; 305 ESPDMADeviceState *espdma; 306 LEDMADeviceState *ledma; 307 SysBusESPState *esp; 308 SysBusPCNetState *lance; 309 310 dma = qdev_new(TYPE_SPARC32_DMA); 311 espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( 312 OBJECT(dma), "espdma")); 313 sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); 314 315 esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); 316 317 ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( 318 OBJECT(dma), "ledma")); 319 sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); 320 321 lance = SYSBUS_PCNET(object_resolve_path_component( 322 OBJECT(ledma), "lance")); 323 qdev_set_nic_properties(DEVICE(lance), nd); 324 325 sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); 326 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); 327 328 sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); 329 scsi_bus_legacy_handle_cmdline(&esp->esp.bus); 330 331 sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); 332 333 return dma; 334 } 335 336 static DeviceState *slavio_intctl_init(hwaddr addr, 337 hwaddr addrg, 338 qemu_irq **parent_irq) 339 { 340 DeviceState *dev; 341 SysBusDevice *s; 342 unsigned int i, j; 343 344 dev = qdev_new("slavio_intctl"); 345 346 s = SYS_BUS_DEVICE(dev); 347 sysbus_realize_and_unref(s, &error_fatal); 348 349 for (i = 0; i < MAX_CPUS; i++) { 350 for (j = 0; j < MAX_PILS; j++) { 351 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); 352 } 353 } 354 sysbus_mmio_map(s, 0, addrg); 355 for (i = 0; i < MAX_CPUS; i++) { 356 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); 357 } 358 359 return dev; 360 } 361 362 #define SYS_TIMER_OFFSET 0x10000ULL 363 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) 364 365 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, 366 qemu_irq *cpu_irqs, unsigned int num_cpus) 367 { 368 DeviceState *dev; 369 SysBusDevice *s; 370 unsigned int i; 371 372 dev = qdev_new("slavio_timer"); 373 qdev_prop_set_uint32(dev, "num_cpus", num_cpus); 374 s = SYS_BUS_DEVICE(dev); 375 sysbus_realize_and_unref(s, &error_fatal); 376 sysbus_connect_irq(s, 0, master_irq); 377 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); 378 379 for (i = 0; i < MAX_CPUS; i++) { 380 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); 381 sysbus_connect_irq(s, i + 1, cpu_irqs[i]); 382 } 383 } 384 385 static qemu_irq slavio_system_powerdown; 386 387 static void slavio_powerdown_req(Notifier *n, void *opaque) 388 { 389 qemu_irq_raise(slavio_system_powerdown); 390 } 391 392 static Notifier slavio_system_powerdown_notifier = { 393 .notify = slavio_powerdown_req 394 }; 395 396 #define MISC_LEDS 0x01600000 397 #define MISC_CFG 0x01800000 398 #define MISC_DIAG 0x01a00000 399 #define MISC_MDM 0x01b00000 400 #define MISC_SYS 0x01f00000 401 402 static void slavio_misc_init(hwaddr base, 403 hwaddr aux1_base, 404 hwaddr aux2_base, qemu_irq irq, 405 qemu_irq fdc_tc) 406 { 407 DeviceState *dev; 408 SysBusDevice *s; 409 410 dev = qdev_new("slavio_misc"); 411 s = SYS_BUS_DEVICE(dev); 412 sysbus_realize_and_unref(s, &error_fatal); 413 if (base) { 414 /* 8 bit registers */ 415 /* Slavio control */ 416 sysbus_mmio_map(s, 0, base + MISC_CFG); 417 /* Diagnostics */ 418 sysbus_mmio_map(s, 1, base + MISC_DIAG); 419 /* Modem control */ 420 sysbus_mmio_map(s, 2, base + MISC_MDM); 421 /* 16 bit registers */ 422 /* ss600mp diag LEDs */ 423 sysbus_mmio_map(s, 3, base + MISC_LEDS); 424 /* 32 bit registers */ 425 /* System control */ 426 sysbus_mmio_map(s, 4, base + MISC_SYS); 427 } 428 if (aux1_base) { 429 /* AUX 1 (Misc System Functions) */ 430 sysbus_mmio_map(s, 5, aux1_base); 431 } 432 if (aux2_base) { 433 /* AUX 2 (Software Powerdown Control) */ 434 sysbus_mmio_map(s, 6, aux2_base); 435 } 436 sysbus_connect_irq(s, 0, irq); 437 sysbus_connect_irq(s, 1, fdc_tc); 438 slavio_system_powerdown = qdev_get_gpio_in(dev, 0); 439 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); 440 } 441 442 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) 443 { 444 DeviceState *dev; 445 SysBusDevice *s; 446 447 dev = qdev_new("eccmemctl"); 448 qdev_prop_set_uint32(dev, "version", version); 449 s = SYS_BUS_DEVICE(dev); 450 sysbus_realize_and_unref(s, &error_fatal); 451 sysbus_connect_irq(s, 0, irq); 452 sysbus_mmio_map(s, 0, base); 453 if (version == 0) { // SS-600MP only 454 sysbus_mmio_map(s, 1, base + 0x1000); 455 } 456 } 457 458 static void apc_init(hwaddr power_base, qemu_irq cpu_halt) 459 { 460 DeviceState *dev; 461 SysBusDevice *s; 462 463 dev = qdev_new("apc"); 464 s = SYS_BUS_DEVICE(dev); 465 sysbus_realize_and_unref(s, &error_fatal); 466 /* Power management (APC) XXX: not a Slavio device */ 467 sysbus_mmio_map(s, 0, power_base); 468 sysbus_connect_irq(s, 0, cpu_halt); 469 } 470 471 static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 472 int height, int depth) 473 { 474 DeviceState *dev; 475 SysBusDevice *s; 476 477 dev = qdev_new("sun-tcx"); 478 qdev_prop_set_uint32(dev, "vram_size", vram_size); 479 qdev_prop_set_uint16(dev, "width", width); 480 qdev_prop_set_uint16(dev, "height", height); 481 qdev_prop_set_uint16(dev, "depth", depth); 482 s = SYS_BUS_DEVICE(dev); 483 sysbus_realize_and_unref(s, &error_fatal); 484 485 /* 10/ROM : FCode ROM */ 486 sysbus_mmio_map(s, 0, addr); 487 /* 2/STIP : Stipple */ 488 sysbus_mmio_map(s, 1, addr + 0x04000000ULL); 489 /* 3/BLIT : Blitter */ 490 sysbus_mmio_map(s, 2, addr + 0x06000000ULL); 491 /* 5/RSTIP : Raw Stipple */ 492 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); 493 /* 6/RBLIT : Raw Blitter */ 494 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); 495 /* 7/TEC : Transform Engine */ 496 sysbus_mmio_map(s, 5, addr + 0x00700000ULL); 497 /* 8/CMAP : DAC */ 498 sysbus_mmio_map(s, 6, addr + 0x00200000ULL); 499 /* 9/THC : */ 500 if (depth == 8) { 501 sysbus_mmio_map(s, 7, addr + 0x00300000ULL); 502 } else { 503 sysbus_mmio_map(s, 7, addr + 0x00301000ULL); 504 } 505 /* 11/DHC : */ 506 sysbus_mmio_map(s, 8, addr + 0x00240000ULL); 507 /* 12/ALT : */ 508 sysbus_mmio_map(s, 9, addr + 0x00280000ULL); 509 /* 0/DFB8 : 8-bit plane */ 510 sysbus_mmio_map(s, 10, addr + 0x00800000ULL); 511 /* 1/DFB24 : 24bit plane */ 512 sysbus_mmio_map(s, 11, addr + 0x02000000ULL); 513 /* 4/RDFB32: Raw framebuffer. Control plane */ 514 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); 515 /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ 516 if (depth == 8) { 517 sysbus_mmio_map(s, 13, addr + 0x00301000ULL); 518 } 519 520 sysbus_connect_irq(s, 0, irq); 521 } 522 523 static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, 524 int height, int depth) 525 { 526 DeviceState *dev; 527 SysBusDevice *s; 528 529 dev = qdev_new("cgthree"); 530 qdev_prop_set_uint32(dev, "vram-size", vram_size); 531 qdev_prop_set_uint16(dev, "width", width); 532 qdev_prop_set_uint16(dev, "height", height); 533 qdev_prop_set_uint16(dev, "depth", depth); 534 s = SYS_BUS_DEVICE(dev); 535 sysbus_realize_and_unref(s, &error_fatal); 536 537 /* FCode ROM */ 538 sysbus_mmio_map(s, 0, addr); 539 /* DAC */ 540 sysbus_mmio_map(s, 1, addr + 0x400000ULL); 541 /* 8-bit plane */ 542 sysbus_mmio_map(s, 2, addr + 0x800000ULL); 543 544 sysbus_connect_irq(s, 0, irq); 545 } 546 547 /* NCR89C100/MACIO Internal ID register */ 548 549 #define TYPE_MACIO_ID_REGISTER "macio_idreg" 550 551 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; 552 553 static void idreg_init(hwaddr addr) 554 { 555 DeviceState *dev; 556 SysBusDevice *s; 557 558 dev = qdev_new(TYPE_MACIO_ID_REGISTER); 559 s = SYS_BUS_DEVICE(dev); 560 sysbus_realize_and_unref(s, &error_fatal); 561 562 sysbus_mmio_map(s, 0, addr); 563 address_space_write_rom(&address_space_memory, addr, 564 MEMTXATTRS_UNSPECIFIED, 565 idreg_data, sizeof(idreg_data)); 566 } 567 568 OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) 569 570 struct IDRegState { 571 SysBusDevice parent_obj; 572 573 MemoryRegion mem; 574 }; 575 576 static void idreg_realize(DeviceState *ds, Error **errp) 577 { 578 IDRegState *s = MACIO_ID_REGISTER(ds); 579 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 580 Error *local_err = NULL; 581 582 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", 583 sizeof(idreg_data), &local_err); 584 if (local_err) { 585 error_propagate(errp, local_err); 586 return; 587 } 588 589 vmstate_register_ram_global(&s->mem); 590 memory_region_set_readonly(&s->mem, true); 591 sysbus_init_mmio(dev, &s->mem); 592 } 593 594 static void idreg_class_init(ObjectClass *oc, void *data) 595 { 596 DeviceClass *dc = DEVICE_CLASS(oc); 597 598 dc->realize = idreg_realize; 599 } 600 601 static const TypeInfo idreg_info = { 602 .name = TYPE_MACIO_ID_REGISTER, 603 .parent = TYPE_SYS_BUS_DEVICE, 604 .instance_size = sizeof(IDRegState), 605 .class_init = idreg_class_init, 606 }; 607 608 #define TYPE_TCX_AFX "tcx_afx" 609 OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) 610 611 struct AFXState { 612 SysBusDevice parent_obj; 613 614 MemoryRegion mem; 615 }; 616 617 /* SS-5 TCX AFX register */ 618 static void afx_init(hwaddr addr) 619 { 620 DeviceState *dev; 621 SysBusDevice *s; 622 623 dev = qdev_new(TYPE_TCX_AFX); 624 s = SYS_BUS_DEVICE(dev); 625 sysbus_realize_and_unref(s, &error_fatal); 626 627 sysbus_mmio_map(s, 0, addr); 628 } 629 630 static void afx_realize(DeviceState *ds, Error **errp) 631 { 632 AFXState *s = TCX_AFX(ds); 633 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 634 Error *local_err = NULL; 635 636 memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", 4, 637 &local_err); 638 if (local_err) { 639 error_propagate(errp, local_err); 640 return; 641 } 642 643 vmstate_register_ram_global(&s->mem); 644 sysbus_init_mmio(dev, &s->mem); 645 } 646 647 static void afx_class_init(ObjectClass *oc, void *data) 648 { 649 DeviceClass *dc = DEVICE_CLASS(oc); 650 651 dc->realize = afx_realize; 652 } 653 654 static const TypeInfo afx_info = { 655 .name = TYPE_TCX_AFX, 656 .parent = TYPE_SYS_BUS_DEVICE, 657 .instance_size = sizeof(AFXState), 658 .class_init = afx_class_init, 659 }; 660 661 #define TYPE_OPENPROM "openprom" 662 typedef struct PROMState PROMState; 663 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, 664 TYPE_OPENPROM) 665 666 struct PROMState { 667 SysBusDevice parent_obj; 668 669 MemoryRegion prom; 670 }; 671 672 /* Boot PROM (OpenBIOS) */ 673 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 674 { 675 hwaddr *base_addr = (hwaddr *)opaque; 676 return addr + *base_addr - PROM_VADDR; 677 } 678 679 static void prom_init(hwaddr addr, const char *bios_name) 680 { 681 DeviceState *dev; 682 SysBusDevice *s; 683 char *filename; 684 int ret; 685 686 dev = qdev_new(TYPE_OPENPROM); 687 s = SYS_BUS_DEVICE(dev); 688 sysbus_realize_and_unref(s, &error_fatal); 689 690 sysbus_mmio_map(s, 0, addr); 691 692 /* load boot prom */ 693 if (bios_name == NULL) { 694 bios_name = PROM_FILENAME; 695 } 696 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 697 if (filename) { 698 ret = load_elf(filename, NULL, 699 translate_prom_address, &addr, NULL, 700 NULL, NULL, NULL, 1, EM_SPARC, 0, 0); 701 if (ret < 0 || ret > PROM_SIZE_MAX) { 702 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 703 } 704 g_free(filename); 705 } else { 706 ret = -1; 707 } 708 if (ret < 0 || ret > PROM_SIZE_MAX) { 709 error_report("could not load prom '%s'", bios_name); 710 exit(1); 711 } 712 } 713 714 static void prom_realize(DeviceState *ds, Error **errp) 715 { 716 PROMState *s = OPENPROM(ds); 717 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 718 Error *local_err = NULL; 719 720 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", 721 PROM_SIZE_MAX, &local_err); 722 if (local_err) { 723 error_propagate(errp, local_err); 724 return; 725 } 726 727 vmstate_register_ram_global(&s->prom); 728 memory_region_set_readonly(&s->prom, true); 729 sysbus_init_mmio(dev, &s->prom); 730 } 731 732 static Property prom_properties[] = { 733 {/* end of property list */}, 734 }; 735 736 static void prom_class_init(ObjectClass *klass, void *data) 737 { 738 DeviceClass *dc = DEVICE_CLASS(klass); 739 740 device_class_set_props(dc, prom_properties); 741 dc->realize = prom_realize; 742 } 743 744 static const TypeInfo prom_info = { 745 .name = TYPE_OPENPROM, 746 .parent = TYPE_SYS_BUS_DEVICE, 747 .instance_size = sizeof(PROMState), 748 .class_init = prom_class_init, 749 }; 750 751 #define TYPE_SUN4M_MEMORY "memory" 752 typedef struct RamDevice RamDevice; 753 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, 754 TYPE_SUN4M_MEMORY) 755 756 struct RamDevice { 757 SysBusDevice parent_obj; 758 HostMemoryBackend *memdev; 759 }; 760 761 /* System RAM */ 762 static void ram_realize(DeviceState *dev, Error **errp) 763 { 764 RamDevice *d = SUN4M_RAM(dev); 765 MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); 766 767 sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); 768 } 769 770 static void ram_initfn(Object *obj) 771 { 772 RamDevice *d = SUN4M_RAM(obj); 773 object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, 774 (Object **)&d->memdev, 775 object_property_allow_set_link, 776 OBJ_PROP_LINK_STRONG); 777 object_property_set_description(obj, "memdev", "Set RAM backend" 778 "Valid value is ID of a hostmem backend"); 779 } 780 781 static void ram_class_init(ObjectClass *klass, void *data) 782 { 783 DeviceClass *dc = DEVICE_CLASS(klass); 784 785 dc->realize = ram_realize; 786 } 787 788 static const TypeInfo ram_info = { 789 .name = TYPE_SUN4M_MEMORY, 790 .parent = TYPE_SYS_BUS_DEVICE, 791 .instance_size = sizeof(RamDevice), 792 .instance_init = ram_initfn, 793 .class_init = ram_class_init, 794 }; 795 796 static void cpu_devinit(const char *cpu_type, unsigned int id, 797 uint64_t prom_addr, qemu_irq **cpu_irqs) 798 { 799 SPARCCPU *cpu; 800 CPUSPARCState *env; 801 802 cpu = SPARC_CPU(object_new(cpu_type)); 803 env = &cpu->env; 804 805 qemu_register_reset(sun4m_cpu_reset, cpu); 806 object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, 807 &error_fatal); 808 qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); 809 cpu_sparc_set_id(env, id); 810 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); 811 env->prom_addr = prom_addr; 812 } 813 814 static void dummy_fdc_tc(void *opaque, int irq, int level) 815 { 816 } 817 818 static void sun4m_hw_init(MachineState *machine) 819 { 820 const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; 821 DeviceState *slavio_intctl; 822 unsigned int i; 823 Nvram *nvram; 824 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; 825 qemu_irq fdc_tc; 826 unsigned long kernel_size; 827 uint32_t initrd_size; 828 DriveInfo *fd[MAX_FD]; 829 FWCfgState *fw_cfg; 830 DeviceState *dev, *ms_kb_orgate, *serial_orgate; 831 SysBusDevice *s; 832 unsigned int smp_cpus = machine->smp.cpus; 833 unsigned int max_cpus = machine->smp.max_cpus; 834 Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, 835 TYPE_MEMORY_BACKEND, NULL); 836 NICInfo *nd = &nd_table[0]; 837 838 if (machine->ram_size > hwdef->max_mem) { 839 error_report("Too much memory for this machine: %" PRId64 "," 840 " maximum %" PRId64, 841 machine->ram_size / MiB, hwdef->max_mem / MiB); 842 exit(1); 843 } 844 845 /* init CPUs */ 846 for(i = 0; i < smp_cpus; i++) { 847 cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); 848 } 849 850 for (i = smp_cpus; i < MAX_CPUS; i++) 851 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); 852 853 /* Create and map RAM frontend */ 854 dev = qdev_new("memory"); 855 object_property_set_link(OBJECT(dev), "memdev", ram_memdev, &error_fatal); 856 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 857 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); 858 859 /* models without ECC don't trap when missing ram is accessed */ 860 if (!hwdef->ecc_base) { 861 empty_slot_init("ecc", machine->ram_size, 862 hwdef->max_mem - machine->ram_size); 863 } 864 865 prom_init(hwdef->slavio_base, machine->firmware); 866 867 slavio_intctl = slavio_intctl_init(hwdef->intctl_base, 868 hwdef->intctl_base + 0x10000ULL, 869 cpu_irqs); 870 871 for (i = 0; i < 32; i++) { 872 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); 873 } 874 for (i = 0; i < MAX_CPUS; i++) { 875 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); 876 } 877 878 if (hwdef->idreg_base) { 879 idreg_init(hwdef->idreg_base); 880 } 881 882 if (hwdef->afx_base) { 883 afx_init(hwdef->afx_base); 884 } 885 886 iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); 887 888 if (hwdef->iommu_pad_base) { 889 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. 890 Software shouldn't use aliased addresses, neither should it crash 891 when does. Using empty_slot instead of aliasing can help with 892 debugging such accesses */ 893 empty_slot_init("iommu.alias", 894 hwdef->iommu_pad_base, hwdef->iommu_pad_len); 895 } 896 897 qemu_check_nic_model(nd, TYPE_LANCE); 898 sparc32_dma_init(hwdef->dma_base, 899 hwdef->esp_base, slavio_irq[18], 900 hwdef->le_base, slavio_irq[16], nd); 901 902 if (graphic_depth != 8 && graphic_depth != 24) { 903 error_report("Unsupported depth: %d", graphic_depth); 904 exit (1); 905 } 906 if (vga_interface_type != VGA_NONE) { 907 if (vga_interface_type == VGA_CG3) { 908 if (graphic_depth != 8) { 909 error_report("Unsupported depth: %d", graphic_depth); 910 exit(1); 911 } 912 913 if (!(graphic_width == 1024 && graphic_height == 768) && 914 !(graphic_width == 1152 && graphic_height == 900)) { 915 error_report("Unsupported resolution: %d x %d", graphic_width, 916 graphic_height); 917 exit(1); 918 } 919 920 /* sbus irq 5 */ 921 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 922 graphic_width, graphic_height, graphic_depth); 923 vga_interface_created = true; 924 } else { 925 /* If no display specified, default to TCX */ 926 if (graphic_depth != 8 && graphic_depth != 24) { 927 error_report("Unsupported depth: %d", graphic_depth); 928 exit(1); 929 } 930 931 if (!(graphic_width == 1024 && graphic_height == 768)) { 932 error_report("Unsupported resolution: %d x %d", 933 graphic_width, graphic_height); 934 exit(1); 935 } 936 937 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, 938 graphic_width, graphic_height, graphic_depth); 939 vga_interface_created = true; 940 } 941 } 942 943 for (i = 0; i < MAX_VSIMMS; i++) { 944 /* vsimm registers probed by OBP */ 945 if (hwdef->vsimm[i].reg_base) { 946 char *name = g_strdup_printf("vsimm[%d]", i); 947 empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); 948 g_free(name); 949 } 950 } 951 952 if (hwdef->sx_base) { 953 create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); 954 } 955 956 dev = qdev_new("sysbus-m48t08"); 957 qdev_prop_set_int32(dev, "base-year", 1968); 958 s = SYS_BUS_DEVICE(dev); 959 sysbus_realize_and_unref(s, &error_fatal); 960 sysbus_connect_irq(s, 0, slavio_irq[0]); 961 sysbus_mmio_map(s, 0, hwdef->nvram_base); 962 nvram = NVRAM(dev); 963 964 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); 965 966 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device 967 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ 968 dev = qdev_new(TYPE_ESCC); 969 qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); 970 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 971 qdev_prop_set_uint32(dev, "it_shift", 1); 972 qdev_prop_set_chr(dev, "chrB", NULL); 973 qdev_prop_set_chr(dev, "chrA", NULL); 974 qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); 975 qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); 976 s = SYS_BUS_DEVICE(dev); 977 sysbus_realize_and_unref(s, &error_fatal); 978 sysbus_mmio_map(s, 0, hwdef->ms_kb_base); 979 980 /* Logically OR both its IRQs together */ 981 ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 982 object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); 983 qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); 984 sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); 985 sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); 986 qdev_connect_gpio_out(DEVICE(ms_kb_orgate), 0, slavio_irq[14]); 987 988 dev = qdev_new(TYPE_ESCC); 989 qdev_prop_set_uint32(dev, "disabled", 0); 990 qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); 991 qdev_prop_set_uint32(dev, "it_shift", 1); 992 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 993 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 994 qdev_prop_set_uint32(dev, "chnBtype", escc_serial); 995 qdev_prop_set_uint32(dev, "chnAtype", escc_serial); 996 997 s = SYS_BUS_DEVICE(dev); 998 sysbus_realize_and_unref(s, &error_fatal); 999 sysbus_mmio_map(s, 0, hwdef->serial_base); 1000 1001 /* Logically OR both its IRQs together */ 1002 serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 1003 object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, 1004 &error_fatal); 1005 qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); 1006 sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); 1007 sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); 1008 qdev_connect_gpio_out(DEVICE(serial_orgate), 0, slavio_irq[15]); 1009 1010 if (hwdef->apc_base) { 1011 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); 1012 } 1013 1014 if (hwdef->fd_base) { 1015 /* there is zero or one floppy drive */ 1016 memset(fd, 0, sizeof(fd)); 1017 fd[0] = drive_get(IF_FLOPPY, 0, 0); 1018 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, 1019 &fdc_tc); 1020 } else { 1021 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); 1022 } 1023 1024 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, 1025 slavio_irq[30], fdc_tc); 1026 1027 if (hwdef->cs_base) { 1028 sysbus_create_simple("sun-CS4231", hwdef->cs_base, 1029 slavio_irq[5]); 1030 } 1031 1032 if (hwdef->dbri_base) { 1033 /* ISDN chip with attached CS4215 audio codec */ 1034 /* prom space */ 1035 create_unimplemented_device("sun-DBRI.prom", 1036 hwdef->dbri_base + 0x1000, 0x30); 1037 /* reg space */ 1038 create_unimplemented_device("sun-DBRI", 1039 hwdef->dbri_base + 0x10000, 0x100); 1040 } 1041 1042 if (hwdef->bpp_base) { 1043 /* parallel port */ 1044 create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); 1045 } 1046 1047 initrd_size = 0; 1048 kernel_size = sun4m_load_kernel(machine->kernel_filename, 1049 machine->initrd_filename, 1050 machine->ram_size, &initrd_size); 1051 1052 nvram_init(nvram, (uint8_t *)&nd->macaddr, machine->kernel_cmdline, 1053 machine->boot_order, machine->ram_size, kernel_size, 1054 graphic_width, graphic_height, graphic_depth, 1055 hwdef->nvram_machine_id, "Sun4m"); 1056 1057 if (hwdef->ecc_base) 1058 ecc_init(hwdef->ecc_base, slavio_irq[28], 1059 hwdef->ecc_version); 1060 1061 dev = qdev_new(TYPE_FW_CFG_MEM); 1062 fw_cfg = FW_CFG(dev); 1063 qdev_prop_set_uint32(dev, "data_width", 1); 1064 qdev_prop_set_bit(dev, "dma_enabled", false); 1065 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, 1066 OBJECT(fw_cfg)); 1067 s = SYS_BUS_DEVICE(dev); 1068 sysbus_realize_and_unref(s, &error_fatal); 1069 sysbus_mmio_map(s, 0, CFG_ADDR); 1070 sysbus_mmio_map(s, 1, CFG_ADDR + 2); 1071 1072 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 1073 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 1074 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); 1075 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 1076 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); 1077 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); 1078 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); 1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); 1080 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 1081 if (machine->kernel_cmdline) { 1082 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); 1083 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, 1084 machine->kernel_cmdline); 1085 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 1086 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 1087 strlen(machine->kernel_cmdline) + 1); 1088 } else { 1089 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); 1090 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 1091 } 1092 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); 1093 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 1094 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 1095 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 1096 } 1097 1098 enum { 1099 ss5_id = 32, 1100 vger_id, 1101 lx_id, 1102 ss4_id, 1103 scls_id, 1104 sbook_id, 1105 ss10_id = 64, 1106 ss20_id, 1107 ss600mp_id, 1108 }; 1109 1110 static void sun4m_machine_class_init(ObjectClass *oc, void *data) 1111 { 1112 MachineClass *mc = MACHINE_CLASS(oc); 1113 1114 mc->init = sun4m_hw_init; 1115 mc->block_default_type = IF_SCSI; 1116 mc->default_boot_order = "c"; 1117 mc->default_display = "tcx"; 1118 mc->default_ram_id = "sun4m.ram"; 1119 } 1120 1121 static void ss5_class_init(ObjectClass *oc, void *data) 1122 { 1123 MachineClass *mc = MACHINE_CLASS(oc); 1124 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1125 static const struct sun4m_hwdef ss5_hwdef = { 1126 .iommu_base = 0x10000000, 1127 .iommu_pad_base = 0x10004000, 1128 .iommu_pad_len = 0x0fffb000, 1129 .tcx_base = 0x50000000, 1130 .cs_base = 0x6c000000, 1131 .slavio_base = 0x70000000, 1132 .ms_kb_base = 0x71000000, 1133 .serial_base = 0x71100000, 1134 .nvram_base = 0x71200000, 1135 .fd_base = 0x71400000, 1136 .counter_base = 0x71d00000, 1137 .intctl_base = 0x71e00000, 1138 .idreg_base = 0x78000000, 1139 .dma_base = 0x78400000, 1140 .esp_base = 0x78800000, 1141 .le_base = 0x78c00000, 1142 .apc_base = 0x6a000000, 1143 .afx_base = 0x6e000000, 1144 .aux1_base = 0x71900000, 1145 .aux2_base = 0x71910000, 1146 .nvram_machine_id = 0x80, 1147 .machine_id = ss5_id, 1148 .iommu_version = 0x05000000, 1149 .max_mem = 0x10000000, 1150 }; 1151 1152 mc->desc = "Sun4m platform, SPARCstation 5"; 1153 mc->is_default = true; 1154 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1155 smc->hwdef = &ss5_hwdef; 1156 } 1157 1158 static void ss10_class_init(ObjectClass *oc, void *data) 1159 { 1160 MachineClass *mc = MACHINE_CLASS(oc); 1161 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1162 static const struct sun4m_hwdef ss10_hwdef = { 1163 .iommu_base = 0xfe0000000ULL, 1164 .tcx_base = 0xe20000000ULL, 1165 .slavio_base = 0xff0000000ULL, 1166 .ms_kb_base = 0xff1000000ULL, 1167 .serial_base = 0xff1100000ULL, 1168 .nvram_base = 0xff1200000ULL, 1169 .fd_base = 0xff1700000ULL, 1170 .counter_base = 0xff1300000ULL, 1171 .intctl_base = 0xff1400000ULL, 1172 .idreg_base = 0xef0000000ULL, 1173 .dma_base = 0xef0400000ULL, 1174 .esp_base = 0xef0800000ULL, 1175 .le_base = 0xef0c00000ULL, 1176 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1177 .aux1_base = 0xff1800000ULL, 1178 .aux2_base = 0xff1a01000ULL, 1179 .ecc_base = 0xf00000000ULL, 1180 .ecc_version = 0x10000000, /* version 0, implementation 1 */ 1181 .nvram_machine_id = 0x72, 1182 .machine_id = ss10_id, 1183 .iommu_version = 0x03000000, 1184 .max_mem = 0xf00000000ULL, 1185 }; 1186 1187 mc->desc = "Sun4m platform, SPARCstation 10"; 1188 mc->max_cpus = 4; 1189 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1190 smc->hwdef = &ss10_hwdef; 1191 } 1192 1193 static void ss600mp_class_init(ObjectClass *oc, void *data) 1194 { 1195 MachineClass *mc = MACHINE_CLASS(oc); 1196 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1197 static const struct sun4m_hwdef ss600mp_hwdef = { 1198 .iommu_base = 0xfe0000000ULL, 1199 .tcx_base = 0xe20000000ULL, 1200 .slavio_base = 0xff0000000ULL, 1201 .ms_kb_base = 0xff1000000ULL, 1202 .serial_base = 0xff1100000ULL, 1203 .nvram_base = 0xff1200000ULL, 1204 .counter_base = 0xff1300000ULL, 1205 .intctl_base = 0xff1400000ULL, 1206 .dma_base = 0xef0081000ULL, 1207 .esp_base = 0xef0080000ULL, 1208 .le_base = 0xef0060000ULL, 1209 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1210 .aux1_base = 0xff1800000ULL, 1211 .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ 1212 .ecc_base = 0xf00000000ULL, 1213 .ecc_version = 0x00000000, /* version 0, implementation 0 */ 1214 .nvram_machine_id = 0x71, 1215 .machine_id = ss600mp_id, 1216 .iommu_version = 0x01000000, 1217 .max_mem = 0xf00000000ULL, 1218 }; 1219 1220 mc->desc = "Sun4m platform, SPARCserver 600MP"; 1221 mc->max_cpus = 4; 1222 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1223 smc->hwdef = &ss600mp_hwdef; 1224 } 1225 1226 static void ss20_class_init(ObjectClass *oc, void *data) 1227 { 1228 MachineClass *mc = MACHINE_CLASS(oc); 1229 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1230 static const struct sun4m_hwdef ss20_hwdef = { 1231 .iommu_base = 0xfe0000000ULL, 1232 .tcx_base = 0xe20000000ULL, 1233 .slavio_base = 0xff0000000ULL, 1234 .ms_kb_base = 0xff1000000ULL, 1235 .serial_base = 0xff1100000ULL, 1236 .nvram_base = 0xff1200000ULL, 1237 .fd_base = 0xff1700000ULL, 1238 .counter_base = 0xff1300000ULL, 1239 .intctl_base = 0xff1400000ULL, 1240 .idreg_base = 0xef0000000ULL, 1241 .dma_base = 0xef0400000ULL, 1242 .esp_base = 0xef0800000ULL, 1243 .le_base = 0xef0c00000ULL, 1244 .bpp_base = 0xef4800000ULL, 1245 .apc_base = 0xefa000000ULL, /* XXX should not exist */ 1246 .aux1_base = 0xff1800000ULL, 1247 .aux2_base = 0xff1a01000ULL, 1248 .dbri_base = 0xee0000000ULL, 1249 .sx_base = 0xf80000000ULL, 1250 .vsimm = { 1251 { 1252 .reg_base = 0x9c000000ULL, 1253 .vram_base = 0xfc000000ULL 1254 }, { 1255 .reg_base = 0x90000000ULL, 1256 .vram_base = 0xf0000000ULL 1257 }, { 1258 .reg_base = 0x94000000ULL 1259 }, { 1260 .reg_base = 0x98000000ULL 1261 } 1262 }, 1263 .ecc_base = 0xf00000000ULL, 1264 .ecc_version = 0x20000000, /* version 0, implementation 2 */ 1265 .nvram_machine_id = 0x72, 1266 .machine_id = ss20_id, 1267 .iommu_version = 0x13000000, 1268 .max_mem = 0xf00000000ULL, 1269 }; 1270 1271 mc->desc = "Sun4m platform, SPARCstation 20"; 1272 mc->max_cpus = 4; 1273 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); 1274 smc->hwdef = &ss20_hwdef; 1275 } 1276 1277 static void voyager_class_init(ObjectClass *oc, void *data) 1278 { 1279 MachineClass *mc = MACHINE_CLASS(oc); 1280 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1281 static const struct sun4m_hwdef voyager_hwdef = { 1282 .iommu_base = 0x10000000, 1283 .tcx_base = 0x50000000, 1284 .slavio_base = 0x70000000, 1285 .ms_kb_base = 0x71000000, 1286 .serial_base = 0x71100000, 1287 .nvram_base = 0x71200000, 1288 .fd_base = 0x71400000, 1289 .counter_base = 0x71d00000, 1290 .intctl_base = 0x71e00000, 1291 .idreg_base = 0x78000000, 1292 .dma_base = 0x78400000, 1293 .esp_base = 0x78800000, 1294 .le_base = 0x78c00000, 1295 .apc_base = 0x71300000, /* pmc */ 1296 .aux1_base = 0x71900000, 1297 .aux2_base = 0x71910000, 1298 .nvram_machine_id = 0x80, 1299 .machine_id = vger_id, 1300 .iommu_version = 0x05000000, 1301 .max_mem = 0x10000000, 1302 }; 1303 1304 mc->desc = "Sun4m platform, SPARCstation Voyager"; 1305 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1306 smc->hwdef = &voyager_hwdef; 1307 } 1308 1309 static void ss_lx_class_init(ObjectClass *oc, void *data) 1310 { 1311 MachineClass *mc = MACHINE_CLASS(oc); 1312 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1313 static const struct sun4m_hwdef ss_lx_hwdef = { 1314 .iommu_base = 0x10000000, 1315 .iommu_pad_base = 0x10004000, 1316 .iommu_pad_len = 0x0fffb000, 1317 .tcx_base = 0x50000000, 1318 .slavio_base = 0x70000000, 1319 .ms_kb_base = 0x71000000, 1320 .serial_base = 0x71100000, 1321 .nvram_base = 0x71200000, 1322 .fd_base = 0x71400000, 1323 .counter_base = 0x71d00000, 1324 .intctl_base = 0x71e00000, 1325 .idreg_base = 0x78000000, 1326 .dma_base = 0x78400000, 1327 .esp_base = 0x78800000, 1328 .le_base = 0x78c00000, 1329 .aux1_base = 0x71900000, 1330 .aux2_base = 0x71910000, 1331 .nvram_machine_id = 0x80, 1332 .machine_id = lx_id, 1333 .iommu_version = 0x04000000, 1334 .max_mem = 0x10000000, 1335 }; 1336 1337 mc->desc = "Sun4m platform, SPARCstation LX"; 1338 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1339 smc->hwdef = &ss_lx_hwdef; 1340 } 1341 1342 static void ss4_class_init(ObjectClass *oc, void *data) 1343 { 1344 MachineClass *mc = MACHINE_CLASS(oc); 1345 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1346 static const struct sun4m_hwdef ss4_hwdef = { 1347 .iommu_base = 0x10000000, 1348 .tcx_base = 0x50000000, 1349 .cs_base = 0x6c000000, 1350 .slavio_base = 0x70000000, 1351 .ms_kb_base = 0x71000000, 1352 .serial_base = 0x71100000, 1353 .nvram_base = 0x71200000, 1354 .fd_base = 0x71400000, 1355 .counter_base = 0x71d00000, 1356 .intctl_base = 0x71e00000, 1357 .idreg_base = 0x78000000, 1358 .dma_base = 0x78400000, 1359 .esp_base = 0x78800000, 1360 .le_base = 0x78c00000, 1361 .apc_base = 0x6a000000, 1362 .aux1_base = 0x71900000, 1363 .aux2_base = 0x71910000, 1364 .nvram_machine_id = 0x80, 1365 .machine_id = ss4_id, 1366 .iommu_version = 0x05000000, 1367 .max_mem = 0x10000000, 1368 }; 1369 1370 mc->desc = "Sun4m platform, SPARCstation 4"; 1371 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); 1372 smc->hwdef = &ss4_hwdef; 1373 } 1374 1375 static void scls_class_init(ObjectClass *oc, void *data) 1376 { 1377 MachineClass *mc = MACHINE_CLASS(oc); 1378 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1379 static const struct sun4m_hwdef scls_hwdef = { 1380 .iommu_base = 0x10000000, 1381 .tcx_base = 0x50000000, 1382 .slavio_base = 0x70000000, 1383 .ms_kb_base = 0x71000000, 1384 .serial_base = 0x71100000, 1385 .nvram_base = 0x71200000, 1386 .fd_base = 0x71400000, 1387 .counter_base = 0x71d00000, 1388 .intctl_base = 0x71e00000, 1389 .idreg_base = 0x78000000, 1390 .dma_base = 0x78400000, 1391 .esp_base = 0x78800000, 1392 .le_base = 0x78c00000, 1393 .apc_base = 0x6a000000, 1394 .aux1_base = 0x71900000, 1395 .aux2_base = 0x71910000, 1396 .nvram_machine_id = 0x80, 1397 .machine_id = scls_id, 1398 .iommu_version = 0x05000000, 1399 .max_mem = 0x10000000, 1400 }; 1401 1402 mc->desc = "Sun4m platform, SPARCClassic"; 1403 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1404 smc->hwdef = &scls_hwdef; 1405 } 1406 1407 static void sbook_class_init(ObjectClass *oc, void *data) 1408 { 1409 MachineClass *mc = MACHINE_CLASS(oc); 1410 Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); 1411 static const struct sun4m_hwdef sbook_hwdef = { 1412 .iommu_base = 0x10000000, 1413 .tcx_base = 0x50000000, /* XXX */ 1414 .slavio_base = 0x70000000, 1415 .ms_kb_base = 0x71000000, 1416 .serial_base = 0x71100000, 1417 .nvram_base = 0x71200000, 1418 .fd_base = 0x71400000, 1419 .counter_base = 0x71d00000, 1420 .intctl_base = 0x71e00000, 1421 .idreg_base = 0x78000000, 1422 .dma_base = 0x78400000, 1423 .esp_base = 0x78800000, 1424 .le_base = 0x78c00000, 1425 .apc_base = 0x6a000000, 1426 .aux1_base = 0x71900000, 1427 .aux2_base = 0x71910000, 1428 .nvram_machine_id = 0x80, 1429 .machine_id = sbook_id, 1430 .iommu_version = 0x05000000, 1431 .max_mem = 0x10000000, 1432 }; 1433 1434 mc->desc = "Sun4m platform, SPARCbook"; 1435 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); 1436 smc->hwdef = &sbook_hwdef; 1437 } 1438 1439 static const TypeInfo sun4m_machine_types[] = { 1440 { 1441 .name = MACHINE_TYPE_NAME("SS-5"), 1442 .parent = TYPE_SUN4M_MACHINE, 1443 .class_init = ss5_class_init, 1444 }, { 1445 .name = MACHINE_TYPE_NAME("SS-10"), 1446 .parent = TYPE_SUN4M_MACHINE, 1447 .class_init = ss10_class_init, 1448 }, { 1449 .name = MACHINE_TYPE_NAME("SS-600MP"), 1450 .parent = TYPE_SUN4M_MACHINE, 1451 .class_init = ss600mp_class_init, 1452 }, { 1453 .name = MACHINE_TYPE_NAME("SS-20"), 1454 .parent = TYPE_SUN4M_MACHINE, 1455 .class_init = ss20_class_init, 1456 }, { 1457 .name = MACHINE_TYPE_NAME("Voyager"), 1458 .parent = TYPE_SUN4M_MACHINE, 1459 .class_init = voyager_class_init, 1460 }, { 1461 .name = MACHINE_TYPE_NAME("LX"), 1462 .parent = TYPE_SUN4M_MACHINE, 1463 .class_init = ss_lx_class_init, 1464 }, { 1465 .name = MACHINE_TYPE_NAME("SS-4"), 1466 .parent = TYPE_SUN4M_MACHINE, 1467 .class_init = ss4_class_init, 1468 }, { 1469 .name = MACHINE_TYPE_NAME("SPARCClassic"), 1470 .parent = TYPE_SUN4M_MACHINE, 1471 .class_init = scls_class_init, 1472 }, { 1473 .name = MACHINE_TYPE_NAME("SPARCbook"), 1474 .parent = TYPE_SUN4M_MACHINE, 1475 .class_init = sbook_class_init, 1476 }, { 1477 .name = TYPE_SUN4M_MACHINE, 1478 .parent = TYPE_MACHINE, 1479 .class_size = sizeof(Sun4mMachineClass), 1480 .class_init = sun4m_machine_class_init, 1481 .abstract = true, 1482 } 1483 }; 1484 1485 DEFINE_TYPES(sun4m_machine_types) 1486 1487 static void sun4m_register_types(void) 1488 { 1489 type_register_static(&idreg_info); 1490 type_register_static(&afx_info); 1491 type_register_static(&prom_info); 1492 type_register_static(&ram_info); 1493 } 1494 1495 type_init(sun4m_register_types) 1496