1a2664ca0SArtyom Tarasenko /* 2a2664ca0SArtyom Tarasenko * QEMU Sun4v/Niagara System Emulator 3a2664ca0SArtyom Tarasenko * 4a2664ca0SArtyom Tarasenko * Copyright (c) 2016 Artyom Tarasenko 5a2664ca0SArtyom Tarasenko * 6a2664ca0SArtyom Tarasenko * Permission is hereby granted, free of charge, to any person obtaining a copy 7a2664ca0SArtyom Tarasenko * of this software and associated documentation files (the "Software"), to deal 8a2664ca0SArtyom Tarasenko * in the Software without restriction, including without limitation the rights 9a2664ca0SArtyom Tarasenko * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10a2664ca0SArtyom Tarasenko * copies of the Software, and to permit persons to whom the Software is 11a2664ca0SArtyom Tarasenko * furnished to do so, subject to the following conditions: 12a2664ca0SArtyom Tarasenko * 13a2664ca0SArtyom Tarasenko * The above copyright notice and this permission notice shall be included in 14a2664ca0SArtyom Tarasenko * all copies or substantial portions of the Software. 15a2664ca0SArtyom Tarasenko * 16a2664ca0SArtyom Tarasenko * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17a2664ca0SArtyom Tarasenko * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18a2664ca0SArtyom Tarasenko * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19a2664ca0SArtyom Tarasenko * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20a2664ca0SArtyom Tarasenko * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21a2664ca0SArtyom Tarasenko * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22a2664ca0SArtyom Tarasenko * THE SOFTWARE. 23a2664ca0SArtyom Tarasenko */ 24a2664ca0SArtyom Tarasenko 25a2664ca0SArtyom Tarasenko #include "qemu/osdep.h" 26a2664ca0SArtyom Tarasenko #include "qapi/error.h" 27a2664ca0SArtyom Tarasenko #include "qemu-common.h" 28a2664ca0SArtyom Tarasenko #include "cpu.h" 29a2664ca0SArtyom Tarasenko #include "hw/hw.h" 30a2664ca0SArtyom Tarasenko #include "hw/boards.h" 31a2664ca0SArtyom Tarasenko #include "hw/char/serial.h" 32a2664ca0SArtyom Tarasenko #include "hw/empty_slot.h" 33a2664ca0SArtyom Tarasenko #include "hw/loader.h" 34a2664ca0SArtyom Tarasenko #include "hw/sparc/sparc64.h" 35a2664ca0SArtyom Tarasenko #include "hw/timer/sun4v-rtc.h" 36a2664ca0SArtyom Tarasenko #include "exec/address-spaces.h" 37a2664ca0SArtyom Tarasenko #include "sysemu/block-backend.h" 385e3a5494SArtyom Tarasenko #include "qemu/error-report.h" 395e3a5494SArtyom Tarasenko #include "sysemu/qtest.h" 40a2664ca0SArtyom Tarasenko 41a2664ca0SArtyom Tarasenko 42a2664ca0SArtyom Tarasenko typedef struct NiagaraBoardState { 43a2664ca0SArtyom Tarasenko MemoryRegion hv_ram; 44a2664ca0SArtyom Tarasenko MemoryRegion partition_ram; 45a2664ca0SArtyom Tarasenko MemoryRegion nvram; 46a2664ca0SArtyom Tarasenko MemoryRegion md_rom; 47a2664ca0SArtyom Tarasenko MemoryRegion hv_rom; 48a2664ca0SArtyom Tarasenko MemoryRegion vdisk_ram; 49a2664ca0SArtyom Tarasenko MemoryRegion prom; 50a2664ca0SArtyom Tarasenko } NiagaraBoardState; 51a2664ca0SArtyom Tarasenko 52a2664ca0SArtyom Tarasenko #define NIAGARA_HV_RAM_BASE 0x100000ULL 53a2664ca0SArtyom Tarasenko #define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */ 54a2664ca0SArtyom Tarasenko 55a2664ca0SArtyom Tarasenko #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL 56a2664ca0SArtyom Tarasenko 57a2664ca0SArtyom Tarasenko #define NIAGARA_UART_BASE 0x1f10000000ULL 58a2664ca0SArtyom Tarasenko 59a2664ca0SArtyom Tarasenko #define NIAGARA_NVRAM_BASE 0x1f11000000ULL 60a2664ca0SArtyom Tarasenko #define NIAGARA_NVRAM_SIZE 0x2000 61a2664ca0SArtyom Tarasenko 62a2664ca0SArtyom Tarasenko #define NIAGARA_MD_ROM_BASE 0x1f12000000ULL 63a2664ca0SArtyom Tarasenko #define NIAGARA_MD_ROM_SIZE 0x2000 64a2664ca0SArtyom Tarasenko 65a2664ca0SArtyom Tarasenko #define NIAGARA_HV_ROM_BASE 0x1f12080000ULL 66a2664ca0SArtyom Tarasenko #define NIAGARA_HV_ROM_SIZE 0x2000 67a2664ca0SArtyom Tarasenko 68a2664ca0SArtyom Tarasenko #define NIAGARA_IOBBASE 0x9800000000ULL 69a2664ca0SArtyom Tarasenko #define NIAGARA_IOBSIZE 0x0100000000ULL 70a2664ca0SArtyom Tarasenko 71a2664ca0SArtyom Tarasenko #define NIAGARA_VDISK_BASE 0x1f40000000ULL 72a2664ca0SArtyom Tarasenko #define NIAGARA_RTC_BASE 0xfff0c1fff8ULL 73a2664ca0SArtyom Tarasenko #define NIAGARA_UART_BASE 0x1f10000000ULL 74a2664ca0SArtyom Tarasenko 75a2664ca0SArtyom Tarasenko /* Firmware layout 76a2664ca0SArtyom Tarasenko * 77a2664ca0SArtyom Tarasenko * |------------------| 78a2664ca0SArtyom Tarasenko * | openboot.bin | 79a2664ca0SArtyom Tarasenko * |------------------| PROM_ADDR + OBP_OFFSET 80a2664ca0SArtyom Tarasenko * | q.bin | 81a2664ca0SArtyom Tarasenko * |------------------| PROM_ADDR + Q_OFFSET 82a2664ca0SArtyom Tarasenko * | reset.bin | 83a2664ca0SArtyom Tarasenko * |------------------| PROM_ADDR 84a2664ca0SArtyom Tarasenko */ 85a2664ca0SArtyom Tarasenko #define NIAGARA_PROM_BASE 0xfff0000000ULL 86a2664ca0SArtyom Tarasenko #define NIAGARA_Q_OFFSET 0x10000ULL 87a2664ca0SArtyom Tarasenko #define NIAGARA_OBP_OFFSET 0x80000ULL 88a2664ca0SArtyom Tarasenko #define PROM_SIZE_MAX (4 * 1024 * 1024) 89a2664ca0SArtyom Tarasenko 905e3a5494SArtyom Tarasenko static void add_rom_or_fail(const char *file, const hwaddr addr) 915e3a5494SArtyom Tarasenko { 925e3a5494SArtyom Tarasenko /* XXX remove qtest_enabled() check once firmware files are 935e3a5494SArtyom Tarasenko * in the qemu tree 945e3a5494SArtyom Tarasenko */ 955e3a5494SArtyom Tarasenko if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) { 965e3a5494SArtyom Tarasenko error_report("Unable to load a firmware for -M niagara"); 975e3a5494SArtyom Tarasenko exit(1); 985e3a5494SArtyom Tarasenko } 995e3a5494SArtyom Tarasenko 1005e3a5494SArtyom Tarasenko } 101a2664ca0SArtyom Tarasenko /* Niagara hardware initialisation */ 102a2664ca0SArtyom Tarasenko static void niagara_init(MachineState *machine) 103a2664ca0SArtyom Tarasenko { 104a2664ca0SArtyom Tarasenko NiagaraBoardState *s = g_new(NiagaraBoardState, 1); 105a2664ca0SArtyom Tarasenko DriveInfo *dinfo = drive_get_next(IF_PFLASH); 106a2664ca0SArtyom Tarasenko MemoryRegion *sysmem = get_system_memory(); 107a2664ca0SArtyom Tarasenko 108a2664ca0SArtyom Tarasenko /* init CPUs */ 109*58530461SIgor Mammedov sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE); 110a2664ca0SArtyom Tarasenko /* set up devices */ 111a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram", 112a2664ca0SArtyom Tarasenko NIAGARA_HV_RAM_SIZE); 113a2664ca0SArtyom Tarasenko memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram); 114a2664ca0SArtyom Tarasenko 115a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->partition_ram, NULL, 116a2664ca0SArtyom Tarasenko "sun4v-partition.ram", 117a2664ca0SArtyom Tarasenko machine->ram_size); 118a2664ca0SArtyom Tarasenko memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE, 119a2664ca0SArtyom Tarasenko &s->partition_ram); 120a2664ca0SArtyom Tarasenko 121a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->nvram, NULL, 122a2664ca0SArtyom Tarasenko "sun4v.nvram", NIAGARA_NVRAM_SIZE); 123a2664ca0SArtyom Tarasenko memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram); 124a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->md_rom, NULL, 125a2664ca0SArtyom Tarasenko "sun4v-md.rom", NIAGARA_MD_ROM_SIZE); 126a2664ca0SArtyom Tarasenko memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom); 127a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->hv_rom, NULL, 128a2664ca0SArtyom Tarasenko "sun4v-hv.rom", NIAGARA_HV_ROM_SIZE); 129a2664ca0SArtyom Tarasenko memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom); 130a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->prom, NULL, 131a2664ca0SArtyom Tarasenko "sun4v.prom", PROM_SIZE_MAX); 132a2664ca0SArtyom Tarasenko memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom); 133a2664ca0SArtyom Tarasenko 1345e3a5494SArtyom Tarasenko add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE); 1355e3a5494SArtyom Tarasenko add_rom_or_fail("1up-md.bin", NIAGARA_MD_ROM_BASE); 1365e3a5494SArtyom Tarasenko add_rom_or_fail("1up-hv.bin", NIAGARA_HV_ROM_BASE); 137a2664ca0SArtyom Tarasenko 1385e3a5494SArtyom Tarasenko add_rom_or_fail("reset.bin", NIAGARA_PROM_BASE); 1395e3a5494SArtyom Tarasenko add_rom_or_fail("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET); 1405e3a5494SArtyom Tarasenko add_rom_or_fail("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET); 141a2664ca0SArtyom Tarasenko 142a2664ca0SArtyom Tarasenko /* the virtual ramdisk is kind of initrd, but it resides 143a2664ca0SArtyom Tarasenko outside of the partition RAM */ 144a2664ca0SArtyom Tarasenko if (dinfo) { 145a2664ca0SArtyom Tarasenko BlockBackend *blk = blk_by_legacy_dinfo(dinfo); 146a2664ca0SArtyom Tarasenko int size = blk_getlength(blk); 147a2664ca0SArtyom Tarasenko if (size > 0) { 148a2664ca0SArtyom Tarasenko memory_region_allocate_system_memory(&s->vdisk_ram, NULL, 149a2664ca0SArtyom Tarasenko "sun4v_vdisk.ram", size); 150a2664ca0SArtyom Tarasenko memory_region_add_subregion(get_system_memory(), 151a2664ca0SArtyom Tarasenko NIAGARA_VDISK_BASE, &s->vdisk_ram); 152a2664ca0SArtyom Tarasenko dinfo->is_default = 1; 153a2664ca0SArtyom Tarasenko rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1); 154a2664ca0SArtyom Tarasenko } else { 155a2664ca0SArtyom Tarasenko fprintf(stderr, "qemu: could not load ram disk '%s'\n", 156a2664ca0SArtyom Tarasenko blk_bs(blk)->filename); 157a2664ca0SArtyom Tarasenko exit(1); 158a2664ca0SArtyom Tarasenko } 159a2664ca0SArtyom Tarasenko } 160a5a08302SArtyom Tarasenko if (serial_hds[0]) { 161a2664ca0SArtyom Tarasenko serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200, 162a2664ca0SArtyom Tarasenko serial_hds[0], DEVICE_BIG_ENDIAN); 163a5a08302SArtyom Tarasenko } 164a2664ca0SArtyom Tarasenko empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE); 165a2664ca0SArtyom Tarasenko sun4v_rtc_init(NIAGARA_RTC_BASE); 166a2664ca0SArtyom Tarasenko } 167a2664ca0SArtyom Tarasenko 168a2664ca0SArtyom Tarasenko static void niagara_class_init(ObjectClass *oc, void *data) 169a2664ca0SArtyom Tarasenko { 170a2664ca0SArtyom Tarasenko MachineClass *mc = MACHINE_CLASS(oc); 171a2664ca0SArtyom Tarasenko 172a2664ca0SArtyom Tarasenko mc->desc = "Sun4v platform, Niagara"; 173a2664ca0SArtyom Tarasenko mc->init = niagara_init; 174a2664ca0SArtyom Tarasenko mc->max_cpus = 1; /* XXX for now */ 175a2664ca0SArtyom Tarasenko mc->default_boot_order = "c"; 176*58530461SIgor Mammedov mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 177a2664ca0SArtyom Tarasenko } 178a2664ca0SArtyom Tarasenko 179a2664ca0SArtyom Tarasenko static const TypeInfo niagara_type = { 180a2664ca0SArtyom Tarasenko .name = MACHINE_TYPE_NAME("niagara"), 181a2664ca0SArtyom Tarasenko .parent = TYPE_MACHINE, 182a2664ca0SArtyom Tarasenko .class_init = niagara_class_init, 183a2664ca0SArtyom Tarasenko }; 184a2664ca0SArtyom Tarasenko 185a2664ca0SArtyom Tarasenko static void niagara_register_types(void) 186a2664ca0SArtyom Tarasenko { 187a2664ca0SArtyom Tarasenko type_register_static(&niagara_type); 188a2664ca0SArtyom Tarasenko } 189a2664ca0SArtyom Tarasenko 190a2664ca0SArtyom Tarasenko type_init(niagara_register_types) 191