xref: /qemu/hw/sparc64/niagara.c (revision ab9056ff)
1 /*
2  * QEMU Sun4v/Niagara System Emulator
3  *
4  * Copyright (c) 2016 Artyom Tarasenko
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a copy
7  * of this software and associated documentation files (the "Software"), to deal
8  * in the Software without restriction, including without limitation the rights
9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10  * copies of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22  * THE SOFTWARE.
23  */
24 
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "cpu.h"
28 #include "hw/boards.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/loader.h"
32 #include "hw/sparc/sparc64.h"
33 #include "hw/rtc/sun4v-rtc.h"
34 #include "exec/address-spaces.h"
35 #include "sysemu/block-backend.h"
36 #include "qemu/error-report.h"
37 #include "sysemu/qtest.h"
38 #include "sysemu/sysemu.h"
39 #include "qapi/error.h"
40 
41 typedef struct NiagaraBoardState {
42     MemoryRegion hv_ram;
43     MemoryRegion partition_ram;
44     MemoryRegion nvram;
45     MemoryRegion md_rom;
46     MemoryRegion hv_rom;
47     MemoryRegion vdisk_ram;
48     MemoryRegion prom;
49 } NiagaraBoardState;
50 
51 #define NIAGARA_HV_RAM_BASE 0x100000ULL
52 #define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */
53 
54 #define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL
55 
56 #define NIAGARA_UART_BASE   0x1f10000000ULL
57 
58 #define NIAGARA_NVRAM_BASE  0x1f11000000ULL
59 #define NIAGARA_NVRAM_SIZE  0x2000
60 
61 #define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
62 #define NIAGARA_MD_ROM_SIZE 0x2000
63 
64 #define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
65 #define NIAGARA_HV_ROM_SIZE 0x2000
66 
67 #define NIAGARA_IOBBASE     0x9800000000ULL
68 #define NIAGARA_IOBSIZE     0x0100000000ULL
69 
70 #define NIAGARA_VDISK_BASE  0x1f40000000ULL
71 #define NIAGARA_RTC_BASE    0xfff0c1fff8ULL
72 #define NIAGARA_UART_BASE   0x1f10000000ULL
73 
74 /* Firmware layout
75  *
76  * |------------------|
77  * |   openboot.bin   |
78  * |------------------| PROM_ADDR + OBP_OFFSET
79  * |      q.bin       |
80  * |------------------| PROM_ADDR + Q_OFFSET
81  * |     reset.bin    |
82  * |------------------| PROM_ADDR
83  */
84 #define NIAGARA_PROM_BASE   0xfff0000000ULL
85 #define NIAGARA_Q_OFFSET    0x10000ULL
86 #define NIAGARA_OBP_OFFSET  0x80000ULL
87 #define PROM_SIZE_MAX       (4 * MiB)
88 
89 static void add_rom_or_fail(const char *file, const hwaddr addr)
90 {
91     /* XXX remove qtest_enabled() check once firmware files are
92      * in the qemu tree
93      */
94     if (!qtest_enabled() && rom_add_file_fixed(file, addr, -1)) {
95         error_report("Unable to load a firmware for -M niagara");
96         exit(1);
97     }
98 
99 }
100 /* Niagara hardware initialisation */
101 static void niagara_init(MachineState *machine)
102 {
103     NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
104     DriveInfo *dinfo = drive_get_next(IF_PFLASH);
105     MemoryRegion *sysmem = get_system_memory();
106 
107     /* init CPUs */
108     sparc64_cpu_devinit(machine->cpu_type, NIAGARA_PROM_BASE);
109     /* set up devices */
110     memory_region_init_ram(&s->hv_ram, NULL, "sun4v-hv.ram",
111                            NIAGARA_HV_RAM_SIZE, &error_fatal);
112     memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);
113 
114     memory_region_allocate_system_memory(&s->partition_ram, NULL,
115                                          "sun4v-partition.ram",
116                                          machine->ram_size);
117     memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
118                                 &s->partition_ram);
119 
120     memory_region_init_ram(&s->nvram, NULL, "sun4v.nvram", NIAGARA_NVRAM_SIZE,
121                            &error_fatal);
122     memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
123     memory_region_init_ram(&s->md_rom, NULL, "sun4v-md.rom",
124                            NIAGARA_MD_ROM_SIZE, &error_fatal);
125     memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
126     memory_region_init_ram(&s->hv_rom, NULL, "sun4v-hv.rom",
127                            NIAGARA_HV_ROM_SIZE, &error_fatal);
128     memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
129     memory_region_init_ram(&s->prom, NULL, "sun4v.prom", PROM_SIZE_MAX,
130                            &error_fatal);
131     memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);
132 
133     add_rom_or_fail("nvram1", NIAGARA_NVRAM_BASE);
134     add_rom_or_fail("1up-md.bin", NIAGARA_MD_ROM_BASE);
135     add_rom_or_fail("1up-hv.bin", NIAGARA_HV_ROM_BASE);
136 
137     add_rom_or_fail("reset.bin", NIAGARA_PROM_BASE);
138     add_rom_or_fail("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET);
139     add_rom_or_fail("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET);
140 
141     /* the virtual ramdisk is kind of initrd, but it resides
142        outside of the partition RAM */
143     if (dinfo) {
144         BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
145         int size = blk_getlength(blk);
146         if (size > 0) {
147             memory_region_init_ram(&s->vdisk_ram, NULL, "sun4v_vdisk.ram", size,
148                                    &error_fatal);
149             memory_region_add_subregion(get_system_memory(),
150                                         NIAGARA_VDISK_BASE, &s->vdisk_ram);
151             dinfo->is_default = 1;
152             rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
153         } else {
154             error_report("could not load ram disk '%s'",
155                          blk_bs(blk)->filename);
156             exit(1);
157         }
158     }
159     if (serial_hd(0)) {
160         serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
161                        serial_hd(0), DEVICE_BIG_ENDIAN);
162     }
163     create_unimplemented_device("sun4v-iob", NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
164     sun4v_rtc_init(NIAGARA_RTC_BASE);
165 }
166 
167 static void niagara_class_init(ObjectClass *oc, void *data)
168 {
169     MachineClass *mc = MACHINE_CLASS(oc);
170 
171     mc->desc = "Sun4v platform, Niagara";
172     mc->init = niagara_init;
173     mc->max_cpus = 1; /* XXX for now */
174     mc->default_boot_order = "c";
175     mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
176 }
177 
178 static const TypeInfo niagara_type = {
179     .name = MACHINE_TYPE_NAME("niagara"),
180     .parent = TYPE_MACHINE,
181     .class_init = niagara_class_init,
182 };
183 
184 static void niagara_register_types(void)
185 {
186     type_register_static(&niagara_type);
187 }
188 
189 type_init(niagara_register_types)
190