1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qapi/error.h" 26 #include "qemu-common.h" 27 #include "cpu.h" 28 #include "hw/hw.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci-host/apb.h" 31 #include "hw/i386/pc.h" 32 #include "hw/char/serial.h" 33 #include "hw/timer/m48t59.h" 34 #include "hw/block/fdc.h" 35 #include "net/net.h" 36 #include "qemu/timer.h" 37 #include "sysemu/sysemu.h" 38 #include "hw/boards.h" 39 #include "hw/nvram/sun_nvram.h" 40 #include "hw/nvram/chrp_nvram.h" 41 #include "hw/sparc/sparc64.h" 42 #include "hw/nvram/fw_cfg.h" 43 #include "hw/sysbus.h" 44 #include "hw/ide.h" 45 #include "hw/loader.h" 46 #include "elf.h" 47 #include "qemu/cutils.h" 48 49 //#define DEBUG_EBUS 50 51 #ifdef DEBUG_EBUS 52 #define EBUS_DPRINTF(fmt, ...) \ 53 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 54 #else 55 #define EBUS_DPRINTF(fmt, ...) 56 #endif 57 58 #define KERNEL_LOAD_ADDR 0x00404000 59 #define CMDLINE_ADDR 0x003ff000 60 #define PROM_SIZE_MAX (4 * 1024 * 1024) 61 #define PROM_VADDR 0x000ffd00000ULL 62 #define APB_SPECIAL_BASE 0x1fe00000000ULL 63 #define APB_MEM_BASE 0x1ff00000000ULL 64 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 65 #define PROM_FILENAME "openbios-sparc64" 66 #define NVRAM_SIZE 0x2000 67 #define MAX_IDE_BUS 2 68 #define BIOS_CFG_IOPORT 0x510 69 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 70 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 71 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 72 73 #define IVEC_MAX 0x40 74 75 struct hwdef { 76 const char * const default_cpu_model; 77 uint16_t machine_id; 78 uint64_t prom_addr; 79 uint64_t console_serial_base; 80 }; 81 82 typedef struct EbusState { 83 PCIDevice pci_dev; 84 MemoryRegion bar0; 85 MemoryRegion bar1; 86 } EbusState; 87 88 void DMA_init(ISABus *bus, int high_page_enable) 89 { 90 } 91 92 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 93 Error **errp) 94 { 95 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 96 } 97 98 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 99 const char *arch, ram_addr_t RAM_size, 100 const char *boot_devices, 101 uint32_t kernel_image, uint32_t kernel_size, 102 const char *cmdline, 103 uint32_t initrd_image, uint32_t initrd_size, 104 uint32_t NVRAM_image, 105 int width, int height, int depth, 106 const uint8_t *macaddr) 107 { 108 unsigned int i; 109 int sysp_end; 110 uint8_t image[0x1ff0]; 111 NvramClass *k = NVRAM_GET_CLASS(nvram); 112 113 memset(image, '\0', sizeof(image)); 114 115 /* OpenBIOS nvram variables partition */ 116 sysp_end = chrp_nvram_create_system_partition(image, 0); 117 118 /* Free space partition */ 119 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 120 121 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 122 123 for (i = 0; i < sizeof(image); i++) { 124 (k->write)(nvram, i, image[i]); 125 } 126 127 return 0; 128 } 129 130 static uint64_t sun4u_load_kernel(const char *kernel_filename, 131 const char *initrd_filename, 132 ram_addr_t RAM_size, uint64_t *initrd_size, 133 uint64_t *initrd_addr, uint64_t *kernel_addr, 134 uint64_t *kernel_entry) 135 { 136 int linux_boot; 137 unsigned int i; 138 long kernel_size; 139 uint8_t *ptr; 140 uint64_t kernel_top; 141 142 linux_boot = (kernel_filename != NULL); 143 144 kernel_size = 0; 145 if (linux_boot) { 146 int bswap_needed; 147 148 #ifdef BSWAP_NEEDED 149 bswap_needed = 1; 150 #else 151 bswap_needed = 0; 152 #endif 153 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 154 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 155 if (kernel_size < 0) { 156 *kernel_addr = KERNEL_LOAD_ADDR; 157 *kernel_entry = KERNEL_LOAD_ADDR; 158 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 159 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 160 TARGET_PAGE_SIZE); 161 } 162 if (kernel_size < 0) { 163 kernel_size = load_image_targphys(kernel_filename, 164 KERNEL_LOAD_ADDR, 165 RAM_size - KERNEL_LOAD_ADDR); 166 } 167 if (kernel_size < 0) { 168 fprintf(stderr, "qemu: could not load kernel '%s'\n", 169 kernel_filename); 170 exit(1); 171 } 172 /* load initrd above kernel */ 173 *initrd_size = 0; 174 if (initrd_filename) { 175 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 176 177 *initrd_size = load_image_targphys(initrd_filename, 178 *initrd_addr, 179 RAM_size - *initrd_addr); 180 if ((int)*initrd_size < 0) { 181 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 182 initrd_filename); 183 exit(1); 184 } 185 } 186 if (*initrd_size > 0) { 187 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 188 ptr = rom_ptr(*kernel_addr + i); 189 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 190 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 191 stl_p(ptr + 28, *initrd_size); 192 break; 193 } 194 } 195 } 196 } 197 return kernel_size; 198 } 199 200 typedef struct ResetData { 201 SPARCCPU *cpu; 202 uint64_t prom_addr; 203 } ResetData; 204 205 static void isa_irq_handler(void *opaque, int n, int level) 206 { 207 static const int isa_irq_to_ivec[16] = { 208 [1] = 0x29, /* keyboard */ 209 [4] = 0x2b, /* serial */ 210 [6] = 0x27, /* floppy */ 211 [7] = 0x22, /* parallel */ 212 [12] = 0x2a, /* mouse */ 213 }; 214 qemu_irq *irqs = opaque; 215 int ivec; 216 217 assert(n < 16); 218 ivec = isa_irq_to_ivec[n]; 219 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 220 if (ivec) { 221 qemu_set_irq(irqs[ivec], level); 222 } 223 } 224 225 /* EBUS (Eight bit bus) bridge */ 226 static ISABus * 227 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) 228 { 229 qemu_irq *isa_irq; 230 PCIDevice *pci_dev; 231 ISABus *isa_bus; 232 233 pci_dev = pci_create_simple(bus, devfn, "ebus"); 234 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 235 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 236 isa_bus_irqs(isa_bus, isa_irq); 237 return isa_bus; 238 } 239 240 static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) 241 { 242 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 243 244 if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), 245 pci_address_space_io(pci_dev), errp)) { 246 return; 247 } 248 249 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 250 pci_dev->config[0x05] = 0x00; 251 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 252 pci_dev->config[0x07] = 0x03; // status = medium devsel 253 pci_dev->config[0x09] = 0x00; // programming i/f 254 pci_dev->config[0x0D] = 0x0a; // latency_timer 255 256 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 257 0, 0x1000000); 258 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 259 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 260 0, 0x4000); 261 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 262 } 263 264 static void ebus_class_init(ObjectClass *klass, void *data) 265 { 266 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 267 268 k->realize = pci_ebus_realize; 269 k->vendor_id = PCI_VENDOR_ID_SUN; 270 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 271 k->revision = 0x01; 272 k->class_id = PCI_CLASS_BRIDGE_OTHER; 273 } 274 275 static const TypeInfo ebus_info = { 276 .name = "ebus", 277 .parent = TYPE_PCI_DEVICE, 278 .instance_size = sizeof(EbusState), 279 .class_init = ebus_class_init, 280 }; 281 282 #define TYPE_OPENPROM "openprom" 283 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 284 285 typedef struct PROMState { 286 SysBusDevice parent_obj; 287 288 MemoryRegion prom; 289 } PROMState; 290 291 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 292 { 293 hwaddr *base_addr = (hwaddr *)opaque; 294 return addr + *base_addr - PROM_VADDR; 295 } 296 297 /* Boot PROM (OpenBIOS) */ 298 static void prom_init(hwaddr addr, const char *bios_name) 299 { 300 DeviceState *dev; 301 SysBusDevice *s; 302 char *filename; 303 int ret; 304 305 dev = qdev_create(NULL, TYPE_OPENPROM); 306 qdev_init_nofail(dev); 307 s = SYS_BUS_DEVICE(dev); 308 309 sysbus_mmio_map(s, 0, addr); 310 311 /* load boot prom */ 312 if (bios_name == NULL) { 313 bios_name = PROM_FILENAME; 314 } 315 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 316 if (filename) { 317 ret = load_elf(filename, translate_prom_address, &addr, 318 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 319 if (ret < 0 || ret > PROM_SIZE_MAX) { 320 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 321 } 322 g_free(filename); 323 } else { 324 ret = -1; 325 } 326 if (ret < 0 || ret > PROM_SIZE_MAX) { 327 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 328 exit(1); 329 } 330 } 331 332 static int prom_init1(SysBusDevice *dev) 333 { 334 PROMState *s = OPENPROM(dev); 335 336 memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, 337 &error_fatal); 338 vmstate_register_ram_global(&s->prom); 339 memory_region_set_readonly(&s->prom, true); 340 sysbus_init_mmio(dev, &s->prom); 341 return 0; 342 } 343 344 static Property prom_properties[] = { 345 {/* end of property list */}, 346 }; 347 348 static void prom_class_init(ObjectClass *klass, void *data) 349 { 350 DeviceClass *dc = DEVICE_CLASS(klass); 351 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 352 353 k->init = prom_init1; 354 dc->props = prom_properties; 355 } 356 357 static const TypeInfo prom_info = { 358 .name = TYPE_OPENPROM, 359 .parent = TYPE_SYS_BUS_DEVICE, 360 .instance_size = sizeof(PROMState), 361 .class_init = prom_class_init, 362 }; 363 364 365 #define TYPE_SUN4U_MEMORY "memory" 366 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 367 368 typedef struct RamDevice { 369 SysBusDevice parent_obj; 370 371 MemoryRegion ram; 372 uint64_t size; 373 } RamDevice; 374 375 /* System RAM */ 376 static int ram_init1(SysBusDevice *dev) 377 { 378 RamDevice *d = SUN4U_RAM(dev); 379 380 memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, 381 &error_fatal); 382 vmstate_register_ram_global(&d->ram); 383 sysbus_init_mmio(dev, &d->ram); 384 return 0; 385 } 386 387 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 388 { 389 DeviceState *dev; 390 SysBusDevice *s; 391 RamDevice *d; 392 393 /* allocate RAM */ 394 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 395 s = SYS_BUS_DEVICE(dev); 396 397 d = SUN4U_RAM(dev); 398 d->size = RAM_size; 399 qdev_init_nofail(dev); 400 401 sysbus_mmio_map(s, 0, addr); 402 } 403 404 static Property ram_properties[] = { 405 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 406 DEFINE_PROP_END_OF_LIST(), 407 }; 408 409 static void ram_class_init(ObjectClass *klass, void *data) 410 { 411 DeviceClass *dc = DEVICE_CLASS(klass); 412 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 413 414 k->init = ram_init1; 415 dc->props = ram_properties; 416 } 417 418 static const TypeInfo ram_info = { 419 .name = TYPE_SUN4U_MEMORY, 420 .parent = TYPE_SYS_BUS_DEVICE, 421 .instance_size = sizeof(RamDevice), 422 .class_init = ram_class_init, 423 }; 424 425 static void sun4uv_init(MemoryRegion *address_space_mem, 426 MachineState *machine, 427 const struct hwdef *hwdef) 428 { 429 SPARCCPU *cpu; 430 Nvram *nvram; 431 unsigned int i; 432 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 433 PCIBus *pci_bus, *pci_bus2, *pci_bus3; 434 ISABus *isa_bus; 435 SysBusDevice *s; 436 qemu_irq *ivec_irqs, *pbm_irqs; 437 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 438 DriveInfo *fd[MAX_FD]; 439 DeviceState *dev; 440 FWCfgState *fw_cfg; 441 442 /* init CPUs */ 443 cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model, 444 hwdef->prom_addr); 445 446 /* set up devices */ 447 ram_init(0, machine->ram_size); 448 449 prom_init(hwdef->prom_addr, bios_name); 450 451 ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); 452 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, 453 &pci_bus3, &pbm_irqs); 454 pci_vga_init(pci_bus); 455 456 // XXX Should be pci_bus3 457 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); 458 459 i = 0; 460 if (hwdef->console_serial_base) { 461 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 462 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 463 i++; 464 } 465 466 serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); 467 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 468 469 for(i = 0; i < nb_nics; i++) 470 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 471 472 ide_drive_get(hd, ARRAY_SIZE(hd)); 473 474 pci_cmd646_ide_init(pci_bus, hd, 1); 475 476 isa_create_simple(isa_bus, "i8042"); 477 478 /* Floppy */ 479 for(i = 0; i < MAX_FD; i++) { 480 fd[i] = drive_get(IF_FLOPPY, 0, i); 481 } 482 dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); 483 if (fd[0]) { 484 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 485 &error_abort); 486 } 487 if (fd[1]) { 488 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 489 &error_abort); 490 } 491 qdev_prop_set_uint32(dev, "dma", -1); 492 qdev_init_nofail(dev); 493 494 /* Map NVRAM into I/O (ebus) space */ 495 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 496 s = SYS_BUS_DEVICE(nvram); 497 memory_region_add_subregion(get_system_io(), 0x2000, 498 sysbus_mmio_get_region(s, 0)); 499 500 initrd_size = 0; 501 initrd_addr = 0; 502 kernel_size = sun4u_load_kernel(machine->kernel_filename, 503 machine->initrd_filename, 504 ram_size, &initrd_size, &initrd_addr, 505 &kernel_addr, &kernel_entry); 506 507 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 508 machine->boot_order, 509 kernel_addr, kernel_size, 510 machine->kernel_cmdline, 511 initrd_addr, initrd_size, 512 /* XXX: need an option to load a NVRAM image */ 513 0, 514 graphic_width, graphic_height, graphic_depth, 515 (uint8_t *)&nd_table[0].macaddr); 516 517 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 518 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 519 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 520 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 521 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 522 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 523 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 524 if (machine->kernel_cmdline) { 525 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 526 strlen(machine->kernel_cmdline) + 1); 527 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 528 } else { 529 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 530 } 531 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 532 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 533 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 534 535 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 536 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 537 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 538 539 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 540 } 541 542 enum { 543 sun4u_id = 0, 544 sun4v_id = 64, 545 }; 546 547 static const struct hwdef hwdefs[] = { 548 /* Sun4u generic PC-like machine */ 549 { 550 .default_cpu_model = "TI UltraSparc IIi", 551 .machine_id = sun4u_id, 552 .prom_addr = 0x1fff0000000ULL, 553 .console_serial_base = 0, 554 }, 555 /* Sun4v generic PC-like machine */ 556 { 557 .default_cpu_model = "Sun UltraSparc T1", 558 .machine_id = sun4v_id, 559 .prom_addr = 0x1fff0000000ULL, 560 .console_serial_base = 0, 561 }, 562 }; 563 564 /* Sun4u hardware initialisation */ 565 static void sun4u_init(MachineState *machine) 566 { 567 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 568 } 569 570 /* Sun4v hardware initialisation */ 571 static void sun4v_init(MachineState *machine) 572 { 573 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 574 } 575 576 static void sun4u_class_init(ObjectClass *oc, void *data) 577 { 578 MachineClass *mc = MACHINE_CLASS(oc); 579 580 mc->desc = "Sun4u platform"; 581 mc->init = sun4u_init; 582 mc->max_cpus = 1; /* XXX for now */ 583 mc->is_default = 1; 584 mc->default_boot_order = "c"; 585 } 586 587 static const TypeInfo sun4u_type = { 588 .name = MACHINE_TYPE_NAME("sun4u"), 589 .parent = TYPE_MACHINE, 590 .class_init = sun4u_class_init, 591 }; 592 593 static void sun4v_class_init(ObjectClass *oc, void *data) 594 { 595 MachineClass *mc = MACHINE_CLASS(oc); 596 597 mc->desc = "Sun4v platform"; 598 mc->init = sun4v_init; 599 mc->max_cpus = 1; /* XXX for now */ 600 mc->default_boot_order = "c"; 601 } 602 603 static const TypeInfo sun4v_type = { 604 .name = MACHINE_TYPE_NAME("sun4v"), 605 .parent = TYPE_MACHINE, 606 .class_init = sun4v_class_init, 607 }; 608 609 static void sun4u_register_types(void) 610 { 611 type_register_static(&ebus_info); 612 type_register_static(&prom_info); 613 type_register_static(&ram_info); 614 615 type_register_static(&sun4u_type); 616 type_register_static(&sun4v_type); 617 } 618 619 type_init(sun4u_register_types) 620