1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "qemu/units.h" 26 #include "qemu/error-report.h" 27 #include "qapi/error.h" 28 #include "qemu-common.h" 29 #include "cpu.h" 30 #include "hw/hw.h" 31 #include "hw/pci/pci.h" 32 #include "hw/pci/pci_bridge.h" 33 #include "hw/pci/pci_bus.h" 34 #include "hw/pci/pci_host.h" 35 #include "hw/pci-host/sabre.h" 36 #include "hw/i386/pc.h" 37 #include "hw/char/serial.h" 38 #include "hw/char/parallel.h" 39 #include "hw/timer/m48t59.h" 40 #include "hw/input/i8042.h" 41 #include "hw/block/fdc.h" 42 #include "net/net.h" 43 #include "qemu/timer.h" 44 #include "sysemu/sysemu.h" 45 #include "hw/boards.h" 46 #include "hw/nvram/sun_nvram.h" 47 #include "hw/nvram/chrp_nvram.h" 48 #include "hw/sparc/sparc64.h" 49 #include "hw/nvram/fw_cfg.h" 50 #include "hw/sysbus.h" 51 #include "hw/ide.h" 52 #include "hw/ide/pci.h" 53 #include "hw/loader.h" 54 #include "elf.h" 55 #include "trace.h" 56 57 #define KERNEL_LOAD_ADDR 0x00404000 58 #define CMDLINE_ADDR 0x003ff000 59 #define PROM_SIZE_MAX (4 * MiB) 60 #define PROM_VADDR 0x000ffd00000ULL 61 #define PBM_SPECIAL_BASE 0x1fe00000000ULL 62 #define PBM_MEM_BASE 0x1ff00000000ULL 63 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) 64 #define PROM_FILENAME "openbios-sparc64" 65 #define NVRAM_SIZE 0x2000 66 #define MAX_IDE_BUS 2 67 #define BIOS_CFG_IOPORT 0x510 68 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 69 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 70 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 71 72 #define IVEC_MAX 0x40 73 74 struct hwdef { 75 uint16_t machine_id; 76 uint64_t prom_addr; 77 uint64_t console_serial_base; 78 }; 79 80 typedef struct EbusState { 81 /*< private >*/ 82 PCIDevice parent_obj; 83 84 ISABus *isa_bus; 85 qemu_irq isa_bus_irqs[ISA_NUM_IRQS]; 86 uint64_t console_serial_base; 87 MemoryRegion bar0; 88 MemoryRegion bar1; 89 } EbusState; 90 91 #define TYPE_EBUS "ebus" 92 #define EBUS(obj) OBJECT_CHECK(EbusState, (obj), TYPE_EBUS) 93 94 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 95 Error **errp) 96 { 97 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 98 } 99 100 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 101 const char *arch, ram_addr_t RAM_size, 102 const char *boot_devices, 103 uint32_t kernel_image, uint32_t kernel_size, 104 const char *cmdline, 105 uint32_t initrd_image, uint32_t initrd_size, 106 uint32_t NVRAM_image, 107 int width, int height, int depth, 108 const uint8_t *macaddr) 109 { 110 unsigned int i; 111 int sysp_end; 112 uint8_t image[0x1ff0]; 113 NvramClass *k = NVRAM_GET_CLASS(nvram); 114 115 memset(image, '\0', sizeof(image)); 116 117 /* OpenBIOS nvram variables partition */ 118 sysp_end = chrp_nvram_create_system_partition(image, 0); 119 120 /* Free space partition */ 121 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); 122 123 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 124 125 for (i = 0; i < sizeof(image); i++) { 126 (k->write)(nvram, i, image[i]); 127 } 128 129 return 0; 130 } 131 132 static uint64_t sun4u_load_kernel(const char *kernel_filename, 133 const char *initrd_filename, 134 ram_addr_t RAM_size, uint64_t *initrd_size, 135 uint64_t *initrd_addr, uint64_t *kernel_addr, 136 uint64_t *kernel_entry) 137 { 138 int linux_boot; 139 unsigned int i; 140 long kernel_size; 141 uint8_t *ptr; 142 uint64_t kernel_top = 0; 143 144 linux_boot = (kernel_filename != NULL); 145 146 kernel_size = 0; 147 if (linux_boot) { 148 int bswap_needed; 149 150 #ifdef BSWAP_NEEDED 151 bswap_needed = 1; 152 #else 153 bswap_needed = 0; 154 #endif 155 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 156 kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); 157 if (kernel_size < 0) { 158 *kernel_addr = KERNEL_LOAD_ADDR; 159 *kernel_entry = KERNEL_LOAD_ADDR; 160 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 161 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 162 TARGET_PAGE_SIZE); 163 } 164 if (kernel_size < 0) { 165 kernel_size = load_image_targphys(kernel_filename, 166 KERNEL_LOAD_ADDR, 167 RAM_size - KERNEL_LOAD_ADDR); 168 } 169 if (kernel_size < 0) { 170 error_report("could not load kernel '%s'", kernel_filename); 171 exit(1); 172 } 173 /* load initrd above kernel */ 174 *initrd_size = 0; 175 if (initrd_filename && kernel_top) { 176 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 177 178 *initrd_size = load_image_targphys(initrd_filename, 179 *initrd_addr, 180 RAM_size - *initrd_addr); 181 if ((int)*initrd_size < 0) { 182 error_report("could not load initial ram disk '%s'", 183 initrd_filename); 184 exit(1); 185 } 186 } 187 if (*initrd_size > 0) { 188 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 189 ptr = rom_ptr(*kernel_addr + i, 32); 190 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 191 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 192 stl_p(ptr + 28, *initrd_size); 193 break; 194 } 195 } 196 } 197 } 198 return kernel_size; 199 } 200 201 typedef struct ResetData { 202 SPARCCPU *cpu; 203 uint64_t prom_addr; 204 } ResetData; 205 206 #define TYPE_SUN4U_POWER "power" 207 #define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) 208 209 typedef struct PowerDevice { 210 SysBusDevice parent_obj; 211 212 MemoryRegion power_mmio; 213 } PowerDevice; 214 215 /* Power */ 216 static void power_mem_write(void *opaque, hwaddr addr, 217 uint64_t val, unsigned size) 218 { 219 /* According to a real Ultra 5, bit 24 controls the power */ 220 if (val & 0x1000000) { 221 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 222 } 223 } 224 225 static const MemoryRegionOps power_mem_ops = { 226 .write = power_mem_write, 227 .endianness = DEVICE_NATIVE_ENDIAN, 228 .valid = { 229 .min_access_size = 4, 230 .max_access_size = 4, 231 }, 232 }; 233 234 static void power_realize(DeviceState *dev, Error **errp) 235 { 236 PowerDevice *d = SUN4U_POWER(dev); 237 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 238 239 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, 240 "power", sizeof(uint32_t)); 241 242 sysbus_init_mmio(sbd, &d->power_mmio); 243 } 244 245 static void power_class_init(ObjectClass *klass, void *data) 246 { 247 DeviceClass *dc = DEVICE_CLASS(klass); 248 249 dc->realize = power_realize; 250 } 251 252 static const TypeInfo power_info = { 253 .name = TYPE_SUN4U_POWER, 254 .parent = TYPE_SYS_BUS_DEVICE, 255 .instance_size = sizeof(PowerDevice), 256 .class_init = power_class_init, 257 }; 258 259 static void ebus_isa_irq_handler(void *opaque, int n, int level) 260 { 261 EbusState *s = EBUS(opaque); 262 qemu_irq irq = s->isa_bus_irqs[n]; 263 264 /* Pass ISA bus IRQs onto their gpio equivalent */ 265 trace_ebus_isa_irq_handler(n, level); 266 if (irq) { 267 qemu_set_irq(irq, level); 268 } 269 } 270 271 /* EBUS (Eight bit bus) bridge */ 272 static void ebus_realize(PCIDevice *pci_dev, Error **errp) 273 { 274 EbusState *s = EBUS(pci_dev); 275 SysBusDevice *sbd; 276 DeviceState *dev; 277 qemu_irq *isa_irq; 278 DriveInfo *fd[MAX_FD]; 279 int i; 280 281 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(), 282 pci_address_space_io(pci_dev), errp); 283 if (!s->isa_bus) { 284 error_setg(errp, "unable to instantiate EBUS ISA bus"); 285 return; 286 } 287 288 /* ISA bus */ 289 isa_irq = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS); 290 isa_bus_irqs(s->isa_bus, isa_irq); 291 qdev_init_gpio_out_named(DEVICE(s), s->isa_bus_irqs, "isa-irq", 292 ISA_NUM_IRQS); 293 294 /* Serial ports */ 295 i = 0; 296 if (s->console_serial_base) { 297 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base, 298 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN); 299 i++; 300 } 301 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS); 302 303 /* Parallel ports */ 304 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS); 305 306 /* Keyboard */ 307 isa_create_simple(s->isa_bus, "i8042"); 308 309 /* Floppy */ 310 for (i = 0; i < MAX_FD; i++) { 311 fd[i] = drive_get(IF_FLOPPY, 0, i); 312 } 313 dev = DEVICE(isa_create(s->isa_bus, TYPE_ISA_FDC)); 314 if (fd[0]) { 315 qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), 316 &error_abort); 317 } 318 if (fd[1]) { 319 qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), 320 &error_abort); 321 } 322 qdev_prop_set_uint32(dev, "dma", -1); 323 qdev_init_nofail(dev); 324 325 /* Power */ 326 dev = qdev_create(NULL, TYPE_SUN4U_POWER); 327 qdev_init_nofail(dev); 328 sbd = SYS_BUS_DEVICE(dev); 329 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, 330 sysbus_mmio_get_region(sbd, 0)); 331 332 /* PCI */ 333 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 334 pci_dev->config[0x05] = 0x00; 335 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 336 pci_dev->config[0x07] = 0x03; // status = medium devsel 337 pci_dev->config[0x09] = 0x00; // programming i/f 338 pci_dev->config[0x0D] = 0x0a; // latency_timer 339 340 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 341 0, 0x1000000); 342 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 343 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 344 0, 0x8000); 345 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 346 } 347 348 static Property ebus_properties[] = { 349 DEFINE_PROP_UINT64("console-serial-base", EbusState, 350 console_serial_base, 0), 351 DEFINE_PROP_END_OF_LIST(), 352 }; 353 354 static void ebus_class_init(ObjectClass *klass, void *data) 355 { 356 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 357 DeviceClass *dc = DEVICE_CLASS(klass); 358 359 k->realize = ebus_realize; 360 k->vendor_id = PCI_VENDOR_ID_SUN; 361 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 362 k->revision = 0x01; 363 k->class_id = PCI_CLASS_BRIDGE_OTHER; 364 dc->props = ebus_properties; 365 } 366 367 static const TypeInfo ebus_info = { 368 .name = TYPE_EBUS, 369 .parent = TYPE_PCI_DEVICE, 370 .class_init = ebus_class_init, 371 .instance_size = sizeof(EbusState), 372 .interfaces = (InterfaceInfo[]) { 373 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 374 { }, 375 }, 376 }; 377 378 #define TYPE_OPENPROM "openprom" 379 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 380 381 typedef struct PROMState { 382 SysBusDevice parent_obj; 383 384 MemoryRegion prom; 385 } PROMState; 386 387 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 388 { 389 hwaddr *base_addr = (hwaddr *)opaque; 390 return addr + *base_addr - PROM_VADDR; 391 } 392 393 /* Boot PROM (OpenBIOS) */ 394 static void prom_init(hwaddr addr, const char *bios_name) 395 { 396 DeviceState *dev; 397 SysBusDevice *s; 398 char *filename; 399 int ret; 400 401 dev = qdev_create(NULL, TYPE_OPENPROM); 402 qdev_init_nofail(dev); 403 s = SYS_BUS_DEVICE(dev); 404 405 sysbus_mmio_map(s, 0, addr); 406 407 /* load boot prom */ 408 if (bios_name == NULL) { 409 bios_name = PROM_FILENAME; 410 } 411 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 412 if (filename) { 413 ret = load_elf(filename, translate_prom_address, &addr, 414 NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); 415 if (ret < 0 || ret > PROM_SIZE_MAX) { 416 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 417 } 418 g_free(filename); 419 } else { 420 ret = -1; 421 } 422 if (ret < 0 || ret > PROM_SIZE_MAX) { 423 error_report("could not load prom '%s'", bios_name); 424 exit(1); 425 } 426 } 427 428 static void prom_realize(DeviceState *ds, Error **errp) 429 { 430 PROMState *s = OPENPROM(ds); 431 SysBusDevice *dev = SYS_BUS_DEVICE(ds); 432 Error *local_err = NULL; 433 434 memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom", 435 PROM_SIZE_MAX, &local_err); 436 if (local_err) { 437 error_propagate(errp, local_err); 438 return; 439 } 440 441 vmstate_register_ram_global(&s->prom); 442 memory_region_set_readonly(&s->prom, true); 443 sysbus_init_mmio(dev, &s->prom); 444 } 445 446 static Property prom_properties[] = { 447 {/* end of property list */}, 448 }; 449 450 static void prom_class_init(ObjectClass *klass, void *data) 451 { 452 DeviceClass *dc = DEVICE_CLASS(klass); 453 454 dc->props = prom_properties; 455 dc->realize = prom_realize; 456 } 457 458 static const TypeInfo prom_info = { 459 .name = TYPE_OPENPROM, 460 .parent = TYPE_SYS_BUS_DEVICE, 461 .instance_size = sizeof(PROMState), 462 .class_init = prom_class_init, 463 }; 464 465 466 #define TYPE_SUN4U_MEMORY "memory" 467 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 468 469 typedef struct RamDevice { 470 SysBusDevice parent_obj; 471 472 MemoryRegion ram; 473 uint64_t size; 474 } RamDevice; 475 476 /* System RAM */ 477 static void ram_realize(DeviceState *dev, Error **errp) 478 { 479 RamDevice *d = SUN4U_RAM(dev); 480 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 481 482 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, 483 &error_fatal); 484 vmstate_register_ram_global(&d->ram); 485 sysbus_init_mmio(sbd, &d->ram); 486 } 487 488 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 489 { 490 DeviceState *dev; 491 SysBusDevice *s; 492 RamDevice *d; 493 494 /* allocate RAM */ 495 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 496 s = SYS_BUS_DEVICE(dev); 497 498 d = SUN4U_RAM(dev); 499 d->size = RAM_size; 500 qdev_init_nofail(dev); 501 502 sysbus_mmio_map(s, 0, addr); 503 } 504 505 static Property ram_properties[] = { 506 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 507 DEFINE_PROP_END_OF_LIST(), 508 }; 509 510 static void ram_class_init(ObjectClass *klass, void *data) 511 { 512 DeviceClass *dc = DEVICE_CLASS(klass); 513 514 dc->realize = ram_realize; 515 dc->props = ram_properties; 516 } 517 518 static const TypeInfo ram_info = { 519 .name = TYPE_SUN4U_MEMORY, 520 .parent = TYPE_SYS_BUS_DEVICE, 521 .instance_size = sizeof(RamDevice), 522 .class_init = ram_class_init, 523 }; 524 525 static void sun4uv_init(MemoryRegion *address_space_mem, 526 MachineState *machine, 527 const struct hwdef *hwdef) 528 { 529 SPARCCPU *cpu; 530 Nvram *nvram; 531 unsigned int i; 532 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 533 SabreState *sabre; 534 PCIBus *pci_bus, *pci_busA, *pci_busB; 535 PCIDevice *ebus, *pci_dev; 536 SysBusDevice *s; 537 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 538 DeviceState *iommu, *dev; 539 FWCfgState *fw_cfg; 540 NICInfo *nd; 541 MACAddr macaddr; 542 bool onboard_nic; 543 544 /* init CPUs */ 545 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr); 546 547 /* IOMMU */ 548 iommu = qdev_create(NULL, TYPE_SUN4U_IOMMU); 549 qdev_init_nofail(iommu); 550 551 /* set up devices */ 552 ram_init(0, machine->ram_size); 553 554 prom_init(hwdef->prom_addr, bios_name); 555 556 /* Init sabre (PCI host bridge) */ 557 sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); 558 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); 559 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); 560 object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", 561 &error_abort); 562 qdev_init_nofail(DEVICE(sabre)); 563 564 /* Wire up PCI interrupts to CPU */ 565 for (i = 0; i < IVEC_MAX; i++) { 566 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, 567 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); 568 } 569 570 pci_bus = PCI_HOST_BRIDGE(sabre)->bus; 571 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); 572 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); 573 574 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is 575 reserved (leaving no slots free after on-board devices) however slots 576 0-3 are free on busB */ 577 pci_bus->slot_reserved_mask = 0xfffffffc; 578 pci_busA->slot_reserved_mask = 0xfffffff1; 579 pci_busB->slot_reserved_mask = 0xfffffff0; 580 581 ebus = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 0), true, TYPE_EBUS); 582 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base", 583 hwdef->console_serial_base); 584 qdev_init_nofail(DEVICE(ebus)); 585 586 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ 587 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, 588 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); 589 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, 590 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); 591 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, 592 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); 593 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, 594 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); 595 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, 596 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); 597 598 pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); 599 600 memset(&macaddr, 0, sizeof(MACAddr)); 601 onboard_nic = false; 602 for (i = 0; i < nb_nics; i++) { 603 nd = &nd_table[i]; 604 605 if (!nd->model || strcmp(nd->model, "sunhme") == 0) { 606 if (!onboard_nic) { 607 pci_dev = pci_create_multifunction(pci_busA, PCI_DEVFN(1, 1), 608 true, "sunhme"); 609 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr)); 610 onboard_nic = true; 611 } else { 612 pci_dev = pci_create(pci_busB, -1, "sunhme"); 613 } 614 } else { 615 pci_dev = pci_create(pci_busB, -1, nd->model); 616 } 617 618 dev = &pci_dev->qdev; 619 qdev_set_nic_properties(dev, nd); 620 qdev_init_nofail(dev); 621 } 622 623 /* If we don't have an onboard NIC, grab a default MAC address so that 624 * we have a valid machine id */ 625 if (!onboard_nic) { 626 qemu_macaddr_default_if_unset(&macaddr); 627 } 628 629 ide_drive_get(hd, ARRAY_SIZE(hd)); 630 631 pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide"); 632 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1); 633 qdev_init_nofail(&pci_dev->qdev); 634 pci_ide_create_devs(pci_dev, hd); 635 636 /* Map NVRAM into I/O (ebus) space */ 637 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 638 s = SYS_BUS_DEVICE(nvram); 639 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, 640 sysbus_mmio_get_region(s, 0)); 641 642 initrd_size = 0; 643 initrd_addr = 0; 644 kernel_size = sun4u_load_kernel(machine->kernel_filename, 645 machine->initrd_filename, 646 ram_size, &initrd_size, &initrd_addr, 647 &kernel_addr, &kernel_entry); 648 649 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 650 machine->boot_order, 651 kernel_addr, kernel_size, 652 machine->kernel_cmdline, 653 initrd_addr, initrd_size, 654 /* XXX: need an option to load a NVRAM image */ 655 0, 656 graphic_width, graphic_height, graphic_depth, 657 (uint8_t *)&macaddr); 658 659 dev = qdev_create(NULL, TYPE_FW_CFG_IO); 660 qdev_prop_set_bit(dev, "dma_enabled", false); 661 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); 662 qdev_init_nofail(dev); 663 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, 664 &FW_CFG_IO(dev)->comb_iomem); 665 666 fw_cfg = FW_CFG(dev); 667 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); 668 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 669 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 670 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 671 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 672 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 673 if (machine->kernel_cmdline) { 674 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 675 strlen(machine->kernel_cmdline) + 1); 676 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 677 } else { 678 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 679 } 680 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 681 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 682 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 683 684 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 685 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 686 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 687 688 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 689 } 690 691 enum { 692 sun4u_id = 0, 693 sun4v_id = 64, 694 }; 695 696 static const struct hwdef hwdefs[] = { 697 /* Sun4u generic PC-like machine */ 698 { 699 .machine_id = sun4u_id, 700 .prom_addr = 0x1fff0000000ULL, 701 .console_serial_base = 0, 702 }, 703 /* Sun4v generic PC-like machine */ 704 { 705 .machine_id = sun4v_id, 706 .prom_addr = 0x1fff0000000ULL, 707 .console_serial_base = 0, 708 }, 709 }; 710 711 /* Sun4u hardware initialisation */ 712 static void sun4u_init(MachineState *machine) 713 { 714 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 715 } 716 717 /* Sun4v hardware initialisation */ 718 static void sun4v_init(MachineState *machine) 719 { 720 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 721 } 722 723 static void sun4u_class_init(ObjectClass *oc, void *data) 724 { 725 MachineClass *mc = MACHINE_CLASS(oc); 726 727 mc->desc = "Sun4u platform"; 728 mc->init = sun4u_init; 729 mc->block_default_type = IF_IDE; 730 mc->max_cpus = 1; /* XXX for now */ 731 mc->is_default = 1; 732 mc->default_boot_order = "c"; 733 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi"); 734 } 735 736 static const TypeInfo sun4u_type = { 737 .name = MACHINE_TYPE_NAME("sun4u"), 738 .parent = TYPE_MACHINE, 739 .class_init = sun4u_class_init, 740 }; 741 742 static void sun4v_class_init(ObjectClass *oc, void *data) 743 { 744 MachineClass *mc = MACHINE_CLASS(oc); 745 746 mc->desc = "Sun4v platform"; 747 mc->init = sun4v_init; 748 mc->block_default_type = IF_IDE; 749 mc->max_cpus = 1; /* XXX for now */ 750 mc->default_boot_order = "c"; 751 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); 752 } 753 754 static const TypeInfo sun4v_type = { 755 .name = MACHINE_TYPE_NAME("sun4v"), 756 .parent = TYPE_MACHINE, 757 .class_init = sun4v_class_init, 758 }; 759 760 static void sun4u_register_types(void) 761 { 762 type_register_static(&power_info); 763 type_register_static(&ebus_info); 764 type_register_static(&prom_info); 765 type_register_static(&ram_info); 766 767 type_register_static(&sun4u_type); 768 type_register_static(&sun4v_type); 769 } 770 771 type_init(sun4u_register_types) 772