1 /* 2 * QEMU Sun4u/Sun4v System Emulator 3 * 4 * Copyright (c) 2005 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "hw/hw.h" 25 #include "hw/pci/pci.h" 26 #include "hw/pci-host/apb.h" 27 #include "hw/i386/pc.h" 28 #include "hw/char/serial.h" 29 #include "hw/timer/m48t59.h" 30 #include "hw/block/fdc.h" 31 #include "net/net.h" 32 #include "qemu/timer.h" 33 #include "sysemu/sysemu.h" 34 #include "hw/boards.h" 35 #include "hw/nvram/openbios_firmware_abi.h" 36 #include "hw/nvram/fw_cfg.h" 37 #include "hw/sysbus.h" 38 #include "hw/ide.h" 39 #include "hw/loader.h" 40 #include "elf.h" 41 #include "sysemu/block-backend.h" 42 #include "exec/address-spaces.h" 43 44 //#define DEBUG_IRQ 45 //#define DEBUG_EBUS 46 //#define DEBUG_TIMER 47 48 #ifdef DEBUG_IRQ 49 #define CPUIRQ_DPRINTF(fmt, ...) \ 50 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) 51 #else 52 #define CPUIRQ_DPRINTF(fmt, ...) 53 #endif 54 55 #ifdef DEBUG_EBUS 56 #define EBUS_DPRINTF(fmt, ...) \ 57 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) 58 #else 59 #define EBUS_DPRINTF(fmt, ...) 60 #endif 61 62 #ifdef DEBUG_TIMER 63 #define TIMER_DPRINTF(fmt, ...) \ 64 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) 65 #else 66 #define TIMER_DPRINTF(fmt, ...) 67 #endif 68 69 #define KERNEL_LOAD_ADDR 0x00404000 70 #define CMDLINE_ADDR 0x003ff000 71 #define PROM_SIZE_MAX (4 * 1024 * 1024) 72 #define PROM_VADDR 0x000ffd00000ULL 73 #define APB_SPECIAL_BASE 0x1fe00000000ULL 74 #define APB_MEM_BASE 0x1ff00000000ULL 75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) 76 #define PROM_FILENAME "openbios-sparc64" 77 #define NVRAM_SIZE 0x2000 78 #define MAX_IDE_BUS 2 79 #define BIOS_CFG_IOPORT 0x510 80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) 81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) 82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) 83 84 #define IVEC_MAX 0x40 85 86 #define TICK_MAX 0x7fffffffffffffffULL 87 88 struct hwdef { 89 const char * const default_cpu_model; 90 uint16_t machine_id; 91 uint64_t prom_addr; 92 uint64_t console_serial_base; 93 }; 94 95 typedef struct EbusState { 96 PCIDevice pci_dev; 97 MemoryRegion bar0; 98 MemoryRegion bar1; 99 } EbusState; 100 101 int DMA_get_channel_mode (int nchan) 102 { 103 return 0; 104 } 105 int DMA_read_memory (int nchan, void *buf, int pos, int size) 106 { 107 return 0; 108 } 109 int DMA_write_memory (int nchan, void *buf, int pos, int size) 110 { 111 return 0; 112 } 113 void DMA_hold_DREQ (int nchan) {} 114 void DMA_release_DREQ (int nchan) {} 115 void DMA_schedule(int nchan) {} 116 117 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit) 118 { 119 } 120 121 void DMA_register_channel (int nchan, 122 DMA_transfer_handler transfer_handler, 123 void *opaque) 124 { 125 } 126 127 static void fw_cfg_boot_set(void *opaque, const char *boot_device, 128 Error **errp) 129 { 130 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); 131 } 132 133 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, 134 const char *arch, ram_addr_t RAM_size, 135 const char *boot_devices, 136 uint32_t kernel_image, uint32_t kernel_size, 137 const char *cmdline, 138 uint32_t initrd_image, uint32_t initrd_size, 139 uint32_t NVRAM_image, 140 int width, int height, int depth, 141 const uint8_t *macaddr) 142 { 143 unsigned int i; 144 uint32_t start, end; 145 uint8_t image[0x1ff0]; 146 struct OpenBIOS_nvpart_v1 *part_header; 147 NvramClass *k = NVRAM_GET_CLASS(nvram); 148 149 memset(image, '\0', sizeof(image)); 150 151 start = 0; 152 153 // OpenBIOS nvram variables 154 // Variable partition 155 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 156 part_header->signature = OPENBIOS_PART_SYSTEM; 157 pstrcpy(part_header->name, sizeof(part_header->name), "system"); 158 159 end = start + sizeof(struct OpenBIOS_nvpart_v1); 160 for (i = 0; i < nb_prom_envs; i++) 161 end = OpenBIOS_set_var(image, end, prom_envs[i]); 162 163 // End marker 164 image[end++] = '\0'; 165 166 end = start + ((end - start + 15) & ~15); 167 OpenBIOS_finish_partition(part_header, end - start); 168 169 // free partition 170 start = end; 171 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; 172 part_header->signature = OPENBIOS_PART_FREE; 173 pstrcpy(part_header->name, sizeof(part_header->name), "free"); 174 175 end = 0x1fd0; 176 OpenBIOS_finish_partition(part_header, end - start); 177 178 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); 179 180 for (i = 0; i < sizeof(image); i++) { 181 (k->write)(nvram, i, image[i]); 182 } 183 184 return 0; 185 } 186 187 static uint64_t sun4u_load_kernel(const char *kernel_filename, 188 const char *initrd_filename, 189 ram_addr_t RAM_size, uint64_t *initrd_size, 190 uint64_t *initrd_addr, uint64_t *kernel_addr, 191 uint64_t *kernel_entry) 192 { 193 int linux_boot; 194 unsigned int i; 195 long kernel_size; 196 uint8_t *ptr; 197 uint64_t kernel_top; 198 199 linux_boot = (kernel_filename != NULL); 200 201 kernel_size = 0; 202 if (linux_boot) { 203 int bswap_needed; 204 205 #ifdef BSWAP_NEEDED 206 bswap_needed = 1; 207 #else 208 bswap_needed = 0; 209 #endif 210 kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, 211 kernel_addr, &kernel_top, 1, ELF_MACHINE, 0); 212 if (kernel_size < 0) { 213 *kernel_addr = KERNEL_LOAD_ADDR; 214 *kernel_entry = KERNEL_LOAD_ADDR; 215 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, 216 RAM_size - KERNEL_LOAD_ADDR, bswap_needed, 217 TARGET_PAGE_SIZE); 218 } 219 if (kernel_size < 0) { 220 kernel_size = load_image_targphys(kernel_filename, 221 KERNEL_LOAD_ADDR, 222 RAM_size - KERNEL_LOAD_ADDR); 223 } 224 if (kernel_size < 0) { 225 fprintf(stderr, "qemu: could not load kernel '%s'\n", 226 kernel_filename); 227 exit(1); 228 } 229 /* load initrd above kernel */ 230 *initrd_size = 0; 231 if (initrd_filename) { 232 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); 233 234 *initrd_size = load_image_targphys(initrd_filename, 235 *initrd_addr, 236 RAM_size - *initrd_addr); 237 if ((int)*initrd_size < 0) { 238 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 239 initrd_filename); 240 exit(1); 241 } 242 } 243 if (*initrd_size > 0) { 244 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { 245 ptr = rom_ptr(*kernel_addr + i); 246 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ 247 stl_p(ptr + 24, *initrd_addr + *kernel_addr); 248 stl_p(ptr + 28, *initrd_size); 249 break; 250 } 251 } 252 } 253 } 254 return kernel_size; 255 } 256 257 void cpu_check_irqs(CPUSPARCState *env) 258 { 259 CPUState *cs; 260 uint32_t pil = env->pil_in | 261 (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); 262 263 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ 264 if (env->ivec_status & 0x20) { 265 return; 266 } 267 cs = CPU(sparc_env_get_cpu(env)); 268 /* check if TM or SM in SOFTINT are set 269 setting these also causes interrupt 14 */ 270 if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { 271 pil |= 1 << 14; 272 } 273 274 /* The bit corresponding to psrpil is (1<< psrpil), the next bit 275 is (2 << psrpil). */ 276 if (pil < (2 << env->psrpil)){ 277 if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 278 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", 279 env->interrupt_index); 280 env->interrupt_index = 0; 281 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 282 } 283 return; 284 } 285 286 if (cpu_interrupts_enabled(env)) { 287 288 unsigned int i; 289 290 for (i = 15; i > env->psrpil; i--) { 291 if (pil & (1 << i)) { 292 int old_interrupt = env->interrupt_index; 293 int new_interrupt = TT_EXTINT | i; 294 295 if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt 296 && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { 297 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " 298 "current %x >= pending %x\n", 299 env->tl, cpu_tsptr(env)->tt, new_interrupt); 300 } else if (old_interrupt != new_interrupt) { 301 env->interrupt_index = new_interrupt; 302 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, 303 old_interrupt, new_interrupt); 304 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 305 } 306 break; 307 } 308 } 309 } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { 310 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " 311 "current interrupt %x\n", 312 pil, env->pil_in, env->softint, env->interrupt_index); 313 env->interrupt_index = 0; 314 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 315 } 316 } 317 318 static void cpu_kick_irq(SPARCCPU *cpu) 319 { 320 CPUState *cs = CPU(cpu); 321 CPUSPARCState *env = &cpu->env; 322 323 cs->halted = 0; 324 cpu_check_irqs(env); 325 qemu_cpu_kick(cs); 326 } 327 328 static void cpu_set_ivec_irq(void *opaque, int irq, int level) 329 { 330 SPARCCPU *cpu = opaque; 331 CPUSPARCState *env = &cpu->env; 332 CPUState *cs; 333 334 if (level) { 335 if (!(env->ivec_status & 0x20)) { 336 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); 337 cs = CPU(cpu); 338 cs->halted = 0; 339 env->interrupt_index = TT_IVEC; 340 env->ivec_status |= 0x20; 341 env->ivec_data[0] = (0x1f << 6) | irq; 342 env->ivec_data[1] = 0; 343 env->ivec_data[2] = 0; 344 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 345 } 346 } else { 347 if (env->ivec_status & 0x20) { 348 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); 349 cs = CPU(cpu); 350 env->ivec_status &= ~0x20; 351 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 352 } 353 } 354 } 355 356 typedef struct ResetData { 357 SPARCCPU *cpu; 358 uint64_t prom_addr; 359 } ResetData; 360 361 void cpu_put_timer(QEMUFile *f, CPUTimer *s) 362 { 363 qemu_put_be32s(f, &s->frequency); 364 qemu_put_be32s(f, &s->disabled); 365 qemu_put_be64s(f, &s->disabled_mask); 366 qemu_put_sbe64s(f, &s->clock_offset); 367 368 timer_put(f, s->qtimer); 369 } 370 371 void cpu_get_timer(QEMUFile *f, CPUTimer *s) 372 { 373 qemu_get_be32s(f, &s->frequency); 374 qemu_get_be32s(f, &s->disabled); 375 qemu_get_be64s(f, &s->disabled_mask); 376 qemu_get_sbe64s(f, &s->clock_offset); 377 378 timer_get(f, s->qtimer); 379 } 380 381 static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, 382 QEMUBHFunc *cb, uint32_t frequency, 383 uint64_t disabled_mask) 384 { 385 CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); 386 387 timer->name = name; 388 timer->frequency = frequency; 389 timer->disabled_mask = disabled_mask; 390 391 timer->disabled = 1; 392 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 393 394 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); 395 396 return timer; 397 } 398 399 static void cpu_timer_reset(CPUTimer *timer) 400 { 401 timer->disabled = 1; 402 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 403 404 timer_del(timer->qtimer); 405 } 406 407 static void main_cpu_reset(void *opaque) 408 { 409 ResetData *s = (ResetData *)opaque; 410 CPUSPARCState *env = &s->cpu->env; 411 static unsigned int nr_resets; 412 413 cpu_reset(CPU(s->cpu)); 414 415 cpu_timer_reset(env->tick); 416 cpu_timer_reset(env->stick); 417 cpu_timer_reset(env->hstick); 418 419 env->gregs[1] = 0; // Memory start 420 env->gregs[2] = ram_size; // Memory size 421 env->gregs[3] = 0; // Machine description XXX 422 if (nr_resets++ == 0) { 423 /* Power on reset */ 424 env->pc = s->prom_addr + 0x20ULL; 425 } else { 426 env->pc = s->prom_addr + 0x40ULL; 427 } 428 env->npc = env->pc + 4; 429 } 430 431 static void tick_irq(void *opaque) 432 { 433 SPARCCPU *cpu = opaque; 434 CPUSPARCState *env = &cpu->env; 435 436 CPUTimer* timer = env->tick; 437 438 if (timer->disabled) { 439 CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); 440 return; 441 } else { 442 CPUIRQ_DPRINTF("tick: fire\n"); 443 } 444 445 env->softint |= SOFTINT_TIMER; 446 cpu_kick_irq(cpu); 447 } 448 449 static void stick_irq(void *opaque) 450 { 451 SPARCCPU *cpu = opaque; 452 CPUSPARCState *env = &cpu->env; 453 454 CPUTimer* timer = env->stick; 455 456 if (timer->disabled) { 457 CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); 458 return; 459 } else { 460 CPUIRQ_DPRINTF("stick: fire\n"); 461 } 462 463 env->softint |= SOFTINT_STIMER; 464 cpu_kick_irq(cpu); 465 } 466 467 static void hstick_irq(void *opaque) 468 { 469 SPARCCPU *cpu = opaque; 470 CPUSPARCState *env = &cpu->env; 471 472 CPUTimer* timer = env->hstick; 473 474 if (timer->disabled) { 475 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); 476 return; 477 } else { 478 CPUIRQ_DPRINTF("hstick: fire\n"); 479 } 480 481 env->softint |= SOFTINT_STIMER; 482 cpu_kick_irq(cpu); 483 } 484 485 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) 486 { 487 return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); 488 } 489 490 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) 491 { 492 return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); 493 } 494 495 void cpu_tick_set_count(CPUTimer *timer, uint64_t count) 496 { 497 uint64_t real_count = count & ~timer->disabled_mask; 498 uint64_t disabled_bit = count & timer->disabled_mask; 499 500 int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - 501 cpu_to_timer_ticks(real_count, timer->frequency); 502 503 TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n", 504 timer->name, real_count, 505 timer->disabled?"disabled":"enabled", timer); 506 507 timer->disabled = disabled_bit ? 1 : 0; 508 timer->clock_offset = vm_clock_offset; 509 } 510 511 uint64_t cpu_tick_get_count(CPUTimer *timer) 512 { 513 uint64_t real_count = timer_to_cpu_ticks( 514 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, 515 timer->frequency); 516 517 TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n", 518 timer->name, real_count, 519 timer->disabled?"disabled":"enabled", timer); 520 521 if (timer->disabled) 522 real_count |= timer->disabled_mask; 523 524 return real_count; 525 } 526 527 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) 528 { 529 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 530 531 uint64_t real_limit = limit & ~timer->disabled_mask; 532 timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; 533 534 int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + 535 timer->clock_offset; 536 537 if (expires < now) { 538 expires = now + 1; 539 } 540 541 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " 542 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", 543 timer->name, real_limit, 544 timer->disabled?"disabled":"enabled", 545 timer, limit, 546 timer_to_cpu_ticks(now - timer->clock_offset, 547 timer->frequency), 548 timer_to_cpu_ticks(expires - now, timer->frequency)); 549 550 if (!real_limit) { 551 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", 552 timer->name); 553 timer_del(timer->qtimer); 554 } else if (timer->disabled) { 555 timer_del(timer->qtimer); 556 } else { 557 timer_mod(timer->qtimer, expires); 558 } 559 } 560 561 static void isa_irq_handler(void *opaque, int n, int level) 562 { 563 static const int isa_irq_to_ivec[16] = { 564 [1] = 0x29, /* keyboard */ 565 [4] = 0x2b, /* serial */ 566 [6] = 0x27, /* floppy */ 567 [7] = 0x22, /* parallel */ 568 [12] = 0x2a, /* mouse */ 569 }; 570 qemu_irq *irqs = opaque; 571 int ivec; 572 573 assert(n < 16); 574 ivec = isa_irq_to_ivec[n]; 575 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); 576 if (ivec) { 577 qemu_set_irq(irqs[ivec], level); 578 } 579 } 580 581 /* EBUS (Eight bit bus) bridge */ 582 static ISABus * 583 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) 584 { 585 qemu_irq *isa_irq; 586 PCIDevice *pci_dev; 587 ISABus *isa_bus; 588 589 pci_dev = pci_create_simple(bus, devfn, "ebus"); 590 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); 591 isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); 592 isa_bus_irqs(isa_bus, isa_irq); 593 return isa_bus; 594 } 595 596 static int 597 pci_ebus_init1(PCIDevice *pci_dev) 598 { 599 EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); 600 601 isa_bus_new(DEVICE(pci_dev), get_system_memory(), 602 pci_address_space_io(pci_dev)); 603 604 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem 605 pci_dev->config[0x05] = 0x00; 606 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error 607 pci_dev->config[0x07] = 0x03; // status = medium devsel 608 pci_dev->config[0x09] = 0x00; // programming i/f 609 pci_dev->config[0x0D] = 0x0a; // latency_timer 610 611 memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), 612 0, 0x1000000); 613 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); 614 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), 615 0, 0x4000); 616 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); 617 return 0; 618 } 619 620 static void ebus_class_init(ObjectClass *klass, void *data) 621 { 622 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 623 624 k->init = pci_ebus_init1; 625 k->vendor_id = PCI_VENDOR_ID_SUN; 626 k->device_id = PCI_DEVICE_ID_SUN_EBUS; 627 k->revision = 0x01; 628 k->class_id = PCI_CLASS_BRIDGE_OTHER; 629 } 630 631 static const TypeInfo ebus_info = { 632 .name = "ebus", 633 .parent = TYPE_PCI_DEVICE, 634 .instance_size = sizeof(EbusState), 635 .class_init = ebus_class_init, 636 }; 637 638 #define TYPE_OPENPROM "openprom" 639 #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) 640 641 typedef struct PROMState { 642 SysBusDevice parent_obj; 643 644 MemoryRegion prom; 645 } PROMState; 646 647 static uint64_t translate_prom_address(void *opaque, uint64_t addr) 648 { 649 hwaddr *base_addr = (hwaddr *)opaque; 650 return addr + *base_addr - PROM_VADDR; 651 } 652 653 /* Boot PROM (OpenBIOS) */ 654 static void prom_init(hwaddr addr, const char *bios_name) 655 { 656 DeviceState *dev; 657 SysBusDevice *s; 658 char *filename; 659 int ret; 660 661 dev = qdev_create(NULL, TYPE_OPENPROM); 662 qdev_init_nofail(dev); 663 s = SYS_BUS_DEVICE(dev); 664 665 sysbus_mmio_map(s, 0, addr); 666 667 /* load boot prom */ 668 if (bios_name == NULL) { 669 bios_name = PROM_FILENAME; 670 } 671 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 672 if (filename) { 673 ret = load_elf(filename, translate_prom_address, &addr, 674 NULL, NULL, NULL, 1, ELF_MACHINE, 0); 675 if (ret < 0 || ret > PROM_SIZE_MAX) { 676 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); 677 } 678 g_free(filename); 679 } else { 680 ret = -1; 681 } 682 if (ret < 0 || ret > PROM_SIZE_MAX) { 683 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); 684 exit(1); 685 } 686 } 687 688 static int prom_init1(SysBusDevice *dev) 689 { 690 PROMState *s = OPENPROM(dev); 691 692 memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, 693 &error_abort); 694 vmstate_register_ram_global(&s->prom); 695 memory_region_set_readonly(&s->prom, true); 696 sysbus_init_mmio(dev, &s->prom); 697 return 0; 698 } 699 700 static Property prom_properties[] = { 701 {/* end of property list */}, 702 }; 703 704 static void prom_class_init(ObjectClass *klass, void *data) 705 { 706 DeviceClass *dc = DEVICE_CLASS(klass); 707 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 708 709 k->init = prom_init1; 710 dc->props = prom_properties; 711 } 712 713 static const TypeInfo prom_info = { 714 .name = TYPE_OPENPROM, 715 .parent = TYPE_SYS_BUS_DEVICE, 716 .instance_size = sizeof(PROMState), 717 .class_init = prom_class_init, 718 }; 719 720 721 #define TYPE_SUN4U_MEMORY "memory" 722 #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) 723 724 typedef struct RamDevice { 725 SysBusDevice parent_obj; 726 727 MemoryRegion ram; 728 uint64_t size; 729 } RamDevice; 730 731 /* System RAM */ 732 static int ram_init1(SysBusDevice *dev) 733 { 734 RamDevice *d = SUN4U_RAM(dev); 735 736 memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, 737 &error_abort); 738 vmstate_register_ram_global(&d->ram); 739 sysbus_init_mmio(dev, &d->ram); 740 return 0; 741 } 742 743 static void ram_init(hwaddr addr, ram_addr_t RAM_size) 744 { 745 DeviceState *dev; 746 SysBusDevice *s; 747 RamDevice *d; 748 749 /* allocate RAM */ 750 dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); 751 s = SYS_BUS_DEVICE(dev); 752 753 d = SUN4U_RAM(dev); 754 d->size = RAM_size; 755 qdev_init_nofail(dev); 756 757 sysbus_mmio_map(s, 0, addr); 758 } 759 760 static Property ram_properties[] = { 761 DEFINE_PROP_UINT64("size", RamDevice, size, 0), 762 DEFINE_PROP_END_OF_LIST(), 763 }; 764 765 static void ram_class_init(ObjectClass *klass, void *data) 766 { 767 DeviceClass *dc = DEVICE_CLASS(klass); 768 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 769 770 k->init = ram_init1; 771 dc->props = ram_properties; 772 } 773 774 static const TypeInfo ram_info = { 775 .name = TYPE_SUN4U_MEMORY, 776 .parent = TYPE_SYS_BUS_DEVICE, 777 .instance_size = sizeof(RamDevice), 778 .class_init = ram_class_init, 779 }; 780 781 static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) 782 { 783 SPARCCPU *cpu; 784 CPUSPARCState *env; 785 ResetData *reset_info; 786 787 uint32_t tick_frequency = 100*1000000; 788 uint32_t stick_frequency = 100*1000000; 789 uint32_t hstick_frequency = 100*1000000; 790 791 if (cpu_model == NULL) { 792 cpu_model = hwdef->default_cpu_model; 793 } 794 cpu = cpu_sparc_init(cpu_model); 795 if (cpu == NULL) { 796 fprintf(stderr, "Unable to find Sparc CPU definition\n"); 797 exit(1); 798 } 799 env = &cpu->env; 800 801 env->tick = cpu_timer_create("tick", cpu, tick_irq, 802 tick_frequency, TICK_NPT_MASK); 803 804 env->stick = cpu_timer_create("stick", cpu, stick_irq, 805 stick_frequency, TICK_INT_DIS); 806 807 env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, 808 hstick_frequency, TICK_INT_DIS); 809 810 reset_info = g_malloc0(sizeof(ResetData)); 811 reset_info->cpu = cpu; 812 reset_info->prom_addr = hwdef->prom_addr; 813 qemu_register_reset(main_cpu_reset, reset_info); 814 815 return cpu; 816 } 817 818 static void sun4uv_init(MemoryRegion *address_space_mem, 819 MachineState *machine, 820 const struct hwdef *hwdef) 821 { 822 SPARCCPU *cpu; 823 Nvram *nvram; 824 unsigned int i; 825 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; 826 PCIBus *pci_bus, *pci_bus2, *pci_bus3; 827 ISABus *isa_bus; 828 SysBusDevice *s; 829 qemu_irq *ivec_irqs, *pbm_irqs; 830 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; 831 DriveInfo *fd[MAX_FD]; 832 FWCfgState *fw_cfg; 833 834 /* init CPUs */ 835 cpu = cpu_devinit(machine->cpu_model, hwdef); 836 837 /* set up devices */ 838 ram_init(0, machine->ram_size); 839 840 prom_init(hwdef->prom_addr, bios_name); 841 842 ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); 843 pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, 844 &pci_bus3, &pbm_irqs); 845 pci_vga_init(pci_bus); 846 847 // XXX Should be pci_bus3 848 isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); 849 850 i = 0; 851 if (hwdef->console_serial_base) { 852 serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, 853 NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); 854 i++; 855 } 856 857 serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); 858 parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); 859 860 for(i = 0; i < nb_nics; i++) 861 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); 862 863 ide_drive_get(hd, ARRAY_SIZE(hd)); 864 865 pci_cmd646_ide_init(pci_bus, hd, 1); 866 867 isa_create_simple(isa_bus, "i8042"); 868 for(i = 0; i < MAX_FD; i++) { 869 fd[i] = drive_get(IF_FLOPPY, 0, i); 870 } 871 fdctrl_init_isa(isa_bus, fd); 872 873 /* Map NVRAM into I/O (ebus) space */ 874 nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); 875 s = SYS_BUS_DEVICE(nvram); 876 memory_region_add_subregion(get_system_io(), 0x2000, 877 sysbus_mmio_get_region(s, 0)); 878 879 initrd_size = 0; 880 initrd_addr = 0; 881 kernel_size = sun4u_load_kernel(machine->kernel_filename, 882 machine->initrd_filename, 883 ram_size, &initrd_size, &initrd_addr, 884 &kernel_addr, &kernel_entry); 885 886 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, 887 machine->boot_order, 888 kernel_addr, kernel_size, 889 machine->kernel_cmdline, 890 initrd_addr, initrd_size, 891 /* XXX: need an option to load a NVRAM image */ 892 0, 893 graphic_width, graphic_height, graphic_depth, 894 (uint8_t *)&nd_table[0].macaddr); 895 896 fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); 897 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); 898 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); 899 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); 900 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); 901 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); 902 if (machine->kernel_cmdline) { 903 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 904 strlen(machine->kernel_cmdline) + 1); 905 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); 906 } else { 907 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); 908 } 909 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); 910 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); 911 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); 912 913 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); 914 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); 915 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); 916 917 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); 918 } 919 920 enum { 921 sun4u_id = 0, 922 sun4v_id = 64, 923 niagara_id, 924 }; 925 926 static const struct hwdef hwdefs[] = { 927 /* Sun4u generic PC-like machine */ 928 { 929 .default_cpu_model = "TI UltraSparc IIi", 930 .machine_id = sun4u_id, 931 .prom_addr = 0x1fff0000000ULL, 932 .console_serial_base = 0, 933 }, 934 /* Sun4v generic PC-like machine */ 935 { 936 .default_cpu_model = "Sun UltraSparc T1", 937 .machine_id = sun4v_id, 938 .prom_addr = 0x1fff0000000ULL, 939 .console_serial_base = 0, 940 }, 941 /* Sun4v generic Niagara machine */ 942 { 943 .default_cpu_model = "Sun UltraSparc T1", 944 .machine_id = niagara_id, 945 .prom_addr = 0xfff0000000ULL, 946 .console_serial_base = 0xfff0c2c000ULL, 947 }, 948 }; 949 950 /* Sun4u hardware initialisation */ 951 static void sun4u_init(MachineState *machine) 952 { 953 sun4uv_init(get_system_memory(), machine, &hwdefs[0]); 954 } 955 956 /* Sun4v hardware initialisation */ 957 static void sun4v_init(MachineState *machine) 958 { 959 sun4uv_init(get_system_memory(), machine, &hwdefs[1]); 960 } 961 962 /* Niagara hardware initialisation */ 963 static void niagara_init(MachineState *machine) 964 { 965 sun4uv_init(get_system_memory(), machine, &hwdefs[2]); 966 } 967 968 static QEMUMachine sun4u_machine = { 969 .name = "sun4u", 970 .desc = "Sun4u platform", 971 .init = sun4u_init, 972 .max_cpus = 1, // XXX for now 973 .is_default = 1, 974 .default_boot_order = "c", 975 }; 976 977 static QEMUMachine sun4v_machine = { 978 .name = "sun4v", 979 .desc = "Sun4v platform", 980 .init = sun4v_init, 981 .max_cpus = 1, // XXX for now 982 .default_boot_order = "c", 983 }; 984 985 static QEMUMachine niagara_machine = { 986 .name = "Niagara", 987 .desc = "Sun4v platform, Niagara", 988 .init = niagara_init, 989 .max_cpus = 1, // XXX for now 990 .default_boot_order = "c", 991 }; 992 993 static void sun4u_register_types(void) 994 { 995 type_register_static(&ebus_info); 996 type_register_static(&prom_info); 997 type_register_static(&ram_info); 998 } 999 1000 static void sun4u_machine_init(void) 1001 { 1002 qemu_register_machine(&sun4u_machine); 1003 qemu_register_machine(&sun4v_machine); 1004 qemu_register_machine(&niagara_machine); 1005 } 1006 1007 type_init(sun4u_register_types) 1008 machine_init(sun4u_machine_init); 1009