1 /* 2 * ASPEED AST2400 SMC Controller (SPI Flash Only) 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "sysemu/sysemu.h" 28 #include "qemu/log.h" 29 #include "include/qemu/error-report.h" 30 #include "exec/address-spaces.h" 31 32 #include "hw/ssi/aspeed_smc.h" 33 34 /* CE Type Setting Register */ 35 #define R_CONF (0x00 / 4) 36 #define CONF_LEGACY_DISABLE (1 << 31) 37 #define CONF_ENABLE_W4 20 38 #define CONF_ENABLE_W3 19 39 #define CONF_ENABLE_W2 18 40 #define CONF_ENABLE_W1 17 41 #define CONF_ENABLE_W0 16 42 #define CONF_FLASH_TYPE4 9 43 #define CONF_FLASH_TYPE3 7 44 #define CONF_FLASH_TYPE2 5 45 #define CONF_FLASH_TYPE1 3 46 #define CONF_FLASH_TYPE0 1 47 48 /* CE Control Register */ 49 #define R_CE_CTRL (0x04 / 4) 50 #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ 51 #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ 52 #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ 53 #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ 54 #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ 55 56 /* Interrupt Control and Status Register */ 57 #define R_INTR_CTRL (0x08 / 4) 58 #define INTR_CTRL_DMA_STATUS (1 << 11) 59 #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) 60 #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) 61 #define INTR_CTRL_DMA_EN (1 << 3) 62 #define INTR_CTRL_CMD_ABORT_EN (1 << 2) 63 #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) 64 65 /* CEx Control Register */ 66 #define R_CTRL0 (0x10 / 4) 67 #define CTRL_CMD_SHIFT 16 68 #define CTRL_CMD_MASK 0xff 69 #define CTRL_CE_STOP_ACTIVE (1 << 2) 70 #define CTRL_CMD_MODE_MASK 0x3 71 #define CTRL_READMODE 0x0 72 #define CTRL_FREADMODE 0x1 73 #define CTRL_WRITEMODE 0x2 74 #define CTRL_USERMODE 0x3 75 #define R_CTRL1 (0x14 / 4) 76 #define R_CTRL2 (0x18 / 4) 77 #define R_CTRL3 (0x1C / 4) 78 #define R_CTRL4 (0x20 / 4) 79 80 /* CEx Segment Address Register */ 81 #define R_SEG_ADDR0 (0x30 / 4) 82 #define SEG_SIZE_SHIFT 24 /* 8MB units */ 83 #define SEG_SIZE_MASK 0x7f 84 #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ 85 #define SEG_START_MASK 0x7f 86 #define R_SEG_ADDR1 (0x34 / 4) 87 #define R_SEG_ADDR2 (0x38 / 4) 88 #define R_SEG_ADDR3 (0x3C / 4) 89 #define R_SEG_ADDR4 (0x40 / 4) 90 91 /* Misc Control Register #1 */ 92 #define R_MISC_CTRL1 (0x50 / 4) 93 94 /* Misc Control Register #2 */ 95 #define R_MISC_CTRL2 (0x54 / 4) 96 97 /* DMA Control/Status Register */ 98 #define R_DMA_CTRL (0x80 / 4) 99 #define DMA_CTRL_DELAY_MASK 0xf 100 #define DMA_CTRL_DELAY_SHIFT 8 101 #define DMA_CTRL_FREQ_MASK 0xf 102 #define DMA_CTRL_FREQ_SHIFT 4 103 #define DMA_CTRL_MODE (1 << 3) 104 #define DMA_CTRL_CKSUM (1 << 2) 105 #define DMA_CTRL_DIR (1 << 1) 106 #define DMA_CTRL_EN (1 << 0) 107 108 /* DMA Flash Side Address */ 109 #define R_DMA_FLASH_ADDR (0x84 / 4) 110 111 /* DMA DRAM Side Address */ 112 #define R_DMA_DRAM_ADDR (0x88 / 4) 113 114 /* DMA Length Register */ 115 #define R_DMA_LEN (0x8C / 4) 116 117 /* Checksum Calculation Result */ 118 #define R_DMA_CHECKSUM (0x90 / 4) 119 120 /* Misc Control Register #2 */ 121 #define R_TIMINGS (0x94 / 4) 122 123 /* SPI controller registers and bits */ 124 #define R_SPI_CONF (0x00 / 4) 125 #define SPI_CONF_ENABLE_W0 0 126 #define R_SPI_CTRL0 (0x4 / 4) 127 #define R_SPI_MISC_CTRL (0x10 / 4) 128 #define R_SPI_TIMINGS (0x14 / 4) 129 130 /* 131 * Default segments mapping addresses and size for each slave per 132 * controller. These can be changed when board is initialized with the 133 * Segment Address Registers but they don't seem do be used on the 134 * field. 135 */ 136 static const AspeedSegments aspeed_segments_legacy[] = { 137 { 0x10000000, 32 * 1024 * 1024 }, 138 }; 139 140 static const AspeedSegments aspeed_segments_fmc[] = { 141 { 0x20000000, 64 * 1024 * 1024 }, 142 { 0x24000000, 32 * 1024 * 1024 }, 143 { 0x26000000, 32 * 1024 * 1024 }, 144 { 0x28000000, 32 * 1024 * 1024 }, 145 { 0x2A000000, 32 * 1024 * 1024 } 146 }; 147 148 static const AspeedSegments aspeed_segments_spi[] = { 149 { 0x30000000, 64 * 1024 * 1024 }, 150 }; 151 152 static const AspeedSMCController controllers[] = { 153 { "aspeed.smc.smc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, 154 CONF_ENABLE_W0, 5, aspeed_segments_legacy, 0x6000000 }, 155 { "aspeed.smc.fmc", R_CONF, R_CE_CTRL, R_CTRL0, R_TIMINGS, 156 CONF_ENABLE_W0, 5, aspeed_segments_fmc, 0x10000000 }, 157 { "aspeed.smc.spi", R_SPI_CONF, 0xff, R_SPI_CTRL0, R_SPI_TIMINGS, 158 SPI_CONF_ENABLE_W0, 1, aspeed_segments_spi, 0x10000000 }, 159 }; 160 161 static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, 162 unsigned size) 163 { 164 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u" 165 PRIx64 "\n", __func__, addr, size); 166 return 0; 167 } 168 169 static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, 170 uint64_t data, unsigned size) 171 { 172 qemu_log_mask(LOG_GUEST_ERROR, "%s: To 0x%" HWADDR_PRIx " of size %u: 0x%" 173 PRIx64 "\n", __func__, addr, size, data); 174 } 175 176 static const MemoryRegionOps aspeed_smc_flash_default_ops = { 177 .read = aspeed_smc_flash_default_read, 178 .write = aspeed_smc_flash_default_write, 179 .endianness = DEVICE_LITTLE_ENDIAN, 180 .valid = { 181 .min_access_size = 1, 182 .max_access_size = 4, 183 }, 184 }; 185 186 static inline int aspeed_smc_flash_mode(const AspeedSMCState *s, int cs) 187 { 188 return s->regs[s->r_ctrl0 + cs] & CTRL_CMD_MODE_MASK; 189 } 190 191 static inline bool aspeed_smc_is_usermode(const AspeedSMCState *s, int cs) 192 { 193 return aspeed_smc_flash_mode(s, cs) == CTRL_USERMODE; 194 } 195 196 static inline bool aspeed_smc_is_writable(const AspeedSMCState *s, int cs) 197 { 198 return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + cs)); 199 } 200 201 static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) 202 { 203 AspeedSMCFlash *fl = opaque; 204 const AspeedSMCState *s = fl->controller; 205 uint64_t ret = 0; 206 int i; 207 208 if (aspeed_smc_is_usermode(s, fl->id)) { 209 for (i = 0; i < size; i++) { 210 ret |= ssi_transfer(s->spi, 0x0) << (8 * i); 211 } 212 } else { 213 qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n", 214 __func__); 215 ret = -1; 216 } 217 218 return ret; 219 } 220 221 static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, 222 unsigned size) 223 { 224 AspeedSMCFlash *fl = opaque; 225 const AspeedSMCState *s = fl->controller; 226 int i; 227 228 if (!aspeed_smc_is_writable(s, fl->id)) { 229 qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%" 230 HWADDR_PRIx "\n", __func__, addr); 231 return; 232 } 233 234 if (!aspeed_smc_is_usermode(s, fl->id)) { 235 qemu_log_mask(LOG_UNIMP, "%s: usermode not implemented\n", 236 __func__); 237 return; 238 } 239 240 for (i = 0; i < size; i++) { 241 ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); 242 } 243 } 244 245 static const MemoryRegionOps aspeed_smc_flash_ops = { 246 .read = aspeed_smc_flash_read, 247 .write = aspeed_smc_flash_write, 248 .endianness = DEVICE_LITTLE_ENDIAN, 249 .valid = { 250 .min_access_size = 1, 251 .max_access_size = 4, 252 }, 253 }; 254 255 static bool aspeed_smc_is_ce_stop_active(const AspeedSMCState *s, int cs) 256 { 257 return s->regs[s->r_ctrl0 + cs] & CTRL_CE_STOP_ACTIVE; 258 } 259 260 static void aspeed_smc_update_cs(const AspeedSMCState *s) 261 { 262 int i; 263 264 for (i = 0; i < s->num_cs; ++i) { 265 qemu_set_irq(s->cs_lines[i], aspeed_smc_is_ce_stop_active(s, i)); 266 } 267 } 268 269 static void aspeed_smc_reset(DeviceState *d) 270 { 271 AspeedSMCState *s = ASPEED_SMC(d); 272 int i; 273 274 memset(s->regs, 0, sizeof s->regs); 275 276 /* Unselect all slaves */ 277 for (i = 0; i < s->num_cs; ++i) { 278 s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; 279 } 280 281 aspeed_smc_update_cs(s); 282 } 283 284 static bool aspeed_smc_is_implemented(AspeedSMCState *s, hwaddr addr) 285 { 286 return (addr == s->r_conf || addr == s->r_timings || addr == s->r_ce_ctrl || 287 (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs)); 288 } 289 290 static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) 291 { 292 AspeedSMCState *s = ASPEED_SMC(opaque); 293 294 addr >>= 2; 295 296 if (addr >= ARRAY_SIZE(s->regs)) { 297 qemu_log_mask(LOG_GUEST_ERROR, 298 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", 299 __func__, addr); 300 return 0; 301 } 302 303 if (!aspeed_smc_is_implemented(s, addr)) { 304 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 305 __func__, addr); 306 return 0; 307 } 308 309 return s->regs[addr]; 310 } 311 312 static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, 313 unsigned int size) 314 { 315 AspeedSMCState *s = ASPEED_SMC(opaque); 316 uint32_t value = data; 317 318 addr >>= 2; 319 320 if (addr >= ARRAY_SIZE(s->regs)) { 321 qemu_log_mask(LOG_GUEST_ERROR, 322 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", 323 __func__, addr); 324 return; 325 } 326 327 if (!aspeed_smc_is_implemented(s, addr)) { 328 qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", 329 __func__, addr); 330 return; 331 } 332 333 /* 334 * Not much to do apart from storing the value and set the cs 335 * lines if the register is a controlling one. 336 */ 337 s->regs[addr] = value; 338 if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { 339 aspeed_smc_update_cs(s); 340 } 341 } 342 343 static const MemoryRegionOps aspeed_smc_ops = { 344 .read = aspeed_smc_read, 345 .write = aspeed_smc_write, 346 .endianness = DEVICE_LITTLE_ENDIAN, 347 .valid.unaligned = true, 348 }; 349 350 static void aspeed_smc_realize(DeviceState *dev, Error **errp) 351 { 352 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 353 AspeedSMCState *s = ASPEED_SMC(dev); 354 AspeedSMCClass *mc = ASPEED_SMC_GET_CLASS(s); 355 int i; 356 char name[32]; 357 hwaddr offset = 0; 358 359 s->ctrl = mc->ctrl; 360 361 /* keep a copy under AspeedSMCState to speed up accesses */ 362 s->r_conf = s->ctrl->r_conf; 363 s->r_ce_ctrl = s->ctrl->r_ce_ctrl; 364 s->r_ctrl0 = s->ctrl->r_ctrl0; 365 s->r_timings = s->ctrl->r_timings; 366 s->conf_enable_w0 = s->ctrl->conf_enable_w0; 367 368 /* Enforce some real HW limits */ 369 if (s->num_cs > s->ctrl->max_slaves) { 370 qemu_log_mask(LOG_GUEST_ERROR, "%s: num_cs cannot exceed: %d\n", 371 __func__, s->ctrl->max_slaves); 372 s->num_cs = s->ctrl->max_slaves; 373 } 374 375 s->spi = ssi_create_bus(dev, "spi"); 376 377 /* Setup cs_lines for slaves */ 378 sysbus_init_irq(sbd, &s->irq); 379 s->cs_lines = g_new0(qemu_irq, s->num_cs); 380 ssi_auto_connect_slaves(dev, s->cs_lines, s->spi); 381 382 for (i = 0; i < s->num_cs; ++i) { 383 sysbus_init_irq(sbd, &s->cs_lines[i]); 384 } 385 386 aspeed_smc_reset(dev); 387 388 memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, 389 s->ctrl->name, ASPEED_SMC_R_MAX * 4); 390 sysbus_init_mmio(sbd, &s->mmio); 391 392 /* 393 * Memory region where flash modules are remapped 394 */ 395 snprintf(name, sizeof(name), "%s.flash", s->ctrl->name); 396 397 memory_region_init_io(&s->mmio_flash, OBJECT(s), 398 &aspeed_smc_flash_default_ops, s, name, 399 s->ctrl->mapping_window_size); 400 sysbus_init_mmio(sbd, &s->mmio_flash); 401 402 s->flashes = g_new0(AspeedSMCFlash, s->num_cs); 403 404 for (i = 0; i < s->num_cs; ++i) { 405 AspeedSMCFlash *fl = &s->flashes[i]; 406 407 snprintf(name, sizeof(name), "%s.%d", s->ctrl->name, i); 408 409 fl->id = i; 410 fl->controller = s; 411 fl->size = s->ctrl->segments[i].size; 412 memory_region_init_io(&fl->mmio, OBJECT(s), &aspeed_smc_flash_ops, 413 fl, name, fl->size); 414 memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); 415 offset += fl->size; 416 } 417 } 418 419 static const VMStateDescription vmstate_aspeed_smc = { 420 .name = "aspeed.smc", 421 .version_id = 1, 422 .minimum_version_id = 1, 423 .fields = (VMStateField[]) { 424 VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), 425 VMSTATE_END_OF_LIST() 426 } 427 }; 428 429 static Property aspeed_smc_properties[] = { 430 DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), 431 DEFINE_PROP_END_OF_LIST(), 432 }; 433 434 static void aspeed_smc_class_init(ObjectClass *klass, void *data) 435 { 436 DeviceClass *dc = DEVICE_CLASS(klass); 437 AspeedSMCClass *mc = ASPEED_SMC_CLASS(klass); 438 439 dc->realize = aspeed_smc_realize; 440 dc->reset = aspeed_smc_reset; 441 dc->props = aspeed_smc_properties; 442 dc->vmsd = &vmstate_aspeed_smc; 443 mc->ctrl = data; 444 } 445 446 static const TypeInfo aspeed_smc_info = { 447 .name = TYPE_ASPEED_SMC, 448 .parent = TYPE_SYS_BUS_DEVICE, 449 .instance_size = sizeof(AspeedSMCState), 450 .class_size = sizeof(AspeedSMCClass), 451 .abstract = true, 452 }; 453 454 static void aspeed_smc_register_types(void) 455 { 456 int i; 457 458 type_register_static(&aspeed_smc_info); 459 for (i = 0; i < ARRAY_SIZE(controllers); ++i) { 460 TypeInfo ti = { 461 .name = controllers[i].name, 462 .parent = TYPE_ASPEED_SMC, 463 .class_init = aspeed_smc_class_init, 464 .class_data = (void *)&controllers[i], 465 }; 466 type_register(&ti); 467 } 468 } 469 470 type_init(aspeed_smc_register_types) 471