xref: /qemu/hw/ssi/imx_spi.c (revision 58369e22) 
1 /*
2  * IMX SPI Controller
3  *
4  * Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
7  * See the COPYING file in the top-level directory.
8  *
9  */
10 
11 #include "qemu/osdep.h"
12 #include "hw/ssi/imx_spi.h"
13 #include "sysemu/sysemu.h"
14 
15 #ifndef DEBUG_IMX_SPI
16 #define DEBUG_IMX_SPI 0
17 #endif
18 
19 #define DPRINTF(fmt, args...) \
20     do { \
21         if (DEBUG_IMX_SPI) { \
22             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
23                                              __func__, ##args); \
24         } \
25     } while (0)
26 
27 static char const *imx_spi_reg_name(uint32_t reg)
28 {
29     static char unknown[20];
30 
31     switch (reg) {
32     case ECSPI_RXDATA:
33         return  "ECSPI_RXDATA";
34     case ECSPI_TXDATA:
35         return  "ECSPI_TXDATA";
36     case ECSPI_CONREG:
37         return  "ECSPI_CONREG";
38     case ECSPI_CONFIGREG:
39         return  "ECSPI_CONFIGREG";
40     case ECSPI_INTREG:
41         return  "ECSPI_INTREG";
42     case ECSPI_DMAREG:
43         return  "ECSPI_DMAREG";
44     case ECSPI_STATREG:
45         return  "ECSPI_STATREG";
46     case ECSPI_PERIODREG:
47         return  "ECSPI_PERIODREG";
48     case ECSPI_TESTREG:
49         return  "ECSPI_TESTREG";
50     case ECSPI_MSGDATA:
51         return  "ECSPI_MSGDATA";
52     default:
53         sprintf(unknown, "%d ?", reg);
54         return unknown;
55     }
56 }
57 
58 static const VMStateDescription vmstate_imx_spi = {
59     .name = TYPE_IMX_SPI,
60     .version_id = 1,
61     .minimum_version_id = 1,
62     .fields = (VMStateField[]) {
63         VMSTATE_FIFO32(tx_fifo, IMXSPIState),
64         VMSTATE_FIFO32(rx_fifo, IMXSPIState),
65         VMSTATE_INT16(burst_length, IMXSPIState),
66         VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
67         VMSTATE_END_OF_LIST()
68     },
69 };
70 
71 static void imx_spi_txfifo_reset(IMXSPIState *s)
72 {
73     fifo32_reset(&s->tx_fifo);
74     s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
75     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
76 }
77 
78 static void imx_spi_rxfifo_reset(IMXSPIState *s)
79 {
80     fifo32_reset(&s->rx_fifo);
81     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
82     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
83     s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
84 }
85 
86 static void imx_spi_update_irq(IMXSPIState *s)
87 {
88     int level;
89 
90     if (fifo32_is_empty(&s->rx_fifo)) {
91         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
92     } else {
93         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
94     }
95 
96     if (fifo32_is_full(&s->rx_fifo)) {
97         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
98     } else {
99         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
100     }
101 
102     if (fifo32_is_empty(&s->tx_fifo)) {
103         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
104     } else {
105         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
106     }
107 
108     if (fifo32_is_full(&s->tx_fifo)) {
109         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
110     } else {
111         s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
112     }
113 
114     level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
115 
116     qemu_set_irq(s->irq, level);
117 
118     DPRINTF("IRQ level is %d\n", level);
119 }
120 
121 static uint8_t imx_spi_selected_channel(IMXSPIState *s)
122 {
123     return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
124 }
125 
126 static uint32_t imx_spi_burst_length(IMXSPIState *s)
127 {
128     return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
129 }
130 
131 static bool imx_spi_is_enabled(IMXSPIState *s)
132 {
133     return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
134 }
135 
136 static bool imx_spi_channel_is_master(IMXSPIState *s)
137 {
138     uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
139 
140     return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
141 }
142 
143 static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
144 {
145     uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
146 
147     return imx_spi_channel_is_master(s) &&
148            !(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
149            ((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
150 }
151 
152 static void imx_spi_flush_txfifo(IMXSPIState *s)
153 {
154     uint32_t tx;
155     uint32_t rx;
156 
157     DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
158             fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
159 
160     while (!fifo32_is_empty(&s->tx_fifo)) {
161         int tx_burst = 0;
162         int index = 0;
163 
164         if (s->burst_length <= 0) {
165             s->burst_length = imx_spi_burst_length(s);
166 
167             DPRINTF("Burst length = %d\n", s->burst_length);
168 
169             if (imx_spi_is_multiple_master_burst(s)) {
170                 s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
171             }
172         }
173 
174         tx = fifo32_pop(&s->tx_fifo);
175 
176         DPRINTF("data tx:0x%08x\n", tx);
177 
178         tx_burst = MIN(s->burst_length, 32);
179 
180         rx = 0;
181 
182         while (tx_burst) {
183             uint8_t byte = tx & 0xff;
184 
185             DPRINTF("writing 0x%02x\n", (uint32_t)byte);
186 
187             /* We need to write one byte at a time */
188             byte = ssi_transfer(s->bus, byte);
189 
190             DPRINTF("0x%02x read\n", (uint32_t)byte);
191 
192             tx = tx >> 8;
193             rx |= (byte << (index * 8));
194 
195             /* Remove 8 bits from the actual burst */
196             tx_burst -= 8;
197             s->burst_length -= 8;
198             index++;
199         }
200 
201         DPRINTF("data rx:0x%08x\n", rx);
202 
203         if (fifo32_is_full(&s->rx_fifo)) {
204             s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
205         } else {
206             fifo32_push(&s->rx_fifo, (uint8_t)rx);
207         }
208 
209         if (s->burst_length <= 0) {
210             s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
211 
212             if (!imx_spi_is_multiple_master_burst(s)) {
213                 s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
214                 break;
215             }
216         }
217     }
218 
219     if (fifo32_is_empty(&s->tx_fifo)) {
220         s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
221     }
222 
223     /* TODO: We should also use TDR and RDR bits */
224 
225     DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
226             fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
227 }
228 
229 static void imx_spi_reset(DeviceState *dev)
230 {
231     IMXSPIState *s = IMX_SPI(dev);
232 
233     DPRINTF("\n");
234 
235     memset(s->regs, 0, sizeof(s->regs));
236 
237     s->regs[ECSPI_STATREG] = 0x00000003;
238 
239     imx_spi_rxfifo_reset(s);
240     imx_spi_txfifo_reset(s);
241 
242     imx_spi_update_irq(s);
243 
244     s->burst_length = 0;
245 }
246 
247 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
248 {
249     uint32_t value = 0;
250     IMXSPIState *s = opaque;
251     uint32_t index = offset >> 2;
252 
253     if (index >=  ECSPI_MAX) {
254         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
255                       HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
256         return 0;
257     }
258 
259     switch (index) {
260     case ECSPI_RXDATA:
261         if (!imx_spi_is_enabled(s)) {
262             value = 0;
263         } else if (fifo32_is_empty(&s->rx_fifo)) {
264             /* value is undefined */
265             value = 0xdeadbeef;
266         } else {
267             /* read from the RX FIFO */
268             value = fifo32_pop(&s->rx_fifo);
269         }
270 
271         break;
272     case ECSPI_TXDATA:
273         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
274                       TYPE_IMX_SPI, __func__);
275 
276         /* Reading from TXDATA gives 0 */
277 
278         break;
279     case ECSPI_MSGDATA:
280         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
281                       TYPE_IMX_SPI, __func__);
282 
283         /* Reading from MSGDATA gives 0 */
284 
285         break;
286     default:
287         value = s->regs[index];
288         break;
289     }
290 
291     DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
292 
293     imx_spi_update_irq(s);
294 
295     return (uint64_t)value;
296 }
297 
298 static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
299                            unsigned size)
300 {
301     IMXSPIState *s = opaque;
302     uint32_t index = offset >> 2;
303     uint32_t change_mask;
304 
305     if (index >=  ECSPI_MAX) {
306         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
307                       HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
308         return;
309     }
310 
311     DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
312             (uint32_t)value);
313 
314     change_mask = s->regs[index] ^ value;
315 
316     switch (index) {
317     case ECSPI_RXDATA:
318         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
319                       TYPE_IMX_SPI, __func__);
320         break;
321     case ECSPI_TXDATA:
322     case ECSPI_MSGDATA:
323         /* Is there any difference between TXDATA and MSGDATA ? */
324         /* I'll have to look in the linux driver */
325         if (!imx_spi_is_enabled(s)) {
326             /* Ignore writes if device is disabled */
327             break;
328         } else if (fifo32_is_full(&s->tx_fifo)) {
329             /* Ignore writes if queue is full */
330             break;
331         }
332 
333         fifo32_push(&s->tx_fifo, (uint32_t)value);
334 
335         if (imx_spi_channel_is_master(s) &&
336             (s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
337             /*
338              * Start emitting if current channel is master and SMC bit is
339              * set.
340              */
341             imx_spi_flush_txfifo(s);
342         }
343 
344         break;
345     case ECSPI_STATREG:
346         /* the RO and TC bits are write-one-to-clear */
347         value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
348         s->regs[ECSPI_STATREG] &= ~value;
349 
350         break;
351     case ECSPI_CONREG:
352         s->regs[ECSPI_CONREG] = value;
353 
354         if (!imx_spi_is_enabled(s)) {
355             /* device is disabled, so this is a reset */
356             imx_spi_reset(DEVICE(s));
357             return;
358         }
359 
360         if (imx_spi_channel_is_master(s)) {
361             int i;
362 
363             /* We are in master mode */
364 
365             for (i = 0; i < 4; i++) {
366                 qemu_set_irq(s->cs_lines[i],
367                              i == imx_spi_selected_channel(s) ? 0 : 1);
368             }
369 
370             if ((value & change_mask & ECSPI_CONREG_SMC) &&
371                 !fifo32_is_empty(&s->tx_fifo)) {
372                 /* SMC bit is set and TX FIFO has some slots filled in */
373                 imx_spi_flush_txfifo(s);
374             } else if ((value & change_mask & ECSPI_CONREG_XCH) &&
375                 !(value & ECSPI_CONREG_SMC)) {
376                 /* This is a request to start emitting */
377                 imx_spi_flush_txfifo(s);
378             }
379         }
380 
381         break;
382     default:
383         s->regs[index] = value;
384 
385         break;
386     }
387 
388     imx_spi_update_irq(s);
389 }
390 
391 static const struct MemoryRegionOps imx_spi_ops = {
392     .read = imx_spi_read,
393     .write = imx_spi_write,
394     .endianness = DEVICE_NATIVE_ENDIAN,
395     .valid = {
396         /*
397          * Our device would not work correctly if the guest was doing
398          * unaligned access. This might not be a limitation on the real
399          * device but in practice there is no reason for a guest to access
400          * this device unaligned.
401          */
402         .min_access_size = 4,
403         .max_access_size = 4,
404         .unaligned = false,
405     },
406 };
407 
408 static void imx_spi_realize(DeviceState *dev, Error **errp)
409 {
410     IMXSPIState *s = IMX_SPI(dev);
411     int i;
412 
413     s->bus = ssi_create_bus(dev, "spi");
414 
415     memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
416                           TYPE_IMX_SPI, 0x1000);
417     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
418     sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
419 
420     ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
421 
422     for (i = 0; i < 4; ++i) {
423         sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
424     }
425 
426     s->burst_length = 0;
427 
428     fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
429     fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
430 }
431 
432 static void imx_spi_class_init(ObjectClass *klass, void *data)
433 {
434     DeviceClass *dc = DEVICE_CLASS(klass);
435 
436     dc->realize = imx_spi_realize;
437     dc->vmsd = &vmstate_imx_spi;
438     dc->reset = imx_spi_reset;
439     dc->desc = "i.MX SPI Controller";
440 }
441 
442 static const TypeInfo imx_spi_info = {
443     .name          = TYPE_IMX_SPI,
444     .parent        = TYPE_SYS_BUS_DEVICE,
445     .instance_size = sizeof(IMXSPIState),
446     .class_init    = imx_spi_class_init,
447 };
448 
449 static void imx_spi_register_types(void)
450 {
451     type_register_static(&imx_spi_info);
452 }
453 
454 type_init(imx_spi_register_types)
455