xref: /qemu/hw/ssi/xilinx_spi.c (revision c734cd40) 
1 /*
2  * QEMU model of the Xilinx SPI Controller
3  *
4  * Copyright (C) 2010 Edgar E. Iglesias.
5  * Copyright (C) 2012 Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
6  * Copyright (C) 2012 PetaLogix
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 
27 #include "qemu/osdep.h"
28 #include "hw/sysbus.h"
29 #include "migration/vmstate.h"
30 #include "qemu/log.h"
31 #include "qemu/module.h"
32 #include "qemu/fifo8.h"
33 
34 #include "hw/irq.h"
35 #include "hw/qdev-properties.h"
36 #include "hw/ssi/ssi.h"
37 #include "qom/object.h"
38 
39 #ifdef XILINX_SPI_ERR_DEBUG
40 #define DB_PRINT(...) do { \
41     fprintf(stderr,  ": %s: ", __func__); \
42     fprintf(stderr, ## __VA_ARGS__); \
43     } while (0)
44 #else
45     #define DB_PRINT(...)
46 #endif
47 
48 #define R_DGIER     (0x1c / 4)
49 #define R_DGIER_IE  (1 << 31)
50 
51 #define R_IPISR     (0x20 / 4)
52 #define IRQ_DRR_NOT_EMPTY    (1 << (31 - 23))
53 #define IRQ_DRR_OVERRUN      (1 << (31 - 26))
54 #define IRQ_DRR_FULL         (1 << (31 - 27))
55 #define IRQ_TX_FF_HALF_EMPTY (1 << 6)
56 #define IRQ_DTR_UNDERRUN     (1 << 3)
57 #define IRQ_DTR_EMPTY        (1 << (31 - 29))
58 
59 #define R_IPIER     (0x28 / 4)
60 #define R_SRR       (0x40 / 4)
61 #define R_SPICR     (0x60 / 4)
62 #define R_SPICR_TXFF_RST     (1 << 5)
63 #define R_SPICR_RXFF_RST     (1 << 6)
64 #define R_SPICR_MTI          (1 << 8)
65 
66 #define R_SPISR     (0x64 / 4)
67 #define SR_TX_FULL    (1 << 3)
68 #define SR_TX_EMPTY   (1 << 2)
69 #define SR_RX_FULL    (1 << 1)
70 #define SR_RX_EMPTY   (1 << 0)
71 
72 #define R_SPIDTR    (0x68 / 4)
73 #define R_SPIDRR    (0x6C / 4)
74 #define R_SPISSR    (0x70 / 4)
75 #define R_TX_FF_OCY (0x74 / 4)
76 #define R_RX_FF_OCY (0x78 / 4)
77 #define R_MAX       (0x7C / 4)
78 
79 #define FIFO_CAPACITY 256
80 
81 #define TYPE_XILINX_SPI "xlnx.xps-spi"
82 typedef struct XilinxSPI XilinxSPI;
83 DECLARE_INSTANCE_CHECKER(XilinxSPI, XILINX_SPI,
84                          TYPE_XILINX_SPI)
85 
86 struct XilinxSPI {
87     SysBusDevice parent_obj;
88 
89     MemoryRegion mmio;
90 
91     qemu_irq irq;
92     int irqline;
93 
94     uint8_t num_cs;
95     qemu_irq *cs_lines;
96 
97     SSIBus *spi;
98 
99     Fifo8 rx_fifo;
100     Fifo8 tx_fifo;
101 
102     uint32_t regs[R_MAX];
103 };
104 
105 static void txfifo_reset(XilinxSPI *s)
106 {
107     fifo8_reset(&s->tx_fifo);
108 
109     s->regs[R_SPISR] &= ~SR_TX_FULL;
110     s->regs[R_SPISR] |= SR_TX_EMPTY;
111 }
112 
113 static void rxfifo_reset(XilinxSPI *s)
114 {
115     fifo8_reset(&s->rx_fifo);
116 
117     s->regs[R_SPISR] |= SR_RX_EMPTY;
118     s->regs[R_SPISR] &= ~SR_RX_FULL;
119 }
120 
121 static void xlx_spi_update_cs(XilinxSPI *s)
122 {
123     int i;
124 
125     for (i = 0; i < s->num_cs; ++i) {
126         qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
127     }
128 }
129 
130 static void xlx_spi_update_irq(XilinxSPI *s)
131 {
132     uint32_t pending;
133 
134     s->regs[R_IPISR] |=
135             (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
136             (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
137 
138     pending = s->regs[R_IPISR] & s->regs[R_IPIER];
139 
140     pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
141     pending = !!pending;
142 
143     /* This call lies right in the data paths so don't call the
144        irq chain unless things really changed.  */
145     if (pending != s->irqline) {
146         s->irqline = pending;
147         DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
148                     pending, s->regs[R_IPISR], s->regs[R_IPIER]);
149         qemu_set_irq(s->irq, pending);
150     }
151 
152 }
153 
154 static void xlx_spi_do_reset(XilinxSPI *s)
155 {
156     memset(s->regs, 0, sizeof s->regs);
157 
158     rxfifo_reset(s);
159     txfifo_reset(s);
160 
161     s->regs[R_SPISSR] = ~0;
162     xlx_spi_update_irq(s);
163     xlx_spi_update_cs(s);
164 }
165 
166 static void xlx_spi_reset(DeviceState *d)
167 {
168     xlx_spi_do_reset(XILINX_SPI(d));
169 }
170 
171 static inline int spi_master_enabled(XilinxSPI *s)
172 {
173     return !(s->regs[R_SPICR] & R_SPICR_MTI);
174 }
175 
176 static void spi_flush_txfifo(XilinxSPI *s)
177 {
178     uint32_t tx;
179     uint32_t rx;
180 
181     while (!fifo8_is_empty(&s->tx_fifo)) {
182         tx = (uint32_t)fifo8_pop(&s->tx_fifo);
183         DB_PRINT("data tx:%x\n", tx);
184         rx = ssi_transfer(s->spi, tx);
185         DB_PRINT("data rx:%x\n", rx);
186         if (fifo8_is_full(&s->rx_fifo)) {
187             s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
188         } else {
189             fifo8_push(&s->rx_fifo, (uint8_t)rx);
190             if (fifo8_is_full(&s->rx_fifo)) {
191                 s->regs[R_SPISR] |= SR_RX_FULL;
192                 s->regs[R_IPISR] |= IRQ_DRR_FULL;
193             }
194         }
195 
196         s->regs[R_SPISR] &= ~SR_RX_EMPTY;
197         s->regs[R_SPISR] &= ~SR_TX_FULL;
198         s->regs[R_SPISR] |= SR_TX_EMPTY;
199 
200         s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
201         s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
202     }
203 
204 }
205 
206 static uint64_t
207 spi_read(void *opaque, hwaddr addr, unsigned int size)
208 {
209     XilinxSPI *s = opaque;
210     uint32_t r = 0;
211 
212     addr >>= 2;
213     switch (addr) {
214     case R_SPIDRR:
215         if (fifo8_is_empty(&s->rx_fifo)) {
216             DB_PRINT("Read from empty FIFO!\n");
217             return 0xdeadbeef;
218         }
219 
220         s->regs[R_SPISR] &= ~SR_RX_FULL;
221         r = fifo8_pop(&s->rx_fifo);
222         if (fifo8_is_empty(&s->rx_fifo)) {
223             s->regs[R_SPISR] |= SR_RX_EMPTY;
224         }
225         break;
226 
227     case R_SPISR:
228         r = s->regs[addr];
229         break;
230 
231     default:
232         if (addr < ARRAY_SIZE(s->regs)) {
233             r = s->regs[addr];
234         }
235         break;
236 
237     }
238     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
239     xlx_spi_update_irq(s);
240     return r;
241 }
242 
243 static void
244 spi_write(void *opaque, hwaddr addr,
245             uint64_t val64, unsigned int size)
246 {
247     XilinxSPI *s = opaque;
248     uint32_t value = val64;
249 
250     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
251     addr >>= 2;
252     switch (addr) {
253     case R_SRR:
254         if (value != 0xa) {
255             DB_PRINT("Invalid write to SRR %x\n", value);
256         } else {
257             xlx_spi_do_reset(s);
258         }
259         break;
260 
261     case R_SPIDTR:
262         s->regs[R_SPISR] &= ~SR_TX_EMPTY;
263         fifo8_push(&s->tx_fifo, (uint8_t)value);
264         if (fifo8_is_full(&s->tx_fifo)) {
265             s->regs[R_SPISR] |= SR_TX_FULL;
266         }
267         if (!spi_master_enabled(s)) {
268             goto done;
269         } else {
270             DB_PRINT("DTR and master enabled\n");
271         }
272         spi_flush_txfifo(s);
273         break;
274 
275     case R_SPISR:
276         DB_PRINT("Invalid write to SPISR %x\n", value);
277         break;
278 
279     case R_IPISR:
280         /* Toggle the bits.  */
281         s->regs[addr] ^= value;
282         break;
283 
284     /* Slave Select Register.  */
285     case R_SPISSR:
286         s->regs[addr] = value;
287         xlx_spi_update_cs(s);
288         break;
289 
290     case R_SPICR:
291         /* FIXME: reset irq and sr state to empty queues.  */
292         if (value & R_SPICR_RXFF_RST) {
293             rxfifo_reset(s);
294         }
295 
296         if (value & R_SPICR_TXFF_RST) {
297             txfifo_reset(s);
298         }
299         value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
300         s->regs[addr] = value;
301 
302         if (!(value & R_SPICR_MTI)) {
303             spi_flush_txfifo(s);
304         }
305         break;
306 
307     default:
308         if (addr < ARRAY_SIZE(s->regs)) {
309             s->regs[addr] = value;
310         }
311         break;
312     }
313 
314 done:
315     xlx_spi_update_irq(s);
316 }
317 
318 static const MemoryRegionOps spi_ops = {
319     .read = spi_read,
320     .write = spi_write,
321     .endianness = DEVICE_NATIVE_ENDIAN,
322     .valid = {
323         .min_access_size = 4,
324         .max_access_size = 4
325     }
326 };
327 
328 static void xilinx_spi_realize(DeviceState *dev, Error **errp)
329 {
330     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
331     XilinxSPI *s = XILINX_SPI(dev);
332     int i;
333 
334     DB_PRINT("\n");
335 
336     s->spi = ssi_create_bus(dev, "spi");
337 
338     sysbus_init_irq(sbd, &s->irq);
339     s->cs_lines = g_new0(qemu_irq, s->num_cs);
340     for (i = 0; i < s->num_cs; ++i) {
341         sysbus_init_irq(sbd, &s->cs_lines[i]);
342     }
343 
344     memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
345                           "xilinx-spi", R_MAX * 4);
346     sysbus_init_mmio(sbd, &s->mmio);
347 
348     s->irqline = -1;
349 
350     fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
351     fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
352 }
353 
354 static const VMStateDescription vmstate_xilinx_spi = {
355     .name = "xilinx_spi",
356     .version_id = 1,
357     .minimum_version_id = 1,
358     .fields = (VMStateField[]) {
359         VMSTATE_FIFO8(tx_fifo, XilinxSPI),
360         VMSTATE_FIFO8(rx_fifo, XilinxSPI),
361         VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
362         VMSTATE_END_OF_LIST()
363     }
364 };
365 
366 static Property xilinx_spi_properties[] = {
367     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
368     DEFINE_PROP_END_OF_LIST(),
369 };
370 
371 static void xilinx_spi_class_init(ObjectClass *klass, void *data)
372 {
373     DeviceClass *dc = DEVICE_CLASS(klass);
374 
375     dc->realize = xilinx_spi_realize;
376     dc->reset = xlx_spi_reset;
377     device_class_set_props(dc, xilinx_spi_properties);
378     dc->vmsd = &vmstate_xilinx_spi;
379 }
380 
381 static const TypeInfo xilinx_spi_info = {
382     .name           = TYPE_XILINX_SPI,
383     .parent         = TYPE_SYS_BUS_DEVICE,
384     .instance_size  = sizeof(XilinxSPI),
385     .class_init     = xilinx_spi_class_init,
386 };
387 
388 static void xilinx_spi_register_types(void)
389 {
390     type_register_static(&xilinx_spi_info);
391 }
392 
393 type_init(xilinx_spi_register_types)
394